Integrated circuit layout modular layout method and system based on AI matching

Abstract

The invention relates to the technical field of integrated circuits, in particular to an integrated circuit layout modular layout method and system based on AI matching. The method selects a target module; the target module is converted to an IC layout area, an initial circuit layout is generated, and an external rectangle and module internal pins are extracted; determining an initial coordinate of an interface point according to a shortest physical path from an internal pin of each module to an external rectangle to which the module belongs; determining a theoretical shortest path according to the respective displaceable range in the interface point combination; determining a path adaptation degree according to the actual connection path and the theoretical shortest path; the overall layout fitness is determined by combining the distribution dense characteristics of the actual connection paths; taking the overall layout fitness as an optimization target, performing iterative optimization through a genetic algorithm until the overall layout fitness converges, and outputting an optimized circuit layout; and inputting the optimized circuit layout into a pre-training AI engine, and outputting a final circuit layout, so that the expandability of layout design is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to an integrated circuit layout modularization layout method and system based on AI matching. BACKGROUND

[0002] With the rapid development of integrated circuit technology, the complexity of circuit system is continuously improved, and IC layout design is facing challenges such as explosive growth of module quantity, diversification of signal types (such as high-frequency signals, differential signals, power signals, etc.), strict layout and wiring constraints, etc.

[0003] At present, the traditional manual layout method is adopted, which seriously depends on the experience of designers, and it is difficult to achieve optimal layout under the requirements of multiple performance indicators, or the existing automatic layout tools are used, such as tools based on rules or traditional optimization algorithms, however, these tools to some extent reduce the manual burden, but the placement of components needs to start from zero and the module interface point position is fixed, lacking dynamic adjustment mechanism, resulting in low design reuse rate, and not considering the key factors affecting design quality such as wiring area congestion and signal path matching characteristics, which still needs a lot of manual adjustment, reducing design efficiency. SUMMARY

[0004] In order to solve the technical problem that the key factors affecting the design quality such as wiring area congestion and signal path matching characteristics are not considered comprehensively, resulting in a large amount of manual adjustment in the follow-up, the present application provides an integrated circuit layout modularization layout method and system based on AI matching, and the technical scheme adopted is as follows: The present application provides an integrated circuit layout modularization layout method based on AI matching, which comprises the following steps: In response to the chip function demand of the user, a target module is selected from a preset IC schematic diagram template library, wherein the template library contains standard schematic diagram modules classified by function; The target module is converted to an IC layout area to generate an initial circuit layout, and the bounding rectangle of each target module and the internal pins of the module are extracted; according to the shortest physical path of each internal pin of the module to its bounding rectangle, the initial coordinates of the interface points of each target module are determined, and a displaceable range is set for each interface point; The matching interface point combination and the actual connection path between the interconnected target modules are obtained, the theoretical shortest path is determined according to the displaceable range of each interface point in the interface point combination, the path adaptation degree is determined according to the actual connection path and the theoretical shortest path, and the overall layout adaptability is determined in combination with the distribution density characteristics of each actual connection path; Taking the overall layout adaptability as the optimization target, the position, direction and interface point position of the target module are iteratively optimized through a genetic algorithm until the overall layout adaptability converges, and an optimized circuit layout is output. The optimized circuit layout is input into a pre-trained AI engine, and detailed optimization and verification are performed according to IC design rules and electrical rules, and a final circuit layout that can be used for manufacturing is output.

[0005] Further, in response to the chip function demand of the user, a target module is selected from a preset IC schematic template library, including: parsing the circuit function keywords and performance constraint conditions in the chip function demand of the user, wherein the performance constraint conditions include at least one of power consumption, bandwidth, signal-to-noise ratio, or interface protocol type; Based on the circuit function keywords, one or more candidate modules required are matched from the preset IC schematic template library, wherein the preset IC schematic template library at least includes a power module, a signal processing module, and an interface module; The target module that meets the performance constraint condition is selected from the candidate module.

[0006] Further, the target module is converted to the IC graph to generate an initial circuit layout, including: For each target module, the components in the target module are preliminarily arranged in the IC layout area according to the relative positions of the components in the standard schematic module; The layout of the components in the target module is adjusted according to the preset component spacing rules, and the bounding rectangle of the target module is determined; According to the preset layout priority, the initial placement position of each target module in the IC layout area is determined, wherein the preset layout priority includes that the target module with special position requirement is preferentially placed, and the target module without special position requirement is sorted according to the area of the bounding rectangle from large to small, and is randomly distributed and placed in the IC layout area.

[0007] Further, the integrated circuit layout modularization layout based on AI matching further includes: After the initial placement of all target modules is completed, overlap detection between target modules is performed; If it is detected that the bounding rectangles overlap, the overlapping target modules are moved by a preset distance along the opposite direction of the overlap until there is no overlap between the bounding rectangles of all target modules.

[0008] Further, the initial coordinates of the interface points of each target module are determined according to the shortest physical path between the internal pins and the bounding rectangle, including: A two-dimensional coordinate system is established with the geometric center of the bounding rectangle of the target module as the origin; The physical coordinates of the internal pins of each module are extracted, the perpendicular distances of each internal pin to the four sides of the bounding rectangle are calculated, and the target side corresponding to the shortest perpendicular distance is selected; The intersection point of the target edge and the direction of the shortest vertical distance is taken as the interface point of the corresponding internal pin, and the initial coordinates of the interface point are recorded.

[0009] Further, the internal pins of the module include input pins, output pins, power pins, and ground pins, wherein the differential signal pins and the functionally associated input and output pins exist in pairs, the power pins, the ground pins, and part of the control pins are in single-ended form, and the initial coordinates of the interface points are determined, including: If there are multiple internal pins in the target module, the initial coordinates of the interface points corresponding to the pins are determined in order according to the pin type priority, and the pin type priority is from high to low: paired differential pair pins, functionally associated input and output pin pairs, single-ended signal pins, power pins, and ground pins. For the pins in paired form, when determining the initial coordinates of the interface points, the relative positional relationship of the two interface points corresponding to a pair of pins on the target edge should be consistent with the relative positional relationship of the internal pins of the module, and the two interface points should be preferentially located on the same target edge.

[0010] Further, the path adaptation degree determination process includes: For each interface point combination of the interconnected target module, the sampling step is dynamically adjusted according to the signal type within the respective displaceable range to generate discrete coordinate sampling points, wherein the sampling step for high-frequency signals is smaller than that for low-frequency signals. The Euclidean distance between each pair of sampling points is calculated, and the minimum distance value among all pairs of sampling points is selected; the straight line path corresponding to the minimum distance is determined as the theoretical shortest path. The ratio of the length of the theoretical shortest path to the physical length of the actual connection path is calculated, and the ratio is corrected in combination with the number of corners of the actual connection path to obtain the path adaptation degree, wherein the number of corners of the actual connection path is determined based on the number of times of direction change of the line segments in the actual connection path.

[0011] Further, in combination with the distribution density characteristics of each actual connection path, the overall layout adaptation degree is determined, including: The IC layout area is divided into equal-area grid cells using the grid division method, and the number of intersection points of the actual connection paths in each grid cell is counted. Grid cells with a number of intersection points exceeding a preset intersection point number threshold are marked as crowded areas, the ratio of the total area of the crowded areas to the total area of the IC layout area is calculated as a crowded coefficient, and the difference between the positive integer 1 and the crowded coefficient is calculated as a first difference. The corresponding preset weight is assigned according to the importance of the signal carried by the path, and the weighted average value of the path adaptation degrees of all interface point combinations is calculated as the average adaptation degree, wherein the weight assigned to high-frequency signal paths is higher than the weight assigned to low-frequency signal paths. The average adaptation degree and the first difference value are weighted and fused based on preset weight coefficients to obtain an overall layout adaptation degree.

[0012] Further, the target module position, direction and interface point position are iteratively optimized by a genetic algorithm with the overall layout adaptation degree as an optimization target until the overall layout adaptation degree converges, and an optimized circuit layout is output, including: The position coordinates of the target module, the preset rotation angle and the coordinate offsets of each interface point within the displaceable range thereof are collectively encoded as chromosome units of the genetic algorithm to form an initial population; The initial population is subjected to selection, crossover and mutation operations with the overall layout adaptation degree as an evaluation function; The highest overall layout adaptation degree of the population after each iteration is recorded, and when the change amplitude of the highest overall layout adaptation degree is less than a preset threshold in a continuous preset number of iterations, it is determined that the overall layout adaptation degree converges, and the iteration is stopped; The chromosome with the highest overall layout adaptation degree is selected from the population at the time of convergence, and the corresponding target module position coordinates, rotation angle and interface point final coordinate parameters are decoded to update the module layout and interface point connection relationship, and an optimized circuit layout is generated and output.

[0013] The AI matching-based integrated circuit layout modularization layout system includes a memory, a processor and a computer program stored in the memory and running on the processor, and the processor implements the steps of the AI matching-based integrated circuit layout modularization layout system method when executing the computer program.

[0014] The present application has the following advantages: By means of the preset IC schematic diagram template library and the AI matching technology, the target module can be quickly selected in response to the user's functional requirements, and the manual screening cost is reduced; the module position, direction and interface point position are iteratively optimized by means of the genetic algorithm, and the design cycle is significantly shortened; the initial coordinates of the interface points are determined based on the shortest physical path, the path adaptation degree is evaluated in combination with the theoretical shortest path and the actual connection path, a single path is realized, and the length of the path of high-frequency signals and differential pair signals is optimized; then, the path adaptation degree and the overall layout adaptation degree of the IC layout area are fused and analyzed comprehensively, the quality of the single path and the overall wiring balance are taken into account, and local congestion is reduced; the displaceable range of the interface points is set, and the module position, direction and interface point coordinates are dynamically adjusted by means of the genetic algorithm, so that the layout can be self-adapted to different functional requirements and constraint conditions, and the scalability of the layout design is improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, and the advantages thereof, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flow chart of an AI matching-based integrated circuit layout modularization layout method provided by an embodiment of the present application; Figure 2 An initial coordinate determination process example diagram of each target module interface point provided by an embodiment of the present application; Figure 3 A path adaptation degree determination process example diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to further illustrate the technical means and effects adopted by the present application to achieve the predetermined purposes, the following will combine the drawings and preferred embodiments to specifically describe the AI matching-based integrated circuit layout modularization layout method and system according to the present application, the specific implementation, structure, features and effects thereof, in detail. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. In addition, the specific features, structures or characteristics in one or more embodiments can be combined in any suitable form.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs.

[0019] The following will specifically describe the specific scheme of the AI matching-based integrated circuit layout modularization layout method and system provided by the present application in combination with the drawings.

[0020] Please refer to Figure 1 which shows a flow chart of an AI matching-based integrated circuit layout modularization layout method provided by an embodiment of the present application, and the method comprises: S101: In response to a chip function requirement of a user, selecting a target module from a preset IC schematic diagram template library, wherein the template library contains standard schematic diagram modules classified by functions.

[0021] It's important to understand that in the field of circuit design, to comply with industry standards, common functional modules typically correspond to several mature circuit topologies. This indicates that the core functions and implementation logic of a large number of circuit modules share commonalities and reusability. Furthermore, the component models and interface parameters in the integrated circuit field have formed mature industry standards. For example, at the component level, the pin definitions and electrical characteristics of similar chips (such as LDO chips) produced by many manufacturers usually follow unified specifications. At the interface level, the pin spacing and signal timing of interfaces are clearly defined by international standards (such as the IEEE). At the same time, it can be understood that in modern IC layout design, a complete circuit system often includes multiple functional modules such as power supply, signal processing, interface communication, and control. The functional boundaries of these modules are clear, and they appear repeatedly in different projects. Therefore, from a functional perspective, common functional modules can be standardized and divided, thereby defining standard schematic diagrams.

[0022] It should be noted that the preset IC schematic template library includes at least a power module, a signal processing module, and an interface module.

[0023] For example, based on the specific circuit functions to be implemented, the system can be systematically classified as follows: Power supply module: responsible for providing stable and reliable power to the entire circuit system, such as linear regulated power supply module (LDO), switching power supply module (Buck / Boost), and isolated power supply module; Signal processing module: responsible for processing input signals by acquisition, amplification, filtering, calculation, and conversion, such as high-frequency signal amplification module (100MHz-1GHz) and differential signal filtering module (RC / LC filtering); Interface module: realizes data interaction between the circuit and external devices, such as USB 3.0 interface module and Ethernet interface module.

[0024] It should be noted that each standard schematic module not only contains abstract circuit symbol connections, but also relates to specific component composition, component parameters (such as resistance values, capacitance values, etc.), and optional typical layout constraint suggestions (such as matching requirements or shielding requirements for sensitive analog components).

[0025] To collect users' chip function requirements, the system can provide a requirement input interface. The interface provides a natural language description input box, and to avoid the ambiguity of natural language descriptions, it also provides a structured parameter form. Users need to fill in the key performance constraints corresponding to the functions. The form content corresponds one-to-one with the parameter specifications of the modules in the template library. Then, after receiving the natural language input and form information from the user, the system converts the input information into machine-recognizable structured data, thereby extracting circuit function keywords and performance constraints.

[0026] It should be noted that extracting circuit function keywords and performance constraints from structured data is a technique well-known to those skilled in the art, and will not be elaborated upon in this embodiment.

[0027] In this embodiment, the circuit function keywords and performance constraints in the user's chip function requirements are parsed; based on the circuit function keywords, one or more candidate modules are matched from the preset IC schematic template library; and the target module that meets the performance constraints is selected from the candidate modules.

[0028] It should be noted that the performance constraints include at least one of the following: power consumption, bandwidth, signal-to-noise ratio, or interface protocol type.

[0029] For example, if a user inputs "I need a host interface controller that supports the USB 3.0 protocol and has a power consumption of less than 500mW", the system will parse out the chip function keyword "USB 3.0 Host" and the performance constraint "power consumption less than 500mW".

[0030] S102: Convert the target module to the IC layout area, generate the initial circuit layout, extract the external rectangle and internal pins of each target module; determine the initial coordinates of the interface points of each target module according to the shortest physical path from the internal pins of each module to its corresponding external rectangle, and set the displacement range for each interface point.

[0031] It's important to understand that the core of generating the initial circuit layout is to transform the abstract schematic module (composed of component connections) into a physical layout. To avoid module malfunctions and to reserve space for subsequent routing, the following two aspects need to be considered during the conversion process: First, electrical functional consistency: the converted IC layout must maintain the internal electrical connections of the module (such as the series / parallel connection of resistors and capacitors); second, the placement of components must meet the basic specifications of IC design.

[0032] It should be noted that circuit layout refers to the circuit board diagram of an IC chip.

[0033] In this embodiment, for each target module, the components within the target module are initially arranged in the IC layout area according to their relative positions in the standard schematic module; the layout of the components inside the target module is adjusted according to the preset component spacing rules, and the outer rectangle of the target module is determined; according to the preset layout priority, the initial placement position of each target module in the IC layout area is determined, wherein the preset layout priority includes prioritizing the placement of target modules with special position requirements, and sorting target modules without special position requirements according to the area of ​​their outer rectangle from largest to smallest, and then randomly distributing them in the IC layout area.

[0034] To accurately achieve the physical mapping of components within the module, as an example, the 3D package models of all components within the module are first retrieved. Then, according to the connection relationships of the components in the module schematic (e.g., the VIN pin of the LDO chip is connected to the input capacitor, and the VOUT pin is connected to the output capacitor), the relative positions of the components are restored in the subspace of the IC layout area. Finally, the positions of the components are fine-tuned according to the preset component spacing rules.

[0035] The 3D packaging model includes length, width, height dimensions and pin locations.

[0036] It should be noted that the preset component spacing rules are based on industry-standard IC design specifications and module characteristics, and include built-in differentiated spacing rules. For example, the spacing between a 0402 package resistor and an adjacent capacitor is not less than 200μm, the minimum spacing between ordinary components (resistors and capacitors) is not less than 200μm, and the spacing between high-voltage pins (such as 220V input) and low-voltage pins (such as 5V output) in the power module is not less than 2000μm to prevent breakdown and discharge.

[0037] The circumscribed rectangle is a key geometric feature that describes the physical boundary of a module.

[0038] To clearly extract the circumscribed rectangle of the target module, as an example, the outermost edge of all components within the module is used as the reference. The minimum X-axis coordinate (left boundary), maximum X-axis coordinate (right boundary), minimum Y-axis coordinate (lower boundary), and maximum Y-axis coordinate (upper boundary) are taken. In addition, a preset margin (e.g., 500μm~1000μm) is extended outward based on the calculated boundary to reserve wiring and heat dissipation space for the entire module. The final determined circumscribed rectangle is stored in the form of "lower left corner coordinate (X1, Y1), upper right corner coordinate (X2, Y2)". At the same time, the area of ​​the circumscribed rectangle ((X2-X1)×(Y2-Y1)) and the geometric center ((X1+X2)÷2, (Y1+Y2)÷2) are calculated as the core reference parameters for subsequent module placement.

[0039] Because some modules need to be fixed in specific areas of the IC due to their functional characteristics, such as interface modules and RF modules needing to be kept away from digital circuit modules, and high-power devices needing to be placed in the corresponding areas of the IC chip's pads or bonding areas, it is necessary to set layout priorities in order to avoid chaotic stacking and ensure the rationality of the layout and the feasibility of subsequent routing.

[0040] It should be noted that the specific requirements for the preset layout priority are determined based on the actual situation of the relevant industry and prior knowledge. This embodiment does not impose specific limitations. For example, the interface module should be close to the I / O pad area of ​​the IC chip.

[0041] It is understandable that large-sized modules usually have high space requirements, and placing them first can prevent them from being squeezed out by smaller modules later, making them impossible to place.

[0042] In this embodiment, to ensure the comparability of the position parameters of all modules, coordinate calibration is performed based on a unified coordinate system of the IC layout area (usually with the lower left corner of the layout area as the origin).

[0043] In this embodiment, after the initial placement of all target modules is completed, overlap detection between target modules is performed; if overlap of the outer rectangles is detected, the overlapping target modules are moved a preset distance in the opposite direction of the overlap until the outer rectangles of all target modules no longer overlap.

[0044] It should be noted that the overlap detection between target modules can be performed by comparing target modules in pairs.

[0045] The opposite direction of overlap refers to the direction of movement that minimizes the overlapping area. It is determined based on the coordinate characteristics of the overlapping area. For example, if target module A and target module B have an overlapping area, and the overlap length in the X-axis direction is greater than the overlap length in the Y-axis direction, it means that the main overlap is in the horizontal direction. In this case, the opposite direction of overlap is the "left-right direction".

[0046] It should be noted that the specific value of the preset distance is dynamically adjusted according to the actual size of the module. This embodiment does not impose a specific limit. For example, a larger distance is used for large-sized target modules and a smaller distance is used for small-sized target modules, usually 500μm~2000μm.

[0047] In this embodiment, when multiple target modules overlap, they are processed in descending order of overlap area: the module pair with the largest overlap area is processed first (for example, target module A and target module B have an overlap area of ​​1000 μm). 2 The overlap area between target module B and target module C is 500 μm. 2 If so, first process target module A and target module B); after each set of overlaps is eliminated, re-detect the positional relationship between all modules to avoid new overlaps caused by moving a certain module (e.g., after moving target module B to eliminate the overlap with target module A, it is necessary to check whether target module B still overlaps with target module C).

[0048] Internal pins of a module are the physical endpoints used by internal components of the target module to achieve electrical connections. They are the intrinsic interfaces of the module's own functions. Internal pins correspond to the physical pads or connection points of the components, have clear physical coordinates, and are directly related to the electrical functions of the module. According to signal type, they can be divided into: power supply pins (such as VCC, VDD): supply power to the module; ground pins (GND): provide circuit reference ground; signal input / output pins (such as SIG_IN, SIG_OUT): transmit data or control signals; differential pair pins (such as DIFF_P, DIFF_N): transmit high-frequency differential signals and must maintain symmetry.

[0049] An interface point is an external interaction point set on the outer rectangle of a module to achieve electrical connection between different modules. It is the external interface between internal pins and external modules. The interface point corresponds one-to-one with the internal pin and inherits its function type (for example, power pins correspond to power interface points, and differential pair pins correspond to differential interface point pairs).

[0050] It should be noted that the same-source interface points of different modules (such as the "VDD output interface point" of target module A and the "VDD input interface point" of target module B) need to be connected by wiring to form a complete circuit; for differential pair interface points, the spacing between the two interface points should be proportional to the spacing of the internal differential pins to ensure signal integrity.

[0051] The process of determining the initial coordinates of each target module interface point is as follows: Figure 2 As shown, it includes: S102-1: Establish a two-dimensional coordinate system with the geometric center of the bounding rectangle of the target module as the origin.

[0052] To ensure uniform position and orientation, a local two-dimensional coordinate system (i.e., a two-dimensional coordinate system) is established with the geometric center as the origin, and its orientation is consistent with the global coordinate system of the IC.

[0053] S102-2: Extract the physical coordinates of the internal pins of each module, calculate the vertical distance from each internal pin to the four sides of the outer rectangle, and filter out the target side corresponding to the shortest vertical distance.

[0054] It is understood that the specific method for calculating the vertical distance is an existing technical means, and will not be described in detail in this embodiment.

[0055] For example, the vertical distances from pin P to the four sides are 2000μm (left boundary of the outer rectangle), 18000μm (right boundary of the outer rectangle), 7000μm (lower boundary of the outer rectangle), and 3000μm (upper boundary of the outer rectangle), respectively. The shortest vertical distance is 2000μm, which corresponds to the left boundary of the target side.

[0056] S102-3: The intersection of the target edge and the shortest vertical distance direction is used as the interface point of the corresponding internal pin, and the initial coordinates of the interface point are recorded.

[0057] The obtained interface point coordinates are recorded in the system, and a one-to-one mapping relationship with the corresponding internal pins is established.

[0058] It is important to understand that in integrated circuit design, not all internal pins of a module appear in pairs. Therefore, the internal pins of a module include input pins, output pins, power supply pins, and ground pins. Differential signal pins and functionally related input / output pins exist in pairs, while power supply pins, ground pins, and some control pins are single-ended.

[0059] Input pins receive signals from external modules or devices and transmit them to the internal circuitry of the module for processing; output pins transmit signals processed by the internal circuitry of the module (such as amplified signals or converted digital signals) to external modules; power pins receive electrical energy from external power sources and provide operating voltage for the internal components of the module; ground pins serve as a potential reference point for the circuit, guiding the current loop within the module and suppressing electromagnetic interference.

[0060] Differential signal pins consist of a pair of positive and negative (N) pins, which transmit differential signals with equal amplitude and opposite polarity, and are suitable for high-frequency and high-speed signal scenarios.

[0061] Functionally associated input / output pins refer to the fixed functional pairing of the output pin of one module with the input pin of another module. For example, the "transmit pin" of the UART communication module needs to be paired with the "receive pin" of the MCU module.

[0062] In this embodiment, if there are multiple internal pins in the target module, the initial coordinates of the interface points corresponding to each pin are determined in order of pin type priority. The pin type priority from high to low is as follows: paired differential pins, functionally associated input / output pin pairs, single-ended signal pins, power supply pins, and ground pins. For paired pins, when determining the initial coordinates of the interface points, the relative position relationship of the two interface points corresponding to a pair of pins on the target edge must be kept consistent with the relative position relationship of the pins inside the module, and the two corresponding interface points are preferably located on the same target edge.

[0063] It is important to understand that if the interface point position is completely fixed, subsequent adjustments to the module position, orientation, or optimization of interconnection paths may result in excessive path detours due to incompatibility of the interface points (e.g., long-distance wiring is required due to misalignment of the interface points of two modules), or spatial conflicts with other modules. If the displacement range is unlimited, it may cause the interface point to detach from the module's external rectangle, or damage the electrical connection logic between the internal pins and the interface point (e.g., excessive displacement may cause the internal wiring impedance to exceed the standard). Therefore, the displacement range must be strictly constrained within a reasonable range that does not affect the module's own function and supports subsequent optimization.

[0064] It should be noted that the specific range of displacement is determined based on the actual situation, and this embodiment does not impose a specific limitation. For example, the interface point must always be located on the four sides of the outer rectangle of the module. Therefore, the displacement range perpendicular to the side of the rectangle is 0 (i.e., movement along this direction is prohibited), and movement is only allowed along the length of the rectangle's side. Different functional pins have different requirements for displacement range, and the maximum allowable offset of horizontal displacement needs to be set in combination with factors such as signal characteristics and power supply stability (for example, for differential pair pins: the spacing between a pair of interface points must be consistent with the spacing between the internal differential pins). There may be multiple interface points on the same outer rectangle side. In order to avoid interface point position conflicts during optimization, it is necessary to ensure that the displacement ranges of each interface point do not overlap. This can be achieved by setting a safety distance (for example, when setting the displacement range of each interface point, a safety distance of at least 200μm must be reserved). Generally speaking, the displacement range needs to be reset according to the IC manufacturing process (such as minimum line width / spacing). For example, the displacement range can be set to 1500-2500μm.

[0065] For high-frequency signal pins, based on the principle of avoiding signal delay and interference, the displacement range should not exceed 1 / 50 of the wavelength (wavelength = speed of light ÷ signal frequency), which is a standard value in the industry to ensure signal integrity.

[0066] S103: Obtain the matching interface point combinations and actual connection paths between interconnected target modules; determine the theoretical shortest path based on the displacement range of each interface point combination; determine the path adaptability based on the actual connection path and the theoretical shortest path; and determine the overall layout adaptability based on the distribution density characteristics of each actual connection path.

[0067] Interconnect target modules are two or more independent functional modules in a circuit system that need to be interconnected through interface points to achieve signal, power, or ground communication. For example, a power supply module (outputting "5V voltage") and an MCU module (requiring "inputting 5V voltage") are interconnect target modules. Interconnect target modules are complementary in function, each with a clearly defined external rectangle, and their internal pins and interface points belong to their respective target modules and are not confused with other target modules.

[0068] Matching interface point combinations refers to selecting interface point pairs or combinations from all interface points of two interconnected target modules that meet the requirements of functional compatibility, electrical adaptation, and physical feasibility. For example, the 5V output interface point of the power supply module must match the 5V input interface point of the MCU module.

[0069] It should be noted that a pair of interconnected target modules may correspond to multiple sets of matching interface point combinations, while a set of matching interface point combinations can only correspond to a pair of interconnected target modules.

[0070] It is important to understand that traditional methods typically treat circuit block diagrams as fixed modules with fixed input and output interface points. This leads to increased wiring costs and lengths during modular layout as the wiring must accommodate these fixed input and output interface points. Furthermore, due to the complexity of connections between different modules—that is, one module connecting to multiple other modules—fixed input and output interface points can cause conflicts between the connections of multiple modules, resulting in complex module layout and wiring, and adding to costs.

[0071] The path adaptability determination process is as follows: Figure 3 As shown, it includes: S103-1: For each pair of interface points of the interconnected target module, the sampling step size is dynamically adjusted according to the signal type within their respective displacement range to generate discrete coordinate sampling points, wherein the sampling step size of high-frequency signals is smaller than that of low-frequency signals.

[0072] The sampling step size refers to the distance between two adjacent sampling points within the displacement range of the interface point.

[0073] Since different signals are extremely sensitive to path length and symmetry, in practical scenarios, the higher the signal frequency, the smaller the sampling step size. Therefore, the specific value of the sampling step size is dynamically adjusted according to the signal type. This embodiment does not impose specific limitations. For example, for high-frequency signals (such as radio frequency signals and high-speed differential signals greater than 1GHz), a small sampling step size is required, usually 50μm~200μm; for medium-frequency signals (such as digital signals of 100MHz~1GHz): the sensitivity is moderate, and the sampling step size is set to 200μm~500μm; for low-frequency signals, the tolerance for position deviation is high, and the sampling step size can be set to 500μm~1000μm.

[0074] It should be noted that the differential pair interface point combination must maintain a fixed spacing (e.g., 200μm) and symmetry. Therefore, during sampling, the points must move synchronously while maintaining a constant spacing.

[0075] For example, if the differential pair DIFF_P and DIFF_N have a displacement range Y∈[1500μm, 2500μm], a sampling step size of 100μm, and a fixed spacing of 200μm, then the sampling points of DIFF_P are 1500μm, 1600μm, ..., 2500μm, and the synchronous sampling points of DIFF_N are 1700μm, 1800μm, ..., 2700μm, generating a total of 11 pairs of differential sampling points.

[0076] S103-2: Calculate the Euclidean distance between each pair of sampling points, and select the minimum distance value among all pairs of sampling points; determine the straight path corresponding to the minimum distance as the theoretical shortest path.

[0077] It should be noted that Euclidean distance is an existing technical method, and will not be described in detail in this embodiment.

[0078] S103-3: Calculate the ratio of the theoretical shortest path length to the physical length of the actual connecting path, and correct this ratio in combination with the number of turns in the actual connecting path to obtain the path fit. The number of turns in the actual connecting path is determined based on the number of times the line segment direction changes in the actual connecting path.

[0079] It is important to understand that in actual circuit design, the combination of interface points cannot always be connected according to the ideal plan. The actual connection path will detour to avoid other modules, making the actual wiring more complex. However, in order to provide a reliable optimization target for the actual connection path, we can analyze the optimal solution path within the displacement range of the interface points to the greatest extent.

[0080] It should be noted that, under actual working conditions, the theoretical shortest path length is not greater than the physical length of the actual connection path. Therefore, the ratio of the physical length of the actual connection path to the theoretical shortest path length is not greater than 1. Thus, the closer the ratio of the physical length of the actual connection path to the theoretical shortest path length is to 1, the closer the actual connection path length is to the theoretical shortest path length, and the higher the physical optimization degree.

[0081] It should be noted that, in actual working conditions, even under ideal circumstances, modules cannot be adjacent to each other at zero distance in order to ensure safety and the normal operation of the circuit system. Therefore, the theoretical shortest path length cannot be zero.

[0082] A turning point is a node in the actual connection path where the direction of a line segment changes. Generally speaking, a change in direction of not less than 45° is considered a turning point (fine-tuning with an angle less than 45° is not counted).

[0083] Since the number of corners reflects the wiring complexity of the actual connection path, the more corners there are, the greater the signal transmission loss. Therefore, the larger the number of corners, the smaller the correction coefficient. Assuming the number of corners is represented by K, the correction formula can be expressed as: C=1÷(1+0.05×K), where C represents the correction coefficient.

[0084] It's important to understand that a higher path fit indicates a shorter actual connection path with fewer turns, making it closer to the theoretical shortest path, and thus a higher path fit.

[0085] It is important to understand that in modular interconnection design, focusing only on the merits of a single connection path (such as the high adaptability of a certain path) may lead to the problem of "local rationality but overall chaos" (for example, each path selects the shortest path, but all paths are clustered in the same area, resulting in overheating or interference). Therefore, it is also possible to control the design quality from a "global perspective".

[0086] In this embodiment, the IC layout area is divided into equal-area grid cells using a grid partitioning method. The number of intersections of the actual connection paths within each grid cell is counted. Grid cells with more than a preset threshold number of intersections are marked as congested areas. The ratio of the total area of ​​the congested areas to the total area of ​​the IC layout area is calculated as the congestion coefficient. The difference between the positive integer 1 and the congestion coefficient is calculated as the first difference. Preset weights are assigned according to the importance of the signals carried by the paths, and the weighted average of the path adaptability of all interface point combinations is calculated as the average adaptability. The weight assigned to high-frequency signal paths is higher than that assigned to low-frequency signals. Based on the preset weight coefficients, the average adaptability and the first difference are weighted and fused to obtain the overall layout adaptability.

[0087] To ensure reasonable connection paths between modules (no signal loss, low latency) and to avoid excessive congestion in local areas (affecting production, heat dissipation, and signal interference), since ICs are planar areas, a grid partitioning method can be used. This involves dividing the IC layout area into equal-area grid cells, thereby avoiding subjective errors caused by judging congested areas based on experience.

[0088] It should be noted that the grid division method is an existing technical means, and will not be described in detail in this embodiment. For example, a 10×10 grid division is used.

[0089] The number of intersections refers to the number of intersections between all actual connection paths (i.e., actual wires and transmission lines on the IC layout area) within an equal-area grid cell. An intersection refers to different paths meeting in the same plane without being conductive. Intersections of layered wiring are not included.

[0090] It should be noted that the specific value of the preset threshold for the number of intersections is determined according to the actual situation, and this embodiment does not impose a specific limitation. For example, based on the IC design specifications, signal type, and manufacturing process, the preset threshold for the number of intersections can be set to 4.

[0091] It should be noted that when laying out the target module, the IC layout area cannot be zero.

[0092] It is important to understand that the smaller the total area of ​​the congested area, the more reasonable the space utilization of the IC layout and the fewer the congested areas, which is more beneficial to signal transmission (reducing interference) and production assembly (avoiding wiring overlap).

[0093] It is important to understand that different signals have different requirements for path rationality. Therefore, preset weights need to be assigned to paths of different signal types. For example, high-frequency signals (such as radio frequency signals and high-speed digital signals) are more sensitive to path length (affecting delay) and turning angles (affecting signal reflection), and are assigned higher weights (e.g., weight = 0.8); low-frequency signals (such as power signals and low-speed control signals) have lower requirements for path rationality and are assigned lower weights (e.g., weight = 0.2). The total weights must satisfy the condition that the sum of the weight percentages of all signal types equals 1. The specific values ​​need to be determined based on the core functions of the IC. For example, communication ICs have higher weights for high-frequency signals, while power ICs have higher weights for power signals.

[0094] It is important to understand that the higher the average fit, the more reasonable the path of important signals on the IC, and the better the overall signal transmission quality.

[0095] It should be noted that the specific values ​​of the preset weight coefficients are determined according to actual needs, and this embodiment does not impose specific limitations. For example, if the core requirement of the IC is "signal quality" (such as a communication device IC), then the weight of the average fit is greater than the weight of the first difference, so the weight of the average fit can be 0.7 and the weight of the first difference can be 0.3; if the core requirement of the IC is "miniaturization and high space utilization" (such as a wearable device IC), then the weight of the first difference is greater than the weight of the average fit, so the weight of the average fit can be 0.4 and the weight of the first difference can be 0.6.

[0096] The greater the overall layout adaptability, the better the IC's "path rationality" and "space utilization" performance, and the more the layout adapts to the design requirements.

[0097] S104: With overall layout fitness as the optimization objective, the position, orientation and interface point position of the target module are iteratively optimized through a genetic algorithm until the overall layout fitness converges, and the optimized circuit layout is output.

[0098] It's important to understand that IC layout optimization is essentially a global optimal solution search problem under multiple constraints—it needs to simultaneously satisfy the goals of high path adaptability, few congested areas, and compliant module positions, and there is coupling between parameters (for example, the rotation angle of a module affects the position of interface points, thus changing the path length). Furthermore, since genetic algorithms involve a complete process of "chromosome encoding - population iteration - convergence determination - result decoding," they can efficiently search for the global optimal solution in a complex parameter space by simulating the "selection-crossover-mutation" mechanism of biological evolution, avoiding getting trapped in local optima (such as adjusting the position of a single module causing congestion in other areas). Therefore, genetic algorithms are chosen as the technical means for IC layout optimization.

[0099] In this embodiment, the position coordinates of the target module, the preset rotation angle, and the coordinate offsets of each interface point within its displacement range are collectively encoded into chromosome units of the genetic algorithm to form an initial population. Using overall layout fitness as the evaluation function, selection, crossover, and mutation operations are performed on the initial population. The highest overall layout fitness of the population after each iteration is recorded. When the change in the highest overall layout fitness is less than a preset threshold during a preset number of consecutive iterations, the overall layout fitness is determined to have converged, and the iteration stops. The chromosome with the highest overall layout fitness is selected from the converged population, and the corresponding target module position coordinates, rotation angle, and final coordinate parameters of the interface points are decoded. Based on these parameters, the module layout and interface point connection relationships are updated, generating and outputting the optimized circuit layout.

[0100] It should be noted that the specific process of the genetic algorithm is a technical means well known to those skilled in the art, and will not be described in detail in this embodiment.

[0101] It should be noted that the selection operation retains chromosomes with high overall layout adaptability, the crossover operation generates new individuals by exchanging the module positions or interface point coordinate offsets in different chromosomes, and the mutation operation randomly adjusts the module orientation or interface point coordinates of some chromosomes.

[0102] The position coordinates of the target module refer to the position coordinates of the geometric center of the target module on the entire IC layout plane. In order to ensure the consistency of the layout of all modules, a unified global coordinate system can be used, such as using the unified coordinate system of the IC layout area as a reference (usually with the lower left corner of the layout area as the origin) for coordinate calibration.

[0103] It should be noted that the specific value of the preset rotation angle is determined according to the actual situation. This embodiment does not impose a specific limitation. For example, the preset rotation angle is set according to the type, package form and design requirements of the module in the IC layout area. For most modules in the general IC layout area, the two angles of 0° and 90° are preferred.

[0104] To avoid invalid iterations (such as when the overall layout fitness no longer improves), a convergence condition needs to be set. The iteration stops when this condition is met. The convergence condition includes a preset number of iterations and a preset threshold. As an example, after each iteration, the highest overall layout fitness of the current population (i.e., the overall layout fitness of the optimal layout scheme for that generation) is recorded. A preset number of iterations K (usually 10-30; a larger K results in higher precision but also higher computational cost) and a preset threshold ε for the fitness change range are set (usually 0.001-0.01, e.g., ε=0.005). If, in K consecutive iterations, the difference between the highest overall layout fitness of two adjacent iterations is less than ε (e.g., 0.85 in generation 10, 0.852 in generation 11, and 0.853 in generation 12, with three consecutive differences less than 0.005), the algorithm is considered converged, and the iteration stops.

[0105] It should be noted that if the iteration count reaches the preset maximum number (e.g., 200 generations) and convergence is still not achieved, the iteration should also be stopped to avoid wasting computational resources.

[0106] S105: Input the optimized circuit layout into the pre-trained AI engine, perform detailed optimization and verification according to IC design rules and electrical rules, and output the final circuit layout that can be used for manufacturing.

[0107] It is important to understand that the "actual connection path" output by the genetic algorithm may have the problem of being "theoretically feasible but not feasible in manufacturing / performance". Alternatively, although the genetic algorithm ensures that the external rectangle of the module does not overlap, there may be the problem of "local spatial conflict" (such as the connector pin being too close to the adjacent capacitor). Or, the genetic algorithm focuses on "path length optimization" and may ignore the "integrity" of the grounding network. Therefore, the AI ​​engine can be trained through existing IC design rules and electrical rules to further optimize and verify the circuit layout.

[0108] It should be noted that the specific content of IC design rules and electrical rules is well known to those skilled in the art and is determined according to actual needs. This embodiment does not impose specific limitations. For example, circuit design geometric rules include: line width not less than the minimum process line width, line spacing not less than the minimum process spacing, and via diameter / pad size matching the package, etc.; circuit design layout rules include: component spacing not less than the minimum assembly gap, and the distance between the solder pad / pad and the chip edge must meet IC manufacturing specifications.

[0109] The AI-matched modular layout system for integrated circuits includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the steps of the AI-matched modular layout method for integrated circuits.

[0110] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0111] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

Claims

1. An AI matching-based integrated circuit layout modularization method, characterized in that, The method comprises: selecting a target module from a preset IC schematic template library in response to a user's chip function requirement, wherein the template library contains standard schematic modules classified by function; converting the target module to an IC layout area to generate an initial circuit layout, extracting the bounding rectangle of each target module and the internal pins of the module; determining the initial coordinates of the interface points of each target module according to the shortest physical path from the internal pins of each module to the bounding rectangle to which they belong, and setting a displaceable range for each interface point; obtaining the matching interface point combination and the actual connection path between the interconnected target modules, determining the theoretically shortest path according to the displaceable range of each interface point in the interface point combination; determining the path adaptation degree according to the actual connection path and the theoretically shortest path; and determining the overall layout adaptation degree in combination with the distribution density characteristics of each actual connection path; taking the overall layout adaptation degree as the optimization target, iteratively optimizing the position, direction and interface point position of the target module through a genetic algorithm until the overall layout adaptation degree converges, and outputting the optimized circuit layout; inputting the optimized circuit layout into a pre-trained AI engine to perform detail optimization and verification according to IC design rules and electrical rules, and outputting a final circuit layout that can be used for manufacturing.

2. The AI matching-based integrated circuit layout modularization method of claim 1, wherein, The method further comprises: analyzing the circuit function keywords and performance constraint conditions in the user's chip function requirement, wherein the performance constraint conditions include at least one of power consumption, bandwidth, signal-to-noise ratio or interface protocol type; based on the circuit function keywords, matching one or more candidate modules required from the preset IC schematic template library, wherein the preset IC schematic template library at least includes power modules, signal processing modules and interface modules; screening target modules that meet the performance constraint conditions from the candidate modules.

3. The AI matching-based integrated circuit layout modularization method of claim 2, wherein, The method further comprises: for each target module, initially arranging the components in the target module in the IC layout area according to the relative positions of the components in the standard schematic module; adjusting the layout of the internal components of the target module according to the preset component spacing rules, and determining the bounding rectangle of the target module; determining the initial placement position of each target module in the IC layout area according to the preset layout priority, wherein the preset layout priority includes preferential placement of target modules with special position requirements, sorting of target modules without special position requirements according to the area of the bounding rectangle from large to small, and random distribution placement in the IC layout area.

4. The AI matching-based integrated circuit layout modularization method of claim 3, wherein, The method further comprises: after completing the initial placement of all target modules, performing overlap detection between the target modules; if it is detected that the bounding rectangles overlap, moving the overlapping target modules in the opposite direction of the overlap by a preset distance until there is no overlap between the bounding rectangles of all target modules.

5. The AI matching-based integrated circuit layout modularization method of claim 1, wherein, The method further comprises: establishing a two-dimensional coordinate system with the geometric center of the bounding rectangle of the target module as the origin; The physical coordinates of the internal pins of each module are extracted, the vertical distances of each internal pin to the four sides of the circumscribed rectangle are calculated, and the target side corresponding to the shortest vertical distance is screened out; The intersection point of the target side and the direction of the shortest vertical distance is taken as the interface point of the corresponding internal pin, and the initial coordinates of the interface point are recorded.

6. The AI matching-based integrated circuit layout modularization method of claim 5, wherein, The internal pins of the module include input pins, output pins, power pins and ground pins, wherein the differential signal pins and the functionally associated input and output pins exist in pairs, the power pins, the ground pins and part of the control pins are in single-ended form, and the initial coordinates of the interface points are determined, including: If there are multiple internal pins in the target module, the initial coordinates of the interface points corresponding to each pin are determined in order according to the pin type priority, and the pin type priority from high to low is as follows: paired differential pair pins, functionally associated input and output pin pairs, single-ended signal pins, power pins and ground pins; For the pins in paired form, when determining the initial coordinates of the interface points, the relative positional relationship of the two interface points corresponding to a pair of pins on the target side should be consistent with the relative positional relationship of the internal pins in the module, and the two interface points should be located on the same target side.

7. The AI matching-based integrated circuit layout modularization method of claim 1, wherein, The path adaptation degree determination process includes: For each pair of interface point combinations of the interconnected target module, the sampling step is dynamically adjusted according to the signal type within the respective displaceable range to generate discrete coordinate sampling points, wherein the sampling step of high-frequency signals is smaller than that of low-frequency signals; The Euclidean distance between each pair of sampling points is calculated, and the minimum distance value among all pairs of sampling points is screened out; the straight line path corresponding to the minimum distance is determined as the theoretical shortest path; The ratio of the length of the theoretical shortest path to the physical length of the actual connection path is calculated, and the ratio is corrected in combination with the number of corners of the actual connection path to obtain the path adaptation degree, wherein the number of corners of the actual connection path is determined based on the number of times of direction change of the line segments in the actual connection path.

8. The AI matching-based integrated circuit layout modularization method of claim 7, wherein, The overall layout adaptability is determined in combination with the distribution density characteristics of each actual connection path, including: The IC layout area is divided into equal-area grid cells using the grid division method, and the number of intersection points of the actual connection paths in each grid cell is counted; Grid cells with a number of intersection points exceeding a preset intersection point number threshold are marked as crowded areas, the ratio of the total area of the crowded areas to the total area of the IC layout area is calculated as a crowded coefficient, and the difference between the positive integer 1 and the crowded coefficient is calculated as a first difference value; The preset weight corresponding to the importance of the signal carried by the path is allocated, the weighted average value of the path adaptation degrees of all interface point combinations is calculated as the average adaptation degree, wherein the weight allocated to the high-frequency signal path is higher than the weight allocated to the low-frequency signal path; The average adaptation degree and the first difference value are weighted and fused based on a preset weight coefficient to obtain the overall layout adaptability.

9. The AI matching based integrated circuit layout modularization method of claim 1, wherein, Taking the overall layout adaptability as the optimization target, the position, direction and interface point position of the target module are iteratively optimized by the genetic algorithm until the overall layout adaptability converges, and the optimized circuit layout is output, including: The position coordinates of the target module, the preset rotation angle, and the coordinate offset of each interface point in the displaceable range thereof are collectively encoded as chromosome units of the genetic algorithm to form an initial population; The selection, crossover, and mutation operations are performed on the initial population with the overall layout fitness as the evaluation function; The highest overall layout fitness of the population after each iteration is recorded, and when the change amplitude of the highest overall layout fitness in a preset number of continuous iterations is less than a preset threshold, it is determined that the overall layout fitness converges, and the iteration is stopped; The chromosome with the highest overall layout fitness is selected from the population at the time of convergence, and the corresponding target module position coordinates, rotation angle, and final coordinate parameters of the interface points are decoded to update the module layout and the interface point connection relationship, and the optimized circuit layout is generated and output.

10. An AI matching based integrated circuit layout modular placement system, comprising: The system comprises a memory, a processor, and a computer program stored in the memory and running on the processor, and the processor implements the steps of the method according to any one of claims 1-9 when executing the computer program. The system comprises a memory, a processor, and a computer program stored in the memory and running on the processor, and the processor implements the steps of the method according to any one of claims 1-9 when executing the computer program.

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