Interface circuit module and server motherboard

Abstract

The application discloses an interface circuit module and a server mainboard, and relates to the technical field of circuit boards. The interface circuit module comprises a connector pad group, a plurality of input signal hole groups and a plurality of output signal hole groups. The plurality of input signal hole groups are electrically connected with the connector pad group, and the plurality of output signal hole groups are electrically connected with the connector pad group. The plurality of input signal hole groups are arranged on a first side of the connector pad group, and the plurality of output signal hole groups are arranged on a second side of the connector pad group. The first side and the second side are arranged on opposite sides of the connector pad group. Through the application, the technical problem of wiring difficulty of the circuit board provided with the interface circuit module in the related art is solved, and the technical effect of reducing the wiring difficulty of the circuit board provided with the interface circuit module is achieved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of circuit boards, in particular to an interface circuit module and a server mainboard. BACKGROUND

[0002] With the continuous development of electronic technology, the isolated form of the circuit board is less and less, and the interface circuit module gradually becomes an indispensable part of the circuit board. The circuit board can be connected with other circuit boards or other circuit components through the connector welded by the interface circuit module and the cable connected by the connector. However, the non-standard interface circuit template will make the wiring of the circuit board where the interface circuit module is located very difficult. SUMMARY

[0003] The application provides an interface circuit module and a server mainboard to at least solve the problem of difficult wiring of the circuit board provided with the interface circuit module in the related art.

[0004] The application provides an interface circuit module, which comprises a connector pad group, a plurality of input signal hole groups and a plurality of output signal hole groups. The plurality of input signal hole groups are electrically connected with the connector pad group, and the plurality of output signal hole groups are electrically connected with the connector pad group. The plurality of input signal hole groups are arranged on a first side of the connector pad group, and the plurality of output signal hole groups are arranged on a second side of the connector pad group. The first side and the second side are arranged on opposite sides of the connector pad group, respectively.

[0005] The application also provides a server mainboard, which comprises at least one processor pad group and at least one interface circuit module as described above. The interface circuit module is electrically connected with the processor pad group.

[0006] According to the application, the interface circuit module comprises a connector pad group, a plurality of input signal hole groups and a plurality of output signal hole groups. The plurality of input signal hole groups are electrically connected with the connector pad group, and the plurality of output signal hole groups are electrically connected with the connector pad group. The plurality of input signal hole groups are arranged on a first side of the connector pad group, and the plurality of output signal hole groups are arranged on a second side of the connector pad group. The first side and the second side are arranged on opposite sides of the connector pad group, respectively. Through such an arrangement, the wiring of the signal hole groups on both sides of the connector pad group is naturally separated, and it is not necessary to repeatedly wind and punch to avoid, thereby reducing the risk of layout congestion and dead lines. Therefore, the technical problem of difficult wiring of the circuit board provided with the interface circuit module in the related art can be solved, and the technical effect of reducing the wiring difficulty of the circuit board provided with the interface circuit module is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. Based on these drawings, other drawings can be obtained by those skilled in the art without any creative effort.

[0008] Figure 1 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 1 ;

[0009] Figure 2 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 2 ;

[0010] Figure 3 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 3 ;

[0011] Figure 4 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 4 ;

[0012] Figure 5 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 5 ;

[0013] Figure 6 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 6 ;

[0014] Figure 7 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 7 ;

[0015] Figure 8 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 8 ;

[0016] Figure 9 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 9 ;

[0017] Figure 10 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 10 ;

[0018] Figure 11 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 10 ;

[0019] Figure 12 is a partial enlarged view of Figure 11 ;

[0020] Figure 13This is a schematic diagram of the interface circuit module according to an embodiment of this application. Figure 10 two;

[0021] Figure 14 This is a schematic diagram of the interface circuit module according to an embodiment of this application. Figure 10 three;

[0022] Figure 15 This is a schematic diagram of the interface circuit module according to an embodiment of this application. Figure 10 Four;

[0023] Figure 16 This is a schematic diagram of the interface circuit module according to an embodiment of this application. Figure 10 five;

[0024] Figure 17 This is a schematic diagram of the interface circuit module according to an embodiment of this application. Figure 10 six;

[0025] Figure 18 This is a schematic diagram of the interface circuit module according to an embodiment of this application. Figure 10 seven;

[0026] Figure 19 yes Figure 18 Local magnification Figure 1 ;

[0027] Figure 20 yes Figure 18 Local magnification Figure 2 ;

[0028] Figure 21 This is a schematic diagram illustrating a method for resisting the effects of bulging according to an embodiment of this application;

[0029] Figure 22 This is a schematic diagram of a via pair according to an embodiment of this application;

[0030] Figure 23 This is a simulation diagram of a remote crosstalk according to an embodiment of this application;

[0031] Figure 24 This is a simulation diagram of near-end crosstalk according to an embodiment of this application;

[0032] Figure 25 This is a flowchart of a method for reducing plate thickness according to an embodiment of this application;

[0033] Figure 26 This is a schematic diagram of a server motherboard according to an embodiment of this application. Figure 1 ;

[0034] Figure 27 This is a schematic diagram of a server motherboard according to an embodiment of this application. Figure 2 ;

[0035] Figure 28 is a schematic diagram of a server motherboard according to an embodiment of the present application Figure 3 ;

[0036] Figure 29 is a schematic diagram of a server motherboard according to an embodiment of the present application Figure 4 ;

[0037] Figure 30 is a schematic diagram of a server motherboard according to an embodiment of the present application Figure 5 ;

[0038] Figure 31 is a flowchart of a method for determining various distances on a server motherboard according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0040] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0041] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0042] The embodiments of the present application provide an interface circuit module, which is described in detail in combination with the components of the interface circuit module.

[0043] The professional terms appearing in the present application are explained as follows:

[0044] Pad group: In the field of circuit board design, a pad group refers to a collection of metal contact points on a circuit board used to connect external components or circuits. The pads are usually made of copper or other conductive materials, and the surface may be plated with tin, silver or gold, etc. to enhance its conductivity and prevent oxidation.

[0045] Electrical Connection: Electrical Connection refers to the electrical path established between two or more circuit elements through conductors to achieve functions such as signal transmission, power supply, or data exchange. In the design and manufacturing of circuit boards, electrical connections are achieved through materials such as metal pads, vias, wires, and solder, ensuring that electronic components can effectively communicate and work as intended.

[0046] Via: Via is an indispensable component in multi-layer circuit board design, which is a kind of vertical metalized hole through different layers of circuit board to establish electrical connection between layers. Via can be divided into several types, including Through-Hole Via, Blind Via and Buried Via. Through-Hole Via is the most common type, which penetrates through all layers of the circuit board, used to connect the top and bottom layers of the circuit board, or as a point of insertion for components. Blind Via only connects the surface layer or inner layer to the nearest inner layer, while Buried Via is completely located between the inner layers of the circuit board without direct contact with the surface layer, mainly used in high-density and high-speed circuit design to reduce the length of signal path and improve the wiring efficiency of the circuit board.

[0047] Ground Via: Ground Via is a special type of via, mainly used for ground return or signal shielding in circuit board design. On the circuit board, Ground Via can connect the ground plane or ground layer with other layers on the circuit board, forming a low-impedance ground path. They are crucial for maintaining the stability of the circuit, reducing noise, and improving signal integrity. Ground Via is often distributed around signal vias or critical signal lines, forming a "ground wall" or "ground cage" to effectively isolate signal lines and avoid electromagnetic interference and crosstalk between signals.

[0048] Equal Length Matching: Equal Length Matching is mainly used to ensure that the propagation time of signals on multiple transmission paths is the same, to avoid synchronization problems caused by differences in signal arrival time, especially in parallel data transmission systems. The purpose of equal length matching is to control the physical length of signal lines and thus control the delay time of signals to achieve consistency, which is particularly critical in high-speed signal processing, computer bus, memory interface, network communication, etc.

[0049] In the embodiments of the present application, an interface circuit module is provided, Figure 1 is a schematic diagram of the interface circuit module according to the embodiments of the present application Figure 1 For example, Figure 1As shown, the interface circuit module comprises: a connector pad group, a plurality of input signal hole groups, and a plurality of output signal hole groups; wherein the plurality of input signal hole groups are electrically connected to the connector pad group, and the plurality of output signal hole groups are electrically connected to the connector pad group; wherein the plurality of input signal hole groups are arranged on a first side of the connector pad group, and the plurality of output signal hole groups are arranged on a second side of the connector pad group, and the first side and the second side are respectively arranged on opposite sides of the connector pad group.

[0050] Through the above interface circuit module, the interface circuit module comprises: a connector pad group, a plurality of input signal hole groups, and a plurality of output signal hole groups; the plurality of input signal hole groups are electrically connected to the connector pad group, and the plurality of output signal hole groups are electrically connected to the connector pad group; and the plurality of input signal hole groups are arranged on a first side of the connector pad group, and the plurality of output signal hole groups are arranged on a second side of the connector pad group, and the first side and the second side are respectively arranged on opposite sides of the connector pad group. Through such an arrangement, the signal hole groups on both sides of the connector pad group are naturally separated, and there is no need to repeatedly wind and punch to avoid, thereby reducing the risk of layout congestion and dead lines. Therefore, the technical problem of circuit board wiring difficulty caused by the arrangement of the interface circuit module in the related art can be solved, and the technical effect of reducing the wiring difficulty of the circuit board arranged with the interface circuit module can be achieved.

[0051] Optionally, in the embodiments of the present application, the connector pad group can be, but is not limited to, a set of metallized areas in the interface circuit module that are in contact with an external connector, and the connector pad group can include, but is not limited to, a plurality of connector pads, each of which is a metallized area in contact with an external connector.

[0052] Optionally, in the embodiments of the present application, the connector pad group can be, but is not limited to, used for welding a connector. Specifically, each pin of the connector can be, but is not limited to, one-to-one corresponding to each connector pad of the connector pad group, and each pin and its corresponding connector pad can be, but is not limited to, welded together by welding material (such as solder paste or solder wire) to achieve electrical connection between the connector and the connector pad group. Since intermetallic compounds are formed during the cooling and solidification of solder, the bonding force between the pin and the pad is enhanced, so that the electrical connection is achieved at the same time as the mechanical connection between the connector and the connector pad.

[0053] Optionally, in the embodiments of the present application, the specifications and types of the aforementioned connector are not limited, and can be MCIO (Mini Cool Edge Input / Output), PCIe (Peripheral Component Interconnect Express), or the like, which can be flexibly set according to actual needs.

[0054] Optionally, in the embodiments of this application, when the connector is MCIO, the interface circuit module can be, but is not limited to, regarded as a modular MCIO fanout.

[0055] Optionally, in this embodiment of the application, the aforementioned connector may, but is not limited to, be connected to the hard drive backplane or other component backplane by plugging in a cable.

[0056] Optionally, in the embodiments of this application, the number of input signal hole groups included in an interface circuit module and the number of output signal hole groups included in the interface circuit module can be the same or different, and can be selected according to the actual circuit design requirements.

[0057] Optionally, in the embodiments of this application, the input signal hole group may be, but is not limited to, a set of vias for introducing signals from an external connector from one layer of the circuit board into the internal circuit board; correspondingly, the output signal hole group may be, but is not limited to, a set of vias for leading signals from the internal circuit board to an external connector.

[0058] Optionally, in the embodiments of this application, the input signal hole group may also be, but is not limited to, a set of vias for introducing signals from the internal circuit board to the external connector. Correspondingly, the output signal hole group may also be, but is not limited to, a set of vias for leading signals from the external connector to the internal circuit board.

[0059] That is, the input signal hole group and the output signal hole group can be, but are not limited to, a set of vias with opposite signal flow directions, but the specific signal flow directions of the input signal hole group and the output signal hole group can be determined according to the actual situation.

[0060] Optionally, in the embodiments of this application, the input signal hole group can be electrically connected to the connector pad group through metal traces on the circuit board, but not limited to the metallization connection between the input signal hole group and the connector pad group.

[0061] Optionally, in the embodiments of this application, the output signal hole group may also be electrically connected to the connector pad group through metal traces on the circuit board, that is, the output signal hole group may be electrically connected to the connector pad group through metallization connection between the output signal hole group and the connector pad group, but not limited to.

[0062] Optionally, in the embodiments of this application, the electrical connection between the multiple sets of input signal hole groups and the connector pad group may include, but is not limited to, the following: each set of input signal hole groups in the multiple sets of input signal hole groups is directly electrically connected to the connector pad group.

[0063] Optionally, in the embodiment of the present application, the electrical connection between the multiple groups of output signal hole groups and the connector pad group can include but is not limited to that each of the multiple groups of output signal hole groups is directly electrically connected with the connector pad group.

[0064] Optionally, in the embodiment of the present application, the input signal hole group can be but is not limited to a differential signal hole group, and the input signal hole group can be but is not limited to used for transmitting differential signals; the output signal hole group can be but is not limited to also a differential signal hole group, and the output signal hole group can be but is not limited to used for transmitting differential signals.

[0065] Optionally, in the embodiment of the present application, the multiple groups of input signal hole groups and the multiple groups of output signal hole groups can be but are not limited to arranged on the two sides of the connector pad group in a manner that the input signal hole groups are on one side and the output signal hole groups are on the other side. As shown in FIG. 1, the multiple groups of input signal hole groups can be but are not limited to arranged on the first side of the connector pad group, and the multiple groups of output signal hole groups can be but are not limited to arranged on the second side of the connector pad group. Figure 1 Figure 1 In the embodiment shown in FIG. 1, only one way of determining the first side and the second side is shown, and in actual application, the other opposite two sides of the connector pad group can also be selected as the first side and the second side.

[0066] As an optional implementation, the input signal hole group includes a first via pair, wherein the distance between the multiple groups of input signal hole groups and the connector pad group is the same, and the line between the two first vias included in the first via pair is parallel to the connector pad group.

[0067] Optionally, in the embodiment of the present application, each of the multiple groups of input signal hole groups can include but is not limited to a pair of first via pairs.

[0068] Optionally, in the embodiment of the present application, the distance between the multiple groups of input signal hole groups included in the interface circuit module and the connector pad group can be but is not limited to the same.

[0069] Optionally, in the embodiment of the present application, the distance between the input signal hole group and the connector pad group can include but is not limited to the distance between a signal point representing the input signal hole group and a pad line representing the connector pad group, wherein the signal point is on the input signal hole group, and the pad line is on the connector pad group. It should be noted that for the input signal hole groups in the same interface circuit module, the signal points representing the input signal hole groups can be but are not limited to determined in the same rule. Figure 2 is a schematic diagram of an interface circuit module according to the embodiment of the present application Figure 2 ​The leftmost point of the via on one side (e.g., the left side) of each group of input signal hole groups can be taken as a signal point representing the input signal hole group, and the first side of the connector pad group can be taken as a pad line representing the connector pad group. The first side can refer to a boundary line of the connector pad group facing the input signal hole group, which can be understood as the starting point or reference line of the signal input path. Figure 2 As shown in FIG. 1B, the distances from each group of input signal hole groups to the connector pad group are the same, i.e., A1=A2=...=An. Figure 3 FIG. 1C is a schematic diagram of an interface circuit module according to an embodiment of the present application. Figure 3 The uppermost point of the via on one side (e.g., the right side) of each group of input signal hole groups can be taken as a signal point representing the input signal hole group, and a line on the connector pad group between the first side and the second side and parallel to the first side / second side can be taken as a pad line representing the connector pad group. The second side can refer to a boundary line of the connector pad group facing the output signal hole group, which can be understood as the starting point or reference line of the signal output path. The first side and the second side can be opposite sides of the connector pad group. The first side can be parallel to the second side. Figure 3 As shown in FIG. 1D, the distances from each group of input signal hole groups to the connector pad group are the same, i.e., B1=B2=...=Bn. Figure 4 FIG. 1E is a schematic diagram of an interface circuit module according to an embodiment of the present application. Figure 4 The uppermost point of the via on one side (e.g., the right side) of each group of input signal hole groups can be taken as a signal point representing the input signal hole group, and a line on the connector pad group between the first side and the second side and parallel to the first side / second side can be taken as a pad line representing the connector pad group. The second side can refer to a boundary line of the connector pad group facing the output signal hole group, which can be understood as the starting point or reference line of the signal output path. The first side and the second side can be opposite sides of the connector pad group. The first side can be parallel to the second side. Figure 4 As shown in FIG. 1F, the distances from each group of input signal hole groups to the connector pad group are the same, i.e., C1=C2=...=Cn.

[0070] Optionally, in the embodiment of the present application, as shown in FIG. 1G, the line between the two first vias included in the first via pair is parallel to the first side or the second side of the connector pad group, i.e., the line between the two first vias is parallel to the connector pad group. Figure 2

[0071] Through the above, the two first vias in the first via pair included in the input signal hole group are arranged in a parallel (i.e., the line between the two first vias is parallel to the connector pad group) and equal (i.e., the distances from the multiple groups of input signal hole groups to the connector pad group are the same) manner on the first side of the connector pad group, which can make the via routing not need to be realized in the form of equal length matching through the bulge, and simplify the wiring difficulty of the first via pair.

[0072] ​As an optional implementation, the input signal hole group further comprises two first ground holes, wherein the two first ground holes are respectively located at two sides of the first via pair, and the two first ground holes are on the extension line of the connection line between the two first vias included in the first via pair.

[0073] Optionally, in the embodiments of the present application, Figure 5 is a schematic diagram of an interface circuit module according to the embodiments of the present application Figure 5 As shown in Figure 5 , the input signal hole group can but is not limited to comprise two first ground holes in addition to the first via pair, the two first ground holes can but are not limited to be respectively located at two sides of the first via pair, and the two first ground holes are on the extension line of the connection line between the two first vias included in the first via pair.

[0074] Through the above, the two first ground holes are symmetrically arranged at two sides of the first via pair and are on the extension line of their connection line, which can effectively construct a local shielding layer to suppress crosstalk between signal lines, especially near-end crosstalk and far-end crosstalk.

[0075] As an optional implementation, the second distance between the target first ground hole and the target first via is equal to the first distance, wherein the first distance is the distance between the two first vias included in the first via pair, the target first ground hole is each ground hole of the two first ground holes, and the target first via is the via adjacent to the target first ground hole in the first via pair.

[0076] Optionally, in the embodiments of the present application, the distances between the pairs of first vias on the interface circuit module can but are not limited to be the same, in order to ensure that the impedance between the vias and the vias is maintained at a required value. Further, in order to ensure that the impedance between the vias and the ground holes is also maintained at the required value, it is necessary to limit the distance between the first ground hole and the directly adjacent first via in the same input signal hole group to be equal to the distance between the two first vias in the input signal hole group.

[0077] Optionally, in the embodiments of the present application, Figure 6 is a schematic diagram of an interface circuit module according to the embodiments of the present application Figure 6 As shown in Figure 6 , the first distance can but is not limited to be the distance between the two via points representing the two first vias in the first via pair, the second distance can but is not limited to be the distance between the ground hole point representing the target first ground hole and the via point representing the target first via, and the second distance can but is not limited to be equal to the first distance. It should be noted that for the ground holes and the vias in the same interface circuit module, the ground hole points and the via points representing the ground holes and the vias can but are not limited to be determined in the same rule, for example, as shown in Figure 6As shown, each ground hole or via hole can be but not limited to a point farthest from the connector pad group as a ground hole point or via hole point of each ground hole or via hole.

[0078] As an optional implementation, the input signal hole group further comprises four second ground holes, wherein the four second ground holes are distributed around the first via hole pair.

[0079] Optionally, in the embodiments of the present application, Figure 7 is a schematic diagram of an interface circuit module according to the embodiments of the present application Figure 7 As shown, Figure 7 In addition to the two first ground holes in the input signal hole group, four second ground holes can also be provided in the input signal hole group, which are arranged around the first via hole pair to form a more intensive shielding layer. These ground holes not only can effectively absorb and shield the electromagnetic field generated by high-speed signal transmission to prevent interference with the adjacent signal lines, but also can build a low-impedance path to guide the electromagnetic energy around the signal line to dissipate quickly to the ground plane, greatly reducing the probability of occurrence of near-end crosstalk and far-end crosstalk, thereby optimizing the signal quality of the entire circuit module.

[0080] As an optional implementation, the third distance between the target second ground hole and the reference first via hole is equal to the first distance, wherein the first distance is the distance between the two first via holes included in the first via hole pair, the target second ground hole is each ground hole of the four second ground holes, and the reference first via hole is the via hole in the first via hole pair closest to the target second ground hole.

[0081] Optionally, in the embodiments of the present application, as described above, in order to ensure that the impedance between the via hole and the ground hole also remains at the required value described above, it is necessary to limit the distance between the second ground hole and the directly adjacent first via hole belonging to the same input signal hole group to be equal to the distance between the two first via holes in the input signal hole group.

[0082] Optionally, in the embodiments of the present application, Figure 8 is a schematic diagram of an interface circuit module according to the embodiments of the present application Figure 8 As shown, Figure 8 The first distance can be but is not limited to the distance between the two via hole points representing the two first via holes in the first via hole pair, the third distance can be but is not limited to the distance between the ground hole point representing the target second ground hole and the via hole point representing the reference first via hole, and the third distance can be but is not limited to equal to the first distance. It should be noted that for the ground holes and via holes in the same interface circuit module, the ground hole points and via hole points representing the ground holes and via holes can be but are not limited to determined by the same rule, for example, as shown in Figure 8As shown, the center point of each ground hole or via hole can be but is not limited to a ground hole point or a via hole point representing the respective ground hole or via hole.

[0083] As an optional implementation, the input signal hole group includes a second via hole pair, wherein the distance from the multiple groups of input signal hole groups to the connector pad group is the same, the first included angle between the line connecting the two second via holes included in the second via hole pair and the first vertical direction of the connector pad group is greater than or equal to 0° and less than 90°.

[0084] Optionally, in the embodiments of the present application, each of the multiple groups of input signal hole groups can but is not limited to include a pair of second via hole pairs.

[0085] Optionally, in the embodiments of the present application, the distance from the multiple groups of input signal hole groups included in the interface circuit module to the connector pad group can but is not limited to be the same.

[0086] Optionally, in the embodiments of the present application, the distance from the input signal hole group to the connector pad group can but is not limited to include the distance between the signal point representing the input signal hole group and the pad line representing the connector pad group, wherein the signal point is located on the input signal hole group and the pad line is located on the connector pad group. It should be noted that for the input signal hole groups in the same interface circuit module, the signal points representing the input signal hole groups can but are not limited to be determined according to the same rule. Figure 9 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 9 The leftmost point of the via hole on one side (such as the left side) of each group of input signal hole groups can be but is not limited to regarded as the signal point representing the input signal hole group, and the first edge of the connector pad group can be but is not limited to regarded as the pad line representing the connector pad group, wherein the first edge can but is not limited to refer to the boundary line of the connector pad group facing the input signal hole group, which can be understood as the starting point or reference line of the signal input path, as shown in Figure 9 As shown, the distance from each group of input signal hole groups to the connector pad group is the same, i.e. D1=D2=...=Dn.

[0087] Optionally, in the embodiments of the present application, as shown in Figure 9As shown, the line connecting two second vias in a second via pair included in the input signal via group can, but is not limited to, have an angle R1 with the first vertical direction of the connector pad group, where 0° ≤ R1 < 90°. It should be noted that the first vertical direction here can, but is not limited to, be a direction perpendicular to the first side and away from the connector pad group, and the line connecting two second vias here can, but is not limited to, refer to the line connecting the via point representing the second via closer to the connector pad group to the via point representing the second via further away from the connector pad group. Furthermore, for ground vias and vias in the same interface circuit module, the ground via point and via point representing the ground via and via can, but is not limited to, be determined using the same rules. All interface circuit modules involved in this application follow this principle, and will not be elaborated further hereafter.

[0088] Optionally, in the embodiments of this application, Figure 10 This is a schematic diagram of the interface circuit module according to an embodiment of this application. Figure 10 .like Figure 10 As shown, the tilting directions of the two second vias in each input signal via pair included in each group of input signal vias on an interface circuit module may, but are not limited to, be different. However, the angle between the line connecting the two second vias in each input signal via pair and the first vertical direction is greater than or equal to 0° and less than 90°. Furthermore, according to... Figure 10 Setting the second via pair as shown will ensure that only two pairs of adjacent vias are in the same direction, resulting in less crosstalk compared to having more than two pairs of adjacent vias in the same direction.

[0089] By placing the two second ground holes on the first side of the connector pad group at an angle rather than parallel to the connector pad group, the lateral space on the first side of the connector pad group can be saved, which is beneficial for the inner layer wiring.

[0090] As an optional implementation, the input signal via group further includes four third ground vias, wherein the four third ground vias are distributed around the second via pair.

[0091] Optionally, in the embodiments of this application, Figure 11 This is a schematic diagram of the interface circuit module according to an embodiment of this application. Figure 10 1. For example Figure 11 As shown, the input signal via group may include, but is not limited to, four third ground vias. These four third ground vias are distributed around the second via pair, which can significantly enhance the electromagnetic shielding effect of the signal, further reduce crosstalk, optimize signal integrity, and achieve more efficient wiring and space utilization without sacrificing signal quality.

[0092] As an optional implementation, two of the four third ground holes are respectively located on two sides of the second via pair, and the two third ground holes are on the extension line of the connecting line between the two second vias included in the second via pair, and the other two of the four third ground holes are respectively located on two sides of the extension line of the connecting line between the two second vias.

[0093] Optionally, in the embodiment of the present application, as shown in Figure 11 the specific distribution of the four third ground holes distributed around the second via pair can include but is not limited to: two of the four third ground holes are respectively located on two sides of the second via pair, and the two third ground holes are on the extension line of the connecting line between the two second vias included in the second via pair, and the remaining two of the four third ground holes (i.e. the other two third ground holes) can be but not limited to respectively located on two sides of the extension line of the connecting line between the two second vias included in the second via pair.

[0094] Through the above, the two third ground holes are located on the extension line of the connecting line of the second via pair, which can directly form a ground shield on the path of the signal line, effectively suppress the crosstalk between signals, especially in terms of near-end crosstalk and far-end crosstalk, and provide stronger isolation and shielding effect. The other two third ground holes are located on two sides of the extension line of the connecting line, which not only provides an additional ground path for the signal line, but also uniformly disperses electromagnetic energy, reduces the strength of the local electromagnetic field, thereby reducing the overall electromagnetic interference level and optimizing the electromagnetic compatibility of the transmission signal.

[0095] As an optional implementation, the fourth distance between the target third ground hole and the reference second via is equal to the fifth distance, where the fifth distance is the distance between the two second vias included in the second via pair, and the target third ground hole is each ground hole of the four third ground holes, and the reference second via is the via closest to the target third ground hole in the second via pair.

[0096] Optionally, in the embodiment of the present application, the distance between the pairs of second vias on the interface circuit module can be but not limited to the same, in order to ensure that the impedance between the vias and the vias is kept at a certain value. Further, in order to ensure that the impedance between the vias and the ground holes is also kept at this certain value, it is necessary to limit the distance between the third ground hole belonging to the same input signal hole group and the directly adjacent second via to be equal to the distance between the two second vias in the input signal hole group.

[0097] Optionally, in the embodiment of the present application, Figure 12 is Figure 11 a partial enlarged view. As Figure 12As shown, the fifth distance can be but is not limited to a distance between two via points representing two second vias in the second via pair respectively, and the fourth distance can be but is not limited to a distance between the via point representing the target third via and the via point representing the reference second via, and the fourth distance can be but is not limited to equal to the fifth distance.

[0098] As an optional implementation, the fifth distance is 31.5 mil, and the sixth distance is 24 mil, where the sixth distance is a distance between the target third via and the reference third via, and the target third via is each of the two third vias, and the reference third via is the via closest to the target third via among the other two third vias.

[0099] Optionally, in the embodiment of the present application, in a general circuit board design, the impedance between the vias and the impedance between the vias and the ground hole can be but is not limited to be determined as 85 ohms, in order to achieve the impedance between the vias and the ground hole as 85 ohms, the fifth distance can be but is not limited to be determined as 31.5 mil, and the corresponding fourth distance is also 31.5 mil.

[0100] Optionally, in the embodiment of the present application, on the basis of limiting the fourth distance and the fifth distance as 31.5 mil, the sixth distance between two adjacent ground holes in the same input signal hole group can be but is not limited to be limited as 24 mil.

[0101] As an optional implementation, the first included angle is greater than or equal to 15° and less than or equal to 22.5°.

[0102] Optionally, in the embodiment of the present application, through the arrangement mode of the second via and the third ground hole, the longitudinal space (i.e. the space in the first vertical direction) occupied by a group of input signal hole groups on the interface circuit module is 31.5×cos(R1)+31.5×cos(R1)+31.5×cos(R1)<31.5+31.5+31.5, that is, through the arrangement mode of the second via and the third ground hole, the longitudinal space occupied by a group of input signal hole groups on the interface circuit module is smaller than the longitudinal space that will be occupied by arranging the second via pair (and the corresponding third ground hole) in the first vertical direction.

[0103] Optionally, in the embodiment of the present application, the distance between the vias is 31.5 mil, and the differential signal vias (i.e. the second via pair) are arranged at an angle of 15°, which is larger than the distance between the two pairs of vias arranged in parallel.

[0104] Optionally, in the embodiments of the present application, since the third ground hole is arranged on the extension line of the connection line of the two second via holes included in the second via hole pair, in order to avoid the influence of the arrangement position of the third ground hole closer to the connector pad group on the wiring of the connector pad group and other inner layer wirings, the aforementioned first included angle can only be 15° at the minimum, i.e., the first included angle is greater than or equal to 15°.

[0105] Optionally, in the embodiments of the present application, since the third ground hole is arranged on the extension line of the connection line of the two second via holes included in the second via hole pair, in order to avoid the input signal hole group occupying too much horizontal space, i.e., to avoid the influence of the arrangement of the third ground hole on the outer side (relative to the second via hole pair) on other inner layer wirings, the aforementioned first included angle can only be 22.5° at the maximum, i.e., the first included angle is less than or equal to 15°.

[0106] As an optional implementation, the output signal hole group includes: a third via hole pair and a first capacitor pair; wherein the first capacitor pair is located between the third via hole pair and the connector pad group, a plurality of first capacitor pairs are electrically connected to the connector pad group, and adjacent first capacitor pairs in each first capacitor pair have different distances to the connector pad group.

[0107] Optionally, in the embodiments of the present application, each of the plurality of output signal hole groups can but is not limited to include a pair of third via hole pairs and a pair of first capacitor pairs, the first capacitor pair can but is not limited to be located between the third via hole pair and the connector pad group, the first capacitor pair can but is not limited to be electrically connected to the third via hole pair, and the first capacitor pair can but is not limited to be electrically connected to the connector pad group.

[0108] Optionally, in the embodiments of the present application, the distance of the first capacitor pair to the connector pad group can but is not limited to include: the distance between the capacitor point representing the first capacitor pair and the pad line representing the connector pad group, wherein the capacitor point is located on the first capacitor pair, and the pad line is located on the connector pad group. It should be noted that for the first capacitor pair in the same interface circuit module, the capacitor point representing the first capacitor pair can but is not limited to be determined according to the same rule. Figure 13 is a schematic diagram of an interface circuit module according to the embodiments of the present application Figure 10 II. The midpoint of the connection line of the center points of the two first capacitors included in each first capacitor pair can but is not limited to be regarded as the capacitor point representing the first capacitor pair, and the second side of the connector pad group can but is not limited to be regarded as the pad line representing the connector pad group, where the second side can but is not limited to refer to a boundary line of the connector pad group facing the output signal hole group, which can be understood as the starting point or reference line of the signal output path, such as Figure 13As shown, the distance from each first capacitor pair to the connector pad group is different, i.e. E1≠E2, E2≠E3, E3≠E4,..., En-1≠En.

[0109] By the above, the first capacitor pairs are arranged staggeredly, so that the distance from each capacitor pair to the connector pad group is different, the direct coupling between capacitors is effectively reduced, mutual interference in the capacitor array is avoided, and the stability of the output signal is improved. In addition, the staggered space of the capacitors and the vias is conducive to the outcoming of the inner layer lines.

[0110] As an optional implementation, the line between the two third vias included in the target third via pair is parallel to the connector pad group; a second included angle between the line between the two third vias included in the reference third via pair and the second vertical direction of the connector pad group is greater than 0° and less than 90°; the third via pairs included in the plurality of output signal hole groups include the target third via pair and the reference third via pair.

[0111] Optionally, in the embodiments of the present application, Figure 14 is a schematic diagram of an interface circuit module according to the embodiments of the present application Figure 10 III. As shown, Figure 14 the output signal hole group can include but is not limited to a target third via pair parallel to the second side (i.e. parallel to the connector pad group), and can also include but is not limited to a reference third via pair at a certain included angle with the second vertical direction.

[0112] Optionally, in the embodiments of the present application, the line between the two third vias included in the target third via pair is parallel to the connector pad group, so that the line of the via included in the target third via pair does not need to be realized by the form of a bulge to match the length, and the wiring difficulty of the target third via pair is simplified.

[0113] Optionally, in the embodiments of the present application, as shown, Figure 14 the second vertical direction can be but is not limited to a direction perpendicular to the second side and away from the connector pad group, and the line between the two third vias can be but is not limited to a line from a via point representing a third via closer to the connector pad group to a via point representing a third via farther away from the connector pad group.

[0114] As an optional implementation, the target third via pair is located in a first area, and the first area is an area on the interface circuit module where no other lines exist; the reference third via pair is located in a second area, and the second area is an area on the interface circuit module where other lines exist.

[0115] Optionally, in the embodiments of the present application, the target third via pair parallel to the connector pad group is located in a first region where no other traces exist, and the reference third via pair not parallel to the connector pad group is located in a second region where other traces exist. The region characteristics of each region are fully considered to ensure the signal quality of the signals transmitted by each trace while achieving good wiring.

[0116] As an optional implementation, the distance between the projection of the other trace on the plane where the reference third via pair is located and the reference third via, which is the via in the reference third via pair closest to the other trace, falls within a target distance range. The target distance range is used to control the signal integrity of the signals transmitted by the reference third via pair and the other trace.

[0117] Optionally, in the embodiments of the present application, more specifically, when the second region is provided with the reference third via pair, the distance between the projection of the other trace on the plane where the reference third via pair is located and the two reference third vias included in the reference third via pair falls within a target distance range. Through such a setting, the mutual influence between the reference third via and the other trace can be controlled within an acceptable range, and the signal integrity of the signals transmitted by the reference third via pair and the other trace can be ensured.

[0118] Optionally, in the embodiments of the present application, the distance between the projection of the other trace on the plane where the reference third via pair is located and the reference third via can but not limited to refer to the distance between the projection line representing the orthogonal projection of the other trace on the plane where the reference third via pair is located and the via point representing the reference third via.

[0119] Optionally, in the embodiments of the present application, falling within the target distance range can but not limited to refer to that the aforementioned distance is greater than or equal to the minimum value of the target distance range and less than or equal to the maximum value of the target distance range.

[0120] As an optional implementation, the target distance range is greater than or equal to 20 mil and less than or equal to 55 mil.

[0121] Optionally, in the embodiments of the present application, the aforementioned target distance range can but not limited to be further limited within the range of 20 mil-55 mil (including the critical value).

[0122] As an optional implementation, the target hole group in the plurality of output signal hole groups further comprises two fourth ground holes, and the reference hole group in the plurality of output signal hole groups further comprises four fifth ground holes; wherein the two fourth ground holes are located between a straight line where two third vias in the third via pair in the target hole group are located and a straight line where two first capacitors in the first capacitor pair in the target hole group are located; wherein two fifth ground holes in the four fifth ground holes are located between the first straight line where two third vias in the third via pair in the reference hole group are located and the second straight line where two first capacitors in the first capacitor pair in the reference hole group are located, and the two fifth ground holes and the other two fifth ground holes in the four fifth ground holes are located on two sides of the first straight line.

[0123] Optionally, in the embodiments of the present application, Figure 15 is a schematic diagram of an interface circuit module according to the embodiments of the present application Figure 10 Four. As Figure 15 shown, the target hole group in the output signal hole group can but not limited to further comprise two fourth ground holes, and the two fourth ground holes can but not limited to be located between a straight line where a third via pair in the target hole group is located and a straight line where a first capacitor pair in the target hole group is located.

[0124] Optionally, in the embodiments of the present application, as Figure 15 shown, the reference hole group in the output signal hole group can but not limited to further comprise four fifth ground holes, and the four fifth ground holes can but not limited to be arranged around a third via pair in the reference hole group. Specifically, two fifth ground holes in the four fifth ground holes can but not limited to be located between a first straight line where a third via pair in the reference hole group is located and a second straight line where a first capacitor pair in the reference hole group is located, and the other two fifth ground holes in the four fifth ground holes and the two fifth ground holes can but not limited to be arranged on two sides of the first straight line respectively.

[0125] By the above arrangement, two fourth ground holes are added in the target hole group, and four fifth ground holes are added in the reference hole group, especially at the positions between the via pairs and the capacitor pairs, a more compact electromagnetic shielding environment can be formed. The layout of the ground holes increases the density of the shielding layer around the signal lines, greatly reduces the electromagnetic coupling between the signal lines, thereby reducing crosstalk and ensuring the integrity and stability of the signals. In addition, various ground hole arrangement schemes for the output signal hole group are also provided in the present application. The selection of which ground hole arrangement scheme can be comprehensively measured according to the board area of the interface circuit module and the requirement for signal integrity, for example, but not limited to, in the case where the board area is relatively sufficient (there can be no other traces in the current area) and the requirement for the integrity of the signals transmitted by the output signal hole group is relatively high (the signal crosstalk can be below a threshold value), the scheme of setting four fifth ground holes can be selected; but not limited to, in the case where the board area is not very sufficient (there can be other traces in the current area) and the requirement for the integrity of the signals transmitted by the output signal hole group is not very high (the signal crosstalk can be above a threshold value), the scheme of setting two fourth ground holes can be selected.

[0126] As an optional implementation, the seventh distance between the target fourth ground hole and the reference third via is equal to the eighth distance, wherein the eighth distance is the distance between the two third vias included in the third via pair in the target hole group, the target fourth ground hole is each ground hole of the two fourth ground holes, and the reference third via is the via in the third via pair included in the target hole group that is closest to the target fourth ground hole; the ninth distance between the target fifth ground hole and the target third via is equal to the tenth distance, wherein the tenth distance is the distance between the two third vias included in the third via pair in the reference hole group, the target fifth ground hole is each ground hole of the four fifth ground holes, and the target third via is the via in the third via pair included in the reference hole group that is closest to the target fifth ground hole.

[0127] Optionally, in the embodiments of the present application, in order to ensure that the impedance between the via and the ground hole and the impedance between the vias remain at the same fixed value, it is necessary to limit the distance between the fourth ground hole belonging to the same target hole group and the third via in the target hole group that is closest to the fourth ground hole to be equal to the distance between the two third vias in the target hole group. Figure 16 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 10 Five. As Figure 16 shown, the eighth distance can be but is not limited to the distance between the two via points of the two third vias in the third via pair included in the target hole group, the seventh distance can be but is not limited to the distance between the ground hole point of the target fourth ground hole and the via point of the reference third via, and the seventh distance can be but is not limited to equal to the eighth distance.

[0128] Optionally, in the embodiments of the present application, in order to ensure that the impedance between the via and the ground hole and the impedance between the via and the via remain at the same selected value, it is necessary to limit the distance between the fifth ground hole belonging to the same reference hole group and the third via closest to the fifth ground hole in the reference hole group to be equal to the distance between the two third vias in the reference hole group. Figure 17 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 10 Six. As shown in Figure 17 , the tenth distance can be but is not limited to the distance between the two via points representing the two third vias in the third via pair included in the reference hole group, and the ninth distance can be but is not limited to the distance between the ground hole point representing the target fifth ground hole and the via point representing the target third via, and the ninth distance can be but is not limited to equal to the tenth distance.

[0129] As an optional implementation, the output signal hole group includes: a fourth via pair and a second capacitor pair; wherein the connection line between the two second capacitors included in the second capacitor pair is perpendicular to the connector pad group, and the distance from the second capacitor pair included in the multiple sets of output signal hole groups to the connector pad group is the same.

[0130] Optionally, in the embodiments of the present application, Figure 18 is a schematic diagram of an interface circuit module according to an embodiment of the present application Figure 10 Seven. As shown in Figure 18 , the output signal hole group can but is not limited to include a fourth via pair and a second capacitor pair, and the connection line between the two second capacitors included in the second capacitor pair is perpendicular to the second side of the connector pad group. In addition, it should be noted that the distance from the second capacitor pair included in the multiple sets of output signal hole groups to the connector pad group can but is not limited to include that the distance between the multiple capacitor points representing the second capacitor pairs included in the multiple sets of output signal hole groups and the pad line representing the connector pad group is the same, as shown in Figure 18 , that is, F1=F2=F3=F4=F5.

[0131] From the above, since the distance from all second capacitor pairs to the connector pad group is the same, this helps to ensure the consistency of signal delay when passing through the capacitor pair. In high-speed circuits, even small differences in signal delay can cause signal integrity problems such as timing errors and data misreading. By controlling the distance from the capacitor pair to the pad group, the delay difference can be reduced, and the synchronization and reliability of signal transmission can be improved. In addition, the connection line of the second capacitor pair is perpendicular to the connector pad group, which helps to reduce the coupling effect between the capacitor pairs. When the capacitor pairs are arranged in parallel, the coupling between them will cause the signal quality to decline. Vertical arrangement can reduce this coupling effect, reduce the interference between signals, and improve the purity of the signal.

[0132] As an optional implementation, distances from the second capacitor pairs included in the plurality of output signal hole groups to the connector pad groups are all greater than or equal to 120 mils.

[0133] Optionally, in the embodiments of the present application, it is required to limit the distances from the second capacitor pairs to the connector pad groups to be greater than a certain value, for example, greater than or equal to 120 mils, which helps to ensure the reliability of the capacitor welding and avoid causing the reliability problem of the capacitor welding.

[0134] As an optional implementation, the lines between the fourth via pairs included in the plurality of output signal hole groups are all perpendicular to the connector pad groups, and the fourth via pairs included in the plurality of output signal hole groups are all arranged on the same side of the second capacitor pairs in the output signal hole groups.

[0135] Optionally, in the embodiments of the present application, Figure 19 is Figure 18 a partial enlargement Figure 1 . As shown in Figure 19 , the lines between the fourth via pairs included in the plurality of output signal hole groups can but are not limited to also be perpendicular to the second side of the connector pad groups. By arranging the fourth via pairs perpendicularly, the transverse space of the second side of the connector pad groups occupied by the fourth via pairs can be effectively reduced, which is beneficial to the inner layer wiring. In addition, the fourth via pairs included in the plurality of output signal hole groups can but are not limited to be all arranged on the same side of the second capacitor pairs, for example, as shown in Figure 19 , that is, all arranged on the right side of the second capacitor pairs. By such a design, the fourth ground hole pairs are added between the two pairs of second capacitor pairs, which can reduce the capacitor coupling.

[0136] As an optional implementation, the output signal hole group further includes four sixth ground holes, wherein two of the four sixth ground holes are located between a third straight line where two fourth vias included in the fourth via pair are located and a fourth straight line where two second capacitors included in the second capacitor pair are located, and the two sixth ground holes are located on two sides of the third straight line.

[0137] Optionally, in the embodiments of the present application, as shown in Figure 18 , the output signal hole group can but is not limited to further include four sixth ground holes, and the four sixth ground holes can but are not limited to be arranged around the fourth via pair included in the output signal hole group.

[0138] Optionally, in the embodiments of the present application, as shown in Figure 19As shown, the specific arrangement of the four sixth vias can include, but is not limited to, that two of the four sixth vias are located between the third straight line and the fourth straight line, and the other two of the four sixth vias are located on the side of the third straight line that is not provided with the two sixth vias.

[0139] Through the above, the two sixth vias are placed between the fourth via pair and the second capacitor pair, which can form an effective electromagnetic shielding wall, which strengthens the isolation between the signal line and the surrounding elements, reduces the coupling and interference between different signal paths, and especially reduces the signal crosstalk between the capacitor pair and the via pair, and improves the purity and integrity of the signal.

[0140] As an optional implementation, the eleventh distance between the target sixth via and the reference fourth via is equal to the twelfth distance, where the twelfth distance is the distance between the two fourth vias included in the fourth via pair, and the target sixth via is each of the four sixth vias, and the reference fourth via is the via in the fourth via pair that is closest to the target sixth via.

[0141] Optionally, in the embodiments of the present application, similar to the foregoing, the distances between the pairs of fourth vias on the interface circuit module can be, but are not limited to, the same, in order to ensure that the impedance between the vias is kept at a known value. Further, in order to ensure that the impedance between the vias and the ground vias is also kept at the known value, it is necessary to limit the distance between the sixth via in the same output signal hole group and the closest fourth via to be equal to the distance between the two fourth vias in the output signal hole group.

[0142] As an optional implementation, the twelfth distance is 31.5 mil, and the thirteenth distance is 24 mil, where the thirteenth distance is the distance between the candidate sixth via and the reference sixth via, the candidate sixth via is each of the two sixth vias, and the reference sixth via is the via in the other two sixth vias that is closest to the candidate sixth via.

[0143] Optionally, in the embodiments of the present application, as described above, in general circuit board design, it can be, but is not limited to, necessary to determine the impedance between the vias and the impedance between the vias and the ground vias to be 85 ohms. In order to achieve the determination of the impedance between the vias and the ground vias to be 85 ohms, it can be, but is not limited to, necessary to determine the twelfth distance to be 31.5 mil, and the corresponding eleventh distance is also 31.5 mil.

[0144] Optionally, in the embodiments of the present application, on the basis of limiting the eleventh distance and the twelfth distance to be 31.5 mil, it can be, but is not limited to, necessary to limit the thirteenth distance between the two adjacent ground vias in the same output signal hole group to be 24 mil.

[0145] As an optional embodiment, the line between two sixth ground holes is perpendicular to the connector pad group, and the line between the other two sixth ground holes is perpendicular to the connector pad group.

[0146] Optionally, in the embodiments of the present application, Figure 20 Figure 18 is a partial enlargement of Figure 2 As shown in Figure 20 , the aforementioned line between two sixth ground holes can but not limited to also be perpendicular to the (second side of the) connector pad group, and the aforementioned line between the other two sixth ground holes can but not limited to also be perpendicular to the (second side of the) connector pad group.

[0147] Through the above, the sixth ground hole perpendicular to the connector pad group is arranged, forming a more effective signal isolation band, which can significantly reduce the crosstalk between the signal lines. And the arrangement of the sixth ground hole perpendicular to the connector pad group also saves the transverse space of the second side of the connector pad group, which is beneficial to the inner layer wire.

[0148] As an optional embodiment, the target trace width of the target trace segment is greater than the reference trace width of the reference trace segment, and in the first trace and / or the second trace, the target impedance of the target trace segment is greater than the reference impedance of the reference trace segment when the trace width of the trace is the reference trace width, the first trace is the trace between the input signal hole group and the connector pad group, and the second trace is the trace between the output signal hole group and the connector pad group.

[0149] Optionally, in the embodiments of the present application, after the via pair is arranged in the aforementioned manner that is not parallel to the connector pad group, in order to equal-length matching, a "bulge" form needs to be adopted, but such a bulge form will inevitably cause impedance discontinuity. In this case, the aforementioned manner can but not limited to be adopted to resist the adverse effects of the bulge on the impedance.

[0150] Optionally, in the embodiments of the present application, the target trace segment can but not limited to refer to the trace segment that occurs "bulge", and the reference trace segment can but not limited to refer to the trace segment that does not occur "bulge". According to formula 1: , formula 2: , formula 3: , (wherein L represents the inductance per unit length, C represents the capacitance per unit length, is the dielectric constant, A is the area of the capacitor plate, and d is the vertical distance between the two plates, ​is the magnetic permeability, N is the number of turns of the coil per unit length, B is the magnetic induction, and l is the length of the coil. As can be seen, when the "bump" appears, the capacitance distance d becomes larger, and other parameters remain unchanged, which will result in a smaller capacitance C and a larger impedance Z. Impedance discontinuity will cause reflection, and reflection will cause signal fluctuation. The reflection coefficient formula is: =Vr / Vi=(Z2-Z1) / (Z2+Z1) (where the reflection coefficient represents the ratio of the reflected signal voltage Vr to the incident signal voltage Vi when the signal reaches the impedance discontinuity point, Z2 represents the target impedance, and Z1 represents the reference impedance), and according to the reflection coefficient formula, the larger the impedance difference, the larger the reflection coefficient, which represents the poorer the signal quality. Further, according to formulas 1, 2, and 3, if the capacitance area A becomes larger and other parameters remain unchanged, the capacitance C will become larger, and the impedance Z will naturally become smaller, which can neutralize the impedance increase caused by the increase in d, and thus impedance matching can be achieved. Figure 21 is a schematic diagram of a method for resisting the influence of a bump according to an embodiment of the present application. As shown in Figure 21 , for the "bump", the relevant trace (conductive path) can be widened, but is not limited to this. By widening the trace, the capacitance area can be increased.

[0151] As an optional implementation, the target trace width is determined according to the target capacitance area and the target distance, the target capacitance area is determined according to the target trace distance, the reference trace distance, the reference trace width, and the target distance, and the target distance is the distance between the starting point of the target trace segment and the ending point of the target trace segment.

[0152] Optionally, in the embodiments of the present application, according to the aforementioned formulas 1, 2, and 3, to achieve the best effect, it is best to make the adjusted impedance of the target trace segment equal to the reference impedance of the reference trace segment, that is, A (target) / A (reference) =d (target) (i.e., the trace distance of the target trace segment) / d (reference) (i.e., the trace distance of the reference trace segment), that is:

[0153] ,

[0154] And A (reference) =f(s (i.e., the target distance), w (reference) (i.e., the reference trace width)), A (target) =f(s, w (target) (i.e., the target trace width)), then the target trace width can be determined according to the target capacitance area A (target) and s and the f function, and further the target capacitance area A (target) can be determined according to the trace distance d (target) of the target trace segment, the trace distance d (reference) of the reference trace segment, the reference trace width w (reference), s, and the aforementioned f function.

[0155] Through the above, the target trace width is calculated by the target capacitance area and the target distance, and the determination of the target capacitance area involves the trace distance of the target trace segment, the trace distance of the reference trace segment, the reference trace width, and the target distance. This calculation method ensures that in the "bump" area, although the signal path length increases, resulting in increased impedance, the increase in impedance can be effectively offset by increasing the capacitance area by adjusting the target trace width, thereby achieving the continuity of impedance.

[0156] Optionally, in the embodiments of the present application, for any pair of via pairs, if the via in the via pair interferes with the inner layer high-speed line trace, the via should be pulled out to make space for the high-speed line, but 6 ground holes are needed to surround the differential signal hole. Figure 22 is a schematic diagram of a via pair according to an embodiment of the present application. As Figure 22 shown, 6 ground holes can be but are not limited to being arranged around each pair of via pairs to surround the differential signal via.

[0157] As an optional implementation, the input signal hole group includes: a fifth via pair, the output signal hole group includes: a sixth via pair; the distance between the vias inside the adjacent fifth via pair is greater than or equal to 160 mil; and / or, the distance between the vias inside the adjacent sixth via pair is greater than or equal to 160 mil.

[0158] Optionally, in the embodiments of the present application, as Figure 22 shown, in order to avoid excessive far-end crosstalk and near-end crosstalk, the distance between the vias inside the adjacent via pairs needs to be greater than or equal to 160 mil. That is, Q ≥ 160 mil.

[0159] Optionally, in the embodiments of the present application, Figure 23 is a simulation diagram of far-end crosstalk according to an embodiment of the present application, Figure 24 is a simulation diagram of near-end crosstalk according to an embodiment of the present application. As Figure 23 shown, it can be seen that when Q is set to be greater than or equal to 160 mil, the far-end crosstalk of a 16 GHz signal is below -80 dB (Decibel), which is much smaller than the Spec (Specification) requirement. As Figure 24 shown, it can be seen that when Q is set to be greater than or equal to 160 mil, the near-end crosstalk of a 16 GHz signal is also below -80 dB, which is also much smaller than the Spec requirement. That is, when the Q distance is greater than 160 mil, the crosstalk is less affected by the board thickness.

[0160] As an optional implementation, the input signal hole group includes a seventh via pair, the output signal hole group includes an eighth via pair, the distance between the vias inside the adjacent seventh via pair is 115 mil, and / or the distance between the vias inside the adjacent eighth via pair is 115 mil.

[0161] Optionally, in the embodiments of the present application, in addition to the via pairs for signals of 16 GHz, the distance between the vias inside the adjacent via pairs for signals of some other frequencies or some special signals of 16 GHz is limited to 115 mil. At the interval of 115 mil, although the crosstalk is higher than that at the interval of 160 mil, the difference can be compensated by other technical means (such as impedance control, signal termination, software algorithm compensation) to find a balance between space limitation and signal quality.

[0162] As an optional implementation, the input signal hole group includes a ninth via pair, the output signal hole group includes a tenth via pair, the distance between the vias inside the adjacent ninth via pair is less than 160 mil, and / or the distance between the vias inside the adjacent tenth via pair is less than 160 mil, and the thickness of the circuit board of the interface circuit module is determined according to the signal crosstalk generated between the vias with a distance less than 160 mil.

[0163] Optionally, in the embodiments of the present application, in the case where the distance between the vias inside the adjacent via pairs cannot be guaranteed to be greater than or equal to 160 mil, the crosstalk can be reduced in the form of reducing the thickness of the board. Specifically, Figure 25 is a flowchart of a method for reducing the thickness of a board according to the embodiments of the present application, which can but not limited to follow the process of reducing the thickness of the board as shown in Figure 25 to optimize the relationship between the thickness of the board and the interval of the vias.

[0164] Through the above, a method for reducing the crosstalk between signals in the case of limited wiring area is given, so that the crosstalk between signals can be effectively controlled in the case of limited wiring area, and the integrity of the signals is guaranteed.

[0165] The embodiments of the present application also provide a server mainboard, Figure 26 is a schematic diagram of a server mainboard according to the embodiments of the present application, Figure 1 as shown in Figure 26 The server mainboard includes at least one processor pad group and at least one interface circuit module as described above, and the interface circuit module is electrically connected with the processor pad group.

[0166] According to the application, the interface circuit module includes a connector pad group, a plurality of input signal hole groups and a plurality of output signal hole groups, the plurality of input signal hole groups are electrically connected with the connector pad group, and the plurality of output signal hole groups are electrically connected with the connector pad group. Since the plurality of input signal hole groups are arranged on a first side of the connector pad group, and the plurality of output signal hole groups are arranged on a second side of the connector pad group, the first side and the second side are arranged on opposite sides of the connector pad group, respectively. By such an arrangement, the wirings of the signal hole groups on the two sides of the connector pad group are naturally separated, and it is not necessary to repeatedly wind and punch to avoid, thereby reducing the risk of layout congestion and dead line. Therefore, the technical problem of difficult circuit board wiring of the circuit board provided with the interface circuit module in the related art can be solved, and the technical effect of reducing the wiring difficulty of the circuit board provided with the interface circuit module can be achieved.

[0167] Optionally, in the embodiment of the application, the processor pad group can be, but is not limited to, a set of metallized areas in the server mainboard that are in contact with the processor, and the processor pad group can include, but is not limited to, a plurality of processor pads, each processor pad serving as one metallized area in contact with the processor.

[0168] Optionally, in the embodiment of the application, the processor pad group can be, but is not limited to, used for welding the processor. The processor herein can be, but is not limited to, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA (Field-Programmable Gate Array), an ASIC (Application-Specific Integrated Circuit), or any other form of computing unit or control chip, which can be flexibly selected according to specific application requirements.

[0169] Optionally, in the embodiment of the application, each processor pad group on the server mainboard can be, but is not limited to, electrically connected with each interface circuit module on the server mainboard.

[0170] As an optional implementation, the at least one processor pad group comprises: a first processor pad group and a second processor pad group, and the at least one interface circuit module comprises: a first interface circuit module, a second interface circuit module, a third interface circuit module and a fourth interface circuit module; wherein the first interface circuit module, the second interface circuit module, the third interface circuit module and the fourth interface circuit module are electrically connected with the processor pad group; wherein the first interface circuit module, the second interface circuit module, the third interface circuit module and the fourth interface circuit module are arranged in sequence along the direction from the first processor pad group to the second processor pad group; wherein a first connecting line between the first interface circuit module and the fourth interface circuit module, a second connecting line between the second interface circuit module and the third interface circuit module, and a third connecting line between the first processor pad group and the second processor pad group are parallel, and the distance between the first connecting line and the third connecting line is smaller than the distance between the second connecting line and the third connecting line.

[0171] Optionally, in the embodiments of the present application, Figure 27 is a schematic diagram of a server mainboard according to the embodiments of the present application Figure 2 As shown in Figure 27 , the server mainboard can but not limited to comprise two processor pad groups: a first processor pad group and a second processor pad group, and can but not limited to comprise four interface circuit modules: a first interface circuit module ①, a second interface circuit module ②, a third interface circuit module ③ and a fourth interface circuit module ④. ①, ②, ③ and ④ can but not limited to be arranged in sequence along the direction from the first processor pad group to the second processor pad group, and the distance G1 between a first connecting line between ① and ④ and a third connecting line between the first processor pad group and the second processor pad group is smaller than the distance G2 between a second connecting line between ② and ③ and the third connecting line between the first processor pad group and the second processor pad group, and the three lines of the first connecting line, the second connecting line and the third connecting line are parallel. In addition, it should be noted that the first connecting line, the second connecting line and the third connecting line marked here are only one way of marking the three lines, and the three lines can also be marked in other ways.

[0172] Through the above, the four interface circuit modules are arranged in sequence along the direction from the first processor pad group to the second processor pad group without overlapping, and the distance between the first connecting line and the third connecting line is smaller than the distance between the second connecting line and the third connecting line, so that this compact layout makes the most of the space of the mainboard, while maintaining sufficient signal path separation degree, avoiding unnecessary signal interference and wiring complexity.

[0173] As an optional implementation, the server motherboard further comprises a memory slot pad group, wherein the memory slot pad group is located between the first processor pad group and the second processor pad group, the memory slot pad group has a heat dissipation channel therebetween, the first interface circuit module, the second interface circuit module, the third interface circuit module and the fourth interface circuit module are all arranged on an extension line of the heat dissipation channel, and the memory slot pad group and the heat dissipation channel are both perpendicular to the third connecting line.

[0174] Optionally, in the embodiments of the present application, the memory slot pad group can be but is not limited to a set of metallized areas in the server motherboard which are in contact with memory slots, and the memory slot pad group can include but is not limited to a plurality of memory slot pads, each of which is a metallized area in contact with a memory slot.

[0175] Optionally, in the embodiments of the present application, the memory slot pad group can be but is not limited to used for welding memory slots. The memory slot here can be but is not limited to used for plugging memory. For example, the memory slot can be but is not limited to a DIMM Slot (Dual In-line Memory Module Slot), and each DIMM (Dual In-line Memory Module) (i.e. memory) can be but is not limited to electrically connected to the server motherboard through the DIMM Slot.

[0176] Optionally, in the embodiments of the present application, the memory slot pad group can have but is not limited to a heat dissipation channel (i.e. air duct) therebetween, which can be but is not limited to used for dissipating heat for the memory connected to the memory slot welded by the memory slot pad group, and for dissipating heat for each interface circuit module.

[0177] Optionally, in the embodiments of the present application, Figure 28 is a schematic diagram of a server motherboard according to the embodiments of the present application Figure 3 As shown in FIG. 1, the server motherboard 100 comprises a first processor pad group 110, a second processor pad group 120, a first interface circuit module 130, a second interface circuit module 140, a third interface circuit module 150 and a fourth interface circuit module 160. Figure 28As shown, the memory slot pad group can be but is not limited to located between the first processor pad group and the second processor pad group, and the memory slot pad group can be but is not limited to perpendicular to the third connecting line. The memory slot pad group can be but is not limited to composed of a plurality of memory slot pad strips, and two adjacent memory slot pad strips can be but are not limited to have a heat dissipation channel therebetween, and each heat dissipation channel can be but is not limited to also perpendicular to the third connecting line, and the first interface circuit module, the second interface circuit module, the third interface circuit module and the fourth interface circuit module can be but are not limited to all arranged on the extension line of the heat dissipation channel. By arranging the first interface circuit module, the second interface circuit module, the third interface circuit module and the fourth interface circuit module on the extension line of the heat dissipation channel, it can be but is not limited to beneficial to generate smaller signal power loss on the circuit board for the wiring between the interface circuit module and the processor pad group, and avoid that the power loss of the wiring excessively affects the signal quality.

[0178] Through the above, the specific layout of the interface circuit module and the memory slot pad group, and the perpendicular design of the cooling channel not only maintain the shortest path of the signal line (i.e. the signal line of the interface circuit module to the processor pad group), but also reasonably plan the space on the server motherboard, avoid unnecessary element stacking or signal line crossing, and further optimize the wiring structure and overall layout of the server motherboard.

[0179] As an optional implementation, the position of the first interface circuit module is determined according to the following formula:

[0180] L1 2 + (L2+D2) 2 =D1 2 , 3 inches≤D1≤(TH1+3) inches, D2≥TH2 inches;

[0181] L1 is the distance of the projection of the first interface circuit module on the third connecting line to the first processor pad group, (L2+D2) is the distance of the first interface circuit module to the third connecting line, D2 is the vertical distance of the first interface circuit module to the memory slot pad group, D1 is the distance of the first interface circuit module to the first processor pad group, TH1 is the first threshold value, and TH2 is the second threshold value.

[0182] Optionally, in the embodiments of the present application, Figure 29 is a schematic diagram of a server motherboard according to the embodiments of the present application Figure 4 As shown in FIG. 1, the server motherboard according to the embodiments of the present application includes a first processor pad group 1, a second processor pad group 2, a third connecting line 3, a memory slot pad group 4, a first interface circuit module 5, a second interface circuit module 6, a third interface circuit module 7 and a fourth interface circuit module 8. Figure 29As shown, in order to avoid the signal power loss caused by the long distance of the signal wire on the circuit board, and further affect the quality of the signal, the distance D1 from the first processor pad group to the first interface circuit module can be limited, but not limited to, and D1 can be limited to less than a certain value. Specifically, 3 inches≤D1≤(TH1+3) inches can be limited, but not limited to, where TH1 can be a very small error threshold, i.e., D1 is preferably limited to 3 inches. In addition, the vertical distance D2 from the first interface circuit module to the memory slot pad group can also be limited to a certain range, which is mainly affected by the structure. The arrangement of each interface circuit module cannot interfere with the normal insertion of the memory into the memory slot pad group to which the memory slot pad group is welded. Specifically, D2≥TH2 inches can be limited, but not limited to, where TH2 can be a minimum distance value that can meet the insertion requirement of the memory.

[0183] As an optional embodiment, the position of the fourth interface circuit module is determined according to the following formula:

[0184] L3 2 + (L4+D4) 2 =D3 2 , 3 inches≤D3≤(TH3+3) inches, and D4≥TH4 inches.

[0185] L3 is the distance from the projection of the fourth interface circuit module on the third wire to the second processor pad group, (L4+D4) is the distance from the fourth interface circuit module to the third wire, D4 is the vertical distance from the fourth interface circuit module to the memory slot pad group, D3 is the distance from the fourth interface circuit module to the second processor pad group, TH3 is a third threshold value, and TH4 is a fourth threshold value.

[0186] Optionally, in the embodiments of the present application, as Figure 29As shown, similar to the foregoing, in order to avoid the signal power loss caused by the long distance of the signal wiring on the circuit board, and further affect the quality of the signal, the distance D3 from the second processor pad group to the fourth interface circuit module can be but not limited to be limited to be less than a certain value. Specifically, 3 inches≤D3≤(TH3+3) inches can be but not limited to be limited, wherein TH3 can be but not limited to be a very small error threshold, i.e., D3 is preferably limited to 3 inches. In addition, the vertical distance D4 from the fourth interface circuit module to the memory slot pad group can also be but not limited to be limited within a certain range, which is mainly affected by the structure. The setting of each interface circuit module cannot affect the normal plugging of the memory into the memory slot pad group welded by the memory slot pad group, and cannot interfere with each other. Specifically, D4≥TH4 inches can be but not limited to be limited, and TH4 can be but not limited to be a minimum distance value that can meet the plugging requirement of the memory.

[0187] As an optional implementation, the connector pad group in the first interface circuit module, the connector pad group in the second interface circuit module, the connector pad group in the third interface circuit module, and the connector pad group in the fourth interface circuit module are all arranged vertically with the heat dissipation channel; or the connector pad group in the first interface circuit module, the connector pad group in the second interface circuit module, the connector pad group in the third interface circuit module, and the connector pad group in the fourth interface circuit module all have a third included angle with the third connecting line, wherein the third included angle is determined according to the heat dissipation requirement of the memory electrically connected to the memory slot welded by the memory slot pad group, the distance between the first interface circuit module and the first processor pad group, and the distance between the fourth interface circuit module and the second processor pad group.

[0188] Optionally, in the embodiment of the present application, as shown in Figure 28 The connector pad group in each interface circuit module can be but not limited to be arranged vertically with the aforementioned heat dissipation channel, which is beneficial to the signal quality of the signal transmitted by the wiring between the interface circuit module and the processor pad group (the shorter the wiring distance, the smaller the signal power loss, and the better the signal quality), but the completely vertical arrangement can cause the reduction of the heat dissipation efficiency of the heat dissipation channel.

[0189] Optionally, in the embodiment of the present application, Figure 30 is a schematic diagram of a server mainboard according to the embodiment of the present application Figure 5 As shown in Figure 30As shown, a trade-off can be made between the heat dissipation efficiency of the heat dissipation channel and the signal quality of the signal transmitted by the traces between the interface circuit module and the processor pad group, which can be determined according to the heat dissipation requirement of the memory electrically connected to the memory slot soldered to the memory slot pad group, the distance D1 between the first interface circuit module and the first processor pad group, and the distance D3 between the fourth interface circuit module and the second processor pad group.

[0190] Optionally, in the embodiments of the present application, Figure 31 is a flowchart of a method for determining various distances on a server mainboard according to an embodiment of the present application. As shown in Figure 31 As shown, a trade-off can be made between the heat dissipation efficiency of the heat dissipation channel and the signal quality of the signal transmitted by the traces between the interface circuit module and the processor pad group, which can be determined according to the heat dissipation requirement of the memory electrically connected to the memory slot soldered to the memory slot pad group, the distance D1 between the first interface circuit module and the first processor pad group, and the distance D3 between the fourth interface circuit module and the second processor pad group.

[0191] Those skilled in the art will further appreciate that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, various components have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

[0192] The interface circuit module and the server mainboard provided by the present application are described in detail above. The principles and implementation manners of the present application are described by applying specific examples in the present document, and the above description of the examples is only used to help understand the method and core idea of the present application. It should be noted that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An interface circuit module, characterized in that, include: Connector pad groups, multiple input signal hole groups, and multiple output signal hole groups; The plurality of input signal hole groups are electrically connected to the connector pad group, and the plurality of output signal hole groups are electrically connected to the connector pad group; The multiple sets of input signal holes are disposed on the first side of the connector pad group, and the multiple sets of output signal holes are disposed on the second side of the connector pad group. The first side and the second side are respectively disposed on opposite sides of the connector pad group. The output signal hole group includes: a set of via pairs, a set of capacitor pairs and at least a set of ground hole pairs. The set of via pairs is electrically connected to the connector pad group through the set of capacitor pairs. The two ground holes included in each ground hole pair in the at least one set of ground hole pairs are respectively disposed on both sides of the line connecting the set of via pairs and the set of capacitor pairs. Wherein, the angle between the line connecting two vias in at least one of the multiple sets of output signal hole groups and the vertical direction of the connector pad group is greater than 0° and less than 90°.

2. The interface circuit module according to claim 1, characterized in that, The input signal hole group includes a first via pair, wherein the multiple input signal hole groups are equidistant from the connector pad group, and the line connecting the two first vias included in the first via pair is parallel to the connector pad group.

3. The interface circuit module according to claim 2, characterized in that, The input signal hole group further includes two first ground holes, wherein the two first ground holes are located on both sides of the first via pair, and the two first ground holes are on the extension line of the line connecting the two first vias included in the first via pair.

4. The interface circuit module according to claim 3, characterized in that, The second spacing between the target first ground hole and the target first via is equal to the first spacing, wherein the first spacing is the spacing between the two first vias included in the first via pair, the target first ground hole is each of the two first ground holes, and the target first via is the via adjacent to the target first ground hole in the first via pair.

5. The interface circuit module according to claim 2, characterized in that, The input signal aperture group further includes four second ground apertures, wherein the four second ground apertures are distributed around the first via pair.

6. The interface circuit module according to claim 5, characterized in that, The third spacing between the target second ground hole and the reference first via is equal to the first spacing, wherein the first spacing is the spacing between the two first vias included in the first via pair, the target second ground hole is each of the four second ground holes, and the reference first via is the via in the first via pair that is closest to the target second ground hole.

7. The interface circuit module according to claim 1, characterized in that, The input signal hole group includes a second via pair, wherein the multiple input signal hole groups are at the same distance from the connector pad group, and the line connecting the two second vias included in the second via pair forms a first angle with the first vertical direction of the connector pad group that is greater than or equal to 0° and less than 90°.

8. The interface circuit module according to claim 7, characterized in that, The input signal aperture group further includes four third ground apertures, wherein the four third ground apertures are distributed around the second via pair.

9. The interface circuit module according to claim 8, characterized in that, Two of the four third ground holes are located on both sides of the second via pair, and the two third ground holes are on the extension line of the line connecting the two second vias included in the second via pair. The other two of the four third ground holes are located on both sides of the extension line of the line connecting the two second vias.

10. The interface circuit module according to claim 9, characterized in that, The fourth spacing between the target third ground hole and the reference second via is equal to the fifth spacing, wherein the fifth spacing is the spacing between the two second vias included in the second via pair, the target third ground hole is each of the four third ground holes, and the reference second via is the via in the second via pair that is closest to the target third ground hole.

11. The interface circuit module according to claim 10, characterized in that, The fifth spacing is 31.5 mils, and the sixth spacing is 24 mils. The sixth spacing is the spacing between the target third borehole and the reference third borehole. The target third borehole is each of the two third boreholes, and the reference third borehole is the borehole among the other two third boreholes that is closest to the target third borehole.

12. The interface circuit module according to claim 11, characterized in that, The first included angle is greater than or equal to 15° and less than or equal to 22.5°.

13. The interface circuit module according to claim 1, characterized in that, The output signal aperture group includes: a third via pair and a first capacitor pair; The first capacitor pair is located between the third via pair and the connector pad group. Multiple sets of the first capacitor pairs are electrically connected to the connector pad group. The distances of adjacent first capacitor pairs from the connector pad group are different.

14. The interface circuit module according to claim 13, characterized in that, The line connecting the two third vias included in the target third via pair is parallel to the connector pad group; The second angle between the line connecting the two third vias included in the reference third via pair and the second vertical direction of the connector pad group is greater than 0° and less than 90°. The third via pair included in the multiple sets of output signal via groups includes: the target third via pair and the reference third via pair.

15. The interface circuit module according to claim 14, characterized in that, The target third via is located in the first region, which is a region on the interface circuit module where there are no other traces. The reference third via is located in the second region, which is the area on the interface circuit module where other traces exist.

16. The interface circuit module according to claim 15, characterized in that, The distance between the projection of the other traces onto the plane where the reference third via pair is located and the reference third via falls within the target distance range, wherein the reference third via is the via in the reference third via pair that is closest to the other traces, and the target distance range is used to control the signal integrity of the signals transmitted by the reference third via pair and the signals transmitted by the other traces.

17. The interface circuit module according to claim 16, characterized in that, The target distance range is greater than or equal to 20 mils and less than or equal to 55 mils.

18. The interface circuit module according to claim 13, characterized in that, The target hole group in the multiple sets of output signal hole groups further includes: two fourth ground holes; the reference hole group in the multiple sets of output signal hole groups further includes: four fifth ground holes. Wherein, the two fourth ground holes are located between the straight line containing the two third vias of the third via pair in the target hole group and the straight line containing the two first capacitors of the first capacitor pair in the target hole group; Specifically, two of the four fifth ground holes are located between the first straight line containing the two third vias of the third via pair in the reference hole group and the second straight line containing the two first capacitors of the first capacitor pair in the reference hole group. The two fifth ground holes and the other two fifth ground holes of the four fifth ground holes are located on both sides of the first straight line.

19. The interface circuit module according to claim 18, characterized in that, The seventh spacing between the target fourth ground hole and the reference third via is equal to the eighth spacing, wherein the eighth spacing is the spacing between the two third vias included in the third via pair in the target hole group, the target fourth ground hole is each of the two fourth ground holes, and the reference third via is the via that is closest to the target fourth ground hole in the third via pair included in the target hole group; The ninth spacing between the target fifth ground hole and the target third via is equal to the tenth spacing, wherein the tenth spacing is the spacing between the two third vias included in the third via pair in the reference hole group, the target fifth ground hole is each of the four fifth ground holes, and the target third via is the via that is closest to the target fifth ground hole in the third via pair included in the reference hole group.

20. The interface circuit module according to claim 1, characterized in that, The output signal aperture group includes: a fourth via pair and a second capacitor pair; Wherein, the line connecting the two second capacitors included in the second capacitor pair is perpendicular to the connector pad group, and the distance from the second capacitor pair included in the multiple sets of output signal hole groups to the connector pad group is the same.

21. The interface circuit module according to claim 20, characterized in that, The distance from the second capacitor pair included in the multiple sets of output signal hole groups to the connector pad group is greater than or equal to 120 mils.

22. The interface circuit module according to claim 20, characterized in that, The connections between the fourth via pairs included in the multiple sets of output signal hole groups are all perpendicular to the connector pad group, and the fourth via pairs included in the multiple sets of output signal hole groups are all located on the same side of the second capacitor pair in their respective output signal hole groups.

23. The interface circuit module according to claim 22, characterized in that, The output signal hole group further includes: four sixth ground holes, wherein two of the four sixth ground holes are located between the third straight line containing the two fourth vias included in the fourth via pair and the fourth straight line containing the two second capacitors included in the second capacitor pair, and the two sixth ground holes and the other two sixth ground holes are located on both sides of the third straight line.

24. The interface circuit module according to claim 23, characterized in that, The eleventh spacing between the target sixth ground hole and the reference fourth via is equal to the twelfth spacing, wherein the twelfth spacing is the spacing between the two fourth vias included in the fourth via pair, the target sixth ground hole is each of the four sixth ground holes, and the reference fourth via is the via in the fourth via pair that is closest to the target sixth ground hole.

25. The interface circuit module according to claim 24, characterized in that, The twelfth spacing is 31.5 mils, and the thirteenth spacing is 24 mils. The thirteenth spacing is the spacing between the candidate sixth borehole and the reference sixth borehole. The candidate sixth borehole is each of the two sixth boreholes. The reference sixth borehole is the borehole among the other two sixth boreholes that is closest to the candidate sixth borehole.

26. The interface circuit module according to claim 23, characterized in that, The line connecting the two sixth ground holes is perpendicular to the connector pad group, and the line connecting the other two sixth ground holes is perpendicular to the connector pad group.

27. The interface circuit module according to claim 1, characterized in that, The target trace width of the target trace segment is greater than the reference trace width of the reference trace segment. In the first trace and / or the second trace, when the trace width is the reference trace width, the target impedance of the target trace segment is greater than the reference impedance of the reference trace segment. The first trace is the trace between the input signal via group and the connector pad group, and the second trace is the trace between the output signal via group and the connector pad group.

28. The interface circuit module according to claim 27, characterized in that, The target trace width is determined based on the target capacitor area and the target distance. The target capacitor area is determined based on the trace distance of the target trace segment, the trace distance of the reference trace segment, the reference trace width, and the target distance. The target distance is the distance between the starting point and the ending point of the target trace segment.

29. The interface circuit module according to claim 1, characterized in that, The input signal hole group includes a fifth via pair, and the output signal hole group includes a sixth via pair. The distance between vias located inside adjacent fifth via pairs is greater than or equal to 160 mils; and / or, The distance between the vias located on the inner side of the adjacent sixth via pair is greater than or equal to 160 mils.

30. The interface circuit module according to claim 1, characterized in that, The input signal hole group includes a seventh via pair, and the output signal hole group includes an eighth via pair. The distance between the vias located on the inner side of adjacent seventh via pairs is 115 mils; and / or, The distance between the vias located on the inner side of the adjacent eighth via pair is 115 mils.

31. The interface circuit module according to claim 1, characterized in that, The input signal hole group includes a ninth via pair, and the output signal hole group includes a tenth via pair. When the distance between vias located inside adjacent ninth via pairs is less than 160 mils, and / or the distance between vias located inside adjacent tenth via pairs is less than 160 mils, the circuit board thickness of the interface circuit module is determined based on the signal crosstalk generated between vias with a distance of less than 160 mils.

32. A server motherboard, characterized in that, include: At least one processor pad group and at least one interface circuit module as described in any one of claims 1 to 31, wherein the interface circuit module is electrically connected to the processor pad group.

33. The server motherboard according to claim 32, characterized in that, At least one processor pad group includes: a first processor pad group and a second processor pad group; at least one of the interface circuit modules includes: a first interface circuit module, a second interface circuit module, a third interface circuit module and a fourth interface circuit module. The first interface circuit module, the second interface circuit module, the third interface circuit module, and the fourth interface circuit module are all electrically connected to the processor pad group. The first interface circuit module, the second interface circuit module, the third interface circuit module, and the fourth interface circuit module are arranged sequentially along the direction from the first processor pad group to the second processor pad group. The first connection between the first interface circuit module and the fourth interface circuit module, the second connection between the second interface circuit module and the third interface circuit module, and the third connection between the first processor pad group and the second processor pad group are parallel, and the distance between the first connection and the third connection is less than the distance between the second connection and the third connection.

34. The server motherboard according to claim 33, characterized in that, The server motherboard further includes: a memory slot pad group, wherein the memory slot pad group is located between the first processor pad group and the second processor pad group, and a heat dissipation channel is provided between the memory slot pad groups. The first interface circuit module, the second interface circuit module, the third interface circuit module and the fourth interface circuit module are all disposed on the extension line of the heat dissipation channel, and the memory slot pad group and the heat dissipation channel are both perpendicular to the third connection line.

35. The server motherboard according to claim 34, characterized in that, The location of the first interface circuit module is determined according to the following formula: L1 2 +(L2+D2) 2 =D1 2 3 inches ≤ D1 ≤ (TH1 + 3) inches, D2 ≥ TH2 inches; L1 is the distance from the projection of the first interface circuit module onto the third connection line to the first processor pad group, (L2+D2) is the distance from the first interface circuit module to the third connection line, D2 is the vertical distance from the first interface circuit module to the memory slot pad group, D1 is the distance from the first interface circuit module to the first processor pad group, TH1 is the first threshold, and TH2 is the second threshold.

36. The server motherboard according to claim 35, characterized in that, The location of the fourth interface circuit module is determined according to the following formula: L3 2 +(L4+D4) 2 =D3 2 3 inches ≤ D3 ≤ (TH3 + 3) inches, D4 ≥ TH4 inches; L3 is the distance from the projection of the fourth interface circuit module onto the third connection line to the second processor pad group, (L4+D4) is the distance from the fourth interface circuit module to the third connection line, D4 ​​is the vertical distance from the fourth interface circuit module to the memory slot pad group, D3 is the distance from the fourth interface circuit module to the second processor pad group, TH3 is the third threshold, and TH4 is the fourth threshold.

37. The server motherboard according to claim 34, characterized in that, The connector pad groups in the first interface circuit module, the second interface circuit module, the third interface circuit module, and the fourth interface circuit module are all arranged perpendicularly to the heat dissipation channel; or... The connector pad groups in the first interface circuit module, the second interface circuit module, the third interface circuit module, and the fourth interface circuit module all have a third included angle with the third connection line. The third included angle is determined based on the heat dissipation requirements of the memory electrically connected to the memory slot to which the memory slot pad group is soldered, the distance between the first interface circuit module and the first processor pad group, and the distance between the fourth interface circuit module and the second processor pad group.

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