Single-transistor NOR flash memory with a pair structure and manufacturing method thereof

Abstract

The application provides a single memory tube NOR flash memory with a group pair structure and a manufacturing method thereof. In the manufacturing method, a second dielectric layer on a substrate covers a first contact structure on a group pair storage unit; a plurality of first self-aligned openings of an etching stop layer on the second dielectric layer respectively correspond to positions of the plurality of first contact structures, and the width of the first self-aligned openings is smaller than the width of the first contact structure; a third dielectric layer and a plurality of spindle structures are sequentially generated on the etching stop layer; a sidewall is formed on both sides of each spindle structure; the spindle structure is removed; the third dielectric layer and the second dielectric layer are etched to form a plurality of local bit line grooves under the mask of the sidewall and the limitation of the etching stop layer, and a part of the bottom surface of a local bit line groove is located below the first self-aligned opening and exposes a column of first contact structures; and a plurality of local bit lines are formed by filling the local bit line grooves with conductive materials. In this way, the spacing between adjacent local bit lines can be reduced, which is beneficial to the reduction of the flash memory area.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and particularly relates to a single storage tube NOR flash memory with a group pair structure and a manufacturing method thereof. BACKGROUND

[0002] Flash memory is a kind of nonvolatile semiconductor memory chip, which can keep the stored data information even in the case of power failure. Moreover, flash memory has the advantages of small size, low power consumption and not easy to be damaged by physical damage, and thus has been widely applied.

[0003] Figure 1 A layout diagram of a storage array of the single storage tube NOR flash memory with a group pair structure. Figure 2 A structure diagram of a group pair storage unit of the single storage tube NOR flash memory with a group pair structure. Figure 1 and Figure 2 As shown in the structure diagram of the group pair storage unit, in the structure of the single storage tube NOR flash memory with a group pair structure, two local bit lines are a group, such as the local bit lines BLm and BLm+1 are a group, and the spacing between the local bit lines in the same group limits the reduction of the lateral size of the group pair storage unit, which affects the size reduction of the single storage tube NOR flash memory with a group pair structure. SUMMARY

[0004] One of the purposes of the present application is to provide a single storage tube NOR flash memory with a group pair structure and a manufacturing method thereof, which can reduce the spacing between adjacent local bit lines, is beneficial to the area reduction of the group pair storage unit of the single storage tube NOR flash memory with a group pair structure, and improves the storage density of the single storage tube NOR flash memory with a group pair structure.

[0005] In order to achieve the above object, the application provides a manufacturing method of a group pair structure single storage tube NOR flash memory. The manufacturing method of the group pair structure single storage tube NOR flash memory comprises the following steps: providing a substrate, wherein the substrate comprises a storage array area, and the storage array area has a plurality of group pair storage units arranged in rows and columns, one group pair storage unit comprises two storage tubes with source areas connected, each storage tube has a first contact structure on the drain area, one column of group pair storage units corresponds to two columns of first contact structures, and the two first contact structures of one group pair storage unit are located in different first contact structure columns; generating a second dielectric layer on the substrate, wherein the second dielectric layer covers a plurality of first contact structures; generating an etching stop layer on the second dielectric layer, wherein the etching stop layer has a plurality of first self-aligned openings, one first self-aligned opening corresponds to the position of one first contact structure, and the width of the first self-aligned opening is smaller than the width of the first contact structure; generating a third dielectric layer on the etching stop layer, wherein the third dielectric layer covers the etching stop layer and the second dielectric layer; generating a plurality of spindle structures on the third dielectric layer, one spindle structure is arranged on one column of group pair storage units, and one spindle structure is located above one column of first contact structures; forming a side wall on both sides of each spindle structure, the side wall between adjacent two spindle structures has a gap, and the gap is located above one column of first contact structures which is not arranged with a spindle structure; removing the spindle structure; etching the third dielectric layer and the second dielectric layer under the mask of the side wall and under the limitation of the etching stop layer and stopping on the etching stop layer and the first contact structure to form a plurality of local bit line grooves, one part of the bottom surface of one local bit line groove is located on the etching stop layer and one part of the bottom surface is located below the first self-aligned opening and exposes one column of first contact structures; and filling the local bit line grooves with conductive material to form a plurality of local bit lines, one local bit line partially passes through the corresponding first self-aligned opening and connects one column of first contact structures.

[0006] Optionally, in the step of providing the substrate, the storage array area has a plurality of first transistors as selection tubes, the plurality of first transistors are arranged at the end of the plurality of columns of group pair storage units respectively, the source area of the first transistor is connected with the drain area of the adjacent storage tube, and the first transistor has a second contact structure on the drain area.

[0007] The substrate further comprises a peripheral circuit area; in the step of providing the substrate, a plurality of second transistors and a plurality of third contact structures connected with the second transistors are formed in the peripheral circuit area.

[0008] The second dielectric layer covers the second contact structures and the third contact structures in the step of forming the second dielectric layer on the substrate;

[0009] The etching stop layer has a plurality of second self-aligned openings and a plurality of third self-aligned openings in the step of forming the etching stop layer on the second dielectric layer, one of the second self-aligned openings corresponds to the position of one of the second contact structures, and the width of the second self-aligned opening is smaller than the width of the second contact structure, one of the third self-aligned openings corresponds to the position of one of the third contact structures;

[0010] The third dielectric layer covers the peripheral circuit region in the step of forming the third dielectric layer on the etching stop layer.

[0011] Optionally, the mandrel structures extend above the corresponding second contact structures in the step of forming a plurality of mandrel structures on the third dielectric layer, and the peripheral circuit region is free of the mandrel structures.

[0012] Optionally, a barrier layer is formed on the substrate after the mandrel structures are removed and before the third dielectric layer and the second dielectric layer are etched and stopped on the etching stop layer and the first contact structures, the barrier layer has a first opening and a plurality of second openings, the first opening exposes the formation region of a plurality of the group of memory cells, one of the second openings corresponds to the position of one of the second contact structures, the barrier layer covers the partial region between the first transistor and the memory transistor to cut off the subsequently formed partial bit line recess, and the barrier layer covers the peripheral circuit region.

[0013] Optionally, the third dielectric layer and the second dielectric layer are etched and stopped on the etching stop layer and the first contact structures in the step, the side wall and the barrier layer are used as a common mask, a plurality of connection recesses are formed on the second contact structures while the partial bit line recess is formed, a part of the bottom surface of the connection recess is located on the etching stop layer and a part of the bottom surface is located below the second self-aligned opening and exposes the corresponding second contact structure; conductive material is filled in the partial bit line recess to form a plurality of partial bit lines in the step of filling conductive material in the partial bit line recess to form a plurality of partial bit lines, and conductive material is filled in the connection recess to form a first conductive structure connected to the second contact structure, the partial bit line and the first conductive structure both belong to a zero-layer metal layer.

[0014] Optionally, after forming the partial bit lines and the first conductive structures, the method further comprises: forming a fourth dielectric layer on the substrate, the fourth dielectric layer covering the third dielectric layer, the partial bit lines and the first conductive structures; etching the fourth dielectric layer, the third dielectric layer and the second dielectric layer and stopping on the first conductive structures and the third contact structures, forming a plurality of first vias and a plurality of second vias, one first via exposing one first conductive structure and one second via exposing one third contact structure through one third self-aligned opening; filling the first vias and the second vias with conductive material to form first conductive holes and second conductive holes; and forming a first metal layer on the substrate, the first metal layer comprising a plurality of metal lines, the first conductive holes and the second conductive holes being connected to corresponding metal lines respectively.

[0015] Optionally, the first vias and the second vias are formed simultaneously.

[0016] Optionally, the first conductive holes are rectangular or elliptical in cross section parallel to the substrate, and the short side width of the first conductive holes is less than the width of the second conductive holes.

[0017] Optionally, the width of the first contact structures is less than the width of the third contact structures, and the width of the second contact structures is equal to the width of the first contact structures.

[0018] Optionally, the pitch value of two adjacent partial bit lines is less than the pitch value of two adjacent first contact structures in the same row.

[0019] Optionally, the pitch value of two adjacent partial bit lines is 1 / 2 of the pitch value of two adjacent first contact structures in the same row.

[0020] The application further provides a group pair structure single storage tube NOR flash memory. The group pair structure single storage tube NOR flash memory comprises: a substrate comprising a storage array region, the storage array region comprising a plurality of group pair storage units arranged in rows and columns, one group pair storage unit comprising two storage tubes connected by two source regions, each storage tube having a first contact structure on a drain region, one column of group pair storage units corresponding to two columns of first contact structures and two first contact structures of one group pair storage unit being located in different first contact structure columns; a second dielectric layer located on the substrate and covering a plurality of first contact structures; an etching stop layer located on the second dielectric layer and having a plurality of first self-aligned openings, one first self-aligned opening corresponding to the position of one first contact structure and the width of the first self-aligned opening being smaller than the width of the first contact structure; and a plurality of local bit lines, one part of one local bit line being located above the etching stop layer and the other part passing through the corresponding first self-aligned opening and connecting one column of first contact structures.

[0021] The application provides a group pair structure single storage tube NOR flash memory and a manufacturing method thereof. The third dielectric layer and the second dielectric layer are etched and stopped on the etching stop layer and the first contact structure under the mask of the sidewall and the limitation of the etching stop layer, a plurality of local bit line grooves are formed, and a plurality of local bit lines are formed by filling the local bit line grooves with conductive materials. Thus, the self-alignment of the local bit line and the corresponding first contact structure can be realized by using the first self-aligned opening in the etching stop layer, the alignment accuracy between the local bit line and the first contact structure is improved, the width of the first self-aligned opening is smaller than the width of the first contact structure, which is conducive to reducing the distance between adjacent local bit lines, thereby reducing the area of the group pair storage unit of the group pair structure single storage tube NOR flash memory and improving the storage density of the group pair structure single storage tube NOR flash memory. The second dielectric layer is generated on the first contact structure, the etching stop layer is generated on the second dielectric layer, and the part of the local bit line in contact with the first contact structure is located below the etching stop layer and the rest part is located above the etching stop layer, i.e., the second dielectric layer and the etching stop layer can increase the distance between the part of the local bit line not directly in contact with the first contact structure and the first contact structure, which is conducive to avoiding the short circuit caused by the breakdown between the first contact structure and the adjacent local bit line (i.e., the local bit line not electrically connected to the first contact structure), ensuring the reliability of the flash memory when the distance between adjacent local bit lines is reduced and the area of the group pair storage unit is reduced, and facilitating the miniaturization of the flash memory area.

[0022] Further, the manufacturing method of the group pair structure single storage tube NOR flash memory provided by the application can realize the process compatibility of the storage array and the peripheral circuit. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 This is a layout diagram of a storage array for a single-tube NOR flash memory with a paired structure.

[0024] Figure 2 This is an architecture diagram of a pair of NOR flash memory cells with a single-tube storage structure.

[0025] Figure 3 This is a flowchart illustrating a method for fabricating a single-tube NOR flash memory with a paired structure according to an embodiment of the present invention.

[0026] Figure 4 This is a top view of a substrate after a memory tube, a first transistor, and a peripheral second transistor have been formed on the substrate in one embodiment of the present invention.

[0027] Figure 5 To form an etch stop layer on the substrate and then along Figure 4 The position shown by line AB is a sectional view.

[0028] Figure 6 To form an etch stop layer on the substrate and then along Figure 4 A cross-sectional view of the location indicated by the CD line.

[0029] Figure 7 This is a top view of a mandrel structure formed on a substrate in one embodiment of the present invention.

[0030] Figure 8 This is a cross-sectional view along line AB after the mandrel structure is formed on the substrate in one embodiment of the present invention.

[0031] Figure 9 This is a cross-sectional view along line CD at the position after the mandrel structure is formed on the substrate, according to one embodiment of the present invention.

[0032] Figure 10 This is a cross-sectional view along line AB at the position after the sidewalls are formed on the substrate, according to one embodiment of the present invention.

[0033] Figure 11 This is a cross-sectional view along line CD at the position shown after the sidewalls are formed on the substrate, according to one embodiment of the present invention.

[0034] Figure 12 This is a top view of a substrate after a barrier layer has been formed in one embodiment of the present invention.

[0035] Figure 13 This is a cross-sectional view along line AB at the position shown in one embodiment of the present invention after a barrier layer has been formed on the substrate.

[0036] Figure 14 This is a cross-sectional view along line CD at the position shown in one embodiment of the present invention after a barrier layer has been formed on the substrate.

[0037] Figure 15 A cross-sectional view along the position shown by the line AB after forming the partial bit line groove on the substrate in one embodiment of the present application.

[0038] Figure 16 A cross-sectional view along the position shown by the line CD after forming the partial bit line groove on the substrate in one embodiment of the present application.

[0039] Figure 17 A plan view after forming the partial bit line on the substrate in one embodiment of the present application.

[0040] Figure 18 A cross-sectional view along the position shown by the line AB after forming the partial bit line on the substrate in one embodiment of the present application.

[0041] Figure 19 A cross-sectional view along the position shown by the line CD after forming the partial bit line on the substrate in one embodiment of the present application.

[0042] Figure 20 A cross-sectional view along the position shown by the line AB after forming the fourth dielectric layer on the substrate in one embodiment of the present application.

[0043] Figure 21 A cross-sectional view along the position shown by the line CD after forming the fourth dielectric layer on the substrate in one embodiment of the present application.

[0044] Figure 22 A plan view of the single storage tube NOR flash memory provided in one embodiment of the present application.

[0045] Figure 23 A cross-sectional view along the position shown by the line AB in one embodiment of the present application. Figure 22

[0046] A cross-sectional view along the position shown by the line CD in one embodiment of the present application. Figure 24 Figure 22

[0047] ​​Explanation of reference numerals: 10a - memory array region; 10b - peripheral circuit region; 11 - substrate; 111 - active region; 112 - isolation structure; 113 - group pair memory cell; 114a - memory tube gate line; 114b - first transistor gate line; 114c - second transistor gate; 115 - first transistor; 116 - second transistor; 12 - first dielectric layer; 131 - first contact structure; 132 - second contact structure; 133 - third contact structure; 14 - second dielectric layer; 15 - etching stop layer; 151 - first self-aligned opening; 152 - second self-aligned opening; 153 - third self-aligned opening; 16 - third dielectric layer; 17 - mandrel structure; 18 - side wall; 18a - gap; 18b - gap; 19 - barrier layer; 19a - first opening; 19b - second opening; 20 - local bit line groove; 21 - connection groove; 22 - local bit line; 23 - first conductive structure; 24 - fourth dielectric layer; 25 - first conductive hole; 25a - first via hole; 26 - second conductive hole; 26a - second via hole; 27 - metal line. DETAILED DESCRIPTION

[0048] The group pair structure single memory tube NOR flash memory and the manufacturing method thereof provided by the present application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are all in a very simplified form and all use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application.

[0049] Figure 3 The flowchart of the manufacturing method of the group pair structure single memory tube NOR flash memory provided by an embodiment of the present application is shown in FIG. 1. According to the manufacturing method of the group pair structure single memory tube NOR flash memory provided by the embodiment, the manufacturing method of the group pair structure single memory tube NOR flash memory includes the following steps. Figure 3

[0050] Step S1, providing a substrate, the substrate including a memory array region, the memory array region having a plurality of group pair memory cells arranged in rows and columns, one group pair memory cell including two memory tubes with source regions connected, each memory tube having a first contact structure on the drain region, one column of group pair memory cells corresponding to two columns of first contact structures and the two first contact structures of one group pair memory cell being located in different first contact structure columns;

[0051] Step S2, generating a second dielectric layer on the substrate, the second dielectric layer covering a plurality of first contact structures;

[0052] Step S3, generating an etching stop layer on the second dielectric layer, the etching stop layer having a plurality of first self-aligned openings, one first self-aligned opening corresponding to the position of one first contact structure, and the width of the first self-aligned opening being smaller than the width of the first contact structure; ​

[0053] Step S4: A third dielectric layer is generated on the etch stop layer, and the third dielectric layer covers the etch stop layer and the second dielectric layer;

[0054] Step S5: Generate multiple spindle structures on the third dielectric layer, set one spindle structure on a column of paired storage cells, and place one spindle structure above a column of first contact structures.

[0055] Step S6: Sidewalls are formed on both sides of each mandrel structure, and there is a gap between the sidewalls of two adjacent mandrel structures. The gap is located above the first contact structure in a row that does not have the mandrel structure set above it.

[0056] Step S7: Remove the mandrel structure;

[0057] Step S8: Under the cover of the sidewalls and the constraint of the etch stop layer, the third dielectric layer and the second dielectric layer are etched and the etching stops on the etch stop layer and the first contact structure, forming multiple local bit line grooves. A portion of the bottom surface of one local bit line groove is located on the etch stop layer, and a portion of the bottom surface is located below the first self-aligned opening, exposing a row of first contact structures; and

[0058] Step S9: Fill the local bit line groove with conductive material to form multiple local bit lines. One local bit line passes through the corresponding first self-aligned opening and connects to a column of first contact structures.

[0059] Figures 4 to 24 This is a schematic diagram illustrating the process of fabricating a single-tube NOR flash memory with a paired structure according to an embodiment of the present invention. The following is in conjunction with... Figure 3 , Figures 4 to 24 The method for fabricating the single-tube NOR flash memory with the paired structure of this application is described.

[0060] Figure 4 This is a top view of a substrate after a memory tube, a first transistor, and a peripheral second transistor have been formed on the substrate in one embodiment of the present invention. Figure 5 To form an etch stop layer on the substrate and then along Figure 4 The position shown by line AB is a sectional view. Figure 6 To form an etch stop layer on the substrate and then along Figure 4 A cross-sectional view of the location indicated by the CD line.

[0061] refer to Figure 4 , Figure 5 and Figure 6 As shown, the substrate 11 provided in step S1 includes a storage array region 10a and a peripheral circuit region 10b. It should be noted that, for ease of illustration, the peripheral circuit region is shown on the CD line in the accompanying drawings of this application. In practice, the positional relationship between the storage array region 10a and the peripheral circuit region 10b is not limited to this.

[0062] With reference to Figure 4 , Figure 5 and Figure 6 shown, the storage array region 10a has a plurality of group pair storage cells 113 arranged in rows and columns, one group pair storage cell 113 includes two storage tubes with source regions connected, each storage tube has a first contact structure 131 on the drain region, one column of group pair storage cells 113 corresponds to two columns of first contact structures 131 and the two first contact structures 131 of one group pair storage cell are located in different first contact structure columns.

[0063] For example, the substrate 11 can include a plurality of active regions 111 and isolation structures 112 separating the active regions 111, one column of group pair storage cells 113 is located on the same active region 111, and the two storage tubes of the same group pair storage cell 113 are arranged in sequence in the elongation direction of the active region 111. For example, the X direction is the elongation direction of the active region 111, and a plurality of active regions 111 are arranged in sequence in the Y direction. In this embodiment, the X direction is the column direction, and the Y direction is the row direction. The active region 111 can be linearly elongated or tortuously elongated. For example, the isolation structure 112 can be a shallow trench isolation structure (STI), but is not limited thereto.

[0064] As shown in Figure 4 , a plurality of storage tube gate lines 114a are formed on the substrate 11, the storage tube gate lines 114a span a plurality of active regions 111, the storage tube gate lines 114a serve as the gate of the storage tube and as the word line. The source region and the drain region of the storage tube are located in the active region 111 on both sides of the storage tube gate line 114a.

[0065] Referring to Figure 4 and Figure 6 shown, the storage array region 10a can have a plurality of first transistors 115 as selection tubes, the plurality of first transistors 115 are arranged at the end of a plurality of columns of group pair storage cells 113, the source region of the first transistor 115 is connected with the drain region of the adjacent storage tube, and the drain region of the first transistor 115 has a second contact structure 132. The plurality of first transistors 115 can be arranged in a row, and the substrate 11 can have a first transistor gate line 114b formed thereon, which serves as the gate of the plurality of first transistors 115. The source region and the drain region of the first transistor 115 are formed in the active region 111 on both sides of the first transistor gate line 114b.

[0066] It should be noted that Figure 4In the array, the group pair storage cells on the leftmost active region 111 are dummy group pair storage cells, and the rest of the group pair storage cells are effective group pair storage cells. The storage tubes in the dummy group pair storage cells and the storage tubes on the right side of the effective group pair storage cells have the same or similar sizes. The dummy group pair storage cell column helps to improve the process window of the storage array. The end of the dummy group pair storage cell column is not provided with a first transistor as a selection tube. The end of the effective group pair storage cell column is provided with a first transistor 115 as a selection tube.

[0067] For example, a column of group pair storage cells 113 and the first transistor 115 at the end thereof can be formed on the same active region 111, which is conducive to saving chip area.

[0068] The active region 111 is formed with a corresponding well region. When the storage tube is N-type, the well region can be a P-well, but is not limited thereto.

[0069] Reference Figure 4 and Figure 6 As shown in FIG. 1, the peripheral circuit region 10b can be formed with a plurality of second transistors 116 and a plurality of third contact structures 133 connected to the second transistors 116. For example, the substrate 11 is formed with a second transistor gate 114c, and the source region and the drain region of the second transistor 116 can be formed in the active region on both sides of the second transistor gate 114c. The second transistor 116 is formed with a plurality of third contact structures 133, part of the third contact structures 133 are connected to the second transistor gate 114c, and part of the third contact structures 133 are connected to the source region or the drain region of the second transistor 116.

[0070] For example, the materials of the storage tube gate line 114a, the first transistor gate line 114b, and the second transistor gate line 114c can be the same, such as polycrystalline silicon, but are not limited thereto. The storage tube gate line 114a, the first transistor gate line 114b, and the second transistor gate line 114c can be formed by etching the same polycrystalline silicon material layer, but are not limited thereto.

[0071] It should be noted that the width of the first contact structure 131 can be smaller than the width of the third contact structure 133, and the width of the second contact structure 132 can be equal to the width of the first contact structure 131, but is not limited thereto. For example, the conductive materials in the first contact structure 131, the second contact structure 132, and the third contact structure 133 can all include tungsten (W), but are not limited thereto.

[0072] Reference Figure 5 and Figure 6As shown, the first dielectric layer 12 is formed on the substrate 11, the first contact structure 131, the second contact structure 132 and the third contact structure 133 are all formed in the first dielectric layer 12, and the top surfaces of the first contact structure 131, the second contact structure 132 and the third contact structure 133 can be flush with the top surface of the first dielectric layer 12 within a process error range, so that the top surfaces of the first contact structure 131, the second contact structure 132 and the third contact structure 133 are exposed from the first dielectric layer 12, but the application is not limited thereto. For example, the material of the first dielectric layer 12 can be silicon oxide, but the application is not limited thereto.

[0073] Step S2 is performed, referring to Figure 5 and Figure 6 As shown, the second dielectric layer 14 is formed on the substrate 11, and the second dielectric layer 14 covers the plurality of first contact structures 131.

[0074] More specifically, the second dielectric layer 14 is located on the first dielectric layer 12, the second dielectric layer 14 covers the memory array region 10a and the peripheral circuit region 10b, or in other words, the second dielectric layer 14 covers the entire substrate 11, and the second dielectric layer 14 also covers the second contact structure 132 and the third contact structure 133. For example, the material of the second dielectric layer 14 includes but is not limited to silicon oxide. For example, the thickness of the second dielectric layer 14 can be greater than or equal to 20 nm and less than or equal to 40 nm, for example, 30 nm, but the application is not limited thereto.

[0075] Step S3 is performed, as shown in Figure 5 The etching stop layer 15 is formed on the second dielectric layer 14, the etching stop layer 15 has a plurality of first self-aligned openings 151, one first self-aligned opening 151 corresponds to one first contact structure 131, and the width of the first self-aligned opening 151 is less than the width of the first contact structure 131.

[0076] It should be noted that, compared with the width of the first self-aligned opening being greater than or equal to the width of the first contact structure, the application makes the width of the first self-aligned opening 151 less than the width of the first contact structure 131, so that even if there is an alignment deviation between the first self-aligned opening 151 and the corresponding first contact structure 131, the boundary of the first self-aligned opening 151 is not easy to exceed the boundary of the first contact structure 131, which is beneficial to improve the alignment accuracy of the first self-aligned opening 151 and the first contact structure 131, and is also beneficial to realize the area reduction of the group pair structure of the single memory tube NOR flash memory.

[0077] Referring to Figure 6As shown, the etching stop layer 15 is also disposed in the peripheral circuit region 10b, and the etching stop layer 15 has a plurality of second self-aligned openings 152 and a plurality of third self-aligned openings 153, one second self-aligned opening 152 corresponding to one second contact structure 132 and the width of the second self-aligned opening 152 being smaller than the width of the second contact structure 132, and one third self-aligned opening 153 corresponding to one third contact structure 133.

[0078] In this embodiment, the spacing between the contact structures in the peripheral circuit region 10b can be much larger than the spacing between the contact structures in the memory array region 10a, and the width of the third self-aligned opening 153 can be smaller than, equal to, or larger than the width of the third contact structure 133. On the other hand, since the peripheral circuit region 10b is not provided with the zero layer metal layer M0, the depth of the subsequent second conductive hole needs to be deeper to connect the first metal layer M1 to the third contact structure 133, and therefore the width of the third self-aligned opening 153 can be equal to or larger than the width of the third contact structure 133 to increase the contact area between the second conductive hole and the third contact structure 133.

[0079] In an embodiment of the present application, the method for generating the etching stop layer 15 on the second dielectric layer 14 can include: depositing an etching stop layer film on the second dielectric layer 14, the etching stop layer film covering the top surface of the substrate 11; coating a photoresist material layer on the etching stop layer film, and performing exposure and development on the photoresist material layer to form a patterned photoresist material layer; etching the etching stop layer film and stopping on the surface of the second dielectric layer 14 or in the second dielectric layer 14 to form the etching stop layer 15, using the patterned photoresist material layer as a mask; and removing the patterned photoresist material layer and performing cleaning. In this way, the process for manufacturing the etching stop layer 15 is relatively simple.

[0080] In another embodiment of the present application, the method for generating the etching stop layer 15 on the second dielectric layer 14 can include: depositing an etching stop layer film on the second dielectric layer 14, the etching stop layer film covering the top surface of the substrate 11; forming a hard mask layer on the etching stop layer film; coating a photoresist material layer on the hard mask layer, and performing exposure and development on the photoresist material layer using a mask used in manufacturing the first contact structure 131 to form a patterned photoresist material layer; etching the hard mask layer to form a plurality of openings using the patterned photoresist material layer as a mask; forming an internal side wall on the inner wall of the plurality of openings of the hard mask layer; etching the etching stop layer film and stopping on the surface of the second dielectric layer 14 or in the second dielectric layer 14 to form the etching stop layer 15, using the hard mask layer and the internal side wall as a mask; and removing the patterned photoresist material layer, the hard mask layer, and the internal side wall. In this way, manufacturing the etching stop layer 15 helps to save mask plates.

[0081] The material of the etching stop layer 15 is different from the material of the second dielectric layer 14 and the material of the third dielectric layer to be formed later. The material of the etching stop layer 15 can be silicon nitride or aluminum oxide, etc.

[0082] Figure 7 A top view of the substrate after forming the mandrel structure in an embodiment of the present application. Figure 8 A cross-sectional view along the line AB of the substrate after forming the mandrel structure in an embodiment of the present application. Figure 9 A cross-sectional view along the line CD of the substrate after forming the mandrel structure in an embodiment of the present application.

[0083] Reference Figure 8 and Figure 9 As shown in FIG. 4, step S4 is performed to form a third dielectric layer 16 on the etching stop layer 15, and the third dielectric layer 16 covers the etching stop layer 15 and the second dielectric layer 14.

[0084] In this embodiment, the third dielectric layer 16 covers the memory array region 10a and the peripheral circuit region 10b, and the third dielectric layer 16 fills the first self-aligned opening 151, the second self-aligned opening 152 and the third self-aligned opening 153.

[0085] For example, the material of the third dielectric layer 16 includes but is not limited to silicon oxide. The materials of the second dielectric layer 14 and the third dielectric layer 16 can be the same, and for the sake of simplicity of the drawing, Figure 8 and Figure 9 The boundary between the third dielectric layer 16 and the second dielectric layer 14 is not shown.

[0086] For example, the thickness of the third dielectric layer 16 can be greater than or equal to 100 nm and less than or equal to 140 nm, for example, 125 nm.

[0087] For example, after forming the third dielectric layer 16, a chemical mechanical polishing process or the like can be used to planarize the third dielectric layer 16 to provide a flat growth plane for the subsequent mandrel structure. The thickness of the third dielectric layer 16 removed by the chemical mechanical polishing can be 40 nm to 50 nm, but is not limited thereto.

[0088] Step S5 is performed, and as shown in FIG. 5, a plurality of mandrel structures 17 are formed on the third dielectric layer 16. Figure 7 、 Figure 8 and Figure 9 One mandrel structure 17 is provided above one column of first contact structures 131.

[0089] Reference Figure 7As shown, the plurality of column group pairs of the storage units 113 are provided with the mandrel structures 17 at the same position, for example, all provided on the right column of the first contact structures 131 of the column group pairs of the storage units 113.

[0090] Referring to Figure 7 , Figure 8 and Figure 9 As shown, the mandrel structures 17 can extend above the corresponding second contact structures 132, that is, the mandrel structures 17 can extend to the second contact structures 132 on the first transistors 115 at the end of the corresponding column group pairs of the storage units 113, and the peripheral circuit region 10b is not formed with the mandrel structures 17.

[0091] For example, the pitch value between the two adjacent mandrel structures 17 can be equal to the pitch value between the two adjacent first contact structures 131 in the same row, but is not limited thereto.

[0092] For example, the method for generating the plurality of mandrel structures 17 on the third dielectric layer 16 can include: forming a mandrel material layer on the third dielectric layer 16; forming a patterned mask layer on the mandrel material layer by a photolithography process; and etching the mandrel material layer to form the plurality of mandrel structures 17 by using the patterned mask layer.

[0093] For example, the material of the mandrel structure 17 is different from the third dielectric layer 16, for example, can be amorphous silicon or amorphous carbon, etc.

[0094] Figure 10 is a cross-sectional view of the position shown along the AB line after forming the side wall on the substrate in an embodiment of the present application. Figure 11 is a cross-sectional view of the position shown along the CD line after forming the side wall on the substrate in an embodiment of the present application.

[0095] Step S6 is performed, and referring to Figures 8 to 11 As shown, the side wall 18 is formed on both sides of each mandrel structure 17, and the side wall 18 between the two adjacent mandrel structures 17 has a gap 18a.

[0096] For example, the method for forming the side wall 18 can include: generating a side wall material layer on the third dielectric layer 16, the side wall material layer covering the third dielectric layer 16 and covering the top surface and the sidewall of the mandrel structure 17; removing the side wall material layer on the top surface of the mandrel structure 17 and part of the side wall material layer on the surface of the third dielectric layer 16 by an anisotropic etching process, and retaining the side wall material layer on the sidewall of the mandrel structure 17 as the side wall 18.

[0097] For example, the material of the side wall 18 is different from the material of the mandrel structure 17, and the material of the side wall 18 is different from the material of the third dielectric layer 16. The material of the side wall 18 includes but is not limited to silicon nitride or polysilicon, etc.

[0098] The step S7 is performed to remove the mandrel structure 17. Referring to Figure 10 and Figure 11 As shown, after the mandrel structure 17 is removed, a gap 18b is formed, and the gap 18b or a void 18a is formed right above the first contact structure 131 or the first self-aligned opening 151, and the gap 18b or a void 18a is formed between the first contact structures 131 in the same row.

[0099] Figure 12 A top view of the substrate after forming the blocking layer in an embodiment of the present application. Figure 13 A cross-sectional view of the substrate along the line AB after forming the blocking layer in an embodiment of the present application. Figure 14 A cross-sectional view of the substrate along the line CD after forming the blocking layer in an embodiment of the present application.

[0100] Referring to Figure 12 and Figure 14 As shown, after the mandrel structure 17 is removed, the blocking layer 19 is formed on the substrate 11, and the blocking layer 19 has the first opening 19a and a plurality of second openings 19b, the first opening 19a exposes the formation region of a plurality of group pairs of memory cells, and one second opening 19b corresponds to one second contact structure 132. Exemplarily, the width and length of the second opening 19b can be greater than the width and length of the second contact structure 132.

[0101] In the embodiment, referring to Figure 12 As shown, the blocking layer 19 covers the partial region between the first transistor and the memory transistor to cut off the subsequent locally formed bit line groove, and the blocking layer 19 covers the peripheral circuit region 10b.

[0102] Exemplarily, the blocking layer 19 can be a photoresist layer, but is not limited thereto.

[0103] Figure 15 A cross-sectional view of the substrate along the line AB after forming the locally formed bit line groove in an embodiment of the present application. Figure 16 A cross-sectional view of the substrate along the line CD after forming the locally formed bit line groove in an embodiment of the present application.

[0104] Referring to Figure 13 and Figure 15 As shown, the step S8 is performed to etch the third dielectric layer 16 and the second dielectric layer 14 under the mask of the side wall 18 (actually under the mask of the side wall 18 and the blocking layer 19) and under the limitation of the etching stop layer 15, and stop on the etching stop layer 15 and the first contact structure 131, to form a plurality of locally formed bit line grooves 20, and a part of the bottom surface of one locally formed bit line groove 20 is located on the etching stop layer 15 and a part of the bottom surface is located below the first self-aligned opening 151 and exposes one row of the first contact structures 131.

[0105] Referring to Figure 14 and Figure 16 As shown in FIG. 8, in step S8, a plurality of connection grooves 21 are formed on the second contact structures 132 while forming the partial bit line grooves 20, a part of the bottom surface of the connection grooves 21 is on the etching stop layer 15 and a part of the bottom surface is below the second self-alignment openings 152 and exposes the corresponding second contact structures 132.

[0106] It should be noted that in the process of etching the third dielectric layer 16 and the second dielectric layer 14, when the downward etching encounters the etching stop layer 15, the etching is basically stopped on the etching stop layer 15, while at the positions of the first self-alignment openings 151 and the second self-alignment openings 152, the downward etching of the second dielectric layer 14 can continue and stop on the first contact structures 131 and the second contact structures 132, thereby forming the partial bit line grooves 20 and the connection grooves 21 with stepped bottom surfaces, realizing the self-alignment of the partial bit line grooves 20 and the first contact structures 131, and realizing the self-alignment of the connection grooves 21 and the second contact structures 132.

[0107] Figure 17 FIG. 10 is a top view of the substrate after forming the partial bit lines in an embodiment of the present application. Figure 18 FIG. 11 is a cross-sectional view along the position shown by line AB after forming the partial bit lines on the substrate in an embodiment of the present application. Figure 19 FIG. 12 is a cross-sectional view along the position shown by line CD after forming the partial bit lines on the substrate in an embodiment of the present application.

[0108] Referring to Figure 17 and Figure 18 As shown in FIG. 9, step S9 is performed, the conductive material is filled in the partial bit line grooves 20 to form a plurality of partial bit lines 22, a part of a partial bit line 22 passes through the corresponding first self-alignment openings 151 and connects a column of the first contact structures 131 and a part of the partial bit line 22 is on the etching stop layer 15.

[0109] Referring to Figure 17 and Figure 19 As shown in FIG. 9, in step S9, the conductive material is filled in the connection grooves 21 to form the first conductive structures 23 connected with the second contact structures 132, the partial bit lines 22 and the first conductive structures 23 all belong to the zero layer metal layer M0. Specifically, the first conductive structures 23 can include a conductive hole extending from the second self-alignment openings 152 to the second contact structures 132 and used for connecting the second contact structures 132, and a connection pad connected with the conductive hole and located on the etching stop layer 15, the area of the connection pad is defined by the second opening 19b of the blocking layer 19, and the width and length of the connection pad can be greater than the width and length of the second contact structure, so as to set the conductive hole connected with the upper metal layer on the connection pad later.

[0110] refer to Figures 13 to 19 As shown, by the limitation of the sidewall 18, after etching the third dielectric layer 16 and the second dielectric layer 14, for each row (Y direction is the row direction) of first contact structures 131, a corresponding local bit line groove 20 is formed directly above each first contact structure 131, and a local bit line groove 20 is also formed between two adjacent first contact structures 131 in the same row, thereby providing reference. Figure 17 As shown, for each row of first contact structure 131, a local bit line 22 connected to it is formed directly above each first contact structure 131, and a local bit line 22 not connected to it is also formed between two adjacent first contact structures 131 in the same row. In this way, the pitch value of the two adjacent local bit lines 22 is less than the pitch value of the two adjacent first contact structures 131 in the same row, thereby realizing the area reduction of the grouped storage cell.

[0111] For example, when the width of the spindle structure 17 is equal to the width of the first contact structure 131, and when the width of the spindle structure 17 (i.e., the gap 18b generated by removing the spindle 17), the width of the sidewall 18, and the width of the gap 18a between adjacent sidewalls 18 are equal, the width of the formed local bit line groove 20 is equal to the spacing between adjacent local bit line grooves 20, so that the width of the finally formed local bit line 22 is equal to the spacing between adjacent local bit lines 22. Thus, the pitch value of two adjacent local bit lines 22 can be half of the pitch value of two adjacent first contact structures 131 in the same row. At this time, the width of the paired memory cell can be reduced by 50%, and the flash memory area is well miniaturized.

[0112] For example, a method for forming the local bit line 22 and the first conductive structure 23 may include: depositing a conductive material on a third dielectric layer 16, the conductive material filling the local bit line groove 20 and the connecting groove 21 and covering the top surface of the third dielectric layer 16; performing chemical mechanical polishing (CMP) to remove the conductive material layer on the top surface of the third dielectric layer 16, retaining the conductive material in the local bit line groove 20 as the local bit line 22, and retaining the conductive material in the connecting groove 21 as the first conductive structure 23. For example, the conductive material includes, but is not limited to, tungsten (W).

[0113] It should be noted that the reference Figures 12 to 18As shown, in the embodiment, the left boundary of the first opening 19a of the barrier layer 19 can be located on the left side of the leftmost sidewall 18, i.e. there can be a set distance between the left boundary of the first opening 19a and the left boundary of the leftmost sidewall 18, so that when the local bit line recess 20 is etched with the barrier layer 19 and the sidewall 18 as masks, a local bit line recess 20 can be formed between the left boundary of the first opening 19a and the left boundary of the leftmost sidewall 18, so that a local bit line 22 can be formed; the right boundary of the first opening 19a is located on (i.e. overlapped with) the rightmost sidewall 18, so that the rightmost sidewall 18 can be prevented from continuing to form a local bit line recess on the right side.

[0114] Figure 20 A cross-sectional view of a position shown along the line AB after a fourth dielectric layer is formed on the substrate in an embodiment of the present application. Figure 21 A cross-sectional view of a position shown along the line CD after a fourth dielectric layer is formed on the substrate in an embodiment of the present application.

[0115] Reference Figure 20 and Figure 21 As shown, after the local bit line 22 and the first conductive structure 23 are formed, a fourth dielectric layer 24 is formed on the substrate 11, the fourth dielectric layer 24 covers the third dielectric layer 16, the local bit line 22 and the first conductive structure 23, and the fourth dielectric layer 24 also covers the peripheral circuit region 10b; a patterned mask layer is formed on the fourth dielectric layer 24, the fourth dielectric layer 24, the third dielectric layer 16 and the second dielectric layer 14 are etched with the patterned mask layer as a mask and stopped on the first conductive structure 23 and the third contact structure 133, a plurality of first through holes 25a and a plurality of second through holes 26a are formed, one first through hole 25a exposes one first conductive structure 23, and one second through hole 26a exposes one third contact structure 133 through one third self-aligned opening 153; tungsten or other conductive material is filled in the first through hole 25a and the second through hole 26a to form a first conductive hole 25 and a second conductive hole 26.

[0116] For example, the cross section of the first via hole 25a parallel to the substrate 11 can be rectangular or elliptical, the cross section of the second via hole 26a parallel to the substrate 11 can be square or circular, etc., and the short side width of the first via hole 25a can be smaller than the width of the second via hole 26a. Since the short side width of the first via hole 25a is smaller, the contact area between the bottom of the first via hole 25a and the zero layer metal layer M0 can be appropriately increased by increasing the width of the long side to reduce the contact resistance. In addition, since the sizes and etching depths of the first via hole 25a and the second via hole 26a are different, the final etching time is determined by the via hole structure with a longer required etching time. Since the zero layer metal layer M0 under the via hole has very good etch selectivity, the simultaneous formation of the first via hole 25a and the second via hole 26a does not cause additional process problems.

[0117] In this embodiment, the first via hole 25a and the second via hole 26a can be formed simultaneously in the same etching process. In other embodiments, the first via hole 25a and the second via hole 26a can also be completed separately.

[0118] In this embodiment, the cross section of the first conductive hole 25 parallel to the substrate can be rectangular or elliptical, etc.; and the short side width of the first conductive hole 25 can be smaller than the width of the second conductive hole 26.

[0119] Figure 22 A top view of a single memory tube NOR flash memory according to an embodiment of the present application. Figure 23 A cross-sectional view along the position indicated by the line AB in Figure 22 A cross-sectional view along the position indicated by the line CD in Figure 24 A cross-sectional view along the position indicated by the line CD in Figure 22 A cross-sectional view along the position indicated by the line CD in

[0120] As shown in FIG. 1, a first metal layer M1 is formed on the substrate 11, and the first metal layer M1 includes a plurality of metal lines 27, and the first conductive hole 25 and the second conductive hole 26 are respectively connected to the corresponding metal line 27. Figure 22 Figure 23 As shown in FIG. 1, a first metal layer M1 is formed on the substrate 11, and the first metal layer M1 includes a plurality of metal lines 27, and the first conductive hole 25 and the second conductive hole 26 are respectively connected to the corresponding metal line 27. Figure 24 As shown in FIG. 1, a first metal layer M1 is formed on the substrate 11, and the first metal layer M1 includes a plurality of metal lines 27, and the first conductive hole 25 and the second conductive hole 26 are respectively connected to the corresponding metal line 27.

[0121] Figure 22 As shown in FIG. 1, a first metal layer M1 is formed on the substrate 11, and the first metal layer M1 includes a plurality of metal lines 27, and the first conductive hole 25 and the second conductive hole 26 are respectively connected to the corresponding metal line 27.

[0122] It should be noted that the plurality of local bit lines 22 can be led out through the corresponding conductive holes at the end of the local bit line 22 in a specific area.

[0123] ​​This embodiment also provides a pair-structured single-tube NOR flash memory, which can be manufactured using the above-described method for manufacturing a pair-structured single-tube NOR flash memory.

[0124] refer to Figure 22 , Figure 23 and Figure 24 As shown, the single-cell NOR flash memory with a paired structure includes: a substrate 11, the substrate 11 including a memory array region 10a, the memory array region 10a having a plurality of paired memory cells 113 arranged in rows and columns, a paired memory cell 113 including two memory cells with two source regions connected together, each memory cell having a first contact structure 131 on its drain region, a column of paired memory cells corresponding to two columns of first contact structures 131, and the two first contact structures 131 of a paired memory cell 113 located in different columns of first contact structures; a second dielectric layer 14, the second dielectric layer 1 4 is located on the substrate 11 and covers a plurality of first contact structures 131; an etch stop layer 15 is located on the second dielectric layer 14 and has a plurality of first self-aligned openings 151, one first self-aligned opening 151 corresponds to one first contact structure 131, and the width of the first self-aligned opening 151 is smaller than the width of the first contact structure 131; and a plurality of local bit lines 22, a portion of a local bit line 22 is located above the etch stop layer 15 and another portion passes through the corresponding first self-aligned opening 151 and connects a row of first contact structures 131.

[0125] In this configuration, the two first contact structures on the drain regions of the two storage tubes of a pair of storage cells are respectively connected to two local bit lines 22. The two local bit lines 22 connected to a pair of storage cells form a group. A pair of storage cells 113 are connected to a corresponding group of local bit lines 22. When one of the two storage tubes of a pair of storage cells is used for data reading and data writing, the other is used as a selection tube. The two local bit lines connected to a pair of storage cells can be source lines for each other.

[0126] Other structural components of a single-tube NOR flash memory with a pair structure can be referred to the description of the method above, and will not be repeated here.

[0127] The group pair structure single storage tube NOR flash memory and the manufacturing method thereof provided by the application, under the mask of the side wall 18 and under the limitation of the etching stop layer 15, the third medium layer 16 and the second medium layer 14 are etched and stopped on the etching stop layer 15 and the first contact structure 131, a plurality of local bit line grooves 20 are formed, and then a plurality of local bit lines 22 are formed by filling the local bit line grooves 20 with conductive material, so that the first self-alignment opening 151 in the etching stop layer 15 is used to realize the self-alignment of the local bit line 22 and the corresponding first contact structure 131, the alignment accuracy between the local bit line 22 and the first contact structure 131 is improved, the width of the first self-alignment opening 151 is smaller than the width of the first contact structure 131, which is beneficial to reducing the distance between adjacent local bit lines 22, and thus the area of the group pair storage unit of the group pair structure single storage tube NOR flash memory can be reduced, and the storage density of the group pair structure single storage tube NOR flash memory is improved; the second medium layer 14 is generated on the first contact structure 131, the etching stop layer 15 is generated on the second medium layer 14, and the part of the local bit line 22 in contact with the first contact structure 131 is located below the etching stop layer 15 and the rest is located on the etching stop layer 15, that is, the second medium layer 14 and the etching stop layer 15 can raise the distance between the part of the local bit line 22 not in direct contact with the first contact structure 131 and the first contact structure 131, which is beneficial to avoiding the short circuit caused by the breakdown between the first contact structure 131 and the adjacent local bit line 22 (i.e. the local bit line 22 that does not need to be electrically connected to the first contact structure 131), and is beneficial to ensuring the reliability of the flash memory when the distance between adjacent local bit lines 22 is reduced and the area of the group pair storage unit is reduced, and is beneficial to realizing the miniaturization of the flash memory area.

[0128] Further, the manufacturing method of the group pair structure single storage tube NOR flash memory provided by the application can realize the process compatibility of the storage array and the peripheral circuit.

[0129] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the application without departing from the spirit and scope of the application, therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application, which does not deviate from the technical solutions of the application, belongs to the protection scope of the technical solutions of the application.

Claims

1. A method for fabricating a single-tube NOR flash memory with a pair structure, characterized in that, include: A substrate is provided, the substrate including a storage array area having a plurality of paired storage cells arranged in rows and columns, one of the paired storage cells including two storage tubes connected to the source area, each of the storage tubes having a first contact structure on the drain area, one column of the paired storage cells corresponding to two columns of the first contact structures, and the two first contact structures of one paired storage cell located in different columns of the first contact structures. A second dielectric layer is formed on the substrate, the second dielectric layer covering a plurality of the first contact structures; An etch stop layer is formed on the second dielectric layer. The etch stop layer has a plurality of first self-aligned openings, one of which corresponds to one of the first contact structures, and the width of the first self-aligned opening is smaller than the width of the first contact structure. A third dielectric layer is formed on the etch stop layer, the third dielectric layer covering the etch stop layer and the second dielectric layer; Multiple spindle structures are generated on the third dielectric layer, one spindle structure is provided on a column of the paired storage units, and one spindle structure is located above a column of the first contact structures; Sidewalls are formed on both sides of each mandrel structure, and there is a gap between the sidewalls of two adjacent mandrel structures. The gap is located above a row of first contact structures that do not have a mandrel structure above them. Remove the aforementioned mandrel structure; Under the cover of the sidewall and the restriction of the etching stop layer, the third dielectric layer and the second dielectric layer are etched and the etching stop layer and the first contact structure are stopped to form multiple local bit line grooves. A portion of the bottom surface of one of the local bit line grooves is located on the etching stop layer and a portion of the bottom surface is located below the first self-aligned opening and exposes a row of the first contact structures. as well as Conductive material is filled into the local bit line groove to form multiple local bit lines. One of the local bit lines passes through the corresponding first self-aligned opening and connects to a column of the first contact structures.

2. The method for fabricating a single-tube NOR flash memory with a pair structure as described in claim 1, characterized in that, In the step of providing the substrate, the memory array region has a plurality of first transistors serving as select transistors, the plurality of first transistors being arranged at the ends of a plurality of columns of the paired memory cells, the source region of the first transistor being connected to the drain region of the adjacent memory cell, and the drain region of the first transistor having a second contact structure. The substrate further includes a peripheral circuit region; in the step of providing the substrate, a plurality of second transistors and a plurality of third contact structures connected to the second transistors are formed in the peripheral circuit region. In the step of forming a second dielectric layer on the substrate, the second dielectric layer covers the second contact structure and the third contact structure; In the step of generating an etch stop layer on the second dielectric layer, the etch stop layer has a plurality of second self-aligned openings and a plurality of third self-aligned openings, one second self-aligned opening corresponds to one second contact structure position, and the width of the second self-aligned opening is smaller than the width of the second contact structure, and one third self-aligned opening corresponds to one third contact structure position. In the step of generating a third dielectric layer on the etch stop layer, the third dielectric layer covers the peripheral circuit area.

3. The method for fabricating a single-tube NOR flash memory with a pair structure as described in claim 2, characterized in that, In the step of generating multiple mandrel structures on the third dielectric layer, the mandrel structure extends above the corresponding second contact structure, and the peripheral circuit area does not form the mandrel structure.

4. The method for fabricating a single-tube NOR flash memory with a pair structure as described in claim 3, characterized in that, After the removal of the spindle structure and before etching the third dielectric layer and the second dielectric layer and stopping at the etching stop layer and the first contact structure, a barrier layer is formed on the substrate. The barrier layer has a first opening and a plurality of second openings. The first opening exposes the formation areas of a plurality of the paired memory cells. One of the second openings corresponds to a position of one of the second contact structures. The barrier layer covers a portion of the area between the first transistor and the memory tube to cut off the subsequently formed local bit line groove. The barrier layer covers the peripheral circuit area.

5. The method for fabricating a single-tube NOR flash memory with a pair structure as described in claim 4, characterized in that, In the step of etching the third dielectric layer and the second dielectric layer and stopping on the etching stop layer and the first contact structure, the sidewall and the barrier layer are used together as a mask to form multiple connecting grooves on the second contact structure while forming the local bit line groove. A portion of the bottom surface of the connecting groove is located on the etching stop layer and a portion of the bottom surface is located below the second self-aligning opening and exposes the corresponding second contact structure. In the step of filling the local bit line groove with conductive material to form multiple local bit lines, conductive material is simultaneously filled in the connecting groove to form a first conductive structure connected to the second contact structure. Both the local bit lines and the first conductive structure belong to the zero-layer metal layer.

6. The method for fabricating a single-tube NOR flash memory with a pair structure as described in claim 5, characterized in that, After forming the local bit line and the first conductive structure, the method further includes: A fourth dielectric layer is formed on the substrate, the fourth dielectric layer covering the third dielectric layer, the local bit line and the first conductive structure; The fourth dielectric layer, the third dielectric layer and the second dielectric layer are etched and stopped on the first conductive structure and the third contact structure to form a plurality of first through holes and a plurality of second through holes. One first through hole exposes one first conductive structure, and one second through hole passes through one third self-aligned opening to expose one third contact structure. A first conductive hole and a second conductive hole are formed by filling the first through hole and the second through hole with conductive material; and A first metal layer is formed on the substrate. The first metal layer includes multiple metal lines, and the first conductive hole and the second conductive hole are respectively connected to the corresponding metal lines.

7. The method for fabricating a single-tube NOR flash memory with a pair structure as described in claim 6, characterized in that, The first through hole and the second through hole are formed simultaneously.

8. The method for fabricating a single-tube NOR flash memory with a pair structure as described in claim 6, characterized in that, The cross-section of the first conductive hole parallel to the substrate is rectangular or elliptical; the width of the short side of the first conductive hole is smaller than the width of the second conductive hole.

9. The method for manufacturing a single-tube NOR flash memory with a pair structure as described in claim 2, characterized in that, The width of the first contact structure is less than the width of the third contact structure, and the width of the second contact structure is equal to the width of the first contact structure.

10. A method for manufacturing a single-tube NOR flash memory with a pair structure as described in any one of claims 1 to 9, characterized in that, The pitch values ​​of two adjacent local bit lines are less than the pitch values ​​of two adjacent first contact structures in the same row.

11. The method for fabricating a single-tube NOR flash memory with a pair structure as described in claim 10, characterized in that, The pitch value of two adjacent local bit lines is half the pitch value of two adjacent first contact structures in the same row.

12. A single-tube NOR flash memory with a pair structure, characterized in that, The single-tube NOR flash memory with a pair structure as described in any one of claims 1 to 11 is manufactured using such method, the single-tube NOR flash memory with a pair structure comprising: The substrate includes a storage array region having multiple pairs of storage cells arranged in rows and columns. Each pair of storage cells includes two storage tubes with two source regions connected together. Each storage tube has a first contact structure on its drain region. A column of the pair of storage cells corresponds to two columns of the first contact structures, and the two first contact structures of a pair of storage cells are located in different columns of the first contact structures. A second dielectric layer is located on the substrate and covers a plurality of the first contact structures; An etching stop layer, located on the second dielectric layer, has a plurality of first self-aligned openings, each first self-aligned opening corresponding to a first contact structure position, and the width of the first self-aligned opening is smaller than the width of the first contact structure; and Multiple local bit lines, a portion of which is located above the etch stop layer and another portion passes through the corresponding first self-aligned opening and connects to a column of the first contact structures.

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