Semiconductor package, camera module and electronic device

Abstract

The application provides a semiconductor package, a camera module and an electronic device. The semiconductor package is a wafer-level chip package for adjusting the orientation of the camera module, comprising a package body, a pin group and a second pin. The pin group is arranged on the package body and comprises a plurality of first pins arranged at intervals. The second pin is arranged on the package body and located on one side of the pin group. The second pin provides one of the control voltage and the driving voltage for the semiconductor package, and one of the plurality of first pins provides the other of the control voltage and the driving voltage for the semiconductor package. The application can further reduce the driving voltage in a low-power consumption scenario, thereby optimizing the power consumption of the optical anti-shake system of the semiconductor package and the camera module.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor package, a camera module, and an electronic device. Background Technology

[0002] With the increasing popularity of mobile electronic devices (such as smartphones and wearable devices), the performance requirements for them are becoming more and more demanding. For example, the imaging quality and response performance of the camera module of an electronic device directly determine the user's shooting experience, and the quality of imaging and response performance mainly depends on the performance of the driver chip, which needs to achieve high-precision control and high-efficiency driving within a limited space.

[0003] In related technologies, camera modules typically include optical components, driving components, and a semiconductor package. The semiconductor package controls the movement of the driving components to automatically adjust the autofocus and optical image stabilization of the optical components, thereby achieving fast focusing and stable shooting. The semiconductor package typically includes a driving circuit and a control circuit. The control circuit processes sensor signals (such as Hall sensors or TMR sensors) and generates control commands, while the driving circuit drives the driving components of the camera assembly according to the commands. However, currently, the driving voltage is limited by the minimum operating voltage of the control circuit, making it impossible to further reduce the driving voltage in low-power scenarios and hindering the optimization of the semiconductor package's power consumption. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a semiconductor package, a camera module, and an electronic device, which can further reduce the driving voltage in low-power scenarios, and facilitate the optimization of the power consumption of the optical image stabilization system of the semiconductor package and the camera module.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] A first aspect of this application provides a semiconductor package, which is a wafer-level chip package for adjusting the orientation of a camera module, comprising:

[0007] Encapsulated body;

[0008] A pin group, which is disposed on the package body and includes a plurality of first pins arranged at intervals;

[0009] The second pin is disposed on the package body and located on one side of the pin group, wherein the second pin provides one of a control voltage and a drive voltage to the semiconductor package, and one of the plurality of first pins provides the other of a control voltage and a drive voltage to the semiconductor package.

[0010] In one possible implementation, the horizontal cross-sectional shape of the encapsulation body is rectangular, and along the length direction of the encapsulation body, the encapsulation body has a first edge and a second edge that are disposed opposite to each other.

[0011] The second pin is located in the area formed by the pin group and at least one of the first edge and the second edge.

[0012] In one possible implementation, the number of the second pins is one, the second pin is disposed between the pin group and the first edge, and is located near the corner formed by the first edge and the edge connecting the first edge, and is offset from the adjacent first pin;

[0013] Alternatively, the number of the second pins is one, and the second pin is located between the pin group and the second edge, near the corner formed by the second edge and the edge that connects to it, and is offset from the adjacent first pin.

[0014] In one possible implementation, there are two second pins, one of which is located between the pin group and the first edge, near the corner formed by the first edge and the edge it connects to; the other second pin is located between the pin group and the second edge, near the corner formed by the second edge and the edge it connects to.

[0015] The two second pins are arranged in a centrally symmetrical manner with respect to the center of the package body.

[0016] In one possible implementation, of the second pin and the two adjacent first pins, the second pin is located on the side of the center line connecting the two first pins away from the center of the package body; wherein the center line connecting the two first pins is inclined relative to the length direction of the package body.

[0017] In one possible implementation, a plurality of first pins are arranged at circumferential intervals along the package body, and three adjacent first pins form a triangular layout; wherein, the plurality of first pins include a first sub-pin, a second sub-pin, a third sub-pin, a fourth sub-pin, a fifth sub-pin, and a sixth sub-pin;

[0018] The number of second pins is two, one of which is located in the area formed by the first sub-pin, the sixth sub-pin, and the first edge, and the other of which is located in the area formed by the third sub-pin, the fourth sub-pin, and the second edge;

[0019] The second sub-pin, one of the two second pins, provides one of a control voltage and a drive voltage to the semiconductor package; the second sub-pin, one of the two second pins, provides the other of a control voltage and a drive voltage to the semiconductor package.

[0020] In one possible implementation, the first sub-pin serves as the ground pin of the semiconductor package, the third sub-pin serves as the first signal pin of the semiconductor package, the fourth sub-pin serves as the second signal pin of the semiconductor package, and the fifth and sixth sub-pins serve as the output pins of the semiconductor package.

[0021] In one possible implementation, the package body includes a semiconductor chip and a redistribution layer, the semiconductor chip including a first pad and a second pad;

[0022] The redistribution layer is stacked on the semiconductor chip, and the redistribution layer includes a first wiring layer and a second wiring layer that are insulated from each other. The first pad is electrically connected to one of a plurality of first pins through the first wiring layer, and the first pin is a pin that provides control voltage or drive voltage to the semiconductor package.

[0023] The second pad is electrically connected to the second pin through the second wiring layer.

[0024] A second aspect of this application provides a camera module, including:

[0025] Optical components;

[0026] A driving component, the driving component being used to drive the optical component to perform orientation adjustment;

[0027] The semiconductor package of the first aspect cooperates with the driving component to provide driving instructions to the driving component.

[0028] A third aspect of this application provides an electronic device including the camera module described in the second aspect.

[0029] In the semiconductor package, camera module, and electronic device provided in this application embodiment, a second pin is added to the existing pin group. This second pin provides one of the control voltage and the driving voltage to the semiconductor package, while one of the multiple first pins provides the other of the control voltage and the driving voltage to the semiconductor package. This separates the power paths of the control circuit and the driving circuit, achieving voltage supply independence. This solves the problem in related technologies where the driving voltage is limited by the minimum operating voltage of the control voltage. Furthermore, it allows the driving voltage to be dynamically adjusted to reduce the driving voltage even when it is below the minimum operating voltage, thereby decoupling the driving voltage from the control voltage and optimizing the power consumption of the optical image stabilization system of the semiconductor package and camera module.

[0030] In addition, semiconductor packages are also wafer-level chip packages, which can make reasonable use of the idle area of ​​the wafer and add a second pin while keeping the size of the package body unchanged, thus avoiding increasing the size of the semiconductor package.

[0031] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor package, camera module, and electronic device provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a semiconductor package provided in an embodiment of this application;

[0034] Figure 2 Circuit diagram of a semiconductor package provided in an embodiment of this application;

[0035] Figure 3 A schematic diagram of a camera module provided in an embodiment of this application;

[0036] Figure 4 A circuit diagram of a camera module provided in an embodiment of this application.

[0037] Explanation of reference numerals in the attached figures:

[0038] 100: Package body; 110: First edge; 120: Second edge; 130: Third edge; 140: Fourth edge;

[0039] 200: First pin; 210: First sub-pin; 220: Second sub-pin; 230: Third sub-pin; 240: Fourth sub-pin; 250: Fifth sub-pin; 260: Sixth sub-pin;

[0040] 300: Second pin;

[0041] 400: Control circuit;

[0042] 500: Drive circuit;

[0043] 600: Camera module; 610: Driver component. Detailed Implementation

[0044] As described in the background section, camera modules in related technologies typically include optical components, driving components, and a semiconductor package. The semiconductor package controls the movement of the driving components to adjust the autofocus and optical image stabilization of the optical components, thereby achieving fast focusing and stable shooting. The semiconductor package typically uses a single pin to power both the control and driving circuits. Because the control and driving circuits share the same power path, the voltage adjustment range of the driving circuit is limited by the minimum operating voltage of the control circuit (e.g., 1.8V). For example, when the driving circuit needs to reduce the voltage to save power, it must ensure that the voltage is not lower than the minimum operating voltage of the control circuit (e.g., 1.8V); otherwise, the control circuit will not function properly. Therefore, it is impossible to further reduce the driving voltage in low-power scenarios, and consequently, it is impossible to dynamically adjust the driving voltage and optimize overall power consumption.

[0045] This design has significant drawbacks in dynamic voltage regulation scenarios: the drive voltage cannot fall below the minimum requirements of the control circuit, limiting the potential for power consumption optimization. Furthermore, existing packaging solutions (such as 6-pin WLCSP packages) cannot expand the number of pins without increasing chip area, thus restricting functional expansion. Therefore, related technologies have significant shortcomings in terms of power consumption control, voltage regulation flexibility, and package compatibility.

[0046] To address the aforementioned technical problems, this application provides a semiconductor package, a camera module, and an electronic device. By adding a second pin to the existing pin group, this second pin provides either a control voltage or a drive voltage to the semiconductor package. One of the multiple first pins provides the other of the control voltage and drive voltage to the semiconductor package. This separates the power paths of the control circuit and the drive circuit, achieving voltage supply independence. It solves the problem in related technologies where the drive voltage is limited by the minimum operating voltage of the control voltage. This allows the drive voltage to be dynamically adjusted to reduce its value even when it falls below the minimum operating voltage, thereby decoupling the drive voltage from the control voltage and optimizing the power consumption of the optical image stabilization system in the semiconductor package and camera module.

[0047] In addition, semiconductor packages are also wafer-level chip packages, which can make reasonable use of the idle area of ​​the wafer and add a second pin while keeping the size of the package body unchanged, thus avoiding increasing the size of the semiconductor package.

[0048] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0049] Please refer to Figure 1 This application provides a semiconductor package, which is a wafer-level chip package for adjusting the orientation of a camera module. Alternatively, the semiconductor package is integrated into the camera module, serving as a control chip to adjust the orientation of the optical components of the camera module.

[0050] The semiconductor package includes a package body 100, which includes a semiconductor chip (not shown in the figure) and a redistribution layer (not shown in the figure). The semiconductor chip integrates an integrated circuit, which may include control circuits and drive circuits. The integrated circuit can be connected to pins through the redistribution layer to realize the electrical connection between the package body 100 and the pre-controlled component.

[0051] The semiconductor package also includes a pin group disposed on the package body 100. For example, the pin group is disposed on the side of the redistribution layer away from the semiconductor chip, and the pin group is electrically connected to the pads of the semiconductor chip through the redistribution layer.

[0052] The pin group includes a plurality of first pins 200 arranged at intervals. These first pins 200 can be arranged regularly or irregularly. For example, the plurality of first pins 200 are arranged in two rows and columns, with the first pins 200 staggered in adjacent rows. It should be noted that the number of first pins 200 is typically six, arranged in two rows and three columns, with the first pins 200 staggered in both the row and column directions.

[0053] The semiconductor package also includes a second pin 300, which is disposed on one side of the pin group. In the embodiments of this application, both the first pin 200 and the second pin 300 can be tin-plated pins.

[0054] In this embodiment, the second pin 300 provides either a control voltage or a drive voltage to the semiconductor package, and one of the plurality of first pins 200 provides both the control voltage and the drive voltage to the semiconductor package. In some embodiments, one of the plurality of first pins 200 provides a control voltage to the semiconductor package, and correspondingly, the second pin 300 provides a drive voltage to the semiconductor package. In other embodiments, one of the plurality of first pins 200 provides a drive voltage to the semiconductor package, and correspondingly, the second pin 300 provides a control voltage to the semiconductor package.

[0055] This separates the power supply paths of the control circuit and the drive circuit, achieving voltage supply independence and solving the problem in related technologies where the drive voltage is limited by the minimum operating voltage of the control voltage. This allows the drive voltage to be dynamically adjusted to reduce the drive voltage even when it is below the minimum operating voltage, thereby decoupling the drive voltage from the control voltage and optimizing the power consumption of the optical image stabilization system of the semiconductor package and camera module.

[0056] In addition, semiconductor packages are also wafer-level chip packages, which can make reasonable use of the idle area of ​​the wafer and add a second pin while keeping the size of the package body unchanged, thus avoiding increasing the size of the semiconductor package and promoting the development of semiconductor packages towards integration.

[0057] In one possible implementation, the horizontal cross-sectional shape of the package body 100 is rectangular, or in other words, the top view shape of the package body 100 is rectangular. Along the length direction of the package body 100, the package body 100 has a first edge 110 and a second edge 120 that are disposed opposite to each other. Alternatively, in the direction of the arrangement of the plurality of first pins 200, the package body 100 has a first edge 110 and a second edge 120 that are disposed opposite to each other.

[0058] The second pin 300 is located in the area formed by the pin group and at least one of the first edge 110 and the second edge 120. Exemplarily, the number of second pins 300 is one, and the second pin 300 is disposed in the area formed by the pin group and the first edge 110. Alternatively, the second pin 300 is disposed in the area formed by the pin group and the second edge 120.

[0059] In this way, when packaging the package body 100, the area between the pin group and the first edge 110 and / or the second edge 120 can be fully utilized. Under the premise of realizing the separate setting of control voltage and driving voltage, the size of the semiconductor package is not increased, which facilitates the development of semiconductor packages towards integration and smaller size.

[0060] In one possible implementation, the number of second pins 300 is one. The second pin 300 is located between the pin group and the first edge 110, near the corner formed by the first edge 110 and the edge it connects to, and is offset from the adjacent first pin 200.

[0061] Alternatively, the number of second pins 300 is one. The second pin 300 is located between the pin group and the second edge 120, near the corner formed by the second edge 120 and the edge it connects to, and is offset from the adjacent first pin 200.

[0062] For example, the package body 100 further includes a third edge 130 and a fourth edge 140, which are respectively connected to the first edge 110 and the second edge 120, and are spaced apart along the width direction of the package body 100. Figure 1 Taking the orientation shown as an example, the third edge 130 is the left edge of the encapsulation body 100, and the fourth edge 140 is the right edge of the encapsulation body 100.

[0063] In some embodiments, when there is only one second pin 300, the second pin 300 is disposed between the pin group and the first edge 110, and is located at the corner formed by the first edge 110 and the third edge 130. The first pin 200, which is closest to the second pin 300, is disposed near the fourth edge 140.

[0064] In other embodiments, when there is only one second pin 300, the second pin 300 is disposed between the pin group and the second edge 120, and is located at the corner formed by the second edge 120 and the fourth edge 140. The first pin 200, which is closest to the second pin 300, is disposed near the third edge 130.

[0065] In this way, when packaging the package body 100, the area between the pin group and the first edge 110 and / or the second edge 120 can be fully utilized. Under the premise of realizing the separate setting of control voltage and drive voltage, the safe distance between the first pin 200, which is closest to the second pin 300, and the first pin 200 is increased, preventing electrical interference between the first pin 200 and the second pin 300 and improving the performance of the semiconductor package.

[0066] In one possible implementation, there are two second pins 300. One second pin 300 is located between the pin group and the first edge 110, and near the corner formed by the first edge 110 and the edge it connects to. The other second pin 300 is located between the pin group and the second edge 120, and near the corner formed by the second edge 120 and the edge it connects to. The two second pins 300 are centrally symmetrical with respect to the center of the package body 100.

[0067] This embodiment of the application, by providing a second pin 300 at each of the two corners, increases the layout flexibility of the wiring layer electrically connected to the second pin 300, based on the original wiring layer. This helps optimize signal transmission paths, reduce wiring crossings and interference, and further improve the electrical performance and overall reliability of the semiconductor package. Furthermore, the two second pins 300 are centrally symmetrically arranged with respect to the center of the package body 100, which not only improves the regularity of the semiconductor package but also facilitates the fabrication of the second pins 300.

[0068] In one possible implementation, among the second pin 300 and the two adjacent first pins 200, the second pin 300 is located on the side opposite to the center line of the two first pins 200; wherein the center line of the two first pins 200 is inclined relative to the length direction of the package body 100.

[0069] In this way, the second pin 300 can be located at the upper left and lower right corners of the package body 100, so as to make full use of the edge corners of the package body 100, meet the requirements of driving voltage and control voltage partitioning, and maintain the area of ​​the semiconductor package body unchanged.

[0070] In one possible implementation, the horizontal cross-sectional shape of the second pin 300 can be regular or irregular. When the horizontal cross-sectional shape of the second pin 300 is regular, it can be circular, square, or fan-shaped. When the cross-sectional shape of the second pin 300 is fan-shaped, the arc edge of the fan faces the center of the package body 100. In this way, while placing the second pin 300 in the edge region of the package body 100, the distance between the second pin 300 and the adjacent first pin 200 is minimized, preventing electrical interference between the first pin 200 and the second pin 300, and improving the safety performance of the semiconductor package.

[0071] When the horizontal cross-sectional shape of the second pin 300 is irregular, it can be understood that the outer contour of the horizontal cross-section of the second pin 300 can be composed of multiple first connecting segments connected in sequence, and each first connecting segment can be a regular line segment, such as a straight line or an arc; the first connecting segment can also be an irregular line segment, such as an irregularly shaped line segment.

[0072] To facilitate defining the function of each first pin 200 and second pin 300 in the pin group, it is advisable to define the arrangement and function of the multiple first pins 200.

[0073] In one possible implementation, multiple first pins 200 are arranged at circumferential intervals along the package body 100, with three adjacent first pins 200 forming a triangular layout. In other words, the multiple first pins 200 are arranged in two rows, and the first pins 200 are staggered in adjacent rows. It should be noted that the number of first pins 200 is usually six, and the six first pins 200 are arranged in two rows and three columns, with the first pins 200 staggered in both the row and column directions.

[0074] The multiple first pins 200 include a first sub-pin 210, a second sub-pin 220, a third sub-pin 230, a fourth sub-pin 240, a fifth sub-pin 250, and a sixth sub-pin 260. The number of second pins 300 is two.

[0075] One of the second pins 300 is located in the area formed by the first sub-pin 210, the sixth sub-pin 260 and the first edge 110, and the other second pin 300 is located in the area formed by the third sub-pin 230, the fourth sub-pin 240 and the second edge 120.

[0076] The second sub-pin 220 and one of the two second pins 300 provide one of a control voltage and a drive voltage to the semiconductor package; the second sub-pin 220 and the second pin 300 provide the other of a control voltage and a drive voltage to the semiconductor package.

[0077] It should be noted that, with Figure 1 Taking the orientation shown as an example, one of the two second pins 300 can be the second pin 300 located in the upper left corner or the second pin 300 located in the lower right corner. Therefore, one of the second pins 300 is in an idle state. In some embodiments, the second sub-pin 220 provides a control voltage to the semiconductor package, and the second pin 300 located in the lower right corner provides a drive voltage to the semiconductor package. In still other embodiments, the second sub-pin 220 provides a drive voltage to the semiconductor package, and the second pin 300 located in the lower right corner provides a control voltage to the semiconductor package.

[0078] Please continue to refer to this. Figure 1 The first sub-pin 210 serves as the ground pin (GND) of the semiconductor package, and the third sub-pin 230 serves as the first signal pin of the semiconductor package. For example, the third sub-pin 230 is used to connect to the clock line (SCL) of the communication interface. The fourth sub-pin 240 serves as the second signal pin of the semiconductor package. For example, the fourth sub-pin 240 is used to connect to the data line (SDA) of the communication interface.

[0079] The fifth sub-pin 250 and the sixth sub-pin 260 serve as output pins of the semiconductor package. For example, the fifth sub-pin 250 and the sixth sub-pin 260 are used to connect to the driving components of the camera module. The fifth sub-pin 250 is OUT1, and the sixth sub-pin 260 is OUT2.

[0080] It is important to understand that the following description uses six first pins 200 as an example. The horizontal cross-sectional shapes of the six first pins 200 can be the same or different. In some embodiments, the horizontal cross-sectional shapes of the six first pins 200 are the same, and the horizontal cross-sectional shape of the first pins 200 is circular. In other embodiments, the horizontal cross-sectional shapes of the six first pins 200 are different. For example, some of the first pins 200 have a circular horizontal cross-sectional shape, and some of the first pins 200 have a horizontal cross-sectional shape that includes multiple second connecting line segments, with an included angle between adjacent second connecting line segments. Each second connecting line segment can be a regular line segment, such as a straight line or an arc; the second connecting line segments can also be irregular line segments, such as irregularly shaped line segments. The size of the included angle can be designed according to the size of the first pins 200 or other design requirements.

[0081] In one possible implementation, the package body 100 further includes a semiconductor chip and a redistribution layer, the semiconductor chip including a first pad and a second pad.

[0082] A redistribution layer is stacked on the semiconductor chip, and the redistribution layer includes a first wiring layer and a second wiring layer that are insulated from each other. A first pad is electrically connected to one of a plurality of first pins 200 through the first wiring layer, and the first pin 200 is a pin that provides a control voltage or a drive voltage to the semiconductor package. A second pad is electrically connected to a second pin 300 through the second wiring layer, and the second pin 300 provides a control voltage or a drive voltage to the semiconductor package.

[0083] This embodiment adjusts the redistribution layer to have independent first and second routing layers. This allows the first pad to be independently led out to the first pin 200, and the second pad to be independently led out to the second pin 300. Thus, the first pin 200 and the second pin 300 can provide independent control voltage and drive voltage to the semiconductor package, respectively, achieving voltage supply independence. This solves the problem in related technologies where the drive voltage is limited by the minimum operating voltage of the control voltage. It allows the drive voltage to be dynamically adjusted to reduce the drive voltage even when it is below the minimum operating voltage, thereby decoupling the drive voltage from the control voltage and optimizing the power consumption of the optical image stabilization system of the semiconductor package and the camera module.

[0084] Please refer to Figure 2 In one possible implementation, the semiconductor chip includes a control circuit 400 and a drive circuit 500; wherein one of a plurality of first pins 200 and one of a second pin 300 are used to provide a control voltage to the control circuit 400, and the other of the plurality of first pins 200 and the second pin 300 is used to provide a drive voltage to the drive circuit 500. In some embodiments, the first pin 200 provides a control voltage to the control circuit 400, and correspondingly, the second pin 300 provides a drive voltage to the drive circuit 500.

[0085] The control circuit 400 also includes an output terminal, and the drive circuit 500 also includes an input terminal. The output terminal of the control circuit 400 is connected to the input terminal of the drive circuit 500 to control the start and stop of the drive circuit 500.

[0086] To facilitate the division of the control circuit 400 and the drive circuit 500, let's consider... Figure 2 The modules within the dashed box on the left constitute the control circuit 400. Figure 2 The module within the dashed box on the right constitutes the drive circuit 500.

[0087] Please continue to refer to this. Figure 2The control circuit 400 may include a digital control and storage module, a signal processing module, a communication interface module, and an auxiliary function module. The digital control and storage module includes a register, a memory module (MTP), and a differential controller (PID). The register stores digital signals and configuration parameters (such as gain and sampling rate), and communicates bidirectionally with the differential controller (PID). The memory module (MTP) is a non-volatile storage module used to persistently store configuration parameters, calibration data, user settings, or historical data. For example, it can store the circuit's gain coefficient, ADC calibration value, and operating mode configuration, retaining the information even after power loss and directly recalling it upon next power-on, ensuring the consistency and stability of the circuit operation. The memory module (MTP) and the register are bidirectionally connected.

[0088] The signal processing module includes an operational amplifier (AMP) and an analog-to-digital converter (A / D). The AMP is connected to a temperature sensor (TSNS) and a Multi Hall sensor to amplify the received signal, increasing its amplitude to meet subsequent processing requirements. The amplified signal is then output to the A / D converter, which converts it into a digital signal for digital circuitry to process.

[0089] The digital signal generated by the analog-to-digital converter (A / D) can be directly transmitted to the register, and then from the register to the differential controller (PID). Alternatively, it can be directly transmitted to the differential controller (PID).

[0090] The communication interface module includes an SCL interface and an SDA interface; the SDA interface is for 12 / 13C interface data signals, and the SCL interface is for 12 / 13C clock data, used for bidirectional data transmission with external devices (such as host computers, other sensors) to realize functions such as configuration distribution and data upload.

[0091] The auxiliary function modules include a low-dropout linear regulator (LDO), an oscillator (OSC), and a bandgap reference (BG). The LDO regulates the VDD input power supply, providing a stable operating voltage for each module in the circuit, such as the modules mentioned above. The OSC generates the clock signal. The bandgap reference (BG) generates a high-precision, low-temperature-drift reference voltage. It provides a stable voltage reference for the analog modules in the circuit (such as ADCs, AMPs, DACs, etc.), ensuring that these modules maintain the accuracy of their measurements or outputs under different temperatures and power supply fluctuations.

[0092] The drive circuit 500 includes a driver and a path constructed from four transistors. The driver amplifies and levels-shifts the weak logic control signal output from the differential controller (PID) to drive the on / off state of the path constructed from the four transistors. Specifically, the input terminal of the driver is connected to the output terminal of the differential controller (PID), and the output terminal of the driver is connected to the gate terminals of the four transistors to control the on / off state of the transistors, thereby driving the external load through the second and third output terminals.

[0093] During this process, one of the second sub-pin 220 and the second pin 300 serves as the control voltage input pin of the control circuit, used to provide the control voltage VDD to the control circuit. The other of the second sub-pin 220 and the second pin 300 is used to provide the drive voltage VM to the drive circuit, so as to ensure that the source and drain of the transistor are connected, and then drive the driving components of the camera module through the fifth sub-pin 250 and the sixth sub-pin 260.

[0094] In this way, the control voltage VDD of the control circuit and the drive voltage VM of the drive circuit are relatively independent. When the control voltage VDD is within the power supply range (1.8V~5V), the drive voltage VM can be adjusted from 0V to 5.5V, so that the drive voltage VM is lower than 1.8V. This solves the problem in related technologies where the drive voltage is limited by the minimum operating voltage of the control voltage. This allows the drive voltage to be further dynamically adjusted to reduce the drive voltage even when it is lower than the minimum operating voltage, thereby decoupling the drive voltage and the control voltage and optimizing the power consumption of the optical image stabilization system of the semiconductor package and the camera module.

[0095] Please refer to Figure 3 and Figure 4 This application embodiment also provides a camera module 600, including:

[0096] Optical components, which may include lenses.

[0097] The driving component 610 is used to drive the optical component to perform orientation adjustment.

[0098] The semiconductor package described in any of the above embodiments cooperates with the driving component to provide driving instructions to the driving component.

[0099] The driving component can be a voice coil motor, which includes a coil and a magnetic component. The semiconductor package is electrically connected to the coil and outputs a controlled current to the coil through the integrated control and driving circuits inside.

[0100] Once the semiconductor package calculates the required compensation direction and displacement based on the received jitter signal (such as a signal from a gyroscope sensor), it outputs a drive current of corresponding magnitude and direction to the coil. As this current flows through the coil, it generates a changing magnetic field. This magnetic field interacts with the fixed magnetic field provided by the magnetic components of the voice coil motor, producing an electromagnetic force (i.e., the Lorentz force) acting on the coil according to Ampere's law (i.e., the Lorentz force principle).

[0101] Since the coil is mechanically connected to optical components (such as the lens barrel), and the magnetic components are usually fixed to the fixed frame of the camera module, the generated electromagnetic force will drive the coil and the optical components connected to it to produce precise translational motion along the X-axis and / or Y-axis in a plane perpendicular to the optical axis.

[0102] By changing the intensity and direction of the current in the coil in real time, the direction and amplitude of the movement of the optical components can be precisely controlled, thereby offsetting the influence of external jitter on the optical path in real time and achieving high-performance optical image stabilization.

[0103] It should be noted that the number of driving components in this embodiment can be one or two. For example, the number of semiconductor packages can be two, and the two semiconductor packages respectively precisely control the optical components to produce precise translational movements along the X-axis and Y-axis directions in a plane perpendicular to the optical axis.

[0104] This application improves the semiconductor package by precisely controlling the translational motion of optical components along the X and Y axes while reducing power consumption. Two second pins are added to the corner edges of the package body using wafer-level chip packaging technology. This decouples the driving voltage from the control voltage, optimizing the power consumption of the optical image stabilization system between the semiconductor package and the camera module. This application also provides an electronic device including the camera module described in any of the above embodiments. The electronic device may include smartphones or wearable devices.

[0105] Since the electronic device includes the camera module described in any of the above embodiments, it has all the structure and all the beneficial effects of the camera module, and will not be described in detail here.

[0106] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0107] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor package, characterized in that, The semiconductor package is a wafer-level chip package used for adjusting the orientation of the camera module, and it includes: Encapsulated body; A pin group, which is disposed on the package body and includes a plurality of first pins arranged at intervals; The second pin is disposed on the package body and located on one side of the pin group. The second pin provides one of a control voltage and a drive voltage to the semiconductor package. One of the plurality of first pins provides the other of a control voltage and a drive voltage to the semiconductor package. The control voltage is the power supply voltage of the control circuit of the semiconductor package, and the drive voltage is the power supply voltage of the drive circuit of the semiconductor package, and the drive voltage is lower than the minimum operating voltage of the control circuit. The second pin is located in the free area formed by the pin group and the edge of the package body.

2. The semiconductor package according to claim 1, characterized in that, The horizontal cross-sectional shape of the packaging body is rectangular, and along the length direction of the packaging body, the packaging body has a first edge and a second edge that are disposed opposite to each other; The second pin is located in the area formed by the pin group and at least one of the first edge and the second edge.

3. The semiconductor package according to claim 2, characterized in that, The number of the second pins is one. The second pin is located between the pin group and the first edge, near the corner formed by the first edge and the edge connecting to it, and is staggered from the adjacent first pin. Alternatively, the number of the second pins is one, and the second pin is located between the pin group and the second edge, near the corner formed by the second edge and the edge that connects to it, and is offset from the adjacent first pin.

4. The semiconductor package according to claim 2, characterized in that, The number of second pins is two, one of which is located between the pin group and the first edge, near the corner formed by the first edge and the edge connecting to it; the other second pin is located between the pin group and the second edge, near the corner formed by the second edge and the edge connecting to it. The two second pins are arranged in a centrally symmetrical manner with respect to the center of the package body.

5. The semiconductor package according to any one of claims 1-4, characterized in that, In the second pin and the two adjacent first pins, the second pin is located on the side of the center line connecting the two first pins away from the center of the package body; wherein the center line connecting the two first pins is inclined relative to the length direction of the package body.

6. The semiconductor package according to claim 2 or 4, characterized in that, Multiple first pins are arranged at circumferential intervals along the package body, and three adjacent first pins form a triangular layout; wherein, the multiple first pins include a first sub-pin, a second sub-pin, a third sub-pin, a fourth sub-pin, a fifth sub-pin, and a sixth sub-pin; The number of second pins is two, one of which is located in the area formed by the first sub-pin, the sixth sub-pin, and the first edge, and the other of which is located in the area formed by the third sub-pin, the fourth sub-pin, and the second edge; The second sub-pin, one of the two second pins, provides one of a control voltage and a drive voltage to the semiconductor package; the second sub-pin, one of the two second pins, provides the other of a control voltage and a drive voltage to the semiconductor package.

7. The semiconductor package according to claim 6, characterized in that, The first sub-pin serves as the ground pin of the semiconductor package, the third sub-pin serves as the first signal pin of the semiconductor package, the fourth sub-pin serves as the second signal pin of the semiconductor package, and the fifth and sixth sub-pins serve as the output pins of the semiconductor package.

8. The semiconductor package according to any one of claims 1-4, characterized in that, The package body includes a semiconductor chip and a redistribution layer, and the semiconductor chip includes a first pad and a second pad. The redistribution layer is stacked on the semiconductor chip, and the redistribution layer includes a first wiring layer and a second wiring layer that are mutually insulated. The first pad is electrically connected to one of a plurality of first pins through the first wiring layer, and the first pin is a pin that provides control voltage or drive voltage to the semiconductor package. The second pad is electrically connected to the second pin through the second wiring layer.

9. A camera module, characterized in that, include: Optical components; A driving component, the driving component being used to drive the optical component to perform orientation adjustment; The semiconductor package according to any one of claims 1-8, wherein the semiconductor package cooperates with the driving component to provide driving commands to the driving component.

10. An electronic device, characterized in that, Includes the camera module as described in claim 9.

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