Pixel driving circuit and display device

Abstract

The invention discloses a pixel driving circuit and a display device, and the pixel driving circuit comprises a data pre-storage sub-circuit which is configured to provide a signal of a data signal end (Data) for a fourth node (N4) under the control of a signal of a second scanning signal end (Gate2), and store a voltage difference between the signal of the fourth node (N4) and the signal of a first power supply end (VDD); the first node control sub-circuit is configured to provide a signal of a first signal end (V1) or a fourth node (N4) for a first node (N1) under the control of signals of a control signal end (CON), a first scanning signal end (Gate1) and a second scanning signal end (Gate2), and a path is formed between the first node (N1) and a third node (N3); the second node control sub-circuit is configured to store a voltage difference between signals of a second node (N2) and a third node (N3) and a voltage difference between signals of the second node (N2) and a second signal end (V2), and provide a signal of an initial signal end (INIT) to a sixth node (N6) under the control of a signal of a reset signal end (Reset).

Description

Pixel driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a pixel driving circuit and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, and low cost. With the continuous development of display technology, display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, comprising: a data pre-storage sub-circuit, a first node control sub-circuit, a second node control sub-circuit, a driving sub-circuit, and a light-emitting control sub-circuit.

[0006] The data pre-storage sub-circuit is electrically connected with a second scan signal end, a data signal end, a first power supply end, and a fourth node respectively, and is configured to provide the signal of the data signal end to the fourth node under the control of the signal of the second scan signal end, and store the voltage difference between the signals of the fourth node and the first power supply end.

[0007] The first node control sub-circuit is electrically connected with a control signal end, a first scan signal end, a second scan signal end, a first signal end, a first node, a third node, and a fourth node respectively, and is configured to provide the signal of the first signal end or the fourth node to the first node under the control of the signals of the control signal end, the first scan signal end, and the second scan signal end, and form a path between the first node and the third node.

[0008] The second node control sub-circuit is electrically connected with a reset signal end, an initial signal end, a second signal end, a second node, a third node, and a sixth node respectively, and is configured to store the voltage difference between the signals of the second node and the third node, and the voltage difference between the signals of the second node and the second signal end, and provide the signal of the initial signal end to the sixth node under the control of the signal of the reset signal end.

[0009] The driving sub-circuit is electrically connected with the first node, the second node and the fifth node respectively, and is configured to output a driving current under the control of signals of the first node, the second node and the fifth node.

[0010] The light emitting control sub-circuit is electrically connected with the light emitting signal end, the first power supply end and the fifth node respectively, and is configured to provide a signal of the first power supply end to the fifth node under the control of a signal of the light emitting signal end.

[0011] In an example embodiment, the second node and the sixth node are the same node.

[0012] In an example embodiment, the light emitting control sub-circuit is further electrically connected with the second node and the sixth node, and is configured to provide a signal of the second node to the sixth node under the control of a signal of the light emitting signal end.

[0013] In an example embodiment, the data pre-storing sub-circuit comprises an eighth transistor and a first capacitor.

[0014] The control electrode of the eighth transistor is electrically connected with the second scan signal end, the first electrode of the eighth transistor is electrically connected with the data signal end, and the second electrode of the eighth transistor is electrically connected with the fourth node.

[0015] The first end of the first capacitor is electrically connected with the first power supply end, and the second end of the first capacitor is electrically connected with the fourth node.

[0016] In an example embodiment, the first node control sub-circuit comprises a first transistor, a second transistor and a fourth transistor.

[0017] The control electrode of the first transistor is electrically connected with the control signal end, the first electrode of the first transistor is electrically connected with the first signal end, and the second electrode of the first transistor is electrically connected with the third node.

[0018] The control electrode of the second transistor is electrically connected with the second scan signal end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node.

[0019] The control electrode of the fourth transistor is electrically connected with the first scan signal end, the first electrode of the fourth transistor is electrically connected with the fourth node, and the second electrode of the fourth transistor is electrically connected with the first node.

[0020] In an example embodiment, the first node control sub-circuit comprises a first transistor, a second transistor and a fourth transistor.

[0021] The control electrode of the first transistor is electrically connected with the control signal end, the first electrode of the first transistor is electrically connected with the first signal end, and the second electrode of the first transistor is electrically connected with the first node.

[0022] The control electrode of the second transistor is electrically connected with the second scan signal end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node;

[0023] The control electrode of the fourth transistor is electrically connected with the first scan signal end, the first electrode of the fourth transistor is electrically connected with the fourth node, and the second electrode of the fourth transistor is electrically connected with the first node.

[0024] In an exemplary embodiment, the second node control sub-circuit comprises a second capacitor, a third capacitor and a seventh transistor;

[0025] The first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with the second node;

[0026] The first end of the third capacitor is electrically connected with the second signal end, and the second end of the third capacitor is electrically connected with the second node;

[0027] The control electrode of the seventh transistor is electrically connected with the reset signal end, the first electrode of the seventh transistor is electrically connected with the initial signal end, and the second electrode of the seventh transistor is electrically connected with the sixth node.

[0028] In an exemplary embodiment, the light emitting control sub-circuit comprises a fifth transistor;

[0029] The control electrode of the fifth transistor is electrically connected with the light emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the fifth node.

[0030] In an exemplary embodiment, the light emitting control sub-circuit comprises a fifth transistor and a sixth transistor;

[0031] The control electrode of the fifth transistor is electrically connected with the light emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the fifth node;

[0032] The control electrode of the sixth transistor is electrically connected with the light emitting signal end, the first electrode of the sixth transistor is electrically connected with the second node, and the second electrode of the sixth transistor is electrically connected with the sixth node.

[0033] In an exemplary embodiment, the data pre-storage sub-circuit comprises an eighth transistor and a first capacitor; the first node control sub-circuit comprises a first transistor, a second transistor and a fourth transistor; the second node control sub-circuit comprises a second capacitor, a third capacitor and a seventh transistor; the light emitting control sub-circuit comprises a fifth transistor, and the driving sub-circuit comprises a third transistor;

[0034] The control electrode of the first transistor is electrically connected with a control signal terminal, the first electrode of the first transistor is electrically connected with a first signal terminal, and the second electrode of the first transistor is electrically connected with one of a third node and a first node;

[0035] The control electrode of the second transistor is electrically connected with a second scan signal terminal, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node;

[0036] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with a fifth node, and the second electrode of the third transistor is electrically connected with a second node;

[0037] The control electrode of the fourth transistor is electrically connected with the first scan signal terminal, the first electrode of the fourth transistor is electrically connected with a fourth node, and the second electrode of the fourth transistor is electrically connected with the first node;

[0038] The control electrode of the fifth transistor is electrically connected with a light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected with a first power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fifth node;

[0039] The control electrode of the seventh transistor is electrically connected with a reset signal terminal, the first electrode of the seventh transistor is electrically connected with an initial signal terminal, and the second electrode of the seventh transistor is electrically connected with a sixth node;

[0040] The control electrode of the eighth transistor is electrically connected with the second scan signal terminal, the first electrode of the eighth transistor is electrically connected with a data signal terminal, and the second electrode of the eighth transistor is electrically connected with the fourth node;

[0041] The first end of the first capacitor is electrically connected with the first power supply terminal, and the second end of the first capacitor is electrically connected with the fourth node;

[0042] The first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with the second node;

[0043] The first end of the third capacitor is electrically connected with the second signal terminal, and the second end of the third capacitor is electrically connected with the second node.

[0044] In an exemplary embodiment, the data prestorage sub-circuit comprises an eighth transistor and a first capacitor; the first node control sub-circuit comprises a first transistor, a second transistor and a fourth transistor; the second node control sub-circuit comprises a second capacitor, a third capacitor and a seventh transistor; the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor, and the driving sub-circuit comprises a third transistor;

[0045] The control electrode of the first transistor is electrically connected with a control signal terminal, the first electrode of the first transistor is electrically connected with a first signal terminal, and the second electrode of the first transistor is electrically connected with one of a third node and a first node;

[0046] The control electrode of the second transistor is electrically connected with a second scanning signal terminal, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node;

[0047] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with a fifth node, and the second electrode of the third transistor is electrically connected with a second node;

[0048] The control electrode of the fourth transistor is electrically connected with the first scanning signal terminal, the first electrode of the fourth transistor is electrically connected with a fourth node, and the second electrode of the fourth transistor is electrically connected with the first node;

[0049] The control electrode of the fifth transistor is electrically connected with a light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected with a first power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fifth node;

[0050] The control electrode of the sixth transistor is electrically connected with the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected with the second node, and the second electrode of the sixth transistor is electrically connected with a sixth node;

[0051] The control electrode of the seventh transistor is electrically connected with a reset signal terminal, the first electrode of the seventh transistor is electrically connected with an initial signal terminal, and the second electrode of the seventh transistor is electrically connected with the sixth node;

[0052] The control electrode of the eighth transistor is electrically connected with the second scanning signal terminal, the first electrode of the eighth transistor is electrically connected with a data signal terminal, and the second electrode of the eighth transistor is electrically connected with the fourth node;

[0053] The first end of the first capacitor is electrically connected with the first power supply terminal, and the second end of the first capacitor is electrically connected with the fourth node;

[0054] The first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with the second node;

[0055] The first end of the third capacitor is electrically connected with the second signal terminal, and the second end of the third capacitor is electrically connected with the second node.

[0056] In an example embodiment, the first signal terminal and the first power supply terminal are the same signal terminal.

[0057] In an example embodiment, the signal of the first signal terminal is a reference signal, and a difference between a voltage value of the reference signal and a voltage value of the signal of the initial signal terminal is greater than a threshold difference value of the third transistor.

[0058] In an exemplary embodiment, the second electrode of the first transistor is electrically connected with the first node, and the control signal terminal and the second scan signal terminal are the same terminal.

[0059] In an exemplary embodiment, the second signal terminal is the same terminal as one of the initial signal terminal and the first power terminal.

[0060] In a second aspect, the present disclosure also provides a display device, comprising: a plurality of pixel driving circuits as described above, a first data unit, a second data unit, a third data unit, and a fourth data unit, wherein the first data unit provides a signal to a first scan signal terminal, the second data unit provides a signal to a second scan signal terminal, the third data unit provides a signal to a reset signal terminal, and the fourth data unit provides a signal to a light-emitting signal terminal.

[0061] The time period during which the first data unit provides an effective level signal to the first scan signal terminal does not overlap with the time period during which the second data unit provides an effective level signal to the second scan signal terminal, and the time period during which the first data unit provides an effective level signal to the first scan signal terminal occurs after the time period during which the second data unit provides an effective level signal to the second scan signal terminal.

[0062] The time period during which the third data unit provides an effective level signal to the reset signal terminal at least partially overlaps with the time period during which the second data unit provides an effective level signal to the second scan signal terminal, and does not overlap with the time period during which the first data unit provides an effective level signal to the first scan signal terminal.

[0063] The time period during which the fourth data unit provides an effective level signal to the light-emitting signal terminal at least partially overlaps with the time period during which the first data unit provides an effective level signal to the first scan signal terminal, and does not overlap with the time period during which the second data unit provides an effective level signal to the second scan signal terminal.

[0064] In an exemplary embodiment, the pixel driving circuit comprises: a first transistor, a second electrode of the first transistor being electrically connected with a third node.

[0065] The display device further comprises: a fifth data unit, the fifth data unit providing a signal to a control signal terminal.

[0066] The time period during which the fifth data unit provides an effective level signal to the control signal terminal at least partially overlaps with the time period during which the first data unit provides an effective level signal to the first scan signal terminal and the time period during which the second data unit provides an effective level signal to the second scan signal terminal, respectively.

[0067] The time period in which the second data unit provides the valid level signal to the second scan signal end is within the time period in which the fifth data unit provides the valid level signal to the control signal end.

[0068] In an exemplary embodiment, the pixel driving circuit comprises a first transistor, a second electrode of the first transistor being electrically connected with a first node;

[0069] The display device further comprises a fifth data unit, the fifth data unit providing a signal to a control signal end;

[0070] The time period in which the fifth data unit provides the valid level signal to the control signal end at least partially overlaps with the time period in which the second data unit provides the valid level signal to the second scan signal end, and does not overlap with the time period in which the first data unit provides the valid level signal to the first scan signal end.

[0071] The time period in which the third data unit provides the valid level signal to the reset signal end and the time period in which the fifth data unit provides the valid level signal to the control signal end are within the time period in which the second data unit provides the valid level signal to the second scan signal end, and the time period in which the third data unit provides the valid level signal to the reset signal end is before the time period in which the fifth data unit provides the valid level signal to the control signal end.

[0072] In an exemplary embodiment, the pixel driving circuit comprises a first transistor, a second electrode of the first transistor being electrically connected with a first node;

[0073] The display device further comprises a fifth data unit, the fifth data unit providing a signal to a control signal end;

[0074] The time period in which the fifth data unit provides the valid level signal to the control signal end is within the time period in which the second data unit provides the valid level signal to the second scan signal end.

[0075] In an exemplary embodiment, the fifth data unit is the same as the second data unit.

[0076] Other aspects can become apparent from a review of the drawings and detailed description.

[0077] SUMMARY

[0078] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the detailed description, serve to explain the technical solutions of the present disclosure, but do not constitute a limitation on the technical solutions of the present disclosure.

[0079] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0080] Fig. 2 is a structural schematic diagram of a pixel driving circuit according to an example embodiment;

[0081] Fig. 3 is a structural schematic diagram of a pixel driving circuit according to another example embodiment;

[0082] Fig. 4 is an equivalent circuit diagram of a data pre-storage sub-circuit;

[0083] Fig. 5 is an equivalent circuit diagram of a first node control sub-circuit;

[0084] Fig. 6 is an equivalent circuit diagram of the first node control sub-circuit;

[0085] Fig. 7 is an equivalent circuit diagram of a second node control sub-circuit;

[0086] Fig. 8 is an equivalent circuit diagram of a light emitting control sub-circuit in the pixel driving circuit according to Fig. 2;

[0087] Fig. 9 is an equivalent circuit diagram of a light emitting control sub-circuit in the pixel driving circuit according to Fig. 3;

[0088] Fig. 10 is a structural schematic diagram of a pixel driving circuit according to an example embodiment;

[0089] Fig. 11 is a structural schematic diagram of a pixel driving circuit according to another example embodiment;

[0090] Fig. 12 is a structural schematic diagram of a pixel driving circuit according to another example embodiment;

[0091] Fig. 13 is a structural schematic diagram of a pixel driving circuit according to another example embodiment;

[0092] Fig. 14 is a driving timing diagram of the pixel driving circuit according to Figs. 10 and 12;

[0093] Fig. 15 is a driving timing diagram of the pixel driving circuit according to Figs. 11 and 13;

[0094] Fig. 16 is a driving timing diagram of the pixel driving circuit according to Figs. 11 and 13.

[0095] Detailed Description

[0096] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, below will be a detailed description of the embodiments of the present disclosure in conjunction with the accompanying drawings. Note that the embodiments can be implemented in multiple different forms. One of ordinary skill in the art can easily understand that the manners and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0097] The scale of the drawings in this disclosure can be used as a reference in an actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and interval of each film layer, and the width and interval of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings. The drawings described in this disclosure are only schematic diagrams, and one embodiment of the disclosure is not limited to the shapes or values shown in the drawings.

[0098] The ordinal numbers "first", "second", "third" and the like in this specification are used to avoid confusion among components, and are not intended to denote a specific number.

[0099] In this specification, words of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like used to describe the positional relationship of components with reference to the drawings are used to explain the positional relationship of components only for the convenience of describing this specification and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately replaced according to the situation.

[0100] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0101] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0102] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using transistors of opposite polarity, the case where the direction of current flow is changed in circuit operation, or the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0103] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between the components to be connected. Examples of the element having some function of electricity include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, and elements having various functions.

[0104] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0105] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0106] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, or a deformation, and the like.

[0107] The display product includes a plurality of sub-pixels, at least one of which includes a pixel driving circuit and a light emitting device. The pixel driving circuit drives the light emitting device to emit light, thereby realizing display. The pixel driving circuit in the display product is difficult to realize high-frequency driving, so that the display product cannot realize high refresh rate.

[0108] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit provided by an embodiment of the present disclosure includes a data pre-storage sub-circuit, a first node control sub-circuit, a second node control sub-circuit, a driving sub-circuit, and a light emitting control sub-circuit.

[0109] As shown in FIG. 1, the data pre-storing sub-circuit is electrically connected with the second scan signal terminal Gate2, the data signal terminal Data, the first power supply terminal VDD and the fourth node N4 respectively, and is configured to provide the signal of the data signal terminal Data to the fourth node N4 under the control of the signal of the second scan signal terminal Gate2, and store the voltage difference between the signals of the fourth node N4 and the first power supply terminal VDD. The first node control sub-circuit is electrically connected with the control signal terminal CON, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first signal terminal V1, the first node N1, the third node N3 and the fourth node N4 respectively, and is configured to provide the signal of the first signal terminal V1 or the fourth node N4 to the first node N1 under the control of the signals of the control signal terminal CON, the first scan signal terminal Gate1 and the second scan signal terminal Gate2, and form a path between the first node N1 and the third node N3. The second node control sub-circuit is electrically connected with the reset signal terminal Reset, the initial signal terminal INIT, the second signal terminal V2, the second node N2, the third node N3 and the sixth node N6 respectively, and is configured to store the voltage difference between the signals of the second node N2 and the third node N3, and the voltage difference between the signal of the second node N2 and the signal of the second signal terminal V2, and provide the signal of the initial signal terminal INIT to the sixth node N6 under the control of the signal of the reset signal terminal Reset. The driving sub-circuit is electrically connected with the first node N1, the second node N2 and the fifth node N5 respectively, and is configured to output a driving current under the control of the signals of the first node N1, the second node N2 and the fifth node N5. The light emitting control sub-circuit is electrically connected with the light emitting signal terminal EM, the first power supply terminal VDD and the fifth node N5 respectively, and is configured to provide the signal of the first power supply terminal VDD to the fifth node N5 under the control of the signal of the light emitting signal terminal EM.

[0110] In an example embodiment, the first power supply terminal VDD can continuously provide a high level signal, and the signal of the first power supply terminal VDD is a direct current signal.

[0111] In an example embodiment, the pixel driving circuit is configured to drive the light emitting device L to emit light. As shown in FIG. 1, the light emitting device is electrically connected with the sixth node N6 and the second power supply terminal VSS respectively.

[0112] In an example embodiment, the second power supply terminal VSS can continuously provide a low level signal, and the signal of the second power supply terminal VSS is a direct current signal.

[0113] In an example embodiment, the light emitting device can include a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked. Illustratively, the anode of the light emitting device is electrically connected with the sixth node N6, and the cathode of the light emitting device is electrically connected with the second power supply terminal VSS.

[0114] In an example embodiment, the light emitting device can include a current driven device, and can employ a current type light emitting diode, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED) or an Organic Light Emitting Diode (OLED) or a Quantum Light Emitting Diode (QLED). A typical size (e.g., length) of a Micro LED can be less than 100 μm, such as 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED can be about 100 μm to 300 μm, such as 120 μm to 260 μm.

[0115] In an example embodiment, the organic light emitting layer can include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Block Layer (EBL), an Emitting Layer (EML), a Hole Block Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked. In an example embodiment, the HILs of all sub-pixels can be a common layer connected together, the EILs of all sub-pixels can be a common layer connected together, the HTLs of all sub-pixels can be a common layer connected together, the ETLs of all sub-pixels can be a common layer connected together, the HBLs of all sub-pixels can be a common layer connected together, the EMLs of adjacent sub-pixels can have a small amount of overlap or can be isolated, and the EBLs of adjacent sub-pixels can have a small amount of overlap or can be isolated.

[0116] The pixel driving circuit provided by the embodiments of the present disclosure can pre-store the signal of the data signal end through the cooperation of the data pre-storing sub-circuit, the first node control sub-circuit and the second node control sub-circuit, so as to ensure the compensation time and the writing time, to realize high-frequency driving of the pixel driving circuit, and to realize high refresh rate of the display product.

[0117] Fig. 2 is a structural schematic diagram of a pixel driving circuit according to an example embodiment. As shown in Fig. 2, the second node N2 and the sixth node N6 can be the same node.

[0118] Fig. 3 is a structural schematic diagram of a pixel driving circuit according to another example embodiment. As shown in Fig. 3, the light emitting control sub-circuit is also electrically connected with the second node N2 and the sixth node N6, and is configured to provide a signal of the second node N2 to the sixth node N6 under the control of a signal of the light emitting signal terminal EM. In Fig. 3, the second node N2 and the sixth node N6 are different nodes.

[0119] Fig. 4 is an equivalent circuit diagram of the data pre-storage sub-circuit. As shown in Fig. 4, in an example embodiment, the data pre-storage sub-circuit includes an eighth transistor T8 and a first capacitor C1. The control electrode of the eighth transistor T8 is electrically connected with the second scan signal terminal Gate2, the first electrode of the eighth transistor T8 is electrically connected with the data signal terminal Data, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4. The first end of the first capacitor C1 is electrically connected with the first power supply terminal VDD, and the second end of the first capacitor C1 is electrically connected with the fourth node N4.

[0120] In an example embodiment, the eighth transistor T8 can be referred to as a pre-storage transistor.

[0121] In an example embodiment, the first capacitor C1 can store a signal of the data signal terminal Data, and ensure the stability of the signal of the fourth node N4.

[0122] Fig. 4 only shows an example structure of the data pre-storage sub-circuit, and those skilled in the art can understand that the implementation of the data pre-storage sub-circuit is not limited thereto.

[0123] Fig. 5 is an equivalent circuit diagram of the first node control sub-circuit. As shown in Fig. 5, in an example embodiment, the first node control sub-circuit includes a first transistor T1, a second transistor T2 and a fourth transistor T4. The control electrode of the first transistor T1 is electrically connected with the control signal terminal CON, the first electrode of the first transistor T1 is electrically connected with the first signal terminal V1, and the second electrode of the first transistor T1 is electrically connected with the third node N3. The control electrode of the second transistor T2 is electrically connected with the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the third node N3. The control electrode of the fourth transistor T4 is electrically connected with the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected with the first node N1.

[0124] Fig. 6 is a second equivalent circuit diagram of the first node control sub-circuit. As shown in Fig. 6, in an exemplary embodiment, the first node control sub-circuit comprises a first transistor T1, a second transistor T2 and a fourth transistor T4. The control electrode of the first transistor T1 is electrically connected with the control signal terminal CON, the first electrode of the first transistor T1 is electrically connected with the first signal terminal V1, and the second electrode of the first transistor T1 is electrically connected with the first node N1. The control electrode of the second transistor T2 is electrically connected with the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the third node N3. The control electrode of the fourth transistor T4 is electrically connected with the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected with the first node N1.

[0125] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data writing transistor.

[0126] Two exemplary structures of the first node control sub-circuit are shown in Fig. 5 and Fig. 6, and those skilled in the art can easily understand that the implementation of the first node control sub-circuit is not limited thereto.

[0127] Fig. 7 is an equivalent circuit diagram of the second node control sub-circuit. As shown in Fig. 7, in an exemplary embodiment, the second node control sub-circuit comprises a second capacitor C2, a third capacitor C3 and a seventh transistor T7. The first end of the second capacitor C2 is electrically connected with the third node N3, and the second end of the second capacitor C2 is electrically connected with the second node N2. The first end of the third capacitor C3 is electrically connected with the second signal terminal V2, and the second end of the third capacitor C3 is electrically connected with the second node N2. The control electrode of the seventh transistor T7 is electrically connected with the reset signal terminal Reset, the first electrode of the seventh transistor T7 is electrically connected with the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected with the sixth node N6.

[0128] In an exemplary embodiment, the seventh transistor T7 can be referred to as an anode reset transistor.

[0129] In an exemplary embodiment, Fig. 7 is described by taking the second node N2 and the sixth node N6 as the same node as an example, and the second node N2 and the sixth node N6 can also be connected through the light emission control sub-circuit.

[0130] In an exemplary embodiment, the second capacitor C2 and the third capacitor C3 can ensure the stability of the signal of the second node N2.

[0131] An exemplary structure of the second node control sub-circuit is shown in Fig. 7, and those skilled in the art can easily understand that the implementation of the second node control sub-circuit is not limited thereto.

[0132] Fig. 8 is an equivalent circuit diagram of the light-emitting control sub-circuit in the pixel driving circuit provided in Fig. 2. As shown in Fig. 8, in an exemplary embodiment, the light-emitting control sub-circuit comprises a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5.

[0133] Fig. 9 is an equivalent circuit diagram of the light-emitting control sub-circuit in the pixel driving circuit provided in Fig. 3. As shown in Fig. 9, in an exemplary embodiment, the light-emitting control sub-circuit comprises a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5. The control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the sixth node N6.

[0134] Figs. 8 and 9 show two exemplary structures of the light-emitting control sub-circuit, and it is easy for those skilled in the art to understand that the implementation of the light-emitting control sub-circuit is not limited thereto.

[0135] In an exemplary embodiment, as shown in Figs. 8 and 9, the driving sub-circuit comprises a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the fifth node N5, and the second electrode of the third transistor T3 is electrically connected to the second node N2.

[0136] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor.

[0137] In an exemplary embodiment, the provision of the sixth transistor T6 in the light-emitting control sub-circuit can reduce the influence of the parasitic capacitance of the light-emitting device corresponding to the different high-pixel driving circuits connected to the second electrode of the third transistor T3, and can improve the reliability of the pixel driving circuit.

[0138] Fig. 10 is a structural schematic diagram of a pixel driving circuit, and Fig. 11 is a structural schematic diagram of a pixel driving circuit. As shown in Figs. 10 and 11, the data pre-storage sub-circuit can comprise an eighth transistor T8 and a first capacitor C1; the first node control sub-circuit can comprise a first transistor T1, a second transistor T2, and a fourth transistor T4; the second node control sub-circuit can comprise a second capacitor C2, a third capacitor C3, and a seventh transistor T7; the light-emitting control sub-circuit can comprise a fifth transistor T5, and the driving sub-circuit can comprise a third transistor T3.

[0139] As shown in FIG. 10 and FIG. 11, the control electrode of the first transistor T1 is electrically connected with the control signal terminal CON, the first electrode of the first transistor T1 is electrically connected with the first signal terminal V1, and the second electrode of the first transistor T1 is electrically connected with one of the third node N3 and the first node N1; the control electrode of the second transistor T2 is electrically connected with the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the third node N3; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the fifth node N5, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected with the first node N1; the control electrode of the fifth transistor T5 is electrically connected with the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected with the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the reset signal terminal Reset, the first electrode of the seventh transistor T7 is electrically connected with the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected with the second node N2 (also the sixth node N6); the control electrode of the eighth transistor T8 is electrically connected with the second scan signal terminal Gate2, the first electrode of the eighth transistor T8 is electrically connected with the data signal terminal Data, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the first end of the first capacitor C1 is electrically connected with the first power supply terminal VDD, and the second end of the first capacitor C1 is electrically connected with the fourth node N4; the first end of the second capacitor C2 is electrically connected with the third node N3, and the second end of the second capacitor C2 is electrically connected with the second node N2; the first end of the third capacitor C3 is electrically connected with the second signal terminal V2, and the second end of the third capacitor C3 is electrically connected with the second node N2. FIG. 10 is an example in which the second electrode of the first transistor T1 is electrically connected with the third node N3, and FIG. 11 is an example in which the second electrode of the first transistor T1 is electrically connected with the first node N1.

[0140] FIG. 12 is a structural schematic diagram of a pixel driving circuit three, and FIG. 13 is a structural schematic diagram of a pixel driving circuit four. As shown in FIG. 12 and FIG. 13, in an exemplary embodiment, the data pre-storage sub-circuit includes the eighth transistor T8 and the first capacitor C1; the first node control sub-circuit includes the first transistor T1, the second transistor T2 and the fourth transistor T4; the second node control sub-circuit includes the second capacitor C2, the third capacitor C3 and the seventh transistor T7; the light-emitting control sub-circuit includes the fifth transistor T5 and the sixth transistor T6, and the driving sub-circuit includes the third transistor T3.

[0141] As shown in FIG. 12 and FIG. 13, the control electrode of the first transistor T1 is electrically connected with the control signal end CON, the first electrode of the first transistor T1 is electrically connected with the first signal end V1, and the second electrode of the first transistor T1 is electrically connected with one of the third node N3 and the first node N1; the control electrode of the second transistor T2 is electrically connected with the second scanning signal end Gate2, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the third node N3; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the fifth node N5, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the first scanning signal end Gate1, the first electrode of the fourth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected with the first node N1; the control electrode of the fifth transistor T5 is electrically connected with the light-emitting signal end EM, the first electrode of the fifth transistor T5 is electrically connected with the first power supply end VDD, and the second electrode of the fifth transistor T5 is electrically connected with the fifth node N5; the control electrode of the sixth transistor T6 is electrically connected with the light-emitting signal end EM, the first electrode of the sixth transistor T6 is electrically connected with the second node N2, and the second electrode of the sixth transistor T6 is electrically connected with the sixth node N6; the control electrode of the seventh transistor T7 is electrically connected with the reset signal end Reset, the first electrode of the seventh transistor T7 is electrically connected with the initial signal end INIT, and the second electrode of the seventh transistor T7 is electrically connected with the sixth node N6; the control electrode of the eighth transistor T8 is electrically connected with the second scanning signal end Gate2, the first electrode of the eighth transistor T8 is electrically connected with the data signal end Data, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the first end of the first capacitor C1 is electrically connected with the first power supply end VDD, and the second end of the first capacitor C1 is electrically connected with the fourth node N4; the first end of the second capacitor C2 is electrically connected with the third node N3, and the second end of the second capacitor C2 is electrically connected with the second node N2; the first end of the third capacitor C3 is electrically connected with the second signal end V2, and the second end of the third capacitor C3 is electrically connected with the second node N2. FIG. 12 is an example of the second electrode of the first transistor T1 being electrically connected with the third node N3, and FIG. 13 is an example of the second electrode of the first transistor T1 being electrically connected with the first node N1.

[0142] In an example embodiment, the transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltage), and the off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0143] In an example embodiment, the pixel driving circuit includes a plurality of transistors, at least one of which is an N-type transistor.

[0144] In an example embodiment, the first transistor T1 to the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 in the pixel driving circuit provided in FIGS. 10 and 11 are all N-type transistors.

[0145] In an example embodiment, the first transistor T1 to the eighth transistor T8 in the pixel driving circuit provided in FIGS. 12 and 13 are all N-type transistors.

[0146] In an example embodiment, the N-type transistor can be an oxide thin film transistor. The active pattern of the oxide thin film transistor uses an oxide semiconductor (Oxide). The oxide thin film transistor has the advantage of low leakage current, which can reduce power consumption and improve display quality.

[0147] In an example embodiment, the first signal terminal V1 can be the same signal terminal as the first power terminal VDD.

[0148] In an example embodiment, the signal of the first signal terminal V1 is a reference signal, and the voltage difference between the voltage of the reference signal and the voltage of the signal of the initial signal terminal INIT is greater than the threshold difference of the third transistor T3.

[0149] In an example embodiment, the second electrode of the first transistor T1 is electrically connected to the first node N1, and the control signal terminal CON and the second scan signal terminal Gate2 can be the same signal terminal.

[0150] In an example embodiment, the display device in which the pixel driving circuit is located further includes a driving circuit located in a non-display area and configured to provide signals to the first scan signal terminal, the second scan signal terminal, the light-emitting signal terminal, the reset signal terminal, and the control signal terminal connected to the pixel driving circuit, and the pixel driving circuit is located in a display area. The control signal terminal CON and the second scan signal terminal Gate2 being the same signal terminal can reduce the size of the driving circuit located in the non-display area.

[0151] In the exemplary embodiments, the second signal terminal V2 is the same as one of the initial signal terminal INIT and the first power supply terminal VDD. For example, the second signal terminal V2 can be the initial signal terminal INIT, or the second signal terminal V2 can be the first power supply terminal VDD.

[0152] In the exemplary embodiments, when the first signal terminal V1 is the first power supply terminal VDD, all the transistors in the pixel driving circuit provided in FIG. 11 and FIG. 13 can be array tested, so that all the transistors in the pixel driving circuit can be ensured to be in good condition before the display product is put into the market, and the waste of materials in the manufacturing process can be avoided.

[0153] In the exemplary embodiments, the pixel driving circuit provided in FIG. 11 can be array tested through two test paths, one of which includes the seventh transistor T7, the third transistor T3, the fifth transistor T5, the first transistor T1, the fourth transistor T4 and the fifth transistor T5, and the other of which includes the second transistor T2, the fourth transistor T4 and the eighth transistor T8.

[0154] In the exemplary embodiments, the pixel driving circuit provided in FIG. 13 can be array tested through two test paths, one of which includes the seventh transistor T7, the sixth transistor T6, the third transistor T3, the fifth transistor T5, the first transistor T1, the fourth transistor T4 and the fifth transistor T5, and the other of which includes the second transistor T2, the fourth transistor T4 and the eighth transistor T8.

[0155] In the exemplary embodiments, any one of the first capacitor C1 to the third capacitor C3 can be a capacitor device made by a process, for example, the capacitor device can be realized by making a special capacitor electrode, and the capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon) and the like. Alternatively, any one of the first capacitor C1 to the third capacitor C3 can be a parasitic capacitor between multiple devices, which can be realized by the transistors themselves and other devices and lines. The connection mode of any one of the first capacitor C1 to the third capacitor C3 includes but is not limited to the above-described mode, and can be other applicable connection modes, and can only store the level of the corresponding node. Here, the exemplary embodiments of the present disclosure do not limit this.

[0156] FIG. 14 is a driving timing diagram of the pixel driving circuit provided in FIG. 10 and FIG. 12. FIG. 15 is a driving timing diagram one of the pixel driving circuit provided in FIG. 11 and FIG. 13, and FIG. 16 is a driving timing diagram two of the pixel driving circuit provided in FIG. 11 and FIG. 13. FIG. 14 to FIG. 16 are described by taking all the transistors in the pixel driving circuit as N-type transistors as an example.

[0157] In the exemplary embodiment, as shown in FIGS. 14 to 16, the period in which the signal of the first scan signal terminal Gate 1 is an active level signal does not overlap the period in which the signal of the second scan signal terminal Gate 2 is an active level signal, and the period in which the signal of the first scan signal terminal Gate 1 is an active level signal occurs after the period in which the signal of the second scan signal terminal Gate 2 is an active level signal.

[0158] In the exemplary embodiment, as shown in FIGS. 14 to 16, the period in which the signal of the reset signal terminal Reset is an active level signal at least partially overlaps the period in which the signal of the second scan signal terminal Gate 2 is an active level signal, and does not overlap the period in which the signal of the first scan signal terminal Gate 1 is an active level signal.

[0159] In the exemplary embodiment, as shown in FIGS. 14 to 16, the period in which the signal of the emission signal terminal EM is an active level signal at least partially overlaps the period in which the signal of the first data unit to the first scan signal terminal Gate 1 is an active level signal, and does not overlap the period in which the signal of the second data unit to the second scan signal terminal Gate 2 is an active level signal.

[0160] In the exemplary embodiment, as shown in FIG. 14, the period in which the signal of the control signal terminal CON is an active level signal at least partially overlaps the period in which the signal of the first scan signal terminal Gate 1 is an active level signal and the period in which the signal of the second scan signal terminal Gate 2 is an active level signal.

[0161] In the exemplary embodiment, as shown in FIG. 14, the period in which the signal of the second scan signal terminal Gate 2 is an active level signal is within the range of the period in which the signal of the control signal terminal CON is an active level signal.

[0162] In the exemplary embodiment, as shown in FIG. 15, the period in which the signal of the control signal terminal CON is an active level signal at least partially overlaps the period in which the signal of the second scan signal terminal Gate 2 is an active level signal, and does not overlap the period in which the signal of the first scan signal terminal Gate 1 is an active level signal.

[0163] In the exemplary embodiment, as shown in FIG. 15, the period in which the signal of the reset signal terminal Reset is an active level signal and the period in which the signal of the control signal terminal CON is an active level signal are within the range of the period in which the signal of the second scan signal terminal Gate 2 is an active level signal, and the period in which the signal of the reset signal terminal Reset is an active level signal occurs before the period in which the signal of the control signal terminal CON is an active level signal.

[0164] In the example embodiment, as shown in FIG. 16, the time period during which the signal of the control signal terminal CON is the active level signal is within the time period during which the signal of the second scan signal terminal Gate2 is the active level signal.

[0165] In the example embodiment, the time period during which the signal of the control signal terminal CON is the active level signal coincides with the time period during which the signal of the second scan signal terminal Gate2 is the active level signal.

[0166] The working process of the pixel driving circuit exemplified by FIG. 10 is described below. As shown in FIGS. 10-14, the working process of the pixel driving circuit provided by FIG. 10 can include:

[0167] In the first stage P11, the initialization stage and the data prestorage stage, the signals of the reset signal terminal Reset, the control signal terminal CON and the second scan signal terminal Gate2 are high level signals, the signals of the first scan signal terminal Gate1 and the emission signal terminal EM1 are low level signals, and the data signal terminal Data writes the data signal. The first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned on, and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0168] The first transistor T1 and the second transistor T2 are turned on, the signal of the first signal terminal V1 initializes the first node N1 through the turned-on first transistor T1, the third node N3 and the turned-on second transistor T2, and clears the charges of the first node N1 and the third node N3. The seventh transistor T7 is turned on, the signal of the initial signal terminal INIT initializes the second node N2 (also the sixth node N6) through the turned-on seventh transistor, and clears the charges of the second node N2 (also the sixth node N6). The eighth transistor T8 is turned on, and the data signal of the data signal terminal Data is written into the fourth node N4 through the turned-on eighth transistor T8, so as to prestore the data signal of the data signal terminal Data in the first capacitor C1.

[0169] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 = V1, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 = Vinit, the voltage value of the signal of the third node N3 satisfies V N3 = V1, the voltage value of the signal of the fourth node N4 satisfies V N4 = Vdata, V1 is the voltage value of the signal of the first signal terminal V1, Vinit is the voltage value of the signal of the initial signal terminal INIT, and Vdata is the voltage value of the data signal.

[0170] In the second stage P12, the signals of the control signal terminal CON and the second scan signal terminal Gate2 are high level signals, the signals of the reset signal terminal Reset, the first scan signal terminal Gate1 and the light emitting signal terminal EM are low level signals, and the data signal terminal Data writes data signals. The first transistor T1, the second transistor T2 and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off.

[0171] The first transistor T1 and the second transistor T2 are turned on, the signal of the first signal terminal V1 continuously initializes the first node N1 through the turned-on first transistor T1, the third node N3 and the turned-on second transistor T2, the third transistor T3 is turned on, and the signal of the fifth node N5 charges the second node N2 (also the sixth node N6) until the voltage value of the signal of the second node N2 (also the sixth node N6) is V1-Vth, and Vth is the threshold voltage of the third transistor T3. The eighth transistor T8 is turned on, and the data signal of the data signal terminal Data is continuously written to the fourth node N4 through the turned-on eighth transistor T8, and the data signal of the data signal terminal Data is pre-stored in the first capacitor C1.

[0172] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 =V1, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 =V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 =V1, and the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata.

[0173] In the third stage P13, the signals of the first scan signal terminal Gate1 and the control signal terminal CON are high level signals, the signals of the reset signal terminal Reset, the second scan signal terminal Gate2 and the light emitting signal terminal EM are low level signals. The first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0174] The first transistor T1 is turned on, and the signal of the first signal terminal V1 is written to the third node N3 through the turned-on first transistor T1 to continuously initialize the third node N3. The fourth transistor T4 is turned on, and the signal of the fourth node N4 is written to the first node N1 through the turned-on fourth transistor T4. Under the action of the second capacitor C2 and the third capacitor C3, the second node N2 (also the sixth node N6) maintains the signal of the previous stage.

[0175] In this stage, the voltage value of the signal of the first node N1 satisfies V N1= Vdata, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 = V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 = V1, the voltage value of the signal of the fourth node N4 satisfies V N4 = Vdata.

[0176] The fourth stage P14 is the light emitting stage, the signals of the first scanning signal end Gate 1 and the light emitting signal end EM are high level signals, the signals of the second scanning signal end Gate 2, the reset signal end Reset and the control signal end CON are low level signals. The fourth transistor T4 and the fifth transistor T5 are turned on, and the first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0177] The fourth transistor T4 is turned on, the first node N1 and the fourth node N4 form a path, the first node N1 is kept stable under the action of the first capacitor C1, and the fifth transistor T5 is turned on to provide a driving current to the first electrode of the light emitting device L from the power supply voltage output by the first power supply end VDD through the turned-on fifth transistor T5 and the turned-on third transistor T3, so as to drive the light emitting device L to emit light.

[0178] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Since the voltage of the signal of the first node N1 satisfies V N1 = Vdata, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 = V1-Vth.

[0179] Therefore, the driving current I of the third transistor T3 is: I = K*(Vgs-Vth) 2 = K*(Vdata-V1+Vth-Vth) 2 = K*(Vdata-V1) 2

[0180] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0181] In the example embodiment, K = 1 / 2 * μ * Cox * W / L, where μ is the mobility of the third transistor, Cox is the oxide layer capacitance per unit area, and W / L is the width-length ratio of the channel region of the active layer of the third transistor, where the oxide layer refers to the film layer between the film layer where the control electrode of the third transistor is located and the film layer where the first electrode and the second electrode of the third transistor are located, and the oxide layer capacitance refers to the capacitance between the conductive film layers on both sides of the oxide layer.

[0182] As can be seen from the derivation of the above current formula, in the light-emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0183] The working process of the pixel driving circuit shown in FIG. 12 is described below. As shown in FIGS. 12 and 14, the working process of the pixel driving circuit provided in FIG. 12 can include:

[0184] In the first stage P11, the initialization stage and the data pre-storage stage, the signals of the reset signal end Reset, the control signal end CON, and the second scan signal end Gate2 are high-level signals, the signals of the first scan signal end Gate1 and the light-emitting signal end EM1 are low-level signals, and the data signal end Data writes the data signal. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0185] The first transistor T1 and the second transistor T2 are turned on, the signal of the first signal end V1 initializes the first node N1 through the turned-on first transistor T1, the third node N3, and the turned-on second transistor T2, and clears the charges of the first node N1 and the third node N3. The seventh transistor T7 is turned on, the signal of the initial signal end INIT initializes the sixth node N6 through the turned-on seventh transistor, and clears the charges of the sixth node N6. The eighth transistor T8 is turned on, and the data signal of the data signal end Data is written into the fourth node N4 through the turned-on eighth transistor T8, so as to pre-store the data signal of the data signal end Data in the first capacitor C1.

[0186] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 = V1, the voltage value of the signal of the sixth node N6 satisfies V N6 = Vinit, the voltage value of the signal of the third node N3 satisfies V N3 = V1, and the voltage value of the signal of the fourth node N4 satisfies V N4=Vdata, where V1 is the voltage value of the signal at the first signal terminal V1, Vinit is the voltage value of the signal at the initial signal terminal INIT, and Vdata is the voltage value of the data signal.

[0187] In the second stage (P12), the threshold compensation stage and data pre-storage stage, the control signal terminal CON and the second scan signal terminal Gate2 are high-level signals, while the reset signal terminal Reset, the first scan signal terminal Gate1, and the light emission signal terminal EM1 are low-level signals. The data signal terminal Data writes data. The first transistor T1, the second transistor T2, and the eighth transistor T8 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0188] The first transistor T1 and the second transistor T2 are turned on. The signal at the first signal terminal V1 continuously initializes the first node N1 through the turned-on first transistor T1, the third node N3, and the turned-on second transistor T2. The third transistor T3 is turned on, and the signal at the fifth node N5 charges the second node N2 until the voltage value of the signal at the second node N2 is V1-Vth, where Vth is the threshold voltage of the third transistor T3. The eighth transistor T8 is turned on, and the data signal at the data signal terminal Data is continuously written to the fourth node N4 through the turned-on eighth transistor T8, pre-storing the data signal at the data signal terminal Data in the first capacitor C1.

[0189] In this stage, the voltage value of the signal at the first node N1 satisfies V N1 =V1, the voltage value of the signal at the second node N2 satisfies V N2 =V1-Vth, the voltage value of the signal at the third node N3 satisfies V N3 =V1, the voltage value of the signal at the fourth node N4 satisfies V N4 =Vdata.

[0190] In the third stage (P13), the data writing stage, the signals at the first scan signal terminal (Gate1) and the control signal terminal (CON) are high-level signals, while the signals at the reset signal terminal (Reset), the second scan signal terminal (Gate2), and the light emission signal terminal (EM) are low-level signals. The first transistor (T1) and the fourth transistor (T4) are turned on, while the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) are turned off.

[0191] The first transistor T1 is turned on, and the signal of the first signal terminal V1 is written into the third node N3 through the turned-on first transistor T1, and the third node N3 is continuously initialized. The fourth transistor T4 is turned on, and the signal of the fourth node N4 is written into the first node N1 through the turned-on fourth transistor T4, and the second node N2 keeps the signal of the last stage under the action of the second capacitor C2 and the third capacitor C3.

[0192] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 =Vdata, the voltage value of the signal of the second node N2 satisfies V N2 =V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 =V1, and the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata.

[0193] In the fourth stage P14, the light emitting stage, the signals of the first scan signal terminal Gate1 and the light emitting signal terminal EM are high level signals, and the signals of the second scan signal terminal Gate2, the reset signal terminal Reset and the control signal terminal CON are low level signals. The fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0194] The fourth transistor T4 is turned on, and the first node N1 and the fourth node N4 form a path, and the first node N1 keeps stable under the action of the first capacitor C1. The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6 to drive the driving current of the light emitting device L to emit light.

[0195] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Since the voltage of the signal of the first node N1 satisfies V N1 =Vdata, the voltage value of the signal of the second node N2 satisfies V N2 =V1-Vth.

[0196] Thus, the driving current I of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(Vdata-V1+Vth-Vth) 2 =K*(Vdata-V1) 2

[0197] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current of the light emitting device L, K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0198] In the example embodiment, K = 1 / 2 * μ * Cox * W / L, wherein μ is the mobility of the third transistor, Cox is the oxide layer capacitance per unit area, and W / L is the width-length ratio of the channel region of the active layer of the third transistor.

[0199] As can be seen from the derivation of the above current formula, in the light emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0200] The working process of the pixel driving circuit provided in FIG. 11 will be described below. As shown in FIG. 11, the working process of the pixel driving circuit provided in FIG. 11 can include:

[0201] In the first stage P21, the first initialization stage and the data pre-storage stage, the signals of the reset signal end Reset and the second scan signal end Gate2 are high level signals, the signals of the control signal end CON, the first scan signal end Gate1 and the light emitting signal end EM1 are low level signals, and the data signal end Data writes the data signal. The second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1, the fourth transistor T4 and the fifth transistor T5 are turned off.

[0202] The second transistor T2 is turned on, and a path is formed between the first node N1 and the third node N3. The seventh transistor T7 is turned on, and the signal of the initial signal end INIT is initialized to the second node N2 (also the sixth node N6) through the turned-on seventh transistor T7, so as to clear the charge of the second node N2 (also the sixth node N6). The eighth transistor T8 is turned on, and the data signal of the data signal end Data is written into the fourth node N4 through the turned-on eighth transistor T8, so as to pre-store the data signal of the data signal end Data in the first capacitor C1.

[0203] In this stage, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 = Vinit, and the voltage value of the signal of the fourth node N4 satisfies V N4 = Vdata, Vinit is the voltage value of the signal of the initial signal end INIT, and Vdata is the voltage value of the data signal.

[0204] In the second stage P22, the signals of the control signal terminal CON and the second scan signal terminal Gate2 are high level signals, the signals of the reset signal terminal Reset, the first scan signal terminal Gate1 and the light emitting signal terminal EM1 are low level signals, and the data signal terminal Data writes data signals. The first transistor T1, the second transistor T2 and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off.

[0205] The first transistor T1 is turned on, the signal of the first signal terminal V1 is written to the first node N1 through the turned-on first transistor T1, the second transistor T2 is turned on, the first node N1 and the third node N3 form a path, and the third node N3 is initialized, the charge of the third node N3 is cleared, the third transistor T3 is turned on, and the signal of the fifth node N5 charges the second node N2 (also the sixth node N6), until the voltage value of the signal of the second node N2 (also the sixth node N6) is V1-Vth, and Vth is the threshold voltage of the third transistor T3. The eighth transistor T8 is turned on, and the data signal of the data signal terminal Data is continuously written to the fourth node N4 through the turned-on eighth transistor T8, and the data signal of the data signal terminal Data is pre-stored in the first capacitor C1.

[0206] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 =V1, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 =V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 =V1, the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata, and V1 is the voltage value of the signal of the first signal terminal V1.

[0207] In the third stage P23, the signal of the first scan signal terminal Gate1 is a high level signal, the signals of the control signal terminal CON, the reset signal terminal Reset, the second scan signal terminal Gate2 and the light emitting signal terminal EM are low level signals. The fourth transistor T4 is turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0208] The fourth transistor T4 is turned on, and the signal of the fourth node N4 is written to the first node N1 through the turned-on fourth transistor T4. Under the action of the second capacitor C2 and the third capacitor C3, the second node N2 (also the sixth node N6) maintains the signal of the previous stage.

[0209] In this stage, the voltage value of the signal of the first node N1 satisfies VN1 = Vdata, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 = V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 = V1, the voltage value of the signal of the fourth node N4 satisfies V N4 = Vdata.

[0210] The fourth stage P24, the light emitting stage, the signals of the first scanning signal end Gate1 and the light emitting signal end EM are high level signals, the signals of the second scanning signal end Gate2, the reset signal end Reset and the control signal end CON are low level signals. The fourth transistor T4 and the fifth transistor T5 are turned on, and the first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0211] The fourth transistor T4 is turned on, the first node N1 and the fourth node N4 form a path, the first node N1 is kept stable under the action of the first capacitor C1, and the fifth transistor T5 is turned on to provide a driving current to the first electrode of the light emitting device L from the power supply voltage output by the first power supply end VDD through the turned-on fifth transistor T5 and the turned-on third transistor T3, so as to drive the light emitting device L to emit light.

[0212] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Since the voltage of the signal of the first node N1 satisfies V N1 = Vdata, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 = V1-Vth.

[0213] Thus, the driving current I of the third transistor T3 is: I = K*(Vgs-Vth) 2 = K*(Vdata-V1+Vth-Vth) 2 = K*(Vdata-V1) 2

[0214] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0215] In the exemplary embodiment, K = 1 / 2*μ*Cox*W / L, wherein μ is the mobility of the third transistor, Cox is the oxide layer capacitance per unit area, and W / L is the width-length ratio of the channel region of the active layer of the third transistor.

[0216] It can be seen from the derivation of the current formula that, in the light emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0217] The working process of the pixel driving circuit exemplified by FIG. 11 is described below. As shown in FIG. 11 and FIG. 16, the working process of the pixel driving circuit provided in FIG. 11 can include:

[0218] In the first stage P31, the initialization stage and the data prestorage stage, the signals of the control signal end CON, the reset signal end Reset and the second scan signal end Gate2 are high-level signals, the signals of the first scan signal end Gate1 and the light emitting signal end EM1 are low-level signals, and the data signal end Data writes the data signal. The first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned on, and the fourth transistor T4 and the fifth transistor T5 are turned off.

[0219] The first transistor T1 is turned on, and the signal of the first signal end V1 is written to the first node N1 through the turned-on first transistor T1, the initialization of the first node N1 is continuously performed, the second transistor T2 is turned on, a path is formed between the first node N1 and the third node N3, the third node N3 is initialized, and the charge of the third node N3 is cleared. The seventh transistor T7 is turned on, and the signal of the initial signal end INIT is initialized to the second node N2 (also the sixth node N6) through the turned-on seventh transistor, and the charge of the second node N2 (also the sixth node N6) is cleared. The eighth transistor T8 is turned on, and the data signal of the data signal end Data is written to the fourth node N4 through the turned-on eighth transistor T8, and the data signal of the data signal end Data is pre-stored in the first capacitor C1.

[0220] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 =V1, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 =Vinit, the voltage value of the signal of the third node N3 satisfies V N3 =V1, the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata, V1 is the voltage value of the signal of the first signal end V1, Vinit is the voltage value of the signal of the initial signal end INIT, and Vdata is the voltage value of the data signal.

[0221] In the second stage P32, the signals of the control signal terminal CON and the second scan signal terminal Gate2 are high level signals, the signals of the reset signal terminal Reset, the first scan signal terminal Gate1 and the light emitting signal terminal EM1 are low level signals, and the data signal terminal Data writes data signals. The first transistor T1, the second transistor T2 and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off.

[0222] The first transistor T1 is turned on, the signal of the first signal terminal V1 is written into the first node N1 through the turned-on first transistor T1, the initialization of the first node N1 is continuously performed, the second transistor T2 is turned on, the first node N1 and the third node N3 form a path, the initialization of the third node N3 is performed, the charge of the third node N3 is cleared, the third transistor T3 is turned on, the signal of the fifth node N5 charges the second node N2 (also the sixth node N6), until the voltage value of the signal of the second node N2 (also the sixth node N6) is V1-Vth, Vth is the threshold voltage of the third transistor T3. The eighth transistor T8 is turned on, and the data signal of the data signal terminal Data is continuously written into the fourth node N4 through the turned-on eighth transistor T8, so that the data signal of the data signal terminal Data is pre-stored in the first capacitor C1.

[0223] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 =V1, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 =V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 =V1, the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata, V1 is the voltage value of the signal of the first signal terminal V1.

[0224] In the third stage P33, the signal of the first scan signal terminal Gate1 is a high level signal, the signals of the control signal terminal CON, the reset signal terminal Reset, the second scan signal terminal Gate2 and the light emitting signal terminal EM are low level signals. The fourth transistor T4 is turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0225] The fourth transistor T4 is turned on, and the signal of the fourth node N4 is written into the first node N1 through the turned-on fourth transistor T4. Under the action of the second capacitor C2 and the third capacitor C3, the second node N2 (also the sixth node N6) keeps the signal of the previous stage.

[0226] In this stage, the voltage value of the signal of the first node N1 satisfies V N1= Vdata, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 = V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 = V1, the voltage value of the signal of the fourth node N4 satisfies V N4 = Vdata.

[0227] In the fourth stage P34, the signals of the first scanning signal end Gate1 and the light emitting signal end EM are high level signals, and the signals of the second scanning signal end Gate2, the reset signal end Reset and the control signal end CON are low level signals. The fourth transistor T4 and the fifth transistor T5 are turned on, and the first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0228] The fourth transistor T4 is turned on, the first node N1 and the fourth node N4 form a path, the first node N1 is kept stable under the action of the first capacitor C1, and the fifth transistor T5 is turned on to provide a driving current to the first electrode of the light emitting device L from the power supply voltage output by the first power supply end VDD through the turned-on fifth transistor T5 and the turned-on third transistor T3, so as to drive the light emitting device L to emit light.

[0229] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Since the voltage of the signal of the first node N1 satisfies V N1 = Vdata, the voltage value of the signal of the second node N2 (also the sixth node N6) satisfies V N2 = V1-Vth.

[0230] Thus, the driving current I of the third transistor T3 is: I = K*(Vgs-Vth) 2 = K*(Vdata-V1+Vth-Vth) 2 = K*(Vdata-V1) 2

[0231] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0232] In the exemplary embodiment, K = 1 / 2*μ*Cox*W / L, wherein μ is the mobility of the third transistor, Cox is the oxide layer capacitance per unit area, and W / L is the width-length ratio of the channel region of the active layer of the third transistor.

[0233] It can be seen from the derivation of the current formula that, in the light emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0234] The working process of the pixel driving circuit exemplified by FIG. 13 is described below. As shown in FIG. 13 and FIG. 15, the working process of the pixel driving circuit provided in FIG. 13 can include:

[0235] In the first stage P21, the first initialization stage and the data pre-storage stage, the signals of the reset signal end Reset and the second scan signal end Gate2 are high-level signals, the signals of the control signal end CON, the first scan signal end Gate1 and the light emitting signal end EM1 are low-level signals, and the data signal end Data writes the data signal. The second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0236] The second transistor T2 is turned on, and a path is formed between the first node N1 and the third node N3. The seventh transistor T7 is turned on, and the signal of the initial signal end INIT initializes the sixth node N6 through the turned-on seventh transistor T7, and clears the charge of the sixth node N6. The eighth transistor T8 is turned on, and the data signal of the data signal end Data is written into the fourth node N4 through the turned-on eighth transistor T8, and the data signal of the data signal end Data is pre-stored in the first capacitor C1.

[0237] In this stage, the voltage value of the signal of the sixth node N6 satisfies V N6 = Vinit, the voltage value of the signal of the fourth node N4 satisfies V N4 = Vdata, Vinit is the voltage value of the signal of the initial signal end INIT, and Vdata is the voltage value of the data signal.

[0238] In the second stage P22, the second initialization stage, the threshold compensation stage and the data pre-storage stage, the signals of the control signal end CON and the second scan signal end Gate2 are high-level signals, the signals of the reset signal end Reset, the first scan signal end Gate1 and the light emitting signal end EM1 are low-level signals, and the data signal end Data writes the data signal. The first transistor T1, the second transistor T2 and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0239] The first transistor T1 is turned on, the signal of the first signal terminal V1 is written into the first node N1 through the turned-on first transistor T1, the first node N1 is continuously initialized, the second transistor T2 is turned on, the first node N1 and the third node N3 form a path, the third node N3 is initialized, the charge of the third node N3 is cleared, the third transistor T3 is turned on, the signal of the fifth node N5 charges the second node N2, until the voltage value of the signal of the second node N2 is V1-Vth, Vth is the threshold voltage of the third transistor T3. The eighth transistor T8 is turned on, the data signal of the data signal terminal Data is continuously written into the fourth node N4 through the turned-on eighth transistor T8, and the data signal of the data signal terminal Data is pre-stored in the first capacitor C1.

[0240] In this phase, the voltage value of the signal of the first node N1 satisfies V N1 =V1, the voltage value of the signal of the second node N2 satisfies V N2 =V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 =V1, and the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata, V1 is the voltage value of the signal of the first signal terminal V1.

[0241] In the third phase P23, the data writing phase, the signal of the first scan signal terminal Gate1 is a high-level signal, the signals of the control signal terminal CON, the reset signal terminal Reset, the second scan signal terminal Gate2 and the light-emitting signal terminal EM are low-level signals. The fourth transistor T4 is turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0242] The fourth transistor T4 is turned on, and the signal of the fourth node N4 is written into the first node N1 through the turned-on fourth transistor T4. Under the action of the second capacitor C2 and the third capacitor C3, the second node N2 keeps the signal of the previous stage.

[0243] In this phase, the voltage value of the signal of the first node N1 satisfies V N1 =Vdata, the voltage value of the signal of the second node N2 satisfies V N2 =V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 =V1, and the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata.

[0244] In the fourth stage P24, the light emitting stage, the signals of the first scan signal terminal Gate1 and the light emitting signal terminal EM are high level signals, and the signals of the second scan signal terminal Gate2, the reset signal terminal Reset and the control signal terminal CON are low level signals. The fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0245] The fourth transistor T4 is turned on, the first node N1 and the fourth node N4 form a path, the first node N1 is kept stable under the action of the first capacitor C1, and the fifth transistor T5 and the sixth transistor T6 are turned on to provide a driving current for the first electrode of the light emitting device L from the power supply voltage output by the first power supply terminal VDD through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, so as to drive the light emitting device L to emit light.

[0246] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Since the voltage of the signal of the first node N1 satisfies V N1 =Vdata, and the voltage value of the signal of the second node N2 satisfies V N2 =V1-Vth.

[0247] Therefore, the driving current I of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(Vdata-V1+Vth-Vth) 2 =K*(Vdata-V1) 2

[0248] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current for driving the light emitting device L, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0249] In the exemplary embodiment, K=1 / 2*μ*Cox*W / L, wherein μ is the mobility of the third transistor, Cox is the oxide layer capacitance per unit area, and W / L is the width-length ratio of the channel region of the active layer of the third transistor.

[0250] As can be seen from the derivation result of the above current formula, in the light emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0251] The working process of the pixel driving circuit exemplified by FIG. 13 is described below. As shown in FIG. 13, the working process of the pixel driving circuit provided by FIG. 13 can include:

[0252] In the first stage P31, initialization stage and data pre-storage stage, the signals of the control signal end CON, the reset signal end Reset and the second scan signal end Gate2 are high-level signals, the signals of the first scan signal end Gate1 and the light-emitting signal end EM1 are low-level signals, and the data signal end Data writes the data signal. The first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0253] The first transistor T1 is turned on, and the signal of the first signal end V1 is written to the first node N1 through the turned-on first transistor T1, the second transistor T2 is turned on, the first node N1 and the third node N3 form a path, the third node N3 is initialized, and the charge of the third node N3 is cleared. The seventh transistor T7 is turned on, and the signal of the initial signal end INIT is initialized to the sixth node N6 through the turned-on seventh transistor T7, and the charge of the sixth node N6 is cleared. The eighth transistor T8 is turned on, and the data signal of the data signal end Data is written to the fourth node N4 through the turned-on eighth transistor T8, and the data signal of the data signal end Data is pre-stored in the first capacitor C1.

[0254] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 =V1, the voltage value of the signal of the sixth node N6 satisfies V N6 =Vinit, the voltage value of the signal of the third node N3 satisfies V N3 =V1, the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata, V1 is the voltage value of the signal of the first signal end V1, Vinit is the voltage value of the signal of the initial signal end INIT, and Vdata is the voltage value of the data signal.

[0255] In the second stage P32, threshold compensation stage and data pre-storage stage, the signals of the control signal end CON and the second scan signal end Gate2 are high-level signals, the signals of the reset signal end Reset, the first scan signal end Gate1 and the light-emitting signal end EM1 are low-level signals, and the data signal end Data writes the data signal. The first transistor T1, the second transistor T2 and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0256] The first transistor T1 is turned on, the signal of the first signal terminal V1 is written into the first node N1 through the turned-on first transistor T1, the first node N1 is continuously initialized, the second transistor T2 is turned on, the first node N1 and the third node N3 form a path, the third node N3 is initialized, the charge of the third node N3 is cleared, the third transistor T3 is turned on, the signal of the fifth node N5 charges the second node N2, until the voltage value of the signal of the second node N2 is V1-Vth, Vth is the threshold voltage of the third transistor T3. The eighth transistor T8 is turned on, and the data signal of the data signal terminal Data is continuously written into the fourth node N4 through the turned-on eighth transistor T8, and the data signal of the data signal terminal Data is pre-stored in the first capacitor C1.

[0257] In this phase, the voltage value of the signal of the first node N1 satisfies V N1 =V1, the voltage value of the signal of the second node N2 satisfies V N2 =V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 =V1, the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata, and V1 is the voltage value of the signal of the first signal terminal V1.

[0258] In the third phase P33, the data writing phase, the signal of the first scan signal terminal Gate1 is a high-level signal, the signals of the control signal terminal CON, the reset signal terminal Reset, the second scan signal terminal Gate2 and the light-emitting signal terminal EM are low-level signals. The fourth transistor T4 is turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0259] The fourth transistor T4 is turned on, and the signal of the fourth node N4 is written into the first node N1 through the turned-on fourth transistor T4. Under the action of the second capacitor C2 and the third capacitor C3, the second node N2 keeps the signal of the previous stage.

[0260] In this phase, the voltage value of the signal of the first node N1 satisfies V N1 =Vdata, the voltage value of the signal of the second node N2 satisfies V N2 =V1-Vth, the voltage value of the signal of the third node N3 satisfies V N3 =V1, the voltage value of the signal of the fourth node N4 satisfies V N4 =Vdata.

[0261] In the fourth stage P34, the light emitting stage, the signals of the first scan signal terminal Gate1 and the light emitting signal terminal EM are high level signals, and the signals of the second scan signal terminal Gate2, the reset signal terminal Reset and the control signal terminal CON are low level signals. The fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0262] The fourth transistor T4 is turned on, the first node N1 and the fourth node N4 form a path, the first node N1 is kept stable under the action of the first capacitor C1, and the fifth transistor T5 and the sixth transistor T6 are turned on to provide a driving current for the first electrode of the light emitting device L from the power supply voltage output by the first power supply terminal VDD through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, so as to drive the light emitting device L to emit light.

[0263] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Since the voltage of the signal of the first node N1 satisfies V N1 =Vdata, and the voltage value of the signal of the second node N2 satisfies V N2 =V1-Vth.

[0264] Therefore, the driving current I of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*(Vdata-V1+Vth-Vth) 2 =K*(Vdata-V1) 2

[0265] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current for driving the light emitting device L, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0266] In the exemplary embodiment, K=1 / 2*μ*Cox*W / L, wherein μ is the mobility of the third transistor, Cox is the oxide layer capacitance per unit area, and W / L is the width-length ratio of the channel region of the active layer of the third transistor.

[0267] As can be seen from the derivation of the above current formula, in the light emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0268] In the exemplary embodiments, the on time of the first transistor T1 in the pixel driving circuit provided in FIGS. 11 and 13 is less than the on time of the first transistor T1 in the pixel driving circuit provided in FIGS. 10 and 12. Therefore, the load of the driving circuit in the display product in which the pixel driving circuit provided in FIGS. 11 and 13 is located is less than the load of the driving circuit in the display product in which the pixel driving circuit provided in FIGS. 10 and 12 is located.

[0269] According to the working processes of the pixel driving circuits provided in FIGS. 10 to 13, it can be known that the threshold compensation phase occurs before the data writing phase, that is, the threshold compensation phase is independent of the data writing phase, and the time of the threshold compensation is no longer limited by the time of the data writing. The disclosure can prolong the time of the threshold voltage compensation to ensure that the threshold voltage can be better compensated.

[0270] According to the working processes of the pixel driving circuits provided in FIGS. 10 to 13, it can be known that, in the second phase, the pixel driving circuit performs both data prestorage and threshold compensation, that is, there is an overlap between the time period in which the data prestorage phase is located and the time period in which the threshold compensation phase is located. The path through which the pixel driving circuit performs the data prestorage includes the eighth transistor T8 and the fourth transistor T4, and the path through which the pixel driving circuit performs the threshold compensation includes the second transistor T2. That is, the path through which the pixel driving circuit performs the data prestorage and the path through which the pixel driving circuit performs the threshold compensation are separated, so that the pixel driving circuit can perform the threshold compensation while also performing the data prestorage, the time of the data prestorage is prolonged, and high-frequency driving of the pixel driving circuit can be implemented.

[0271] The driving rate of the pixel driving circuit provided in the disclosure can meet 120 Hz, 180 Hz and 240 Hz, the effect of the game scene in the display product in which the pixel driving circuit is located can be improved, the precision of the driving circuit can be improved, and the display effect of the display product can also be improved.

[0272] The disclosure also provides a driving method of a pixel driving circuit, configured to drive the pixel driving circuit provided in any one of the preceding embodiments. The driving method of the pixel driving circuit can include the following steps:

[0273] In step 100, the data prestorage subcircuit provides, under the control of the signal at the second scan signal end, the signal at the fourth node with the signal at the data signal end and stores the voltage difference between the signals at the fourth node and the first power supply end.

[0274] In step 200, the first node control subcircuit provides, under the control of the signals at the control signal end, the first scan signal end and the second scan signal end, the signal at the first signal end or the fourth node to the first node and forms a path between the first node and the third node.

[0275] The second node control sub-circuit stores a voltage difference between signals of the second node and the third node and a voltage difference between signals of the second node and the second signal end, and provides a signal of the initial signal end to the sixth node under control of a signal of the reset signal end.

[0276] The driving sub-circuit outputs a driving current under control of signals of the first node, the second node and the fifth node.

[0277] The light emitting control sub-circuit provides a signal of the first power supply end to the fifth node under control of a signal of the light emitting signal end.

[0278] The display device provided by the embodiments of the present disclosure further includes a plurality of pixel driving circuits provided by any one of the foregoing embodiments.

[0279] In an example implementation, the display device further includes a first data unit, a second data unit, a third data unit and a fourth data unit, the first data unit provides a signal to the first scan signal end, the second data unit provides a signal to the second scan signal end, the third data unit provides a signal to the reset signal end, and the fourth data unit provides a signal to the light emitting signal end.

[0280] In an example implementation, a time period during which the first data unit provides an effective level signal to the first scan signal end does not overlap with a time period during which the second data unit provides an effective level signal to the second scan signal end, and the time period during which the first data unit provides an effective level signal to the first scan signal end occurs after the time period during which the second data unit provides an effective level signal to the second scan signal end.

[0281] In an example implementation, a time period during which the third data unit provides an effective level signal to the reset signal end at least partially overlaps with a time period during which the second data unit provides an effective level signal to the second scan signal end, and does not overlap with a time period during which the first data unit provides an effective level signal to the first scan signal end.

[0282] In an example implementation, a time period during which the fourth data unit provides an effective level signal to the light emitting signal end at least partially overlaps with a time period during which the first data unit provides an effective level signal to the first scan signal end, and does not overlap with a time period during which the second data unit provides an effective level signal to the second scan signal end.

[0283] In an example implementation, the pixel driving circuit includes a first transistor, a second electrode of the first transistor being electrically connected with the third node.

[0284] In an exemplary embodiment, the display device further includes a fifth data unit, the fifth data unit providing a signal to the control signal terminal. The time period in which the fifth data unit provides the active level signal to the control signal terminal at least partially overlaps the time period in which the first data unit provides the active level signal to the first scan signal terminal and the time period in which the second data unit provides the active level signal to the second scan signal terminal.

[0285] In an exemplary embodiment, the time period in which the second data unit provides the active level signal to the second scan signal terminal is within the time period in which the fifth data unit provides the active level signal to the control signal terminal.

[0286] In an exemplary embodiment, the pixel driving circuit includes a first transistor, a second electrode of the first transistor being electrically connected to the first node. The display device further includes a fifth data unit, the fifth data unit providing a signal to the control signal terminal.

[0287] In an exemplary embodiment, the time period in which the fifth data unit provides the active level signal to the control signal terminal at least partially overlaps the time period in which the second data unit provides the active level signal to the second scan signal terminal and does not overlap the time period in which the first data unit provides the active level signal to the first scan signal terminal.

[0288] In an exemplary embodiment, the time period in which the third data unit provides the active level signal to the reset signal terminal and the time period in which the fifth data unit provides the active level signal to the control signal terminal are within the time period in which the second data unit provides the active level signal to the second scan signal terminal, and the time period in which the third data unit provides the active level signal to the reset signal terminal precedes the time period in which the fifth data unit provides the active level signal to the control signal terminal.

[0289] In an exemplary embodiment, the pixel driving circuit includes a first transistor, a second electrode of the first transistor being electrically connected to the first node. The display device further includes a fifth data unit, the fifth data unit providing a signal to the control signal terminal.

[0290] In an exemplary embodiment, the time period in which the fifth data unit provides the active level signal to the control signal terminal is within the time period in which the second data unit provides the active level signal to the second scan signal terminal.

[0291] In an exemplary embodiment, the fifth data unit is the same data unit as the second data unit.

[0292] In an exemplary embodiment, the display device can further include a timing controller, a data driver, a gate driver, and a pixel array, the timing controller being connected to the data driver and the gate driver, the data driver being connected to a plurality of data signal lines, and the gate driver being connected to a plurality of gate signal lines. The pixel array can include a plurality of sub-pixels, at least one of the sub-pixels including a pixel driving circuit and a light emitting device connected to the pixel driving circuit. The gate signal lines can be electrically connected to at least one of a first scan signal terminal, a second scan signal terminal, a reset signal terminal, a control signal terminal, and a light emission signal terminal, and the data signal lines can be electrically connected to a data signal terminal.

[0293] In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for a specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for a specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for a specification of the light emission driver to the light emission driver. The data driver can generate a data voltage to be provided to the data signal line using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal and apply a data voltage corresponding to the gray scale value to the data signal line in units of a pixel.

[0294] In an exemplary embodiment, the gate driver can generate a scan signal to be provided to the gate signal line by receiving a clock signal, a gate start signal, and the like from the timing controller. For example, the scan driver can sequentially provide a scan signal having a turn-on level pulse to the gate signal line. For example, the gate driver can be configured in the form of a shift register and can sequentially transmit a scan start signal provided in the form of a turn-on level pulse to a next stage circuit under the control of a clock signal, in a manner of generating a scan signal.

[0295] The display device can include a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units including a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light, the first sub-pixel, the second sub-pixel, and the third sub-pixel each including a pixel driving circuit and a light emitting device. The pixel driving circuit in the first sub-pixel, the second sub-pixel, and the third sub-pixel is connected to a gate signal line and a data signal line, respectively, and is configured to receive a data voltage transmitted from the data signal line under the control of the gate signal line and output a corresponding current to the light emitting device. The light emitting device in the first sub-pixel, the second sub-pixel, and the third sub-pixel is connected to the pixel driving circuit of the sub-pixel in which the light emitting device is located, and is configured to emit light of a corresponding brightness in response to the current output from the pixel driving circuit of the sub-pixel in which the light emitting device is located.

[0296] In an exemplary embodiment, the first sub-pixel can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light.

[0297] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure.

[0298] In an exemplary embodiment, the pixel unit can include three sub-pixels, which can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure. In an exemplary embodiment, the pixel unit can include four sub-pixels, which can be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure.

[0299] In an exemplary embodiment, the display device can be a wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, or any product or component having a display function.

[0300] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0301] For the sake of clarity, the thickness and size of the layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0302] Although the embodiments disclosed by the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A pixel driving circuit, comprising: The data prestorage subcircuit, the first node control subcircuit, the second node control subcircuit, the driving subcircuit and the light emitting control subcircuit; The data prestorage subcircuit is electrically connected with the second scan signal terminal, the data signal terminal, the first power terminal and the fourth node respectively, and is configured to provide the signal of the data signal terminal to the fourth node under the control of the signal of the second scan signal terminal, and store the voltage difference between the signals of the fourth node and the first power terminal; The first node control subcircuit is electrically connected with the control signal terminal, the first scan signal terminal, the second scan signal terminal, the first signal terminal, the first node, the third node and the fourth node respectively, and is configured to provide the signal of the first signal terminal or the fourth node to the first node under the control of the signals of the control signal terminal, the first scan signal terminal and the second scan signal terminal, and form a path between the first node and the third node; The second node control subcircuit is electrically connected with the reset signal terminal, the initial signal terminal, the second signal terminal, the second node, the third node and the sixth node respectively, and is configured to store the voltage difference between the signals of the second node and the third node and the voltage difference between the signals of the second node and the second signal terminal, and provide the signal of the initial signal terminal to the sixth node under the control of the signal of the reset signal terminal; The driving subcircuit is electrically connected with the first node, the second node and the fifth node respectively, and is configured to output a driving current under the control of the signals of the first node, the second node and the fifth node; The light emitting control subcircuit is electrically connected with the light emitting signal terminal, the first power terminal and the fifth node respectively, and is configured to provide the signal of the first power terminal to the fifth node under the control of the signal of the light emitting signal terminal.

2. The pixel driving circuit according to claim 1, wherein The second node and the sixth node are the same node.

3. The pixel driving circuit of claim 1, wherein, The light emitting control subcircuit is further electrically connected with the second node and the sixth node, and is configured to provide the signal of the second node to the sixth node under the control of the signal of the light emitting signal terminal.

4. The pixel driving circuit of claim 1, wherein, The data prestorage subcircuit comprises an eighth transistor and a first capacitor; The control electrode of the eighth transistor is electrically connected with the second scan signal terminal, the first electrode of the eighth transistor is electrically connected with the data signal terminal, and the second electrode of the eighth transistor is electrically connected with the fourth node; The first end of the first capacitor is electrically connected with the first power terminal, and the second end of the first capacitor is electrically connected with the fourth node.

5. The pixel driving circuit of claim 1, wherein, The first node control subcircuit comprises a first transistor, a second transistor and a fourth transistor; The control electrode of the first transistor is electrically connected with the control signal terminal, the first electrode of the first transistor is electrically connected with the first signal terminal, and the second electrode of the first transistor is electrically connected with the third node; The control electrode of the second transistor is electrically connected with the second scan signal terminal, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the fourth transistor is electrically connected with the first scan signal terminal, the first electrode of the fourth transistor is electrically connected with the fourth node, and the second electrode of the fourth transistor is electrically connected with the first node.

6. The pixel driving circuit of claim 1, wherein, The first node control subcircuit comprises a first transistor, a second transistor and a fourth transistor; The control electrode of the first transistor is electrically connected with a control signal terminal, the first electrode of the first transistor is electrically connected with a first signal terminal, and the second electrode of the first transistor is electrically connected with a first node; The control electrode of the second transistor is electrically connected with a second scan signal terminal, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with a third node; The control electrode of the fourth transistor is electrically connected with the first scan signal terminal, the first electrode of the fourth transistor is electrically connected with a fourth node, and the second electrode of the fourth transistor is electrically connected with the first node.

7. The pixel driving circuit of claim 1, wherein, The second node control sub-circuit comprises a second capacitor, a third capacitor and a seventh transistor; The first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with a second node; The first end of the third capacitor is electrically connected with a second signal terminal, and the second end of the third capacitor is electrically connected with the second node; The control electrode of the seventh transistor is electrically connected with a reset signal terminal, the first electrode of the seventh transistor is electrically connected with an initial signal terminal, and the second electrode of the seventh transistor is electrically connected with a sixth node.

8. The pixel driving circuit of claim 2, wherein, The light emitting control sub-circuit comprises a fifth transistor; The control electrode of the fifth transistor is electrically connected with a light emitting signal terminal, the first electrode of the fifth transistor is electrically connected with a first power supply terminal, and the second electrode of the fifth transistor is electrically connected with a fifth node.

9. The pixel driving circuit of claim 3, wherein, The light emitting control sub-circuit comprises a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected with a light emitting signal terminal, the first electrode of the fifth transistor is electrically connected with a first power supply terminal, and the second electrode of the fifth transistor is electrically connected with a fifth node; The control electrode of the sixth transistor is electrically connected with the light emitting signal terminal, the first electrode of the sixth transistor is electrically connected with the second node, and the second electrode of the sixth transistor is electrically connected with the sixth node.

10. The pixel driving circuit of claim 2, wherein, The data prestorage sub-circuit comprises an eighth transistor and a first capacitor; the first node control sub-circuit comprises a first transistor, a second transistor and a fourth transistor; the second node control sub-circuit comprises a second capacitor, a third capacitor and a seventh transistor; the light emitting control sub-circuit comprises a fifth transistor, and the driving sub-circuit comprises a third transistor; The control electrode of the first transistor is electrically connected with a control signal terminal, the first electrode of the first transistor is electrically connected with a first signal terminal, and the second electrode of the first transistor is electrically connected with one of a third node and a first node; The control electrode of the second transistor is electrically connected with a second scan signal terminal, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with a fifth node, and the second electrode of the third transistor is electrically connected with a second node; The control electrode of the fourth transistor is electrically connected with the first scan signal terminal, the first electrode of the fourth transistor is electrically connected with a fourth node, and the second electrode of the fourth transistor is electrically connected with the first node. The control electrode of the fifth transistor is electrically connected with a light emitting signal terminal, the first electrode of the fifth transistor is electrically connected with a first power supply terminal, and the second electrode of the fifth transistor is electrically connected with a fifth node; The control electrode of the seventh transistor is electrically connected with a reset signal terminal, the first electrode of the seventh transistor is electrically connected with an initial signal terminal, and the second electrode of the seventh transistor is electrically connected with the sixth node; The control electrode of the eighth transistor is electrically connected with a second scan signal terminal, the first electrode of the eighth transistor is electrically connected with a data signal terminal, and the second electrode of the eighth transistor is electrically connected with the fourth node; The first end of the first capacitor is electrically connected with the first power supply terminal, and the second end of the first capacitor is electrically connected with the fourth node; The first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with the second node; The first end of the third capacitor is electrically connected with the second signal terminal, and the second end of the third capacitor is electrically connected with the second node. The data prestorage sub-circuit comprises an eighth transistor and a first capacitor; the first node control sub-circuit comprises a first transistor, a second transistor and a fourth transistor; the second node control sub-circuit comprises a second capacitor, a third capacitor and a seventh transistor; the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor, and the driving sub-circuit comprises a third transistor; 11. The pixel driving circuit of claim 3, wherein, The control electrode of the first transistor is electrically connected with a control signal terminal, the first electrode of the first transistor is electrically connected with a first signal terminal, and the second electrode of the first transistor is electrically connected with one of the third node and the first node; The control electrode of the second transistor is electrically connected with a second scan signal terminal, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with a fifth node, and the second electrode of the third transistor is electrically connected with the second node; The control electrode of the fourth transistor is electrically connected with a first scan signal terminal, the first electrode of the fourth transistor is electrically connected with the fourth node, and the second electrode of the fourth transistor is electrically connected with the first node; The control electrode of the fifth transistor is electrically connected with a light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected with a first power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fifth node; The control electrode of the sixth transistor is electrically connected with the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected with the second node, and the second electrode of the sixth transistor is electrically connected with the sixth node; The control electrode of the seventh transistor is electrically connected with a reset signal terminal, the first electrode of the seventh transistor is electrically connected with an initial signal terminal, and the second electrode of the seventh transistor is electrically connected with the sixth node; The control electrode of the eighth transistor is electrically connected with a second scan signal terminal, the first electrode of the eighth transistor is electrically connected with a data signal terminal, and the second electrode of the eighth transistor is electrically connected with the fourth node; The first end of the first capacitor is electrically connected with the first power supply terminal, and the second end of the first capacitor is electrically connected with the fourth node; The first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with the second node; The first end of the third capacitor is electrically connected with the second signal terminal, and the second end of the third capacitor is electrically connected with the second node. The first signal terminal and the first power supply terminal are the same signal terminal.

12. The pixel driving circuit according to any one of claims 1, 10 and 11, wherein, The signal of the first signal terminal is a reference signal, and the voltage difference between the voltage value of the reference signal and the voltage value of the signal of the initial signal terminal is greater than the threshold difference of the third transistor.

13. The pixel driving circuit according to claim 10 or 11, wherein, ​ 14. The pixel driving circuit according to claim 10 or 11, wherein, The second electrode of the first transistor is electrically connected with the first node, and the control signal terminal and the second scan signal terminal are the same signal terminal.

15. The pixel driving circuit according to any one of claims 1, 10 and 11, wherein, The second signal terminal is the same signal terminal as one of the initial signal terminal and the first power supply terminal.

16. A display device comprising: A plurality of pixel driving circuits according to any one of claims 1 to 15, a first data unit, a second data unit, a third data unit and a fourth data unit, wherein the first data unit provides a signal to the first scan signal terminal, the second data unit provides a signal to the second scan signal terminal, the third data unit provides a signal to the reset signal terminal, and the fourth data unit provides a signal to the light emitting signal terminal; The time period during which the first data unit provides the effective level signal to the first scan signal terminal does not overlap with the time period during which the second data unit provides the effective level signal to the second scan signal terminal, and the time period during which the first data unit provides the effective level signal to the first scan signal terminal occurs after the time period during which the second data unit provides the effective level signal to the second scan signal terminal; The time period during which the third data unit provides the effective level signal to the reset signal terminal at least partially overlaps with the time period during which the second data unit provides the effective level signal to the second scan signal terminal, and does not overlap with the time period during which the first data unit provides the effective level signal to the first scan signal terminal; The time period during which the fourth data unit provides the effective level signal to the light emitting signal terminal at least partially overlaps with the time period during which the first data unit provides the effective level signal to the first scan signal terminal, and does not overlap with the time period during which the second data unit provides the effective level signal to the second scan signal terminal.

17. The display device of claim 16, wherein, The pixel driving circuit comprises a first transistor, and a second electrode of the first transistor is electrically connected with a third node. The display device further comprises a fifth data unit, and the fifth data unit provides a signal to the control signal terminal. The time period during which the fifth data unit provides the effective level signal to the control signal terminal at least partially overlaps with the time period during which the first data unit provides the effective level signal to the first scan signal terminal and the time period during which the second data unit provides the effective level signal to the second scan signal terminal. The time period during which the second data unit provides the effective level signal to the second scan signal terminal is within the range of the time period during which the fifth data unit provides the effective level signal to the control signal terminal.

18. The display device of claim 16, wherein, The pixel driving circuit comprises a first transistor, and a second electrode of the first transistor is electrically connected with a first node. The display device further comprises a fifth data unit, and the fifth data unit provides a signal to the control signal terminal. The time period during which the fifth data unit provides the effective level signal to the control signal terminal at least partially overlaps with the time period during which the second data unit provides the effective level signal to the second scan signal terminal, and does not overlap with the time period during which the first data unit provides the effective level signal to the first scan signal terminal. The time period in which the third data unit provides the valid level signal to the reset signal end and the time period in which the fifth data unit provides the valid level signal to the control signal end are within the time period in which the second data unit provides the valid level signal to the second scan signal end, and the time period in which the third data unit provides the valid level signal to the reset signal end is before the time period in which the fifth data unit provides the valid level signal to the control signal end.

19. The display device of claim 16, wherein, The pixel driving circuit comprises a first transistor, a second electrode of the first transistor being electrically connected with a first node; The display device further comprises a fifth data unit, the fifth data unit providing a signal to a control signal end; The time period in which the fifth data unit provides the valid level signal to the control signal end is within the time period in which the second data unit provides the valid level signal to the second scan signal end.

20. The display device of claim 19, wherein, The fifth data unit is the same data unit as the second data unit.

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