Difficult branch transformation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a difficult-to-predict branch transformation method and device, electronic equipment and a computer readable storage medium. The difficult-to-predict branch transformation method comprises the following steps: identifying a target instruction sequence from an instruction sequence; executing an instruction transformation operation on a difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and taking a branch judgment result of the difficult-to-predict branch instruction as a direction identifier; adding the direction identifier to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction; and executing the converted instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction identifier. According to the technical scheme, the target instruction sequence can be recognized from the instruction sequence, the direction identifier is added to the adjusted instruction corresponding to the context instruction, processing of all difficult-to-predict branches is avoided, the number of dynamic instructions can be reduced, the algorithm complexity can be reduced, and therefore assembly line conflicts and scheduling expenses are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a hard-to-predict branch transformation method and device, electronic equipment and computer readable storage medium. BACKGROUND

[0002] Branch prediction is a technique used in computer architecture to improve instruction pipeline efficiency by predicting the direction of program branches to avoid pipeline stall.

[0003] In modern processors, a hard-to-predict (HTP) branch refers to a conditional branch instruction with complex behavior patterns and poor historical regularity in program execution, and its jump direction is difficult to accurately predict by static or dynamic prediction strategies. The existing technology for handling hard-to-predict branches can convert control flow into data dependency through predicate instructions, and eliminate small-grained data-dependent branches in the instruction set architecture by adding a predicate to each regular instruction, However, predicate instructions increase the length of the dependency path and the total number of dynamic instructions, and in addition, when there are instructions in the branch path that cannot be predicated, it is difficult to reduce hard-to-predict branches and increase the complexity of the transformation. SUMMARY

[0004] The embodiments of the present application provide a hard-to-predict branch transformation method, device, electronic equipment and computer readable storage medium, which can reduce the number of dynamic instructions and reduce the complexity of the transformation algorithm.

[0005] In a first aspect, the embodiments of the present application disclose a hard-to-predict branch transformation method, the method comprising: identifying a target instruction sequence from an instruction sequence, the target instruction sequence comprising a hard-to-predict branch instruction and context instructions of the hard-to-predict branch instruction; performing an instruction transformation operation on the hard-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and taking a branch judgment result of the hard-to-predict branch instruction as a direction marker, a value of the direction marker being used to indicate whether the hard-to-predict branch instruction jumps to a target address; adding the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction; performing the transformed instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction marker.

[0006] In a second aspect, the embodiments of the present application disclose a hard-to-predict branch transformation device, the device comprising: an identification module configured to identify a target instruction sequence from an instruction sequence; a transformation module, performing an instruction transformation operation on a difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and taking a branch judgment result of the difficult-to-predict branch instruction as a direction marker; a regulation module, adding the direction marker to each context instruction in the target instruction sequence to obtain a regulation instruction corresponding to each context instruction; an execution module, executing the transformed instruction and the regulation instruction corresponding to the context instruction according to a value of each direction marker.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor, a memory for storing instructions executable by the processor, and wherein the processor is configured to execute the instructions to implement the method in the first aspect.

[0008] In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, when instructions in the computer readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method in the first aspect.

[0009] Embodiments of the present application have the following advantages: The difficult-to-predict branch transformation method of the present application can identify a target instruction sequence containing a difficult-to-predict branch, perform an instruction transformation operation on a difficult-to-predict branch instruction in the target instruction sequence, take a branch judgment result of the difficult-to-predict branch instruction as a direction marker, and add the direction marker to a context instruction in the target instruction sequence to obtain a regulation instruction corresponding to each context instruction. Since the target instruction sequence is identified from a plurality of instruction sequences, only the difficult-to-predict branch instruction in the target instruction sequence is transformed, and other instruction sequences that cannot be processed are excluded, the number of dynamic instructions can be reduced, thereby reducing pipeline conflicts and scheduling overhead. In addition, since the instruction transformation operation is to add the direction marker to the context instruction, only one variable needs to be added, thereby reducing the complexity of the transformation algorithm and improving the performance of the processor. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative labor.

[0011] Figure 1 is a step flow chart of a difficult-to-predict branch transformation method embodiment of the present application; Figure 2is a step flow chart of another unpredictable branch transformation method embodiment of the present application; Figure 3 is a structure block diagram of an unpredictable branch transformation device of the present application; Figure 4 is a structure block diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0013] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a category, and are not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0014] Branch prediction is one of the key factors of modern microprocessor performance. In the case of branch misprediction, if the branch jump direction is not known in advance, the pipeline must be stopped to wait for the result, which makes the microprocessor with high-capability pipeline and large cache fall into a standstill. Branch misprediction can interrupt program flow, resulting in resetting the pipeline and having to refill the cache from slow main memory. Unpredictable branches are usually branch conditions that depend on unpredictable external data or calculation results, such as hash collisions, encryption algorithm judgments, and cyclic redundancy checks (CRC), as well as extremely low bias branches and non-local dependent branches. It can also be determined that the branch instruction is an unpredictable branch by analyzing the relevance between the branch instruction and the data value loaded by the previous load instruction, if the branch condition is directly related to the result of the historical data load.

[0015] Because very low branch misprediction accuracy can cause severe performance loss in microprocessors, it is desirable to provide supplemental branch prediction circuitry such as special branch predictors that provide algorithms that focus on certain types of hard to predict (HTP) branch predictions for predicting branch direction and target address in advance to keep the instruction pipeline executing, with a large performance gain if the prediction is correct, and a waste of time if the prediction is wrong and needs to be rolled back. These HTP branches can be caused by program structures that cause high variance in the history data used for branch prediction. Conventional branch predictors such as local pattern matching branch predictors cannot accurately predict because those branch predictors are based on recognizing captured location correlations. Therefore, it is desirable to perform processing on hard to predict branches through optimized compilers, hardware improvements, and software layer optimizations. Software layer optimizations do not add hardware cost relative to other ways and can continuously improve adaptability and accuracy through algorithmic optimization, thereby improving the performance of the processor such as instructions per cycle (IPC).

[0016] Instructions per cycle is the average number of instructions executed per clock cycle, reflecting instruction level parallelism (ILP) and microarchitectural efficiency, which can be improved by increasing branch prediction accuracy to improve the IPC of the processor to improve the execution efficiency of the processor.

[0017] The work of a processor is to fetch instructions, decode instructions, and execute instructions. Processing of an instruction sequence includes a fetch stage, a decode stage, an execution stage, a memory stage, and a writeback stage. An instruction is an operational command that a processor can recognize and execute, and is a binary code stored in a memory. A branch is a type of instruction that can change the normal order of execution flow of a program. Normally, instructions are executed one after another. A branch instruction tells the processor that the next instruction to be executed is not the next one in order, but an instruction at another address. A path is a sequence or trajectory of instruction flow that a program goes through in actual running. Because of the existence of branch instructions, a program can have multiple instruction flows, and the instructions contained in different instruction flows are referred to as different execution paths.

[0018] A branch target address is the address of the next instruction to be executed (target address) when a branch instruction jumps to execution. The target address is usually calculated by the operand or register of the branch instruction. It can be obtained by relative addressing, inter-register addressing, or inter-memory addressing.

[0019] Method embodiments Reference Figure 1, a step flow chart of an embodiment of the unpredictable branch transformation method is shown, which can specifically include the following steps: Step 101, identifying a target instruction sequence from the instruction sequence, the target instruction sequence including an unpredictable branch instruction and context instructions of the unpredictable branch instruction.

[0020] It should be noted that first, the execution object of the branch transformation method needs to be screened out, and the instruction sequence including the unpredictable branch can be selected as the target instruction sequence from the multiple instruction sequences in the processor. The target instruction sequence can include the unpredictable branch instruction and the context instructions of the unpredictable branch instruction, for example, the unpredictable branch instruction is a conditional branch instruction, and the context instructions are the instructions adjacent to the conditional branch instruction and the associated instructions.

[0021] For the unpredictable branch transformation method, the accuracy of selecting the target instruction sequence will directly affect the program performance and resource utilization efficiency.

[0022] Step 102, performing an instruction transformation operation on the unpredictable branch instruction in the target instruction sequence to obtain a transformed instruction, and taking the branch judgment result of the unpredictable branch instruction as a direction marker, the value of the direction marker being used to indicate whether the unpredictable branch instruction jumps to a target address.

[0023] It should be noted that the instruction transformation operation can be performed on the unpredictable branch instruction in the target instruction sequence to obtain a transformed instruction. The unpredictable branch instruction refers to a branch instruction that is difficult to accurately predict through historical data or pattern matching during program execution. Such instructions usually have the following characteristics: indirect jump, control dependency, and dynamic branch. Indirect jump refers to a target address determined by a register value rather than a PC (Program Counter) offset; control dependency refers to the branch direction or target address waiting for the execution result of other instructions, resulting in the inability to predict in advance in the fetch stage; dynamic branch refers to the branch direction or target address being dynamically adjusted according to input data or environmental changes during program execution. For example, an input-type conditional branch instruction, the instruction transformation operation can transform the conditional branch instruction into a comparison microinstruction, thereby converting the original unpredictable branch instruction into other comparison type microinstructions. The transformed instruction belongs to a microinstruction. Since only the unpredictable branch instruction is transformed, rather than every instruction in the target instruction sequence, the complexity of the transformation algorithm can be reduced.

[0024] The branch judgment result of the unpredictable branch instruction can be used as a direction marker. The branch judgment result is whether the branch judgment condition of the unpredictable branch is established. The direction marker is a self-defined variable, which can be stored in a general register. The value of the direction marker is used to indicate whether the unpredictable branch instruction jumps to a target address. The direction marker is a self-defined integer data, and its value is 1 or 0. 1 represents that the unpredictable branch must jump to the target address, and 0 represents that the unpredictable branch does not have to jump to the target address. The target address represents the next machine address to which the current instruction address indicated by the program counter is automatically incremented to point to the next instruction. The accuracy of the target address is also crucial for branch prediction execution. The target address prediction accuracy can be improved by optimizing indirect jumps, control dependencies, and dynamic branch techniques. As can be seen, the self-defined variable of the direction marker can be added, only one register is used to store the self-defined variable, and no more hardware devices or hardware interfaces are added, thereby saving hardware cost.

[0025] Step 103, add the direction marker to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction.

[0026] It should be noted that the direction marker can be added to each context instruction in the target instruction sequence by the instruction adjustment operation to obtain the adjusted instruction corresponding to each context instruction. The context instruction refers to some instructions adjacent to the unpredictable branch instruction, which can be multiple types of instructions after the unpredictable branch instruction, such as operation instructions, access and storage instructions, conditional branch instructions, jump instructions, etc. The direction marker is obtained by the transformation process of step 102, and is usually stored in a target register. The direction marker can be added to the operation code of each context instruction as a flag bit, and other parameters remain unchanged, thereby forming the adjusted instruction corresponding to each context instruction. The processing of the adjusted instruction depends on the value of the direction marker, and whether to execute the instruction can be determined by reading the value of the direction marker. For example, when the direction marker is read as 1, the adjusted instruction is not executed; when the direction marker is read as 0, the adjusted instruction is executed in sequence.

[0027] As can be seen, the instruction transformation operation and the adjustment operation of the target instruction sequence are performed to obtain the processed instruction sequence, which includes the transformed instruction and the adjusted instruction.

[0028] Each row of instructions in the processed instruction sequence includes a direction marker, thereby completing the processing of the target instruction sequence, and the processing of the unpredictable branch can be completed by simplifying the transformation process.

[0029] Step 104, according to the value of each direction marker, executing the transformed instruction and the adjusted instruction corresponding to the context instruction.

[0030] The value of the direction marker can be a binary value, and the value of the direction marker is used to indicate whether the difficult-to-predict branch instruction jumps to the target address. The transformed instruction corresponding to the difficult-to-predict branch instruction is executed unconditionally, and the adjusted instruction corresponding to the context instruction needs to perform different operations according to the value of the direction marker obtained by the instruction transformation operation. For example, when the direction marker is read as 1, the adjusted instruction is not executed; when the direction marker is read as 0, the adjusted instruction is executed in sequence. Executing the adjusted instruction means that the instruction takes effect, which means that the misprediction flush, the modification of the register value, and the access to the memory. The misprediction flush of the branch instruction means that when the processor predicts the jump line or the target address of the branch instruction incorrectly, all instructions that have entered the pipeline based on the incorrect prediction need to be cleared, and the process of taking instructions from the correct address again. For operation instructions, it can be the modification of the register value, mainly realized by the arithmetic logic unit. For load and store instructions, in the memory access stage, the processor can read the memory data into the register through the data bus after calculating the target address, or write the register data to the specified address.

[0031] Therefore, by using the value of the direction marker, the adjusted instruction corresponding to the context instruction is executed in sequence, which can convert the dynamic branch into static sequential execution, and the adjusted instruction can ensure that the computer executes the target instruction sequence in sequence, avoiding the interference of the out-of-order operation with the effectiveness of the direction marker.

[0032] In the embodiments of the present application, the target instruction sequence is identified from the instruction stream, the difficult-to-predict branch execution instruction transformation process is performed, the transformed instruction and the direction marker are obtained, and the direction marker is added to other branches except the difficult-to-predict branch to generate the adjusted instruction. Therefore, since only the difficult-to-predict branch instruction is transformed, and only the direction marker is added to the context instruction, the number of dynamic instructions can be reduced, thereby reducing the pipeline conflict and scheduling overhead, and by identifying the target instruction sequence from the instruction sequence, the instruction transformation process for a large number of instruction sequences can be avoided, the transformation algorithm complexity can be reduced, the efficiency of the executed instruction can be improved, and the overall performance of the processor can be improved.

[0033] Referring to Figure 2 , another step flowchart of the difficult-to-predict branch transformation method embodiment of the present application is shown, which can specifically include the following steps: Step 201, the target instruction sequence is identified from the instruction sequence, and the target instruction sequence includes the difficult-to-predict branch instruction and the context instruction of the difficult-to-predict branch instruction.

[0034] This step can refer to step 101 described above for details, which will not be repeated here.

[0035] Optionally, step 201 can include: Sub-step 2011, selecting an instruction sequence including a target instruction structure from the instruction sequence as a target instruction sequence.

[0036] Wherein, the target instruction structure includes a difficult-to-predict conditional branch instruction, a context instruction and a transfer instruction; the context instruction is located between the difficult-to-predict conditional branch instruction and the transfer instruction; the context instruction includes at least one of an operation instruction, a load instruction, a store instruction and another conditional branch instruction except the difficult-to-predict conditional branch instruction; and the target address is the address of the transfer instruction.

[0037] Specifically, for a conditional branch that depends on unpredictable external data, it also belongs to a difficult-to-predict branch. For such a difficult-to-predict conditional branch, it includes a difficult-to-predict conditional branch instruction, a context instruction and a transfer instruction. The transfer instruction is an instruction in the instruction stream that will change the program execution order and modify the PC value, including conditional jump, unconditional jump, function call / return and indirect jump. The target address is the memory address to which the transfer instruction jumps. The types of target addresses include immediate target address, relative target address, register target address and memory target address. The context instruction is located between the difficult-to-predict conditional branch instruction and the transfer instruction.

[0038] In this embodiment, an assembly language fragment under the Reduced Instruction Set Computer-Version 5 (RISC-V) architecture is taken as an example, as follows: 10a5a: c299beqza3,10a60 10a5c: 031f0963beqt5,a7,10a8e 10a60: 97aaadda5,a5,a0 10a62: 05b7fd63bgeu a5,s11,10abc<main+0x5a4> It should be noted that this code is commonly used for loop control, conditional judgment and data processing. The following logic is executed: ‌Conditional check‌: First, determine whether the value of register a3 is 0. If it is 0, jump directly to address 10a60 for address calculation.

[0039] ‌Alternative branch‌: If the value of register a3 is not 0, continue to check whether the values of registers t5 and a7 are equal. If they are equal, jump to address 10a8e.

[0040] ‌Address calculation: At address 10a60, register a5 is added to the value of a0, and the result is stored back in a5.

[0041] ‌Boundary check: The value of register a5 is verified against the boundary represented by s11 through an unsigned comparison, and if it is out of bounds, the program jumps to address 10abc (marked at main function offset 0x5a4).

[0042] Optionally, step 201 can further comprise: Sub-step 2012, reading the instruction sequence from a processor instruction buffer, the instruction buffer being located in a cache region between a fetch unit and a decode unit.

[0043] Sub-step 2013, identifying the instruction sequence as a target instruction sequence when a first instruction in the instruction sequence is a conditional branch instruction and the first instruction is separated from a branch instruction by at least one context instruction.

[0044] It is noted that for sub-steps 2012-2013, the processor instruction buffer is used to temporarily save the instructions to be executed fetched from the memory or cache, and is located after the fetch unit and before the decode unit, in order to decouple the fetch and decode, improve parallelism, reduce the blocking caused by the instruction cache delay, and support prediction execution. The fetch unit is used to fetch the next instruction to be executed from the memory. The fetch unit reads the instruction from the instruction cache according to the current PC address; if a branch instruction is encountered, the next fetch address is determined by calling the branch prediction period; the fetched instruction is placed in the instruction buffer for decoding. The decode unit is used to analyze the instruction meaning, extract the operands, and prepare the execution information. Analyzing the instruction meaning refers to translating the binary machine code into the instruction operation type (arithmetic / logic / memory jump, etc.); extracting the operands refers to reading the operands in the register file; preparing the execution information refers to generating control signals. The execution unit is used to perform operations or address calculations, and the execution unit includes an arithmetic logic unit, a branch judgment unit, a multiplier / divider, and an address calculator.

[0045] The instruction structure type matching mode can be used to identify a similar instruction sequence as a target instruction sequence from the instruction sequence. The first instruction in the similar instruction sequence is a conditional branch instruction, and there are other instructions between the conditional branch instruction and a branch instruction, the context instructions including at least one of an operation instruction, a load instruction, a store instruction, and a conditional branch instruction other than the difficult-to-predict branch instruction; and the target address is the address jumped to by the branch instruction.

[0046] Therefore, by reading the instruction sequences in the instruction buffer of the processor, only the instruction sequences meeting the specific static program structure are taken as the target instruction sequences, and the processing and decoding operations are performed. In this way, reading all the instruction sequences in the instruction stream can be effectively avoided, unnecessary memory occupation can be reduced, the amount of processing instructions can be reduced, and the processing efficiency can be improved.

[0047] Optionally, step 201 can include: Sub-step 2014, obtaining the instruction sequences from other paths outside the critical path of the processor pipeline, the critical path being the longest path of the combinational logic; Sub-step 2015, identifying the target instruction sequences from the instruction sequences on the other paths.

[0048] It should be noted that the pipeline critical path is a concept in computer architecture, which determines the shortest clock cycle (i.e., the highest frequency) and the upper limit of the overall performance of the pipeline. The pipeline of the processor is divided into five stages: instruction fetching, decoding, execution, memory access, and write-back. Each stage can be composed of several hardware components. The critical path refers to the longest logic delay path experienced by a signal from input to output within a certain pipeline stage, In the present embodiment, during the actual running of the program, the sequence or trajectory of the instruction stream is on a non-longest logic delay path. Obtaining the instruction sequences from these instruction streams and identifying the target instruction sequences from these instruction sequences can distinguish the instruction streams to be processed, and only the difficult-to-predict branch instructions on the non-critical path are subjected to transformation processing, rather than all the difficult-to-predict branch instructions on all paths. That is, the longest path of the combinational logic in the hardware design affects the frequency of the processor and thus the performance. Therefore, the branch prediction can be advanced to the instruction stream selection in the instruction fetching stage, and the logic structure can be simplified, thereby ensuring the frequency and performance of the processor.

[0049] Optionally, step 201 can include: Sub-step 2016, obtaining the instruction sequences from the microinstruction sequences stored in the microinstruction cache when refilling the microinstruction cache; Sub-step 2017, identifying the target instruction sequences from the instruction sequences.

[0050] For sub-steps 2016 to 2017, it should be noted that a microinstruction is the lowest-level instruction used internally by the processor controller to directly control the hardware to perform basic operations. Each microinstruction is composed of a control signal field. Microinstructions are stored in a microcode memory or a control memory. The microinstruction buffer is a temporary cache area for storing microinstructions that have been fetched from the microcode memory for quick use by the execution stage.

[0051] The operation code is a binary field in the instruction that defines the basic operation, such as addition, subtraction, jump. The operand is the operation object in the instruction, which can be a register operand or an immediate number. The decoder is a hardware module that can translate binary instructions into internal control signals of the processor. After the decoder translates the instruction, it is sent to the execution unit, which is responsible for performing actual calculations according to the instruction.

[0052] When the contents of the microinstruction buffer are invalidated or exhausted, new microinstruction sequences need to be loaded from the microcode memory or instruction decoding unit and filled into the buffer. The refill microinstruction cache processor instruction buffer is used to temporarily save the instructions to be executed taken out from the memory or cache, reduce the blocking caused by the instruction cache delay, and support prediction execution.

[0053] The refill microinstruction cache is an important recovery mechanism when the processor encounters branch prediction errors or cache invalidations during execution. When the trace cache is invalidated or branch prediction fails, the processor needs to retrieve instructions from the secondary cache or main memory and convert complex IA-32 (Intel Architecture 32-bit) instructions into micro-operation codes through the microinstruction sequencer. By obtaining the target instruction sequence during this process, the performance loss caused by target instruction sequence acquisition delay can be effectively reduced, and the overhead of repeatedly decoding the same instruction can be avoided.

[0054] Step 202, the instruction transformation operation is performed on the difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and the branch judgment result of the difficult-to-predict branch instruction is taken as a direction marker, and the value of the direction marker is used to indicate whether the difficult-to-predict branch instruction jumps to a target address.

[0055] This step can specifically refer to step 102 described above, and will not be described here.

[0056] Optionally, step 202 further includes: Sub-step 2021, the difficult-to-predict branch instruction in the target instruction sequence is transformed into a transformed instruction, and the branch judgment result of the difficult-to-predict branch instruction is taken as a direction marker, the transformed instruction is a comparison operation microinstruction type instruction, and the transformed instruction is used to calculate the branch judgment of the difficult-to-predict branch.

[0057] It should be noted that the compare operation microinstruction is a hardware-level command directly executed by the processor control unit, and its core function is to compare two data values through subtraction operation and set a flag bit to reflect the result. The flag bit is set according to the comparison result for subsequent conditional branch instructions. The compare operation microinstruction (e.g., cmp) belongs to the arithmetic logic class microinstruction. Modern processors improve comparison efficiency through parallel microinstruction streams, converting complex instruction set computer (CISC) instructions into RISC micro operations (μops).

[0058] Specifically, the target conditional branch instruction in the target instruction sequence can be converted into a compare operation microinstruction to obtain a transformed instruction, and the target conditional branch instruction is usually the first conditional branch instruction identified first, and other conditional branch instructions nested in the first conditional branch instruction do not perform the transformation operation. Taking an assembly language fragment under the Reduced Instruction Set Computer-Version 5 (RISC-V) architecture as an example, as shown below: bne x2,x3,target bne x5,x7,target2 (irrelevant jump target) target: Logical explanation: compare the values in registers x2 and x3, if the values of the two registers are not equal, the program counter jumps to the address specified by the target label to continue execution; compare the values of registers x5 and x7, if they are not equal, jump to the target2 label.

[0059] The conditional branch instruction bne in the unpredictable branch can be transformed into cmp to obtain the following instruction sequence: cmp x2,x3,flag1 bne_flag flag1, x5,x7,target2 (irrelevant jump target) target: Logical explanation: compare the values of registers x2 and x3; store the comparison result in the flag1 flag register or variable; based on the flag1 flag and register comparison, if flag1 is true (indicating that the previous comparison x2≠x3) and x5≠x7, jump to target2.

[0060] It should be noted that the conditional branch instructions include: beq (Branch if Equal), bne (Branch if Not Equal), beqz (Branch if Equal Zero) and bnez (Branch if Not Zero). The conditional branch of MIPS is based on beq and bne, which realizes jump through register comparison, and replaces beqz with cmp instruction through instruction conversion.

[0061] The pass rate of the pipeline can be improved by decoupling operations, and the flexibility of program flow control is provided by the flag mechanism. The first conditional branch instruction performs a transformation operation, and the second conditional branch instruction immediately following the first conditional branch instruction does not perform a transformation operation, but performs a subsequent adjustment operation. That is, bne is transformed into cmp. As can be seen, the cmp instruction can store the generated flag result in flag1, which can facilitate subsequent sharing of multiple instructions, which avoids repeated comparison operations and thus improves program processing efficiency.

[0062] Optionally, step 202 can further include: Substep 2022, when it is determined that the branch judgment condition carried by the difficult-to-predict branch instruction is established, a first value is written into the direction marker, the first value being used to indicate that the adjusted instruction corresponding to each context instruction is not executed; Substep 2023, when it is determined that the branch judgment condition carried by the difficult-to-predict branch instruction is not established, a second value is written into the direction marker, the second value being used to indicate that the adjusted instruction corresponding to the context instruction is executed.

[0063] It should be noted that the branch judgment condition of the difficult-to-predict branch instruction is usually determined by the instruction type and hardware implementation. The conditional judgment type includes register comparison, flag check and memory value dependence. Memory value dependence refers to that the branch condition may indirectly depend on memory data, and the judgment cannot be made until the data is ready.

[0064] In the present embodiment, in the process of the unpredictable branch transformation, the instruction transformation operation can be performed according to the type of the unpredictable branch instruction. For the unpredictable branch instruction carrying the branch judgment condition, the branch direction and the target address are two key factors. In determining the branch direction, it is needed to judge whether the branch judgment condition carried by the unpredictable branch instruction is established. If the branch judgment condition is established, the first value (for example, 1) is written into the direction marker. In the instruction before transformation, 1 represents the instruction indicating to jump to the target address. In the instruction after transformation, 1 indicates not to execute the adjusted instruction corresponding to each context instruction. If the branch judgment condition is not established, the second value (for example, 0) is written into the direction marker. In the instruction before transformation, 0 represents not jumping to the target address. In the instruction after transformation, 0 indicates executing the adjusted instruction corresponding to each context instruction. As can be seen, by adding the marker as the flag bit, the dependence on memory reading data can be avoided by detecting the flag bit, and the unpredictable branch prediction failure consumption and delay are reduced.

[0065] Optionally, the method further comprises: Step 203, extracting the output value of the comparison result corresponding to the transformed instruction from the target register specified by the transformed instruction; the target register is used to store the comparison result; Step 204, storing the output value of the comparison result into the flag register.

[0066] For steps 203 and 204, for the target register storing the output result specified by the transformed instruction of the unpredictable branch instruction, the reading operation is performed and the output value of the read result is stored into the flag register. The flag register is specially set to store the output value of the comparison result corresponding to the transformed instruction. The type of the output value can be numerical or Boolean.

[0067] Step 205, adding the direction marker to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction.

[0068] This step can refer to the above-mentioned step 103, which will not be described here.

[0069] Optionally, step 205 can further comprise: Sub-step 2051, reading the comparison result as the direction marker from the flag register; Sub-step 2052, adding the direction marker to each context instruction in the target instruction sequence to obtain the adjusted instruction corresponding to each context instruction.

[0070] It should be noted that the flag register is a crucial register in the processor used to store operational status and control instruction execution; it is also known as the program status word. The basic results of the flag register include status flags and control flags. Its functions can include reflecting the characteristics of arithmetic / logic operation results, controlling program flow, and the processor's operating mode. Jumps can be triggered through combinations of flag bits to implement logic such as loops and conditional statements.

[0071] In this embodiment, the comparison result pre-stored in the flag register can be read out as a direction flag, and the direction flag can be added as a flag bit to each context instruction in the target instruction sequence, for example, after the opcode of the context instruction. 10a5c: 031f0963beq_flag flag1,t5,a7,10a8e flag1 refers to the status flag. If the flag is true (1), the branch is triggered. If the flag is false (0), the branch is not triggered. If flag1 is 1, the branch judgment is executed. If the values ​​of registers t5 and a7 are equal, the program jumps to address 10a8e to continue execution.

[0072] Step 206: Execute the transformed instruction and the adjusted instruction corresponding to the context instruction according to the values ​​of each of the direction markers.

[0073] For details of this step, please refer to step 104 above, which will not be repeated here.

[0074] Optionally, step 206 further includes: Sub-step 2061: When the value of the direction indicator is the first value, only the transformed instruction is executed; Sub-step 2062: When the value of the direction indicator is the second value, execute the transformed instruction and the adjusted instruction corresponding to the context instruction.

[0075] It should be noted that the direction indicator can take the value 0 or 1, or it can be extended to other integer values ​​to represent multiple states. The variable type of the direction indicator is not limited to numeric; it can also be a boolean type, and can be true or false.

[0076] In this embodiment, during the execution phase, the transformed instruction sequence of the target instruction sequence is executed. First, the transformed instruction corresponding to the unpredictable branch instruction is executed. Then, different operations can be performed on the transformed target instruction sequence based on different values ​​of the direction identifier. When the value of the direction identifier indicates that the jump condition of the unpredictable branch is met, the adjusted instruction corresponding to the context instruction is not executed; when the value of the direction identifier indicates that the jump condition of the unpredictable branch is not met, the adjusted instruction corresponding to the context instruction is executed.

[0077] Take the assembly language fragment under the Reduced Instruction Set Computer (RISC) Version 5 architecture as an example, as follows: 10a5a: c299beqza3,10a60 10a5c: 031f0963beqt5,a7,10a8e 10a60: 97aaadda5,a5,a0 10a62: 05b7fd63bgeua5,s11,10abc<main+0x5a4> Logical explanation: First, determine if the value of register a3 is 0. If it is 0, directly jump to address 10a60 for address calculation. If the value of register a3 is not 0, continue to check if the values of registers t5 and a7 are equal. If they are, jump to address 10a8e. At address 10a60, add the values of registers a5 and a0, and store the result in a5. Finally, verify if the value of register a5 is greater than the value of register s11 through unsigned comparison. If it is, jump to address 10abc (marked as the main function offset at 0x5a4).

[0078] After instruction transformation, the transformed instructions are: 10a5a: c299cmpa3,zero,flag1 The adjusted instructions are: 10a5c: 031f0963beq_flag flag1,t5,a7,10a8e 10a60: 97aaadda5,a5,a0 10a62: 05b7fd63bgeua5,s11,10abc<main+0x5a4> Logical explanation: First, check if the value of register a3 is 0, and store the comparison result in flag1 flag register. If flag1 is true (a3 = 0) and t5 = a7, skip the addition operation and directly jump to address 10a8e. Otherwise, perform the addition operation a5 += a0, and then check if the value of register a5 is greater than or equal to the value of register s11 to determine whether to jump to address 10abc.

[0079] SPEC CPU 2006 is a CPU subsystem benchmark test suite launched by the Standard Performance Evaluation Corporation (SPEC), mainly used to evaluate the integer and floating point performance of processors.

[0080] The branch prediction accuracy of 0x10a5a is increased from 94.53% to 96.79% and the misprediction rate per Kilo-Instructions (MPKI) is reduced from 11.85 to 6.95 by the processed instructions through the SPEC CPU 2006 test subentry mcf.

[0081] In the embodiment of the application, the target register can be a current program status register, the flag register can be any general register, and the output value of the comparison result can be 0 or 1 or true or false. cmp<register 1><register 2><flag register>; compare the values of register 1 and register 2 and store the comparison result directly in the flag register. Since the results before and after the transformation are consistent, the conditional judgment logic of the instruction is not changed.

[0082] In conclusion, the branch prediction transformation method provided by the application can perform transformation operation only on the difficult-to-predict branch instruction, add only the direction marker to the context instruction, reduce the number of dynamic instructions, thereby reducing the pipeline conflict and scheduling overhead, improving the performance of the processor, and avoiding processing all difficult-to-predict branches by identifying the target instruction sequence from the instruction sequence, thereby reducing the complexity of the transformation algorithm, improving the efficiency of the executed instruction, and improving the overall performance of the processor.

[0083] Reference Figure 3 Fig. 1 shows a difficult-to-predict branch transformation device according to the application, which can specifically include the following modules: The identification module 310 is configured to identify a target instruction sequence from an instruction sequence. The transformation module 320 is configured to perform instruction transformation operation on a difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and take the branch judgment result of the difficult-to-predict branch instruction as a direction marker. The adjustment module 330 is configured to add the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction. The execution module 340 is configured to execute the transformed instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction marker.

[0084] Optionally, the identification module includes: The first selection sub-module is configured to select an instruction sequence including a target instruction structure from the instruction sequence as the target instruction sequence.

[0085] Optionally, the identification module includes: The first reading sub-module is configured to read the instruction sequence from the processor instruction buffer.

[0086] The second selecting sub-module is configured to identify the instruction sequence as a target instruction sequence when the first instruction in the instruction sequence is a conditional branch instruction and the first instruction is separated from a branch instruction by at least one context instruction.

[0087] Optionally, the identifying module comprises: The obtaining sub-module is configured to obtain the instruction sequence from a path other than a critical path of a processor pipeline.

[0088] The identifying sub-module is configured to identify a target instruction sequence from the instruction sequence on the other path.

[0089] Optionally, the transforming module comprises: The transforming sub-module is configured to transform a difficult-to-predict branch instruction in the target instruction sequence into a transformed instruction.

[0090] Optionally, the transforming module comprises: The first determining sub-module is configured to write a first numerical value into the direction marker when it is determined that a branch judgment condition carried by the difficult-to-predict branch instruction is true; The second determining sub-module is configured to write a second numerical value into the direction marker when it is determined that the branch judgment condition carried by the difficult-to-predict branch instruction is false.

[0091] Optionally, the adjusting module comprises: The second reading sub-module is configured to read the direction marker from the marker register; The adding sub-module is configured to add the direction marker to each context instruction in the target instruction sequence respectively to obtain an adjusted instruction corresponding to each context instruction.

[0092] Optionally, the executing module comprises: The first executing sub-module is configured to execute only the transformed instruction when the value of the direction marker is the first numerical value; The second executing sub-module is configured to execute the transformed instruction and the adjusted instruction corresponding to the context instruction when the value of the direction marker is the second numerical value.

[0093] The apparatus further comprises: The extracting module is configured to extract an output value of a comparison result corresponding to the transformed instruction from a target register specified by the transformed instruction; The storage module is configured to store the output value of the comparison result into a marker register.

[0094] In conclusion, the unpredictable branch conversion device provided by the application can perform conversion operation on only the unpredictable branch instruction, and only add a direction marker to the context instruction, thereby reducing the number of dynamic instructions, reducing the pipeline conflict and scheduling overhead, improving the performance of the processor, and avoiding processing all unpredictable branches by identifying the target instruction sequence from the instruction sequence, thereby reducing the complexity of the conversion algorithm, improving the efficiency of the executed instruction, and improving the overall performance of the processor.

[0095] For the device embodiment, the description is relatively simple because it is basically similar to the method embodiment, and the relevant parts can be referred to the description of the method embodiment.

[0096] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0097] For the processor in the above-described embodiments, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0098] Reference Figure 4 is a structural block diagram of an electronic device for unpredictable branch conversion provided by the embodiment of the application. As shown in Figure 4 , the electronic device includes a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the unpredictable branch conversion method of the foregoing embodiments.

[0099] The processor can be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array) or other programmable device, transistor logic device, hardware component or any combination thereof. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0100] The communication bus can include a path for transmitting information between the memory and the communication interface. The communication bus can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, Figure 4 Only one line is used in the figure to represent the bus, but it is understood that the bus can include a plurality of buses. Bus 120 includes a plurality of bus lines, and only one bus line is used in the figure to represent the bus, but it is understood that there is only one bus or only one type of bus.

[0101] The memory can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0102] The embodiment of the present application also provides a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device (a server or a terminal), the processor can execute the Figure 1 The unpredictable branch transformation method shown.

[0103] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between each embodiment can be referred to each other.

[0104] Those skilled in the art should understand that the embodiments of the embodiments of the present application can be provided as a method, an apparatus or a computer program product. Therefore, the embodiments of the present application can be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0105] The embodiments of the present application are described with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It is understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0106] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0107] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices to cause a series of operational steps to be performed on the computer or other programmable terminal devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal devices provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0108] Although preferred embodiments of the present application have been described, those skilled in the art will be able to make additional modifications and variations to the embodiments without departing from the scope of the present application. Accordingly, the appended claims are intended to cover all such modifications and variations as falling within the scope of the embodiments of the present application.

[0109] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0110] The above provides a detailed description of the unpredictable branch transformation method, device, electronic equipment and computer readable storage medium provided by the application. The principles and implementation modes of the application are described by applying specific examples in this paper. The above example is only used to help understand the method and core idea of the application. Meanwhile, for those skilled in the art, according to the idea of the application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the application.

Claims

1. A method of unpredictable branch transformation, comprising: The method comprises: identifying a target instruction sequence from an instruction sequence, the target instruction sequence comprising a difficult-to-predict branch instruction and context instructions of the difficult-to-predict branch instruction; performing an instruction transformation operation on the difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and taking a branch judgment result of the difficult-to-predict branch instruction as a direction marker, a value of the direction marker being used to indicate whether the difficult-to-predict branch instruction jumps to a target address; adding the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction; executing the transformed instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction marker.

2. The method of claim 1, wherein, The identifying a target instruction sequence from an instruction sequence comprises: selecting an instruction sequence comprising a target instruction structure as the target instruction sequence from the instruction sequence; wherein the target instruction structure comprises a difficult-to-predict branch instruction, context instructions and a transfer instruction; the context instructions are located between the difficult-to-predict branch instruction and the transfer instruction; the context instructions comprise at least one of an operation instruction, a load instruction, a store instruction and another conditional branch instruction except the difficult-to-predict branch instruction; and the target address is the address of the transfer instruction.

3. The method of claim 1, wherein, The performing an instruction transformation operation on the difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and taking a branch judgment result of the difficult-to-predict branch instruction as a direction marker comprises: transforming the difficult-to-predict branch instruction in the target instruction sequence into a transformed instruction, the transformed instruction being a comparison operation microinstruction type instruction, and taking a branch judgment result of the difficult-to-predict branch instruction as a direction marker, the transformed instruction being used to calculate the branch judgment of the difficult-to-predict branch.

4. The method of claim 3, wherein, The method further comprises: extracting an output value of a comparison result corresponding to the transformed instruction from a target register specified by the transformed instruction, the target register being used to store the output value of the comparison result; storing the output value of the comparison result into a flag register.

5. The method of claim 4, wherein, The adding the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction comprises: reading the comparison result as a direction marker from the flag register; adding the direction marker to each context instruction in the target instruction sequence respectively to obtain an adjusted instruction corresponding to each context instruction.

6. The method of claim 1, wherein, The performing an instruction transformation operation on the difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and taking a branch judgment result of the difficult-to-predict branch instruction as a direction marker comprises: writing a first value into the direction marker when it is determined that a branch judgment condition carried by the difficult-to-predict branch instruction is established, the first value being used to indicate that an adjusted instruction corresponding to each context instruction is not executed; writing a second value into the direction marker when it is determined that the branch judgment condition carried by the difficult-to-predict branch instruction is not established, the second value being used to indicate that the adjusted instruction corresponding to the context instruction is executed.

7. The method of claim 6, wherein, The execution of the transformed instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction marker includes: When the value of the direction marker is a first value, only the transformed instruction is executed; When the value of the direction marker is a second value, the transformed instruction and the adjusted instruction corresponding to the context instruction are executed.

8. The method of claim 1, wherein, The identifying of the target instruction sequence from the instruction sequence includes: reading the instruction sequence from a processor instruction buffer, the instruction buffer being located in a cache area between a fetch unit and a decode unit; when a first instruction in the instruction sequence is a conditional branch instruction and the first instruction is separated from a branch instruction by at least one context instruction, identifying the instruction sequence as the target instruction sequence.

9. The method of claim 1, wherein, The identifying of the target instruction sequence from the instruction sequence includes: obtaining the instruction sequence from a path other than a critical path of a processor pipeline, the critical path being a longest path of combinational logic; identifying the target instruction sequence from the instruction sequence on the other path.

10. The method of claim 1, wherein, The identifying of the target instruction sequence from the instruction sequence includes: when refilling a microinstruction cache, obtaining the instruction sequence from a microinstruction sequence stored in the microinstruction cache; identifying the target instruction sequence from the instruction sequence.

11. A branch prediction conversion apparatus characterized by comprising: The apparatus includes: an identifying module configured to identify a target instruction sequence from an instruction sequence; a transforming module configured to perform an instruction transformation operation on a difficult-to-predict branch instruction in the target instruction sequence to obtain a transformed instruction, and to use a branch judgment result of the difficult-to-predict branch instruction as a direction marker; an adjusting module configured to add the direction marker to each context instruction in the target instruction sequence to obtain an adjusted instruction corresponding to each context instruction; an execution module configured to execute the transformed instruction and the adjusted instruction corresponding to the context instruction according to the value of each direction marker.

12. An electronic device, comprising: includes: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the method of any one of claims 1-10.

13. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method of any one of claims 1-10.

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