HPSDI controller based on PCIE interface

Abstract

The invention provides an HPSDI (High Performance Serial Digital Interface) controller based on a PCIE (Peripheral Component Interface Express) interface, which comprises a Config control module used for receiving a read-write operation command; the Hpsdi analysis module is used for analyzing the read-write operation command into an SQ instruction; the SQ processing module is used for converting the SQ instruction into an AXI bus format; the PCIE IP core is used for sending the content of the S bus to an EP end through a PCIE interface to complete data reading and writing and generate a CQ frame; the CQ processing module is used for analyzing the CQ frame to generate a CQ field; and the Config control module is used for changing an execution state for representing the read-write operation command in the register, so that a user side reads data from the DDR or writes data into the DDR according to the execution state. According to the HPSDI controller, all functions are achieved through the FPGA, an HPSDI configuration interface is simplified at the same time, the portability of the protocol is improved, and the data transmission efficiency of the HPSDI protocol is improved.

Description

Technical Field

[0001] This invention belongs to the field of aerospace data storage technology, specifically relating to an HPSDI controller based on a PCIE interface. Background Technology

[0002] In the context of the new era, the SSDs (Solid State Drives) used have transitioned from SATA to the PCIe era, from PCIe 1.0, PCIe 2.0, PCIe 3.0 to the current PCIe 4.0. With the continuous increase in storage speed, system data networks have become increasingly complex and massive. It is essential to address the real-time characteristics of data transmission and improve power management and control functions. The transmission speed limits of the Serial Advanced Technology Attached Interface (SIDE) are increasingly intertwined with the storage requirements of space applications. Based on the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express (PCIe) interface and Non-Volatile Memory Express (NVMe)), SSDs can contribute to improving interface performance.

[0003] NVMe is specifically designed for solid-state drives (SSDs), using flash memory as the storage medium. It standardizes the logic interface bus transmission, reducing memory interfaces, optimizing the instruction set, and implementing queue design when the host communicates with the SSD. By improving PCIe latency, enhancing data transmission bandwidth quality, and enabling instruction parallelism at a controllable storage cost, it significantly enhances the performance of SSDs in a PCIe environment. For HPSDI-related interactions between FPGAs and firmware, the commonly used technical solution is single instruction configuration execution (SQ). This involves software configuring the parameters of the read / write instruction (SQ), the storage device generating a read / write query (CQ) upon completion, the firmware receiving the CQ, configuring the parameters, and initiating the next data transfer. The maximum single transfer is 32MB.

[0004] Existing NVMe storage devices all use fragmented data storage, which can improve storage resource utilization, but it limits the amount of data in a single data transfer instruction. Aerospace storage uses a large-scale data storage method with contiguous storage addresses. Therefore, applying the NVMe protocol in aerospace scenarios will increase the instruction interaction between the host and the storage device and reduce the data transfer efficiency between the host and the storage device.

[0005] The existing HPSDI-related interaction methods between FPGAs and firmware (FW) involve numerous parameter configurations when transmitting large amounts of data. Furthermore, since the timeliness of each parameter configuration is affected by the current process in the firmware, the more parameter configurations are performed, the lower the data transfer efficiency becomes.

[0006] Existing FPGAs and FWs implement the HPSDI protocol via a bus, which has limitations for different users and restricts portability. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides an HPSDI controller based on a PCIe interface. The technical problem to be solved by this invention is achieved through the following technical solution:

[0008] This invention provides an HPSDI controller based on a PCIe interface, comprising:

[0009] The Config control module is used to receive read or write operation commands.

[0010] The Hpsdi parsing module is used to parse the read operation command or write operation command into SQ instructions and transmit them to the SQ processing module.

[0011] The SQ processing module is used to convert the SQ instructions into AXI bus format and transmit them to the S bus of the PCIe IP core;

[0012] The PCIe IP core is used to send the contents of the S-bus to the EP end through the PCIe interface, so that the EP end can read data from DDR or write data to DDR, and after the data reading or writing is completed, a CQ frame is generated and transmitted to the CQ processing module.

[0013] The CQ processing module is used to parse the CQ frame, generate CQ fields, and transmit them to the Config control module.

[0014] The Config control module is used to change the execution status of the register that represents the read operation command or write operation command, so that the user terminal can read data from DDR or write data to DDR according to the execution status.

[0015] Beneficial effects:

[0016] This invention provides an HPSDI controller based on a PCIe interface, including a Config control module for receiving read or write operation commands; an HPSDI parsing module for parsing the read or write operation commands into SQ instructions and transmitting them to the SQ processing module; an SQ processing module for converting the SQ instructions into an AXI bus format and transmitting them to the S-bus of a PCIe IP core; a PCIe IP core for sending the contents of the S-bus to an EP end via the PCIe interface, enabling the EP end to read data from or write data to DDR, and generating a CQ frame after the read or write operation is completed, which is then transmitted to the CQ processing module; a CQ processing module for parsing the CQ frame and generating a CQ field, which is transmitted to the Config control module; and a Config control module for changing the execution state of registers representing the read or write operation commands, so that the user end can read data from or write data to DDR according to the execution state. The HPSDI controller of this invention is implemented using an FPGA, achieving all functions while simplifying the HPSDI configuration interface, improving the portability of the protocol, and enhancing the data transmission efficiency of the HPSDI protocol. This invention defines a data user protocol layer to meet the high-reliability data transmission needs of aerospace, enabling reliable transmission of large volumes of data. Big data storage technology based on the HPSDI storage protocol will lay a solid foundation for the development of the aerospace industry.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of an HPSDI controller based on a PCIE interface provided by the present invention;

[0019] Figure 2 This is the initialization flowchart of the present invention;

[0020] Figure 3 This is a flowchart of the read / write operation of the HPSDI controller provided by the present invention;

[0021] Figure 4 This is a schematic diagram of the initialization process of the HPSDI controller provided by the present invention;

[0022] Figure 5 This is a schematic diagram of the HPSDI controller data writing process provided by the present invention;

[0023] Figure 6 This is a schematic diagram of the HPSDI controller data reading process provided by the present invention. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0025] First, a brief introduction to the technical concept of this invention will be given.

[0026] This invention provides a PCIe interface-based HPSDI controller. Unlike the ATA / NVMe protocol commonly used in consumer or industrial applications, the HPSDI protocol has more concise instructions and is optimized for storage system solutions. It is specifically designed for storage systems on aerospace satellites and can effectively reduce the interaction loss between the host software layer and the device software layer, thereby enabling high-speed access to big data.

[0027] This invention designs and develops an HPSDI controller based on an FPGA platform, aiming to improve the efficiency of large data transfer and adapt to the domestically produced aerospace-grade storage controller chip Bifort. The HPSDI configuration bus is transformed into a simple AXI_BRAM bus for user convenience. This controller supports up to the PCIe Gen3 protocol and is backward compatible, with a maximum bandwidth of 8GB / s. The interface supports the AXI Bridge for PCI Express Gen3 Subsystem v3.0 protocol. The workflow of this invention is designed with reference to the HPSDI protocol specification 1.0, primarily responsible for calling various modules to process system commands.

[0028] like Figure 1 As shown, the present invention provides an HPSDI controller based on a PCIe interface, comprising:

[0029] The Config control module is used to receive read or write operation commands.

[0030] The Hpsdi parsing module is used to parse the read operation command or write operation command into SQ instructions and transmit them to the SQ processing module.

[0031] The SQ processing module is used to convert the SQ instructions into AXI bus format and transmit them to the S bus of the PCIe IP core;

[0032] The PCIe IP core is used to send the contents of the S-bus to the EP end through the PCIe interface, so that the EP end can read data from DDR or write data to DDR, and after the data reading or writing is completed, a CQ frame is generated and transmitted to the CQ processing module.

[0033] The CQ processing module is used to parse the CQ frame, generate CQ fields, and transmit them to the Config control module.

[0034] The Config control module is used to change the execution status of the register that represents the read operation command or write operation command, so that the user terminal can read data from DDR or write data to DDR according to the execution status.

[0035] The PCIeIP core communicates with the EP terminal, and the Config control module communicates with the user terminal.

[0036] It is worth noting that the system hardware environment of the HPSDI controller based on the PCIe interface of this invention is as follows: the main control chip is a Xilinx FPGA chip, model XC7Z100FFG900-2. (Reference) Figure 1 ,exist Figure 1 The components are connected via a baseboard as the RC (Root Complex), a PCIe port mode located at the top of the PCIe system. The aerospace-grade storage controller chip Bifort is used as the EP (End Point), a PCIe port mode located at the bottom of the PCIe system. A separate SOC system is built, integrating peripherals such as the PCIe core, serial port, and BRAM. The PCIe controller module of this invention uses the AXI Bridge for PCI Express Gen3 Subsystem, responsible for parsing TLP packet data in the PCIe bus and converting the data to the AXI4 bus.

[0037] The HPSDI controller of this invention is implemented using an FPGA. While performing all the functions achievable by existing technologies, it simplifies the HPSDI configuration interface, improves the portability of the protocol, and enhances the data transmission efficiency of the HPSDI protocol. The HPSDI (High Performance Sensor Data Interface Protocol) proposed in this invention is a storage protocol based on the PCIe interface. It defines a data user protocol layer to meet the high-reliability data transmission requirements of aerospace, enabling reliable transmission of large volumes of data. Big data storage technology based on the HPSDI storage protocol will lay a solid foundation for the development of the aerospace industry.

[0038] exist Figure 1The white-framed section represents the RC module. The entire module is implemented on the Zynq PL side. The RC mainly includes USER, HPSDI, and DDR, with HPSDI being the module ultimately encapsulated into a netlist. The PCIe port on the device under test is in EP mode. The operation is as follows: The RC port's USER / software configures read and write instructions via the BRAM bus. The FPGA converts the standard read / write instructions from the USER / software into an SQ instruction and sends it to the EP side via the PCIe bus. After receiving the instruction, the EP side, with the assistance of the Bifort controller, parses the instruction and assembles the parsed result into a CQ, which is then sent to the RC side via the PCIe bus.

[0039] The SQ instruction is the HPSDI operation request message, including a first SQ instruction and a second SQ instruction. The format of the first SQ instruction and the second SQ instruction is defined as follows: DWORD4: 159:128 bits reserved; DWORD3: 127:112 bits reserved, 111:96 bits for data length; DWORD2: 95:64 bits for data buffer address; DWORD1: 63:32 bits for the starting position of data in the storage device; DWORD0: 31:16 bits for request message sequence number, 15:8 bits reserved, 7:0 for opcode (opcode 00 indicates Identify); 0x0C indicates data read; 0x0B indicates data write. See the table below for specific format definitions:

[0040]

[0041]

[0042] The CQ frame of this invention is the HPSDI operation response message, which includes a first CQ frame and a second CQ frame. The format of the first CQ frame and the second CQ frame is defined as follows:

[0043] Bits 63-32 of DWORD1 are reserved; bits 31-16 of DWORD0 are the request message sequence number, and bits 15-8 are the operation command completion status, where 0x00 indicates operation success, 0x01 indicates request parameter error, 0x02 indicates data transmission error, and 0x03 indicates internal processing error; bits 7-0 of DWORD0 are the opcode, where 0x01 indicates data read and 0x02 indicates data write. See the table below for the specific format:

[0044]

[0045]

[0046] refer to Figure 2 , Figure 2 This is a flowchart of the initialization process of the present invention. The user terminal first writes a 1 to address 0x10 in the register, then writes a 0 to initiate a reset operation to start the initialization process; the effective duration of the high level (1) must be no less than 10 0_clk clock cycles. The user terminal checks the version number by reading address 0x00 in the register; the user terminal checks whether initialization is complete by reading address 0x01 in the register. A value of 1 at address 0x01 indicates that initialization is complete, while a value of 0 indicates that initialization is incomplete.

[0047] refer to Figure 3 , Figure 3 This is a flowchart of the controller read / write operation of the present invention. The user terminal confirms whether the previous read / write operation is complete by sending the opcode of the write or read operation command to the address 0x20 in the register; sends the buffer start address of the read / write operation command to the address 0x24 in the register; sends the starting logic block address of the read / write operation command to the address 0x28 in the register; and sends the number of bytes of the read / write operation command to the address 0x2c in the register, and this number of bytes must be an integer multiple of 512 bytes. A flag to initiate a read / write operation command is sent to the address 0x30 in the register. Sending 1 indicates initiating a read / write operation. After the operation is completed, the FPGA will automatically set this flag to 0 (after setting it to 0, it can be queried at address 0x34). The user terminal confirms whether the current read / write operation is complete by sending the address 0x34 in the register; the user terminal writes 1 to the address 0x38 in the register to clear the interrupt.

[0048] refer to Figure 4 , Figure 4 This is a schematic diagram of the initialization process of the HPSDI controller of the present invention. The HPSDI controller based on the PCIe interface of the present invention also includes a CTRL processing module, used to complete initialization by initializing the configuration space, establishing mappings between modules, initializing mapping addresses, and enabling PCIe devices. After initialization is complete, it outputs an initialization completion flag to the Config control module, so that the Config control module modifies the flag bit value in the register indicating whether initialization is complete. The initialization process of the present invention is as follows:

[0049] 0: The user initiates a reset operation through the Sys_rst interface;

[0050] 1: The CTRL processing module begins its initialization process;

[0051] Initialization steps: 1) Map the RC to the AXIBar to the PCIe Bar;

[0052] 2) Clear the interrupt;

[0053] 3) RC configuration space initialization;

[0054] 4) Waiting for the chain to be established;

[0055] 5) Mapping address from RC AXIBAR to EP PCIE BAR;

[0056] 6) Initialize EP configuration space;

[0057] 7) Configure Bifort iATU;

[0058] 8) RC address filtering configuration;

[0059] 9) Mapping address from EP AXIBAR to RC PCIE BAR;

[0060] 10) Enable RC PCIe Bridge.

[0061] 2: After initialization is complete, output an initialization completion flag to the Config control module;

[0062] 3: Users can determine whether initialization is complete by reading register 0x10.

[0063] refer to Figure 5 , Figure 5 This is a schematic diagram of the data writing process for the HPSDI controller of the present invention, specifically from RC to EP. The data writing process includes:

[0064] The user terminal is used to write data to the DDR;

[0065] The Config control module is used to receive write operation commands;

[0066] The Hpsdi parsing module is used to parse the write operation command into a first SQ instruction and transmit it to the SQ processing module;

[0067] The SQ processing module is used to convert the first SQ instruction into an AXI bus format and transmit it to the S bus of the PCIE IP core.

[0068] PCIe IP core, used to send the contents of the S bus to the EP end through the PCIe interface;

[0069] The EP terminal is used to parse the contents of the S bus to obtain the first SQ instruction, store it in the SQ FIFO, and start the read DMA; read data from DDR through the M interface of the PCIe IP core according to the address parameters in the first SQ instruction; generate the first CQ frame after the data reading is completed and transmit it to the CQ processing module through DMA;

[0070] The CQ processing module is used to parse the first CQ frame to obtain the first CQ field, and transmit the first CQ field to the Config control module;

[0071] The Config control module is used to change the flag bits in the register that indicate the execution status of the first SQ instruction;

[0072] The user terminal determines the operation status of the first SQ instruction by querying the flag bit of the execution status of the first SQ instruction.

[0073] refer to Figure 6 , Figure 6 This is a schematic diagram of the data read process, from EP to RC. The data read process includes:

[0074] The Config control module is used to receive read operation commands;

[0075] The Hpsdi parsing module is used to parse the read operation command into a second SQ instruction and transmit it to the SQ processing module;

[0076] The SQ processing module is used to convert the second SQ instruction into an AXI bus format and transmit it to the S bus of the PCIE IP core;

[0077] The PCIe IP core is used to send the contents of the S-bus to the EP end through the PCIe interface;

[0078] The EP terminal is used to parse the contents of the S bus to obtain the second SQ instruction, store it in the SQ FIFO, and start the read DMA; write read data to the DDR through the M interface of the PCIe IP core according to the address parameters in the second SQ instruction; after the data writing is completed, generate the second CQ frame and transmit it to the CQ processing module through DMA;

[0079] The CQ processing module is used to parse the second CQ frame to obtain the second CQ field, and transmit the second CQ field to the Config control module;

[0080] The Config control module is used to change the flag bit in the register that indicates the execution status of the second SQ instruction;

[0081] The user terminal determines the operation status of the second SQ instruction by querying the flag bit of the execution status of the second SQ instruction.

[0082] This invention enables the construction of high-performance aerospace storage arrays and achieves compatibility with the domestically produced aerospace-grade storage controller chip, Bifort. The invention utilizes radiation-resistant storage disks, increasing the reliability and security of satellite data.

[0083] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An HPSDI controller based on a PCIe interface, characterized in that, include: The Config control module is used to receive read or write operation commands. The Hpsdi parsing module is used to parse the read operation command or write operation command into SQ instructions and transmit them to the SQ processing module. The SQ processing module is used to convert the SQ instructions into AXI bus format and transmit them to the S bus of the PCIe IP core; The PCIe IP core is used to send the contents of the S-bus to the EP end through the PCIe interface, so that the EP end can read data from DDR or write data to DDR, and after the data reading or writing is completed, a CQ frame is generated and transmitted to the CQ processing module. The CQ processing module is used to parse the CQ frame, generate CQ fields, and transmit them to the Config control module. The Config control module is used to change the execution status of the register that represents the read operation command or write operation command, so that the user terminal can read data from DDR or write data to DDR according to the execution status.

2. The HPSDI controller based on a PCIe interface according to claim 1, characterized in that, The PCIe IP core communicates with the EP terminal, and the Config control module communicates with the user terminal.

3. The HPSDI controller based on a PCIe interface according to claim 2, characterized in that, The SQ instruction includes a first SQ instruction and a second SQ instruction. The format of the first SQ instruction and the second SQ instruction is defined as follows: 159:128 bits of DWORD4 are reserved; 127:112 bits of DWORD3 are reserved, and 111:96 bits represent the data length; 95:64 bits of DWORD2 represent the data buffer address; 63:32 bits of DWORD1 represent the starting position of the data in the storage device; 31:16 bits of DWORD0 represent the request message sequence number, 15:8 bits are reserved, and 7:0 represent the opcode, with opcode 00 indicating Identify; 0x0C indicates data read; and 0x0B indicates data write.

4. The HPSDI controller based on a PCIe interface according to claim 3, characterized in that, The CQ frame retains the first CQ frame and the second CQ frame, and the formats of the first CQ frame and the second CQ frame are defined as follows: 63:32 bits of DWORD1 are reserved; 31:16 bits of DWORD0 are the request message sequence number, and 15:8 bits are the operation command completion status, where 0x00 indicates operation success, 0x01 indicates request parameter error, 0x02 indicates data transmission error, and 0x03 indicates internal processing error. Bits 7 and 0 of DWORD 0 are the opcodes, where 0x01 indicates data reading and 0x02 indicates data writing.

5. The HPSDI controller based on a PCIe interface according to claim 1, characterized in that, The HPSDI controller based on the PCIe interface also includes a CTRL processing module, which is used to complete initialization by initializing the configuration space, establishing mapping between modules, initializing the mapping address, and enabling the PCIe device. After initialization is completed, it outputs an initialization completion flag to the Config control module so that the Config control module modifies the flag bit value in the register that indicates whether initialization is complete.

6. The HPSDI controller based on a PCIe interface according to claim 2, characterized in that, The user terminal is used to first write 1 to address 0x10 in the register, and then write 0 to initiate a reset operation to start the initialization process; the user terminal checks the version number by reading address 0x00 in the register, and checks whether the initialization is complete by reading address 0x01 in the register. When the value of address 0x01 is 1, it means that the initialization is complete, and if it is 0, it means that the initialization is not complete.

7. The HPSDI controller based on a PCIe interface according to claim 2, characterized in that, The user terminal confirms whether the previous read / write operation was completed by sending the opcode for the write or read operation command to address 0x20 in the register; sends the buffer start address for the read / write operation command to address 0x24 in the register; sends the starting logical block address for the read / write operation command to address 0x28 in the register; sends the number of bytes for the read / write operation command to address 0x2c in the register; sends a flag to initiate a read / write operation command to address 0x30 in the register; the user terminal confirms whether the current read / write operation is completed by sending the flag to address 0x34 in the register; and clears the interrupt by writing 1 to address 0x38 in the register.

8. The HPSDI controller based on a PCIe interface according to claim 4, characterized in that, The user terminal is used to write data to the DDR; The Config control module is used to receive write operation commands; The Hpsdi parsing module is used to parse the write operation command into a first SQ instruction and transmit it to the SQ processing module; The SQ processing module is used to convert the first SQ instruction into an AXI bus format and transmit it to the S bus of the PCIE IP core. PCIe IP core, used to send the contents of the S bus to the EP end through the PCIe interface; The EP terminal is used to parse the contents of the S bus to obtain the first SQ instruction, store it in the SQ FIFO, and start the read DMA; read data from DDR through the M interface of the PCIe IP core according to the address parameters in the first SQ instruction; generate the first CQ frame after the data reading is completed and transmit it to the CQ processing module through DMA; The CQ processing module is used to parse the first CQ frame to obtain the first CQ field, and transmit the first CQ field to the Config control module; The Config control module is used to change the flag bits in the register that indicate the execution status of the first SQ instruction; The user terminal determines the operation status of the first SQ instruction by querying the flag bit of the execution status of the first SQ instruction.

9. The HPSDI controller based on a PCIe interface according to claim 4, characterized in that, The Config control module is used to receive read operation commands; The Hpsdi parsing module is used to parse the read operation command into a second SQ instruction and transmit it to the SQ processing module; The SQ processing module is used to convert the second SQ instruction into an AXI bus format and transmit it to the S bus of the PCIE IP core; The PCIe IP core is used to send the contents of the S-bus to the EP end through the PCIe interface; The EP terminal is used to parse the contents of the S bus to obtain the second SQ instruction, store it in the SQ FIFO, and start the read DMA; write read data to the DDR through the M interface of the PCIe IP core according to the address parameters in the second SQ instruction; after the data writing is completed, generate the second CQ frame and transmit it to the CQ processing module through DMA; The CQ processing module is used to parse the second CQ frame to obtain the second CQ field, and transmit the second CQ field to the Config control module; The Config control module is used to change the flag bit in the register that indicates the execution status of the second SQ instruction; The user terminal determines the operation status of the second SQ instruction by querying the flag bit of the execution status of the second SQ instruction.

10. The HPSDI controller based on a PCIe interface according to claim 1, characterized in that, The HPSDI controller based on the PCIe interface is designed based on an FPGA platform.

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