Pin arrangement method and apparatus

Abstract

The application discloses a pin arrangement method and device, relates to the technical field of electronic products, and comprises the following steps: acquiring pin information and partition information; through matching of the pin information and the partition information, automatic determination of pins and partitions is realized, and then the partitions corresponding to the pins are determined; in combination with signal characteristics of a wire, the partitions corresponding to the wire are determined; through the partitions corresponding to the pins and the partitions corresponding to the wire, determination of pin interconnection relationships is realized, therefore, the technical problem of low efficiency caused by dependence on manual operation can be solved, and the technical effect of efficiently completing pin and wire arrangement is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic products, and in particular to a pin arrangement method and device. BACKGROUND

[0002] In modern electronic device design, programmable control devices are the core components for realizing digital logic functions. With the increase in the complexity of circuit functions, the number of pins of programmable control devices also increases. In the layout design stage of a printed circuit board, in order to optimize the wiring effect, the pin arrangement needs to be planned to reduce the crossing of wires and improve the wiring continuity.

[0003] In the traditional method, an engineer needs to manually query the pin names, original signal networks and target signal networks of the programmable control device, and arrange these information for the electronic engineer to modify the schematic diagram. However, this process relies on manual operation and has the problem of low efficiency. SUMMARY

[0004] The present application provides a pin arrangement method and device to at least solve the problem of low efficiency in the related art due to reliance on manual operation.

[0005] The present application provides a pin arrangement method, comprising:

[0006] obtaining a plurality of partitions of a programmable control device and partition information of the partitions;

[0007] obtaining at least one pin of the programmable control device and pin information of the pin;

[0008] According to the pin information, the partition information is matched to obtain the partition corresponding to the pin;

[0009] obtaining at least one wire of the programmable control device and signal characteristics of the wire;

[0010] According to the partition corresponding to the pin and the signal characteristics, the partition corresponding to the wire is determined;

[0011] According to the partition corresponding to the pin and the partition corresponding to the wire, a pin interconnection relationship of the partition is generated.

[0012] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above pin arrangement methods.

[0013] Through the present application, the automatic determination of the pin and the partition can be realized through the matching of the pin information and the partition information, and then the partition corresponding to the pin is determined, and in combination with the signal characteristics of the wire, the determination of the pin interconnection relationship is realized, so that the technical problem can be solved, and the technical effect of efficiently completing the pin and wire arrangement can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0015] Figure 1 The scene diagram of the pin arrangement method provided by the embodiments of the present application;

[0016] Figure 2 The flowchart of the pin arrangement method provided by the embodiments of the present application;

[0017] Figure 3 The schematic diagram of the partition of the programmable control device provided by the embodiments of the present application;

[0018] Figure 4 The schematic diagram of the wire placement position provided by the embodiments of the present application;

[0019] Figure 5 The schematic diagram of the subspace unit corresponding to the via hole coordinate provided by the embodiments of the present application;

[0020] Figure 6 The schematic diagram of the matrix of the programmable control device provided by the embodiments of the present application;

[0021] Figure 7 The schematic diagram of the first stage of determining the interconnection path provided by the embodiments of the present application;

[0022] Figure 8 The schematic diagram of the second stage of determining the interconnection path provided by the embodiments of the present application;

[0023] Figure 9 The schematic diagram of the third stage of determining the interconnection path provided by the embodiments of the present application;

[0024] Figure 10 The schematic diagram of the fourth stage of determining the interconnection path provided by the embodiments of the present application;

[0025] Figure 11 The schematic diagram of the fifth stage of determining the interconnection path provided by the embodiments of the present application;

[0026] Figure 12 The structural schematic diagram of the pin arrangement device provided by the embodiments of the present application;

[0027] Figure 13 The structural schematic diagram of the electronic device provided by the present application. DETAILED DESCRIPTION

[0028] With reference to the drawings and specific embodiments, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0029] It should be noted that, in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0030] The pin arrangement method provided by the present application automatically obtains pin information and partition information, and can realize automatic determination of pins and partitions through matching of the above information, and then determine the partitions corresponding to the pins, and further realize determination of pin interconnection relationship in combination with signal characteristics of the traces, thereby realizing efficient pin and trace arrangement.

[0031] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0032] In combination with the specific application environment architecture or specific hardware architecture on which the pin arrangement method is executed, the specific application environment architecture or specific hardware architecture is described herein. For reference Figure 1 , Figure 1 The scenario diagram of the pin arrangement method provided by the embodiments of the present application is shown in FIG. 1, which includes a service device 101 and a programmable control device 102. Figure 1

[0033] The service device 101 can be a server. Alternatively, it can be a server or a cluster composed of multiple servers.

[0034] The programmable control device 102 can be a field programmable gate array (FPGA), a complex programmable logic device (CPLD) or a microcontroller unit (MCU).

[0035] ​Specifically, the service device 101 acquires the partitions and partition information of the programmable controller 102, the pins and pin information, and the signal characteristics of the traces and traces, and processes the partitions and partition information, the pins and pin information, and the signal characteristics of the traces and traces to obtain the pin interconnection relationship of the partitions.

[0036] Figure 2 This is a schematic flowchart of the pin arrangement method provided in the embodiments of this application, as shown below. Figure 2 As shown, embodiments of this application provide a pin arrangement method, which is described in detail below:

[0037] S201: Obtain multiple partitions and partition information of the programmable controller.

[0038] Alternatively, the programmable controller can be an FPGA, CPLD, or MCU, etc.

[0039] Optionally, Figure 3 This is a schematic diagram of a programmable controller partition provided in an embodiment of this application. Figure 3 As shown, taking CPLD as an example, it can be divided into multiple zones according to voltage and function. The voltage of each zone must be consistent with the signal voltage of the external input in order to work properly; otherwise, it will cause a malfunction. Figure 3 The CPLD in this system is divided into nine partitions: partition 1, partition 2, partition 3, partition 9, partition 7, partition 4, partition 8, partition 6, and partition 5. For example, the voltage of partition 1 is 3.3V, the voltage of partition 9 is 1.0V, and partition 7 is connected to an external power supply via a printed circuit board to power the CPLD. The number of partitions varies between different CPLD models. Figure 3 The “AB” in the upper left corner is the combined label of the front and back of the CPLD; the “A” in the upper right corner is the horizontal coordinate reference, used to locate the horizontal position of the array; “I” is the vertical scale reference; the gray dot represents the reference origin, used to define the orientation of the entire array; the “2I” in the lower right corner represents double the vertical scale value, that is, the total length of the array in the vertical direction is 2 I units, used to specify the physical size of the array or the vertical span of the logical area.

[0040] S202: Obtain at least one pin and pin information of the programmable controller.

[0041] Optionally, at least one pin and pin information of the programmable controller can be read using a scripting language, and the pin information can be stored in a two-dimensional pin array.

[0042] Optionally, the pin two-dimensional array includes pin information for at least one pin.

[0043] Optionally, the pin information comprises a pin name, an attribute string of the pin, and an original network signal name.

[0044] S203: According to the pin information, the matching processing is performed with the partition information, so as to obtain the partition corresponding to the pin.

[0045] Optionally, the pin information comprises an attribute string of the pin.

[0046] Correspondingly, the step S202 comprises: parsing the attribute string to obtain the partition identifier of the pin; and performing the matching processing with the partition information according to the partition identifier, so as to obtain the partition corresponding to the pin.

[0047] Optionally, the step S202 comprises Sa~Sf:

[0048] Sa: reading the pin information of any pin from the pin two-dimensional array.

[0049] Sb: parsing the attribute string in the pin information to obtain the partition identifier of the pin.

[0050] Sc: creating the partition two-dimensional array corresponding to the pin by taking the partition identifier as the partition identification, and saving the pin information of any pin to the partition two-dimensional array.

[0051] Sd: removing the pin information of any pin from the pin two-dimensional array.

[0052] Se: traversing the pin information of the remaining pins of the pin two-dimensional array, and performing the following steps for the traversed pin information: parsing the attribute string in the pin information to obtain the partition identifier of the pin; judging whether the partition identifier of the pin is same as the partition identification; if the partition identifier of the pin is same as the partition identification, adding the pin information to the partition two-dimensional array, removing the pin information from the pin two-dimensional array, and parsing the next pin information; if the partition identifier of the pin is not same as the partition identification, parsing the next pin information.

[0053] Sf: after the traversal, repeatedly performing the steps Sa~Se until the pin two-dimensional array is empty.

[0054] Through the attribute string of the pin, the partition identifier used for positioning the partition can be accurately and quickly extracted, and the accurate and efficient partition of the pin is realized.

[0055] Optionally, the partition information comprises a partition voltage and / or a function identification, and the pin information comprises a voltage attribute and / or a function attribute.

[0056] Correspondingly, the step S202 comprises: extracting the voltage attribute and / or the function attribute of the pin from the pin information; and matching the voltage attribute and / or the function attribute with the partition voltage and / or the function identification to determine the partition corresponding to the pin.

[0057] By defining and matching the voltage and function attributes of the partition and the pin, the automation and precision of the pin distribution are realized.

[0058] Optionally, before the step S203, the method further comprises: obtaining a signal attribute of the pin; and performing a screening process on the pin according to the signal attribute and a preset signal screening keyword to remove the pin corresponding to an invalid signal in the establishment process of the pin interconnection relationship; wherein the invalid signal comprises at least one of a power signal, a ground signal and a fixed function signal; and the fixed function signal comprises a serial data line signal and / or a serial clock line signal.

[0059] Optionally, the obtaining of the signal attribute of the pin comprises: parsing the pin information of the pin to obtain an original network signal name; and parsing the original network signal name to obtain the signal attribute.

[0060] Optionally, the preset signal screening keyword can be the invalid signal.

[0061] By automatically identifying and removing the pin corresponding to the invalid signal through the preset signal screening keyword, the pin that cannot participate in the arrangement can be removed, and the pin arrangement efficiency is improved.

[0062] S204: obtaining at least one trace of the programmable control device and a signal feature of the trace.

[0063] Optionally, the at least one trace of the programmable control device and the signal feature of the trace are read through a script language, and the signal feature is stored in a trace two-dimensional array.

[0064] Optionally, the trace two-dimensional array comprises at least one signal feature.

[0065] Optionally, the signal feature comprises a trace endpoint coordinate and a trace signal name.

[0066] It should be noted that, Figure 4 a schematic diagram of a trace placement position provided by an embodiment of the present application, as shown in Figure 4 the trace layout is in the edge region of the programmable control device; the signal feature of the trace is automatically captured based on the characteristics of the edge of the programmable control device through the script language, and the signal feature is stored in the trace two-dimensional array.

[0067] S205: determining a partition corresponding to the trace according to the partition corresponding to the pin and the signal feature.

[0068] Optionally, according to the signal feature, the original network signal name of the pin is matched to determine the pin corresponding to the trace; and according to the pin corresponding to the trace and the partition corresponding to the pin, the partition corresponding to the trace is determined.

[0069] Optionally, according to the signal feature, the original network signal name of the pin is matched to determine the pin corresponding to the trace, including: obtaining the trace signal name of the signal feature; and according to the trace signal name and the original network signal name of the pin, the pin corresponding to the trace is determined.

[0070] Optionally, according to the pin corresponding to the trace and the partition corresponding to the pin, the partition corresponding to the trace is determined, including: according to the partition two-dimensional array corresponding to the pin corresponding to the trace, a partition two-dimensional array corresponding to the trace is created; and the partition two-dimensional array corresponding to the pin and the partition two-dimensional array corresponding to the trace are one-to-one corresponding.

[0071] Through matching the original network signal of the pin and the signal feature, automatic and accurate partition of the trace is realized, and the pin arrangement efficiency is improved.

[0072] S206: According to the pin corresponding to the partition and the partition corresponding to the trace, the pin interconnection relationship of the partition is generated.

[0073] Optionally, in step S206, the via information of the programmable control device is obtained; the trace space matrix is generated according to the via information; the occupation state identifier of the trace space is added in the trace space matrix; the interconnection path between the pins in the partition is determined according to the pin corresponding to the partition and the partition corresponding to the trace, with the trace space matrix as a constraint; and the pin interconnection relationship of the partition is determined according to the interconnection path.

[0074] Optionally, the via information of the programmable control device is obtained by reading at least one via information of the programmable control device through a script language, and storing the via information into a via two-dimensional array.

[0075] Optionally, the via information includes a via serial number, a via signal name, and a via coordinate.

[0076] Optionally, the occupation state identifier includes an occupied identifier and an unoccupied identifier.

[0077] Optionally, according to the via information, the trace space matrix is generated, including: according to the via information, a plurality of via coordinates of the programmable control device are determined; a sub-space unit corresponding to the via coordinate is determined with the via coordinate as the center; the sub-space unit is a rectangular trace space and / or a triangular trace space obliquely surrounding the via coordinate; the occupation state identifier is added to the sub-space unit; and the trace space matrix is generated according to the sub-space unit.

[0078] Through the occupation state identifier and the setting of the space unit, the wiring efficiency and the wiring quality can be improved, the winding can be reduced, and the signal integrity can be improved.

[0079] Optionally, the sub-space unit corresponding to the via hole coordinate is determined by taking the via hole coordinate as the center, including: taking the via hole coordinate as the starting point, offsetting a first range downward, and a region with a first width as a first sub-space; taking the via hole coordinate as the starting point, offsetting a second range to the right, and a region with a second width as a second sub-space; taking the via hole coordinate as the starting point, offsetting a third range downward and to the right, a fourth range downward, and a fifth range to the right, and a lower triangular region as a third sub-space; taking the via hole coordinate as the starting point, offsetting a sixth range downward and to the right, a seventh range downward, and an eighth range to the right, and an upper triangular region as a fourth sub-space; and determining the first sub-space, the second sub-space, the third sub-space, and the fourth sub-space as the sub-space unit corresponding to the via hole coordinate. Figure 5 A schematic diagram of a sub-space unit corresponding to a via hole coordinate is provided for the embodiments of the present application. Figure 5 As shown, taking the sub-space unit corresponding to the first via hole 501 as an example.

[0080] Optionally, the routing space matrix is generated according to the sub-space unit, including: adding the occupation state identifier of the sub-space unit to the via hole two-dimensional array to obtain a two-dimensional array of the routing space matrix.

[0081] Optionally, the sub-space unit corresponding to the via hole coordinate is determined by taking the via hole coordinate as the starting point, offsetting a first range downward by 0.25 mm to 0.75 mm, and a region with a width of 0.5 mm as a first sub-space; taking the via hole coordinate as the starting point, offsetting a second range to the right by 0.25 mm to 0.75 mm, and a region with a width of 0.5 mm as a second sub-space; taking the via hole coordinate as the starting point, offsetting a third range downward and to the right by 0.25 mm to 1.2 mm, a fourth range downward by 0.25 mm to 0.75 mm, and a fifth range to the right by 0.25 mm to 0.75 mm, and a lower triangular region as a third sub-space; taking the via hole coordinate as the starting point, offsetting a sixth range downward and to the right by 0.25 mm to 1.2 mm, a seventh range downward by 0.25 mm to 0.75 mm, and an eighth range to the right by 0.25 mm to 0.75 mm, and an upper triangular region as a fourth sub-space. The first sub-space, the second sub-space, the third sub-space, and the fourth sub-space can each be routed with one wire. When no wire passes through these spaces, the value of the occupation state identifier is 0, indicating that the identifier is not occupied. When a wire passes through these spaces, the value of the occupation state identifier is 1, indicating that the identifier is occupied.

[0082] By discretizing and digitizing the continuous and physical routing space into a routing space matrix that can be processed by a computer algorithm, and by using the matrix as a constraint condition, the optimal interconnection path is automatically and intelligently planned, thereby generating a new pin interconnection relationship with less or no intersection. The efficiency of pin arrangement can be improved, and the accuracy of the interconnection relationship can be improved.

[0083] Optionally, according to the partition corresponding to the pin and the partition corresponding to the trace, the interconnection path between the pins in the partition is determined under the constraint of the trace space matrix, comprising: according to the partition corresponding to the pin and the partition corresponding to the trace, the end point of the trace and at least one target pin of the trace are determined; if the target pin corresponding to the trace is one, the interconnection path of the trace is determined according to the end point and the target pin under the constraint of the trace space matrix; if the target pin corresponding to the trace is multiple, the distance value from the end point to the multiple target pins is calculated; according to the distance value, the priority order of path search is determined; according to the priority order, the interconnection path of the trace is determined in the trace space matrix.

[0084] Optionally, the distance value from the end point to the multiple target pins can be the Euclidean distance from the end point to the multiple target pins.

[0085] Optionally, according to the distance value, the priority order of path search is determined, comprising: according to the distance value, the distance sequence is sorted from small to large; according to the order of the distance sequence, the path search sequence with high to low priority is determined.

[0086] By simplifying the problem to finding an interconnection path under the constraint of the matrix when there is only one target pin, and determining the interconnection path based on the priority order of the distance value when there are multiple targets, the search efficiency can be effectively improved, and the more likely connection is preferentially tried, so that the globally better routing scheme can be found faster in the complex space matrix.

[0087] Optionally, according to the partition corresponding to the pin and the partition corresponding to the trace, the end point of the trace and at least one target pin of the trace are determined, comprising: according to the one-to-one correspondence between the partition corresponding to the pin and the partition corresponding to the trace, the partition to which the pin corresponding to the trace belongs is determined; the pin in the partition is determined as the target pin.

[0088] Optionally, according to the partition corresponding to the pin and the partition corresponding to the trace, the interconnection path between the pins in the partition is determined under the constraint of the trace space matrix, comprising: according to the trace space matrix, the traceable space is determined; according to the via information, the via coordinates are determined; according to the via coordinates and the traceable space, the graph structure is constructed; according to the graph structure, the interconnection path between the pins in the partition is determined by using a preset dynamic programming algorithm.

[0089] Optionally, according to the via coordinates and the traceable space, the graph structure is constructed, comprising: determining the traceable space and the via coordinates as nodes of the graph; for any two nodes, if there is a routable path between them, a connection edge is generated between the two nodes; the weight value of the connection edge is calculated, wherein the weight value is the weighted sum of the path length and the trace intersection probability, wherein the path length is the actual routable distance between the two nodes, and the trace intersection probability is the possibility of intersection between the path and the existing trace; according to the nodes and the connection edges, the graph structure is constructed.

[0090] Optionally, the actual routable distance between the two nodes can be the Manhattan distance or the geometric straight line distance between the two nodes, etc.

[0091] Optionally, according to the graph structure, the interconnection path between the pins in the partition is determined by using a preset dynamic programming algorithm, including: searching the weight values of the connection edges of the graph structure by using the preset dynamic programming algorithm, and selecting the path with the minimum weight value of the connection edges as the interconnection path between the pins in the partition.

[0092] By constructing the graph structure, the optimization path selection in the global perspective is realized, the crossing and redundant paths are significantly reduced, and the pin arrangement efficiency is improved. In addition, the weight value design of the connection edge takes into account the path length and the crossing risk, so that the wiring result balances between efficiency and reliability, and further improves the efficiency and human implementability of the pin arrangement.

[0093] Optionally, in an embodiment of the present application, after the wiring space matrix is generated according to the via information, the process of generating the cross space matrix of the programmable control device is further included, which is described in detail as follows: obtaining the center coordinates of the programmable control device; extending a first length to the right, a second length to the left, a third length upward, and a fourth length downward from the center coordinates as the starting point to form a first rectangle; generating a second rectangle by translating the four vertex coordinates of the first rectangle upward by a fifth length; generating a third rectangle by translating the four vertex coordinates of the first rectangle upward by a sixth length; generating a fourth rectangle by translating the four vertex coordinates of the first rectangle downward by the fifth length; generating a fifth rectangle by translating the four vertex coordinates of the first rectangle downward by the sixth length; the cross space of the programmable control device is divided into multiple rectangular spaces according to the rectangular translation method, the rectangular spaces are added with occupancy state identifiers and stored in the cross two-dimensional matrix; when there is wiring occupancy in the rectangular space, the occupancy state identifier is set to 1, and when there is no wiring occupancy, the occupancy state identifier is set to 0; the rectangular space is added to the wiring space matrix.

[0094] Figure 6 A schematic diagram of the matrix of the programmable control device is provided for the embodiment of the present application, as shown in Figure 6 The wiring space matrix is obtained by matrixing the programmable control device, and the wiring space matrix includes the via surrounding generated sub-space unit and the rectangular space of the cross space.

[0095] By discretizing and digitizing the continuous and physical wiring space into a wiring space matrix that can be processed by computer algorithm, the efficiency of pin arrangement can be improved, and the accuracy of interconnection relationship can be improved.

[0096] The pin arrangement method provided by the embodiment of the application automatically acquires pin information and partition information, and can realize automatic determination of pins and partitions through matching of the information, further determine the partitions corresponding to the pins, and further realize determination of pin interconnection relationship in combination with signal characteristics of the traces, thereby realizing efficient pin and trace arrangement.

[0097] In one embodiment of the application, on the basis of the above embodiment, the interconnection path between the pins in the partition is determined according to the partition corresponding to the pins and the partition corresponding to the traces, with the trace space matrix as a constraint in step S206, and an exemplary implementation process is further provided, which is described in detail as follows.

[0098] Figure 7 The schematic diagram for determining the first stage of the interconnection path provided by the embodiment of the application is referred to Figure 7 , the end point coordinates of the trace 703 are determined; two target pins are determined according to the partition corresponding to the pins and the partition corresponding to the trace 703, which are the first target pin 701 and the second target pin 702 respectively; the distances from the end point coordinates of the trace 703 to the first target pin 701 and the second target pin 702 are calculated to obtain a first distance and a second distance; the first distance and the second distance are compared, and it is determined that the first distance is smaller than the second distance, and then the first target pin 701 is determined as the final target pin; the distances from the end point coordinates of the trace 703 to the first via 501, the second via 502 and the third via 503 are calculated to obtain a first via distance, a second via distance and a third via distance; the sub-space unit of the first via 501 corresponding to the smallest first via distance is selected as the trace path.

[0099] Figure 8 The schematic diagram for determining the second stage of the interconnection path provided by the embodiment of the application is referred to Figure 8 It should be noted that the values of the occupation state identifiers of the sub-space units of the vias in the figure are all 0, and all the sub-spaces can be passed through, and the first sub-space of the first via 501 closest to the end point coordinates of the trace 703 is passed through.

[0100] Figure 9 The schematic diagram for determining the third stage of the interconnection path provided by the embodiment of the application is referred to Figure 9 After passing through the first sub-space of the first via 501, only the third sub-space of the first via 501 can be passed through; after passing through the third sub-space of the first via 501, there are two paths, which are the fourth sub-space of the first via 501 and the second sub-space of the second via 502. The distances from the fourth sub-space of the first via 501 and the second sub-space of the second via 502 to the first target pin 701 are determined, and the second sub-space of the second via 502 closer to the first target pin 701 is selected.

[0101] Figure 10A schematic diagram of the fourth stage of determining the interconnection path is provided for the embodiment of the present application, refer to Figure 10 After passing through the second subspace of the second via hole 502, only the fourth subspace of the second via hole 502 can be passed through; after passing through the fourth subspace of the second via hole 502, there are two paths, which are the first subspace of the fifth via hole 504 and the third subspace of the second via hole 502 respectively; the distances from the first subspace of the fifth via hole 504 and the third subspace of the second via hole 502 to the first target pin 701 are determined, and the first subspace of the fifth via hole 504 closer to the first target pin 701 is selected.

[0102] Figure 11 A schematic diagram of the fifth stage of determining the interconnection path is provided for the embodiment of the present application, refer to Figure 11 After passing through the first subspace of the fifth via hole 504, the spaces that can be passed through include the third subspace of the fifth via hole 504; the distance from the endpoint coordinate of the current trace 703 to the first target pin 701 is calculated; if the distance is less than or equal to the distance from the third subspace of the fifth via hole 504 to the first target pin 701, the trace 703 is connected to the first target pin 701, so as to complete the interconnection path of the first target pin 701.

[0103] In an embodiment of the present application, on the basis of the above-mentioned embodiment, after the step S206, the process of updating the trace connection in the layout design is further included, which is described in detail as follows:

[0104] According to the pin interconnection relationship, a pin interconnection relationship table of the programmable control device is determined; wherein, the table header of the pin interconnection relationship table includes the pin name, the original signal name and the adjusted signal name; according to the pin interconnection relationship table, the trace connection in the layout design of the programmable control device is updated.

[0105] Optionally, the table header of the pin interconnection relationship table further includes the schematic diagram version to be modified or the time.

[0106] The pin arrangement method provided by the embodiment of the present application automatically updates the trace connection in the layout design according to the pin interconnection relationship table, without manual modification, and further improves the pin arrangement efficiency.

[0107] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above-mentioned embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0108] Figure 12 A structural schematic diagram of the pin arrangement device provided by the embodiment of the present application is shown in FIG. 1. Figure 12As shown, the embodiment of the present application further provides a pin arrangement device, comprising: a first obtaining module 1201, a second obtaining module 1202, a matching module 1203, a third obtaining module 1204, a determining module 1205 and a generating module 1206.

[0109] The first obtaining module 1201 is configured to obtain a plurality of partitions of a programmable control device and partition information of the partitions.

[0110] The second obtaining module 1202 is further configured to obtain at least one pin of the programmable control device and pin information of the pin.

[0111] The matching module 1203 is configured to perform matching processing on the pin information and the partition information to obtain a partition corresponding to the pin according to the pin information.

[0112] The third obtaining module 1204 is further configured to obtain at least one trace of the programmable control device and signal characteristics of the trace.

[0113] The determining module 1205 is configured to determine a partition corresponding to the trace according to the partition corresponding to the pin and the signal characteristics.

[0114] The generating module 1206 is configured to generate a pin interconnection relationship of the partition according to the partition corresponding to the pin and the partition corresponding to the trace.

[0115] In a possible implementation, the pin information comprises an attribute string of the pin; accordingly, the matching module 1203 is specifically configured to: parse the attribute string to obtain a partition identifier of the pin; and perform matching processing on the partition information according to the partition identifier to obtain the partition corresponding to the pin.

[0116] In a possible implementation, the partition information comprises a partition voltage and / or a function identifier, and the pin information comprises a voltage attribute and / or a function attribute; accordingly, the matching module 1203 is specifically configured to: extract the voltage attribute and / or the function attribute of the pin from the pin information; and perform matching processing on the partition voltage and / or the function identifier according to the voltage attribute and / or the function attribute to determine the partition corresponding to the pin.

[0117] In a possible implementation, the generating module 1206 is specifically configured to: obtain via information of the programmable control device; generate a trace space matrix according to the via information; wherein an occupation state identifier of a trace space is added in the trace space matrix; determine an interconnection path between pins in the partition according to the partition corresponding to the pin and the partition corresponding to the trace, with the trace space matrix as a constraint; and determine the pin interconnection relationship of the partition according to the interconnection path.

[0118] In a possible implementation, the generating module 1206 is specifically configured to: determine an end point of the trace and at least one target pin of the trace according to the partition corresponding to the pin and the partition corresponding to the trace when determining the interconnection path between the pins in the partition according to the partition corresponding to the pin and the partition corresponding to the trace under the constraint of the trace space matrix; determine the interconnection path of the trace according to the end point and the target pin of the trace under the constraint of the trace space matrix if the target pin corresponding to the trace is one; calculate distance values from the end point to the multiple target pins if the target pin corresponding to the trace is multiple; determine a priority order of path searching according to the distance values; and determine the interconnection path of the trace in the trace space matrix according to the priority order.

[0119] In a possible implementation, the generating module 1206 is specifically configured to: determine multiple via coordinates of the programmable controller device according to the via information when generating the trace space matrix according to the via information; and determine a sub-space unit corresponding to the via coordinates with the via coordinates as the center, where the sub-space unit is a rectangular trace space and / or a triangular trace space that is inclined to the via coordinates; add an occupancy state identifier to the sub-space unit; and generate the trace space matrix according to the sub-space unit.

[0120] In a possible implementation, the pin information includes an original network signal name; and correspondingly, the determining module 1205 is specifically configured to: perform matching processing on the original network signal name of the pin according to the signal characteristics, to determine the pin corresponding to the trace; and determine the partition corresponding to the trace according to the pin corresponding to the trace and the partition corresponding to the pin.

[0121] In a possible implementation, the pin arrangement device further includes:

[0122] The screening module is configured to: acquire a signal attribute of the pin; and perform screening processing on the pin according to the signal attribute and a preset signal screening keyword, to eliminate the pin corresponding to an invalid signal in the establishment process of the pin interconnection relationship, where the invalid signal includes at least one of a power signal, a ground signal, and a fixed function signal, and the fixed function signal includes a serial data line signal and / or a serial clock line signal.

[0123] In a possible implementation, the pin arrangement device further includes:

[0124] The updating module is configured to: determine a pin interconnection relationship table of the programmable controller device according to the pin interconnection relationship, where a table header of the pin interconnection relationship table includes a pin name, an original signal name, and an adjusted signal name; and update trace connection in a layout design of the programmable controller device according to the pin interconnection relationship table.

[0125] The description of the features in the embodiments of the pin arrangement device can refer to the related description of the embodiments of the pin arrangement method, which will not be repeated here.

[0126] Figure 13 The structural schematic diagram of an electronic device is provided in the present application. As shown in the figure, the electronic device provided in the present embodiment comprises at least one processor 1301 and a memory 1302. Optionally, the electronic device further comprises a communication component 1303. The processor 1301, the memory 1302 and the communication component 1303 are connected through a bus 1304. Figure 13

[0127] In the specific implementation process, the at least one processor 1301 executes the computer execution instructions stored in the memory 1302, so that the at least one processor 1301 executes the pin arrangement method embodiments described above.

[0128] The specific implementation process of the processor 1301 can refer to the method embodiments described above, which has similar implementation principles and technical effects, and will not be repeated here.

[0129] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC) and the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the application can be directly embodied as the execution of the hardware processor, or the execution of the combination of the hardware and software modules in the processor.

[0130] The memory can contain a random access memory (RAM), and can also include a non-volatile memory (NVM), for example, at least one disk memory.

[0131] ​The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0132] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above pin arrangement method embodiments when running.

[0133] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0134] Embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the above pin arrangement method embodiments.

[0135] Embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above pin arrangement method embodiments.

[0136] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0137] The above describes in detail the pin arrangement method provided by the present application. The principles and implementation manners of the present application are described by using specific examples, and the above description of the examples is only used to help understand the method of the present application and the core idea thereof. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A pin arrangement method, characterized in that, include: Obtain multiple partitions of the programmable controller and partition information of the partitions; Obtain at least one pin of the programmable controller and the pin information of the pin; Based on the pin information, a matching process is performed with the partition information to obtain the partition corresponding to the pin; Acquire at least one trace of the programmable controller and the signal characteristics of the trace; The partition corresponding to the trace is determined based on the partition corresponding to the pin and the signal characteristics; Read at least one via information of a programmable controller using a scripting language and store the via information in a two-dimensional array of vias; Based on the via information, determine the coordinates of multiple vias of the programmable controller; Centered on the via coordinates, determine the subspace cell corresponding to the via coordinates; wherein, the subspace cell is a rectangular routing space and / or an oblique triangular routing space surrounding the via coordinates; add an occupancy status flag to the subspace cell; generate a routing space matrix based on the subspace cell; when there is a routing occupied in the rectangular space, the occupancy status flag is set to 1, and when there is no routing occupied, the occupancy status flag is set to 0; add the rectangular space to the routing space matrix; Using the routing space matrix as a constraint, based on the partitions corresponding to the pins and the partitions corresponding to the routing, a preset dynamic programming algorithm is used to search for the path with the minimum weight of the connecting edge in the graph structure to determine the interconnection path between the pins in the partition; Based on the interconnection path, determine the pin interconnection relationship of the partition.

2. The method according to claim 1, characterized in that, The pin information includes the attribute string of the pin; Accordingly, the step of matching the pin information with the partition information to obtain the partition corresponding to the pin includes: Parse the attribute string to obtain the partition identifier of the pin; The partition identifier is matched with the partition information to obtain the partition corresponding to the pin.

3. The method according to claim 1, characterized in that, The partition information includes partition voltage and / or function identifier, and the pin information includes voltage attributes and / or function attributes; Accordingly, the step of matching the pin information with the partition information to obtain the partition corresponding to the pin includes: Extract the voltage attributes and / or functional attributes of the pins from the pin information; The voltage and / or functional attributes are matched with the partition voltage and / or functional identifier to determine the partition corresponding to the pin.

4. The method according to claim 1, characterized in that, The step of determining the interconnection path between pins in a partition based on the partition corresponding to the pin and the partition corresponding to the trace, using the trace space matrix as a constraint, includes: Based on the partition corresponding to the pin and the partition corresponding to the trace, determine the endpoint of the trace and at least one target pin of the trace; If the target pin corresponding to the trace is one, then the interconnection path of the trace is determined based on the endpoint and the target pin, using the trace space matrix as a constraint. If there are multiple target pins corresponding to the trace, then calculate the distance from the endpoint to the multiple target pins; Based on the distance values, determine the priority order of path searches; Based on the priority order, the interconnection path of the trace is determined in the trace space matrix.

5. The method according to any one of claims 1 to 3, characterized in that, The pin information includes the original network signal name; Accordingly, determining the partition corresponding to the trace based on the partition corresponding to the pin and the signal characteristics includes: Based on the signal characteristics, a matching process is performed with the original network signal name of the pin to determine the pin corresponding to the trace; The partition corresponding to the trace is determined based on the pin corresponding to the trace and the partition corresponding to the pin.

6. The method according to any one of claims 1 to 3, characterized in that, Before performing the matching process between the pin information and the partition information to obtain the partition corresponding to the pin, the method further includes: Obtain the signal attributes of the pin; Based on the signal attributes and preset signal filtering keywords, the pins are filtered to remove pins corresponding to invalid signals during the establishment of the pin interconnection relationship; wherein, the invalid signals include at least one of power signals, ground signals and fixed function signals; the fixed function signals include serial data line signals and / or serial clock line signals.

7. The method according to any one of claims 1 to 3, characterized in that, After generating the pin interconnection relationship of the partitions based on the partitions corresponding to the pins and the partitions corresponding to the traces, the method further includes: Based on the pin interconnection relationships, a pin interconnection table for the programmable controller is determined; wherein, the header of the pin interconnection table includes the pin name, the original signal name, and the adjusted signal name; Update the routing connections in the layout design of the programmable controller based on the pin interconnection table.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the pin arrangement method as described in any one of claims 1 to 7 when executing the computer program.

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