Domestic autonomous controllable hybrid integrated circuit process design method based on product-level PDK modeling simulation

Abstract

The invention relates to a domestic autonomous controllable hybrid integrated circuit process design method based on product-level PDK modeling simulation. The method comprises the steps that process parameters of a hybrid integrated circuit product are designed, physical parameters of the hybrid integrated circuit product are extracted, a hybrid integrated circuit process design rule is established, and a PDK model framework is constructed. Using the neural network model to complete development of PDK components, and determining parameters of each component of the PDK model; designing a schematic diagram and a layout of the hybrid integrated circuit, importing the schematic diagram and the layout into a PDK model framework, and perfecting parameters of a PDK model; a complete hybrid integrated circuit product PDK model is built by using a domestic EDA tool, the model is in butt joint with the domestic EDA tool, and co-simulation and feedback optimization are performed on the PDK model. Through the PDK modeling simulation design, the problems that the process design period of hybrid integrated circuit products is long and the process design cannot fully meet the processing requirements are solved, the product design efficiency in the field is improved, and meanwhile, the electrical characteristics and the process reliability of the products are improved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of hybrid integrated circuit product process design, and particularly relates to a domestic self-controllable hybrid integrated circuit process design method based on product-level PDK modeling simulation. BACKGROUND

[0002] With the development of hybrid integrated circuits towards miniaturization and high-density integration, the complexity of the superimposed equipment load system is improved, the functions are diversified, and the performance requirements are improved, the circuit complexity and signal rate are significantly increased, thereby causing a series of design problems such as signal integrity (SI), crosstalk, power integrity (PI), electromagnetic compatibility (EMC), etc. Among them, the bandwidth, time delay and link crosstalk of the interconnection and packaging structure seriously limit the overall speed of the system, and the mixed complex high-speed, high-density, low-voltage and large-current requirements also pose a severe challenge to the power integrity (PI) research of the system-level and board-level power distribution. At the same time, with the decrease of chip operating voltage and the increase of operating speed, the stability of the power supply system in the entire working frequency band is required to be higher, and the increase of the main frequency will also lead to problems such as ringing, crosstalk, jitter, phase error and the like in signal quality, which directly affect the system reliability, signal-to-noise ratio and bit error rate and EMI / EMC indicators.

[0003] The traditional hybrid integrated circuit design method lacks standardized integration of process parameters and device models, and it is difficult to match the simulation needs of EDA (electronic design automation) tools, the success rate of one-time design is low, and the international similar design tools have self-controllable risks, which cannot meet the application needs of domestic high-end fields such as civil and aerospace, aviation, weapon equipment and the like. With the rapid development of IC process improvement and artificial intelligence (AI), high-performance computing, high-speed network and 5G communication technology, the DC / DC converter design and simulation verification tools of analog, radio frequency and mixed signal circuits are increasingly critical. The powerful storage capacity, fast processing speed and interactive interface graphics capability of computers have become a good way to realize the automation of complex engineering design or production tasks, shorten the product development cycle and reduce production costs. In order to meet the requirements of survival and development in international competition, modern industrial enterprises must continuously develop new products with high quality, low cost and fast market.

[0004] Therefore, a domestic self-controllable hybrid integrated circuit process design method based on product-level PDK modeling simulation is urgently needed to solve the problems of design and manufacturing disconnection, low simulation confidence and insufficient self-controllability, and meet the industry development needs. SUMMARY

[0005] The purpose of the present application is to provide a domestic self-controllable hybrid integrated circuit process design method based on product-level PDK modeling simulation, which can solve the problem of product design defects caused by insufficient experience of existing process designers in the design process, improve design efficiency and accuracy, shorten the research and development cycle, and realize seamless connection between customers and processing plants; The product designed by the method has process feasibility, fully meets the needs of hybrid integrated circuit product process design, and all method elements are domestic, realizing full self-controllable. In order to achieve the above purpose, the following technical scheme is adopted: A domestic self-controllable hybrid integrated circuit process design method based on product-level PDK modeling simulation, the method comprising the following steps: S1, design the process parameters of the hybrid integrated circuit product, extract the physical parameters of the hybrid integrated circuit product, establish the hybrid integrated circuit process design rule, and based on the process parameters, physical parameters and process design rule, construct a PDK model framework; S2, develop PDK components in the hybrid integrated circuit product using a neural network model, and determine the parameters of each component of the PDK model; S3, based on the parameters of each component of the PDK model, design the schematic diagram and layout of the hybrid integrated circuit product and import them into the PDK model framework to perfect the parameters of the PDK model; S4, based on the PDK model framework, schematic diagram, layout and parameters of the PDK model, use domestic EDA tools to build a complete hybrid integrated circuit product PDK model, interface the built PDK model with domestic EDA tools, and perform collaborative simulation and feedback optimization on the PDK model.

[0006] Further, the framework of the hybrid integrated circuit product PDK model comprises a hybrid integrated circuit substrate model, a component model, a circuit model and a process material model.

[0007] Further, the hybrid integrated circuit substrate model is used to provide mounting space and structural support for the component model and the circuit model, and to provide physical installation reference and electrical connection basis for the component model; The hybrid integrated circuit substrate model is a multilayer wiring structure made of aluminum oxide ceramic material, with a thickness of 0.6mm or 0.1mm.

[0008] Further, the component model is a functional component mounted on the hybrid integrated circuit substrate model, and the component model and the hybrid integrated circuit substrate model form physical fixation and electrical conduction through the process material model; The component model comprises a patch resistor and capacitor model, a domestic chip model and a film patch resistor model, and the component model adopts a component SPCIE model.

[0009] Further, the circuit model is used to build a transmission path, form a complete signal link and power link, and realize electrical connection between different component models; the circuit model comprises a circuit interconnection model, a gold conductor model, a dielectric model, and a pad model; the gold conductor model adopts pure gold material, the pure gold has a gold content of 99.99%, and a thickness of 7-18 um; the pad model adopts platinum-silver material, and has a thickness of 15-30 um.

[0010] Further, the process material model comprises a bonding process model, a welding process model, and an adhesive process model; the bonding process model adopts a pure gold bonding wire with a diameter of 25 um; the welding process model adopts Sn62Pb36Ag2 soldering paste and a 0.1 mm soldering sheet; and the adhesive process model adopts epoxy resin conductive adhesive.

[0011] Further, the step S2 specifically comprises the following steps: S21, constructing a neural network model and a training data set; S22, training the neural network model based on the training data set; S23, determining the parameters of the PDK model of the hybrid integrated circuit product by using the trained neural network model.

[0012] Further, the PDK component in the hybrid integrated circuit product is a passive device model, which is built based on a passive device optimization platform iModeler developed by using a neural network algorithm, and contains a T-coil layout structure. After calling the T-coil template in the iModeler software, the designer can perform various physical size parameterization scanning, and then perform device multi-index optimization by using EM formulas of four parameters. After a large number of discrete S parameter results are input, the best size of the passive device model is established by using a machine learning training algorithm on the basis of a rule base and electrical characteristic parameters, and the selection of the passive device on the surface of the substrate and the recommendation of the printed size of the film resistor are further completed.

[0013] The neural network model comprises three layers of an input layer, a hidden layer, and an output layer, wherein the input layer is basic data of the hybrid integrated circuit product; the hidden layer is set to three layers, and the number of neurons in each layer is 64, 32, and 16, respectively; and the output layer is key parameters of each component of the PDK model.

[0014] Further, the step S4 specifically comprises the following steps: S41, integrating the hybrid integrated circuit substrate model, the circuit model, the component model, and the process material model to build a PDK model of a hybrid integrated circuit product; S43, optimizing the layout by using a domestic EDA tool based on the simulation result.

[0015] Further, the step S41 specifically comprises the following steps: S411, integration of the substrate model and the circuit model: binding the circuit layout and the substrate model through the interlayer alignment function of Chip and Hermes; S412, binding of the component model, the substrate model and the circuit model: through the device positioning function of Chip and Hermes, the calibrated component model is accurately positioned to the substrate surface pad area; S413, selection of process material model: at the junction of the component and the substrate / circuit, add a process material model through the domestic process modeling plug-in Chip and Hermes.

[0016] S42, using the domestic multi-physics simulation tool Chip and the Notus simulation module, simulate the mixed integrated circuit product PDK model built in order of electrical performance, thermal performance and electromagnetic compatibility, and the simulation parameters cover the actual application scenarios of the product.

[0017] Compared with the prior art, the application has the following advantages: (1) The PDK modeling simulation design of the application solves the problem of long process design cycle of mixed integrated circuit products and the problem that process design cannot fully meet the processing requirements, not only improves the product design efficiency in this field, but also improves the electrical characteristics of such products and the process reliability of such products. The model and simulation design described in the application are implemented by a domestic self-controllable method, which can be applied not only to civilian products, but also to high-end fields such as aerospace, aviation and weapon equipment, and has high market benefits.

[0018] (2) The application summarizes experience from the design of more than 100 mixed integrated circuit products, establishes a highly matched component SPCIE model library according to the internal structural characteristics of mixed integrated circuit products, and builds a precise product model, effectively solving the problem of lack of component model in mixed integrated circuit products and the problem that product model cannot be used for simulation. The application improves the electrical performance of mixed integrated circuit products, can adapt to the trend of high power and miniaturization of mixed integrated circuits, and meets market demand. The design method described in the application can be applied in the field of intelligent manufacturing, reduces manual intervention in the design process, shortens the design cycle, avoids design defects, meets the current trend of intelligent and digital manufacturing, can realize mass design process application, and has the characteristics of independent controllable industrialization.

[0019] (3) At present, there is no complete set of self-controllable domestic process design method in the field of hybrid integrated circuit design in China, and most of them rely on foreign typical design tools to complete process layout production, and simple manual calculation and process experience to complete process layout design. In order to solve the problems in the prior art, the application provides a domestic self-controllable hybrid integrated circuit process design method. In the process of the process design method, process optimization is completed based on PDK model simulation. This means has no application example in the design process of multi-layer wiring hybrid integrated circuit product. At present, only through DRC detection, combined with process design specification, some places violating the process design rules are checked out, but simulation optimization feedback based on PDK model is not completed. The PDK model involved in the application is not a simple board-level model establishment and simulation, but a product-level model construction and simulation. At present, there is no precedent in China. Product-level hybrid integrated circuit simulation includes all active and passive device models, process material parameters, manufacturing process information and electrical interconnection models, which can realize real scene application simulation, realize electrical and thermal analysis, power analysis, ripple noise analysis and pressure drop analysis, not the traditional simple board-level analysis. BRIEF DESCRIPTION OF DRAWINGS Figure 1 It is a method flow chart of the design method in the application Figure 2 It is a PDK model schematic diagram of a hybrid integrated circuit product in the application; Figure 3 It is a PDK model schematic diagram of a hybrid integrated circuit product substrate in the application; Figure 4 It is a L parameter simulation result diagram of a hybrid integrated circuit product designed by the method of the application; Figure 5 It is a DCR model diagram of a local chip in a hybrid integrated circuit product designed by the method of the application; Figure 6 It is a CS signal crosstalk analysis model diagram of a hybrid integrated circuit product designed by the method of the application; Figure 7 It is a COMP signal crosstalk analysis model diagram of a hybrid integrated circuit product designed by the method of the application; Figure 8 It is an electrical and thermal analysis simulation diagram of a hybrid integrated circuit product designed by the method of the application.

[0020] Among them: 1, substrate model, 2, glass material model, 3, dielectric model, 4, gold conductor model, 5, patch resistance and capacitance model, 6, chip model. DETAILED DESCRIPTION

[0021] The application will be further described below with reference to the drawings: The application is based on the process of mixed integrated circuit power supply products, and the research contents of modeling and simulation include the construction of a basic platform, the construction of a simulation model, parameter extraction and verification, and the design of actual cases based on PDK. By modeling the standard process PDK based on domestic EDA tools, the ability to design and use independent process PDK in the field of mixed integrated circuit product design can be helped, and the digital design level of mixed integrated circuit products can be improved.

[0022] For the process characteristics of mixed integrated circuit power supply products, the application conducts modeling and simulation research of mixed integrated circuits. First, a basic platform is built to provide a stable technical support framework for subsequent modeling and simulation. Then, a simulation model is built to construct an accurate model that fits the actual process of the product. Then, the parameters are extracted and verified to ensure the accuracy and reliability of the model parameters. Finally, actual cases are verified based on PDK. The application uses domestic EDA tools to model the standard process PDK, which can help the field of mixed integrated circuit product design to form the design and use of independent process PDK, and effectively improve the digital design level of mixed integrated circuit products.

[0023] As shown in Figure 1 A domestic self-controllable mixed integrated circuit process design method based on product-level PDK modeling and simulation, the method comprising the following steps: S1, design the process parameters of the mixed integrated circuit product (including the spacing between the multi-layer wiring of the substrate, the thickness of the circuit conductor, the curing conditions of the process material, etc.), extract the physical parameters of the mixed integrated circuit product (including the electrical characteristics of the components, the thermal conductivity of the substrate material, the circuit transmission loss, etc.), establish the mixed integrated circuit process design rules (including the minimum spacing of the wiring, the size specification of the pad, etc.), and construct the PDK model framework of the mixed integrated circuit product based on the above parameters and rules. The PDK model framework includes a mixed integrated circuit substrate model, a component model, a circuit model and a process material model.

[0024] S2, construct a neural network model (using the domestic Huawei MindSpore framework, including an input layer, a hidden layer and an output layer), develop PDK components (i.e. substrate model, component model, circuit model, process material model) in the mixed integrated circuit product based on the neural network model, and determine the parameters of each component of the PDK model through neural network training and parameter iteration. S3, based on the PDK model parameters determined in S2, design the schematic diagram and layout of the mixed integrated circuit, and import the schematic diagram and layout into the PDK model framework to perfect the detailed parameters of the PDK model, such as the signal node matching parameters of the layout and schematic diagram, the component layout spacing parameters, etc.

[0025] S4, based on the PDK model framework, the parameters of each component of the PDK model, the schematic diagram and the layout, a complete hybrid integrated circuit product PDK model is built by using domestic EDA tools; the built PDK model is connected with domestic EDA tools, and the PDK model is simulated in the order of electrical performance, thermal performance and electromagnetic compatibility; based on the simulation results, the layout of the hybrid integrated circuit is optimized by using domestic EDA tools, and the optimal design scheme is obtained, and the process feasibility of the product is improved.

[0026] The technical scheme of the application is not an industry conventional technical means, but a localized self-controllable software platform application scheme developed in combination with the process design characteristics and design software system of domestic hybrid integrated circuit products. In the application process, a large amount of hybrid integrated circuit process basic data (such as substrate multilayer wiring process parameters, process material performance parameters, etc.) and product level application scene parameter data (such as environmental parameters and load parameters under different working conditions of military and civilian products) are deeply integrated, which can meet the needs of building digital twin models of a large number of product whole machines and application environments in military and civilian fields, and fill the gap of domestic integrated data support scheme. At present, in the field of hybrid integrated circuit process design in China, most of the work is carried out by relying on foreign mainstream design software such as CANDENCE, MENTOR and ANSYS. Such software not only has the problem of scattered function modules and cannot realize the high integration of “design-modeling-simulation”, but more importantly, it is difficult to meet the requirements of technical self-controllability, and has obvious limitations in high-end fields such as aerospace, aviation and weapon equipment. The application integrates layout design, schematic design, PDK model building and multi-physical field simulation solving into the same localized design platform, realizes the whole process of self-controllability. According to the actual measurement verification, the error of the simulation results of the application and the simulation results of the ANSYS software is only 3%, which has very high simulation confidence, and can completely replace foreign software to complete high-precision design simulation work.

[0027] As shown in Figure 2 and Figure 3 , the framework of the hybrid integrated circuit product PDK model includes a hybrid integrated circuit substrate model, a component model, a circuit model and a process material model. The hybrid integrated circuit substrate model and the component model form a three-dimensional model. Figure 2 The model in the application also gives process material parameters and electrical interconnection models, including bonding wire morphology, solder material and IMC layer thickness. Figure 3 The models of media, gold guide and the like involved in the application also give material characteristics and parameters. Since the materials involve confidentiality, the specific models are not disclosed in the application. Figure 2The model is an optimized product-level model based on a process design model established based on a hybrid integrated circuit process design specification. When designing the PDK model, the process material model and the perfect electrical interconnection model are covered to build a hybrid integrated circuit product-level model, which is different from other board-level applications. From Figure 2 The substrate model 1, the glass material model 2, and the dielectric model 3 can be seen in FIG. 1. Figure 3 The substrate model 1, the glass material model 2, the dielectric model 3, the gold conductor model 4, the patch resistor-capacitor model 5, and the chip model 6 can be seen in FIG. 2.

[0028] Further, the hybrid integrated circuit substrate model is the bottom support carrier of the entire hybrid integrated circuit product PDK model; the hybrid integrated circuit substrate model is a multilayer wiring structure made of aluminum oxide ceramic material, with a thickness of 0.6 mm or 1.0 mm. The hybrid integrated circuit substrate model provides installation space and structural support for the component model and the circuit model, and provides physical installation reference and electrical connection basis for the component model. The component model is a functional component mounted on the hybrid integrated circuit substrate model, and the component model and the hybrid integrated circuit substrate model form physical fixation and electrical conduction through process material models (such as welding process, bonding process). The circuit model is used to build transmission paths, form complete signal links and power links, and realize electrical connection between different component models.

[0029] Further, the component model includes a patch resistor-capacitor model, a localized chip model, and a film-coated patch resistor model, the component model adopts a component SPICE model, which can represent the electrical characteristic parameters of the device itself. The component model is installed on the surface layer of the hybrid integrated circuit substrate model through the process material model, the patch resistor-capacitor and the film-coated patch resistor are fixed to the substrate pad through the welding process, and the localized chip is attached to the surface of the substrate through the bonding process.

[0030] Further, the circuit model includes a circuit interconnection model, a gold conductor model, a dielectric model, and a pad model; the gold conductor model adopts pure gold material, the pure gold has a gold content of 99.99%, and the thickness is 7-18 um; the pad model adopts platinum-silver material, and the thickness is 15-30 um. The gold conductor, the dielectric, and the pad are embedded in the aluminum oxide ceramic matrix of the hybrid integrated circuit substrate model through a multilayer wiring process, the hybrid integrated circuit substrate model provides physical bearing space for the circuit model, and the wiring layout of the circuit model needs to match the structure and size of the substrate model.

[0031] Further, the process material model includes a bonding process model, a welding process model and an adhesive process model; the bonding process model adopts pure gold bonding wire with a diameter of 25um; the welding process model adopts Sn62Pb36Ag2 soldering paste and 0.1mm soldering sheet; and the adhesive process model adopts epoxy resin conductive adhesive. The welding process model and the adhesive process model are filled between the bottom of the component model and the surface layer of the hybrid integrated circuit substrate model and the pads of the circuit model, for simultaneously realizing physical fixation and electrical conduction; and the bonding process is used for connecting the component model (chip pin) and the circuit model (gold conductor), to form a conductive link across components.

[0032] As can be seen from the above, the application can be fully applied to the construction of high-reliability military hybrid integrated circuit products, and the unique structures involved in various hybrid integrated circuit products can be modeled, such as film forming printed circuit, bonding wire, conductive adhesive application and multi-layer wiring film forming ceramic substrate.

[0033] Step S12 is used for fine definition of parameters of the PDK model. Through PDK model parameter fine definition, layout schematic diagram synchronous design, design and manufacturing integration and collaboration ability are improved. At the algorithm level, through neural network algorithm training, accurate and rapid modeling is realized; for product-level model simulation, basic data in the hybrid integrated circuit product need to be provided during modeling, and the more the model conforms to the actual application, the higher the simulation result confidence will be.

[0034] The step S2 specifically includes the following steps: S21, constructing a neural network model and a training data set.

[0035] In this embodiment, an existing domestic self-developed neural network algorithm framework is used as the neural network model. Specifically, a Huawei MindSpore framework is used to build a three-layer neural network model including an input layer, a hidden layer and an output layer. The input layer is basic data (power level, working frequency, size limit, environmental temperature range) of the hybrid integrated circuit product; the hidden layer is set to 3 layers, and the number of neurons in each layer is 64, 32 and 16 respectively; and the output layer is key parameters of each component of the PDK model, such as substrate thickness, gold conductor width and component SPICE parameters.

[0036] The embodiment collects basic data of each component of the mixed integrated circuit product PDK model, such as thermal conductivity of substrate material, electrical characteristic test data of components, circuit transmission loss data, process material performance parameters and the like, forms a historical design and measured data sample library containing 100+ groups of mixed integrated circuit products as a training data set. Preferably, 120 groups of historical data of mixed integrated circuit products are collected, each group of data contains basic design parameters (such as power 5W, frequency 1GHz), PDK model parameters (such as substrate thickness 0.6mm, gold conductor thickness 12um) and measured performance data (such as signal transmission loss 0.3dB, power ripple 20mV), form a training data set, and divide it into a training set and a validation set in a ratio of 7:3.

[0037] S22, training a neural network model based on the training data set.

[0038] The embodiment uses an existing domestic self-developed neural network algorithm framework, maps the basic data-model parameters-simulation results, and trains the neural network model using the training data set. The Adam optimizer is used, the learning rate is 0.001, the decay coefficient is 0.9, the loss function is mean square error (MSE), the number of training iterations is set to 1000, the model accuracy is calculated after each iteration through the validation set, and the training is stopped when the validation set MSE≤0.005.

[0039] S23, using the trained neural network model to determine the parameters of the mixed integrated circuit product PDK model. The passive device model in the mixed integrated circuit product is built based on the neural network algorithm developed passive device optimization platform iModeler, which contains T-coil layout structure. After calling the T-coil template in the iModeler software, the designer can perform various physical size parameterization scanning, and then use the EM formula of 4 parameters to perform device multi-index optimization. After a large number of discrete S parameter results are entered, the inference is completed based on the combination of the rule base and the electrical characteristic parameters through the machine learning training algorithm, the passive device model with the best size is established, and the selection of the surface passive device of the substrate and the recommendation of the printed size of the film resistor are further completed. The T-coil template is a platform developed after the secondary optimization of the application template of the mixed integrated circuit product component of the software platform, which covers the parameterized model of a large number of domestic mixed integrated circuit product-specific passive devices. The base data of the target product (such as power level, working frequency, size limit) is input into the trained neural network model, and the neural network model automatically generates initial parameters of the hybrid integrated circuit product PDK model meeting the requirements of domestic self-controllable, such as a substrate thickness of 0.6 mm, a gold conductor thickness of 15 um, a pad thickness of 25 um, and a bonding wire diameter of 25 um. Ten physical prototypes are made, the key performance of the prototypes is tested, the measured data is compared with the simulation data of the model, if the deviation is greater than 5%, the output weight of the neural network model is adjusted, the parameters are regenerated, and the final PDK model parameters are determined until the deviation between the simulation and the measured data is less than or equal to 3%, and the precise model meeting the actual application scenario is quickly converged through iterative optimization, the problems of long parameter debugging period and precision depending on artificial experience in the traditional modeling method are solved, and the confidence of the simulation result is improved.

[0040] The parameters of the hybrid integrated circuit product PDK model include: (1) The substrate material and thickness, the interlayer spacing and wiring width parameters of the multi-layer structure of the hybrid integrated circuit substrate model. In this embodiment, the hybrid integrated circuit substrate model adopts aluminum oxide ceramic material as the substrate, and the thickness of the substrate is 0.6 mm.

[0041] (2) The parameters of the component model. For the SPCIE model of the chip resistor, the domestic chip and the film chip resistor, the direct current resistance, the parasitic capacitance, the frequency response coefficient and other electrical characteristic parameters of the components are extracted and calibrated.

[0042] (3) The parameters of the circuit model. Specifically, the conductivity and thermal expansion coefficient parameters of the gold conductor model are designed, and the soldering compatibility parameters of the pad model are designed.

[0043] (4) The process parameters of the process material model. Specifically, the process parameters such as bonding strength, solder melting point and adhesive curing time are designed to ensure that the model parameters are completely matched with the actual manufacturing process.

[0044] As can be seen from the above, the neural network model is used to realize the fine modeling of the PDK model parameters, shorten the construction period of the PDK model, improve the fitting degree of the model and the actual product, and lay a foundation for subsequent simulation and design optimization. The neural network algorithm can process multi-dimensional and highly coupled process parameters (such as the relationship between the gold conductor thickness and the signal transmission loss, and the correlation between the pad size and the soldering reliability), automatically optimize the parameters of each component of the PDK model (such as the substrate multi-layer wiring spacing and the parasitic parameters of the component SPICE model) through learning of historical design data and measured results, ensure the matching degree of the model parameters and the actual manufacturing process, provide a high confidence model basis for subsequent collaborative simulation, and finally improve the design and manufacturing integration and collaboration ability.

[0045] Using domestically developed EDA tools, schematics and layouts of hybrid integrated circuits were constructed. During schematic design, the PCELL model library of the iModeler component model was called to ensure consistency between the component models and parameters in the schematic and the PDK model. During layout design, the schematic signal nodes were synchronously associated, automatically matching the gold conductor routing rules and pad size specifications in the circuit model, and real-time verification of the consistency between the layout and the schematic, such as signal connection relationships and component package matching, to avoid design discrepancies. Specifically, in domestic... Production In the schematic editor of Xinhe EDA, the component SPICE model library determined in step S2 is called, such as DC / DC chip models and surface-mount resistor and capacitor models. The schematic is drawn according to the functional requirements of the target product, and the parameters of each component must be consistent with the PDK model. In the layout design tool Xinhe Genesis, the existing hybrid integrated circuit dedicated design rule library is loaded to ensure that the layout design meets manufacturing feasibility. Through the tool's schematic and layout bidirectional linkage function, the signal nodes in the schematic are automatically mapped to the circuit model of the layout, and the layout is drawn according to the PDK model parameters. During the design process, the tool performs bidirectional verification in real time. If the schematic is modified, the parameter labels of the corresponding components in the layout are automatically updated; if the layout violates regulations, a violation prompt pops up on the schematic interface, and the violation location is marked. This design ensures that the signal connections and component parameters of the schematic and layout are completely matched, without design discrepancies. During the design process, this invention combines the hybrid integrated circuit process design flow to complete the software application platform development, and all layouts and schematics are designed within the same platform. Seamless integration between modules, including the Notus simulation module, enables direct electrothermal analysis, electrical analysis, electromagnetic analysis, and ripple analysis, improving the efficiency of hybrid integrated circuit product process design. Both passive and active devices undergo parametric design and are integrated with process design DRC testing to ensure compliance with regulations and enhance product application reliability.

[0046] In this embodiment, domestic EDA tools, such as Hermes, are used to complete the modular construction of the PDK model.

[0047] Step S4 specifically includes the following steps: S41. Integrate the hybrid integrated circuit substrate model, circuit model, component model, and process material model to build a hybrid integrated circuit product PDK model.

[0048] In this embodiment, the alumina ceramic is used as the substrate, the multi-layer wiring design is carried out by using the domestic EDA tool, the multi-layer structure is drawn, and the layer spacing, wiring width and overall thickness of the substrate are designed, so that the hybrid integrated circuit substrate model forms the bottom support carrier of the model. In the surface layer and the inner layer wiring layer of the hybrid integrated circuit substrate model, the circuit model is drawn by using the domestic EDA tool. The gold conductor model adopts 99.99% pure gold, and the thickness is selected according to the current density. The dielectric model adopts domestic alumina ceramic dielectric, and the dielectric constant εr=9.8±0.2. The pad model adopts platinum-silver material, the diameter of the pad is in the range of 0.3mm±0.02mm, and the thickness is selected according to the pin size of the soldered device. The design of each parameter ensures that the circuit model and the hybrid integrated circuit substrate model form an integrated interconnection structure. The chip model, the film patch resistance model and the domestic chip model are positioned to the pad area of the surface layer of the hybrid integrated circuit substrate model by using the domestic EDA tool, and the upper functional components are formed. At the junction of the components and the substrate of the hybrid integrated circuit and the circuit, a process material model is added by using the domestic EDA tool, and finally a complete three-dimensional PDK model of the substrate-circuit-component-process material cooperation is formed. The bonding process model adopts pure gold bonding wire, the soldering process model adopts solder paste, and the bonding process model adopts epoxy resin conductive adhesive.

[0049] The step S41 specifically includes the following steps: S411, integration of the substrate model and the circuit model: the circuit layout (gold conductor, dielectric, pad) is bound to the substrate model through the interlayer alignment function of the core and HERMES, to ensure that the gold conductor of the circuit model is embedded in the multi-layer wiring layer of the substrate, forming a substrate-circuit-electrical interconnection-manufacturing process-housing integrated structure, and the tool automatically checks the risk of interlayer short circuit.

[0050] S412, binding of the component model, the substrate model and the circuit model: the calibrated component model is accurately positioned to the pad area of the surface layer of the substrate by using the device positioning function of the core and HERMES, and the tool automatically checks the spacing between the components.

[0051] S413, selection of process material model: at the junction of the components and the substrate / circuit, a process material model is added by using the domestic process modeling plug-in core and HERMES, and the parameters are strictly matched with the domestic manufacturing process. The bonding process model adopts pure gold bonding wire for connecting the chip pin and the circuit gold conductor; the soldering process model adopts Sn62Pb36Ag2 soldering paste for filling the gap between the patch resistance and the pad; and the bonding process model adopts epoxy resin conductive adhesive for fixing the bottom of the chip and the surface layer of the substrate.

[0052] After the mixed integrated circuit product PDK model is built, the three-dimensional model checking function of the EDA tool is used to check whether each component has spatial interference and whether the parameters are consistent with the parameter values obtained in step S2, so that the model is a complete three-dimensional structure of substrate-circuit-component-process material coordination, which can be directly used for simulation.

[0053] In S42, a domestic multi-physics simulation tool chip and a Notus simulation module are used to simulate the built mixed integrated circuit product PDK model in the order of electrical performance, thermal performance and electromagnetic compatibility, and simulation parameters cover the actual application scenarios of the product.

[0054] In S43, a domestic EDA tool optimization layout is used based on the simulation results.

[0055] After the mixed integrated circuit product PDK model is built, a series of collaborative simulations are completed, and in the product simulation stage, the environmental temperature, radiation, electromagnetic environment, heat source type, heat dissipation condition, excitation type and excitation parameter of the product work are fully considered. In the process of use, the layout optimization operation is completed by highly combining the mixed integrated circuit product design rules, the layout design is optimized according to the simulation results through PDK modeling simulation, the optimal solution is found, the test cost is reduced, and the design cycle is shortened. In the process of software development and application, the design rule library needs to be continuously improved to ensure that the rules in the rule library meet the current product manufacturing and design requirements in real time, and the rule library should have high completeness.

[0056] The mixed integrated circuit power module is installed in the power supply system of a radar, an airplane and a ship, and is long-term working in a high-heat, high-cold and high-pressure environment. The ship application also needs to meet the requirements of corrosion resistance and salt mist resistance, and all of them are working environments under circuit input load and long-term 24-hour uninterrupted full-load operation. Common Chang'e series, Long March series and globally famous J-10 fighter jets all use such mixed integrated circuit power modules. Figures 4-8 All are simulation applications based on product-level models, and the simulation results have a small gap with the design parameters, only 3% difference with the actual experimental data, and the simulation output is the result under the set circuit input load.

[0057] Figure 4 is the L parameter simulation result graph, wherein the abscissa represents the frequency, the unit is GHz, and the ordinate is the parasitic inductance value, the unit is nh. As can be seen from the curve in the figure, the parasitic inductance value changes with the increase of the working frequency of the product as a whole. Through the change of the parasitic inductance value, it can be judged whether the parasitic inductance exceeds the design range, and whether the product will produce too high parasitic inductance under normal working frequency is predicted in advance. From the figure, it can be seen that the parasitic inductance of the product is within the design range, and the product can work normally under the normal working frequency. Figure 4It can be known that the product designed by the method has a highest parasitic inductance of 1.718 nh, and a parasitic inductance of about 1.675 nh at a working frequency of about 0.5 GHz, which meets the design parameter requirement, and the development cycle is shortened without physical testing.

[0058] Figure 5 It is a local chip DCR model graph of a mixed integrated circuit product designed by the method. The DCR extraction of the key chip is completed by combining the PDK model of the mixed integrated circuit product designed by the method. The resistance value of the interconnection line under the DC state is calculated through the simulation platform, which provides basic data for subsequent timing analysis and power consumption analysis, and the basic data is a key parameter for verifying whether the circuit can meet the design specifications.

[0059] Figure 6 It is a CS signal crosstalk analysis model graph of a mixed integrated circuit product designed by the method. For the key power chip involved in the mixed integrated circuit product designed by the method, a CS signal crosstalk analysis model is constructed by combining the overall process assembly and material information of the specific product, and the crosstalk analysis of the CS signal by the surrounding signals of the CS signal is completed.

[0060] Figure 7 It is a COMP signal crosstalk analysis model graph of a mixed integrated circuit product designed by the method. For the key power chip in the mixed integrated circuit product designed by the method, a COMP signal crosstalk model is constructed by combining the overall process assembly and material information of the specific product, and the crosstalk analysis of the COMP signal by the surrounding signals of the COMP signal is analyzed.

[0061] Figure 8 It is an electrical and thermal analysis simulation graph of a mixed integrated circuit product designed by the method. The electrical and thermal simulation analysis is an analysis method for simulating the interaction between the electrical performance and thermal characteristics of a circuit or electronic device during operation by using a PDK model, and is mainly used for predicting and optimizing the temperature distribution, power loss and thermal reliability of the mixed integrated circuit product. In order to evaluate the power loss of the internal devices of the product during operation, analyze the conduction, convection and radiation paths of heat in the devices and the entire system, predict temperature analysis, avoid abnormal problems such as performance degradation and shortened life caused by local overheating points, and provide important heat dissipation performance optimization basis for process optimization design. Figure 8 The thermal analysis result in the figure accurately locates the high-temperature area of the product, provides important support data for subsequent thermal design, and shortens the thermal management development cycle.

[0062] The simulation process of the application is not a traditional "substrate-only simulation" or "device-only simulation", but is based on a complete hybrid integrated circuit product-level model, which covers all key parameters such as manufacturing process data (such as solder IMC layer thickness, bonding wire appearance parameters), electrical interconnection model (such as gold conductor transmission link, pad contact impedance), etc., and can realize truly scene-based application simulation (such as electro-thermal coupling analysis, power ripple noise analysis, voltage drop analysis, etc.), which is the first such product-level full-parameter simulation method in the domestic hybrid integrated circuit field, and is the exclusive development and application result of the application. Especially for the film-forming printed resistor widely used in hybrid integrated circuits (different from traditional chip resistors), the application develops a special T-coil layout template, which can complete the parameterization scanning of the physical size of the film-forming printed resistor, and realize multi-index optimization of the device by combining the EM formula of four parameters, and finally establish a passive device model with the best size through a machine learning algorithm, providing accurate guidance for substrate surface passive device selection and film-forming resistor printing size design. This technical detail has important practical significance for hybrid integrated circuit product process design optimization and film-forming resistor performance improvement. In addition, considering the harsh and complex application environment of military hybrid integrated circuits (covering multiple scenarios such as sea, land, air and space, especially the extremely stringent anti-radiation requirements in space environment), the application supports the accurate entry of complex environment simulation conditions (such as extreme temperature, radiation dose, electromagnetic interference, etc.), can build a perfect simulation environment, and output accurate simulation results, which can effectively guide the process design optimization of military products, significantly improve the working reliability of military hybrid integrated circuit products, and meet the stringent requirements of high-end fields on product performance and stability.

[0063] In summary, the application solves the problems of long hybrid integrated circuit process design cycle and long-term reliance on foreign design software for design, and the development and application of the application can realize rapid research and development design of hybrid integrated circuits, and the process design cycle can be shortened by 30%. The software platform completes secondary development, and can seamlessly connect with domestic and foreign EDA tools. The application solves the problem that hybrid integrated circuit process design relies on process design rules from multiple perspectives, without considering thermal and force analysis results under electrical characteristics and input excitation, resulting in low yield of finished products during electrical characteristic testing although the products meet the process design specification requirements. The development and application of the application can avoid the problem of rework design caused by imperfect product process design leading to non-compliance of product electrical characteristics. The application solves the problem that PDK modeling simulation is only applied to board-level simulation of LTCC and PCB, and cannot realize complete and complex hybrid integrated circuit low-frequency product simulation analysis and model building, resulting in the inability to build a complete machine digital twin model. The development and application of the application can realize the first complete hybrid integrated circuit product PDK model self-modeling simulation application in China, meeting the needs of building a complete machine digital twin model.

[0064] The above-described embodiments are merely intended to describe the preferred embodiments of the present application, and are not intended to limit the scope of the present application. Various changes and modifications made by those skilled in the art to the present application without departing from the spirit of the present application should fall within the scope of the present application defined by the claims.

Claims

1. A domestically developed and controllable hybrid integrated circuit process design method based on product-level PDK modeling and simulation, characterized in that, The method includes the following steps: S1. Design the process parameters of the hybrid integrated circuit product, extract the physical parameters of the hybrid integrated circuit product, establish the process design rules of the hybrid integrated circuit, and construct the PDK model framework based on the process parameters, physical parameters and process design rules; S2. Develop PDK components in hybrid integrated circuit products using neural network models, and determine the parameters of each component in the PDK model; S3. Based on the parameters of each component in the PDK model, design the schematic and layout of the hybrid integrated circuit product and import it into the PDK model framework to improve the parameters of the PDK model. S4. Based on the PDK model framework, schematic diagram and layout, and PDK model parameters, build a complete hybrid integrated circuit product PDK model using domestic EDA tools, interface the built PDK model with the domestic EDA tools, and perform co-simulation and feedback optimization on the PDK model.

2. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 1, characterized in that, The PDK model framework includes a hybrid integrated circuit substrate model, a component model, a circuit model, and a process material model.

3. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 2, characterized in that, The hybrid integrated circuit substrate model is used to provide installation space and structural support for component models and circuit models, and to provide physical installation reference and electrical connection basis for component models; the hybrid integrated circuit substrate model is a multi-layer wiring structure made of alumina ceramic material with a thickness of 0.6mm or 1.0mm.

4. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 2, characterized in that, The component model is a functional component mounted on a hybrid integrated circuit substrate model. The component model and the hybrid integrated circuit substrate model are physically fixed and electrically connected through a process material model. The component model includes a surface mount resistor and capacitor model, a domestic chip model, and a film-mount resistor model. The component model adopts a component SPICE model.

5. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 2, characterized in that, The circuit model is used to construct transmission paths, form complete signal and power links, and realize electrical connections between different component models. The circuit model includes a circuit interconnection model, a gold conductor model, a dielectric model, and a pad model. The gold conductor model is made of pure gold with a gold content of 99.99% and a thickness of 7~18um. The pad model is made of platinum silver with a thickness of 15~30um.

6. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 2, characterized in that, The process material model includes a bonding process model, a welding process model, and an adhesive bonding process model; the bonding process model uses pure gold bonding wire with a diameter of 25 μm; the welding process model uses Sn62Pb36Ag2 solder paste and 0.1 mm solder pads; and the adhesive bonding process model uses epoxy conductive adhesive.

7. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 2, characterized in that, Step S2 specifically includes the following steps: S21. Construct the neural network model and training dataset; S22. Train the neural network model based on the training dataset; S23. Using the trained neural network model, determine the parameters of the hybrid integrated circuit product PDK model.

8. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 7, characterized in that, The PDK component in the hybrid integrated circuit product is a passive device model, which is built on the iModeler passive device optimization platform developed using neural network algorithms. The neural network model consists of three layers: an input layer, a hidden layer, and an output layer. The input layer contains the basic data of the hybrid integrated circuit product; the hidden layer has three layers with 64, 32, and 16 neurons in each layer, respectively; and the output layer contains the key parameters of each component of the PDK model.

9. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 2, characterized in that, Step S4 specifically includes the following steps: S41. Integrate the hybrid integrated circuit substrate model, circuit model, component model and process material model to build a hybrid integrated circuit product PDK model; S43. Based on the simulation results, optimize the layout using domestic EDA tools.

10. The method for designing domestically developed and controllable hybrid integrated circuit processes based on product-level PDK modeling and simulation according to claim 9, characterized in that, Step S41 specifically includes the following steps: S411 Integration of substrate model and circuit model: Bind the circuit layout and substrate model through the interlayer alignment function of core and HERMES. S412, Binding of Component Model, Substrate Model and Circuit Model: Using the device positioning function of Core and HERMES, the calibrated component model is accurately positioned to the substrate surface pad area. S413, Optional process material model: At the junction of components and substrate / circuit, process material models are added using domestic process modeling plug-in cores and HERMES; S42. Using domestically produced multiphysics simulation tool core and Notus simulation module, the PDK model of the hybrid integrated circuit product is simulated in the order of electrical performance, thermal performance and electromagnetic compatibility. The simulation parameters cover the actual application scenarios of the product.

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