Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductors. The semiconductor structure is filled with a wide-bandgap dielectric layer in a source trench, so that an electric field is more evenly and flatly distributed in a transverse direction and a longitudinal direction. The wide-bandgap dielectric layer can more finely modulate the electric field inside the device, especially the electric field peak value at the bottom of the gate trench, so that the maximum electric field stress borne by the gate oxide layer is further reduced, thereby enhancing the long-term reliability of the gate oxide layer and the withstand voltage capacity of the device. Meanwhile, the device thermal resistance is reduced, the power density is improved, the thermal stress is reduced, and the mechanical robustness and the service life of the device under severe power cycle working conditions are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In traditional trench power devices, the electric field is highly concentrated at the bottom corner of the gate trench. The gate oxide layer in this area may be at risk of breakdown.

[0003] In existing trench power devices, the gate oxide layer at the bottom of the gate trench is protected by a relatively deep injection region. However, when preparing a relatively deep injection region, a mask of sufficient thickness or a suitable photoresist is required, which places high demands on the etching equipment or requires the use of a high-energy implanter, which places high demands on the implantation equipment, resulting in high preparation costs and complicated preparation. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure that is easy to prepare and has high performance, and a method for preparing the same.

[0005] To achieve the above objectives, in one respect, the present invention provides a method for preparing a semiconductor structure, comprising:

[0006] A substrate is provided, the substrate having a first doping type;

[0007] An epitaxial structure is formed on one side of the substrate. The epitaxial structure includes a drift region, a well region, and a source region. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The drift region and the source region have a first doping type, and the well region has a second doping type.

[0008] The epitaxial structure is etched from one side of the source region to form a source trench;

[0009] A wide bandgap dielectric layer is filled within the source trench;

[0010] The epitaxial structure is etched from one side of the source region to form a gate trench, which is located between the source trenches in a direction parallel to the substrate.

[0011] A gate structure is formed within the gate trench. The gate structure includes a gate oxide layer and a gate, with the gate oxide layer located between the gate and the epitaxial structure.

[0012] In one embodiment, prior to filling the source trench with a wide bandgap dielectric layer, the process includes:

[0013] A first dielectric material layer is formed on the side of the epitaxial structure and the source trench away from the substrate;

[0014] The process of filling the source trench with a wide bandgap dielectric layer includes:

[0015] A wide bandgap dielectric material layer is formed on the side of the first dielectric material layer away from the substrate;

[0016] The wide bandgap dielectric material layer and the first dielectric material layer on the side of the epitaxial structure away from the substrate are removed, and the remaining wide bandgap dielectric material layer forms a wide bandgap dielectric layer, and the remaining first dielectric material layer forms a first dielectric layer.

[0017] In one embodiment, forming an epitaxial structure on one side of the substrate includes:

[0018] An initial epitaxial material layer is formed on one side of the substrate;

[0019] A first ion implantation is performed on the initial epitaxial material layer from the side of the initial epitaxial material layer away from the substrate to form an initial well region, and the remaining initial epitaxial material layer forms the drift region;

[0020] A second ion implantation is performed on the initial well region from the side of the initial well region away from the drift region to form the source region, and the remaining initial well region forms the well region.

[0021] In one embodiment, the process of forming the source trench includes:

[0022] A columnar doped region is formed in the drift region at the bottom of the source trench, the columnar doped region extending from the source trench to the drift region, and the columnar doped region has a second doping type.

[0023] In one embodiment, after forming the gate structure within the gate trench, the process includes:

[0024] A second dielectric layer is formed on the side of the gate structure away from the epitaxial structure, and the second dielectric layer exposes the wide bandgap dielectric layer.

[0025] In one embodiment, the second dielectric layer is formed on the side of the gate structure away from the epitaxial structure, and after the second dielectric layer exposes the wide bandgap dielectric layer, the method further includes:

[0026] An ohmic contact layer is formed on one side of the epitaxial structure exposed by the second dielectric layer.

[0027] In one embodiment, after forming an ohmic contact layer on one side of the epitaxial structure exposed by the dielectric layer, the method further includes:

[0028] A source electrode is formed on the side of the second dielectric layer, the ohmic contact layer, and the wide bandgap dielectric layer away from the substrate;

[0029] A drain electrode is formed on the side of the substrate away from the epitaxial structure.

[0030] In one embodiment, after forming the source on the side of the second dielectric layer, the ohmic contact layer, and the wide bandgap dielectric layer away from the substrate, the process includes:

[0031] A passivation layer is formed on the side of the source electrode away from the epitaxial structure. The passivation layer includes a first passivation layer and a second passivation layer sequentially disposed in a direction perpendicular to the substrate.

[0032] On the other hand, this application also provides a semiconductor structure, including:

[0033] Substrate, the substrate having a first doping type;

[0034] An epitaxial structure is located on one side of the substrate. The epitaxial structure includes a drift region, a well region, and a source region. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The drift region and the source region have a first doping type, and the well region has a second doping type.

[0035] A source trench is located within the epitaxial structure and extends from the source region to the drift region;

[0036] A wide bandgap dielectric layer fills the source trench;

[0037] A gate trench is located within the epitaxial structure and extends from the source region to the drift region. The gate trench is located between the source trenches in a direction parallel to the substrate.

[0038] A gate structure, including a gate oxide layer and a gate, is located within the gate trench.

[0039] In one embodiment, the wide bandgap dielectric layer is made of silicon carbide or gallium nitride.

[0040] Compared with existing technologies, the above technical solution has the following advantages:

[0041] In this semiconductor structure and its fabrication method, a substrate with a first doping type is first provided. Then, an epitaxial structure is formed on one side of the substrate. This epitaxial structure includes a drift region, a well region, and a source region. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The drift region and the source region have the first doping type, and the well region has a second doping type. Next, a source trench is formed on the side of the epitaxial structure away from the substrate, and a wide bandgap dielectric layer is filled within the source trench. Then, a gate trench is formed within the epitaxial structure between the source trenches in a first direction parallel to the substrate. Finally, a gate structure is formed within the gate trench, and the gate structure includes a gate oxide layer and a gate.

[0042] Because a wide bandgap dielectric layer is filled within the source trench, the electric field is distributed more uniformly and flatly in both the lateral and longitudinal directions. This wide bandgap dielectric layer allows for more precise modulation of the electric field within the device, particularly the peak electric field at the bottom of the gate trench. This further reduces the maximum electric field stress borne by the gate oxide layer, thereby enhancing the long-term reliability of the gate oxide layer and the device's breakdown voltage. Simultaneously, it reduces the device's thermal resistance, increases power density, reduces thermal stress, and improves the device's mechanical robustness and lifespan under severe power cycling conditions. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0045] Figure 2 This is a schematic diagram of a semiconductor structure forming an epitaxial structure, provided in an embodiment of this application.

[0046] Figure 3 This application provides a schematic diagram of a structure for forming a source trench.

[0047] Figure 4 This is a schematic diagram of a semiconductor structure forming a columnar doped region, provided in an embodiment of this application.

[0048] Figure 5 This is a schematic diagram of a semiconductor structure forming a first dielectric material layer, provided in an embodiment of this application.

[0049] Figure 6This application provides a schematic diagram of a semiconductor structure forming a wide bandgap dielectric material layer.

[0050] Figure 7 This application provides a schematic diagram of a semiconductor structure forming a wide bandgap dielectric layer.

[0051] Figure 8 This is a schematic diagram of a semiconductor structure forming a gate trench, provided in an embodiment of this application.

[0052] Figure 9 This is a schematic diagram of a semiconductor structure forming a gate oxide layer, provided in an embodiment of this application.

[0053] Figure 10 This is a schematic diagram of a semiconductor structure forming a gate, provided in an embodiment of this application.

[0054] Figure 11 This is a schematic diagram of a semiconductor structure forming a second dielectric layer, provided in an embodiment of this application.

[0055] Figure 12 This is a schematic diagram of a semiconductor structure forming an ohmic contact layer, provided in an embodiment of this application.

[0056] Figure 13 This is a schematic diagram of a semiconductor structure forming a source electrode, provided in an embodiment of this application.

[0057] Figure 14 This is a schematic diagram of a semiconductor structure forming a drain electrode, provided in an embodiment of this application.

[0058] Explanation of reference numerals in the attached figures: Substrate 01; Epitaxial structure 02; Drift region 021; Well region 022; Source region 023; Pillar doped region 024; Source trench 03; First patterned mask layer 031; Wide bandgap dielectric layer 04; Wide bandgap dielectric material layer 041; Gate trench 05; Second patterned mask layer 051; Gate structure 06; Gate oxide material layer 0611; Gate oxide layer 061; Gate 062; First dielectric material layer 071; First dielectric layer 07; Second dielectric layer 08; Source 09; Drain 10; Ohmic contact layer 11. Detailed Implementation

[0059] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0061] It should be understood that when a layer is referred to as "on," "adjacent to," or "connected to" other layers, it can be directly on, adjacent to, or connected to other layers, or there can be intervening layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other layers, there are no intervening layers.

[0062] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0063] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0064] refer to Figure 1 , Figure 1 This application provides a schematic flowchart of a method for fabricating a semiconductor structure; the method for fabricating the semiconductor structure includes:

[0065] S10: Provide substrate 01, which has a first doping type.

[0066] In this step, the first doping type is N-type doping, and the substrate 01 can be a silicon carbide substrate.

[0067] S20: An epitaxial structure 02 is formed on one side of the substrate 01. The epitaxial structure 02 includes a drift region 021, a well region 022, and a source region 023. The well region 022 is located on the side of the drift region 021 away from the substrate 01, and the source region 023 is located on the side of the well region 022 away from the drift region 021. The drift region 021 and the source region 023 have a first doping type, and the well region 022 has a second doping type (e.g., ...). Figure 2 (As shown).

[0068] In this step, the material of the epitaxial structure 02 can be silicon carbide. The drift region 021 and the source region 023 in the epitaxial structure 02 have a first doping type, that is, they can have N-type doping. The well region 022 has a second doping type, which can be P-type doping.

[0069] In the epitaxial structure 02, the drift region 021, the well region 022, and the source region 023 are stacked sequentially from one side of the substrate 01 in a direction perpendicular to the substrate 01.

[0070] S30: Etch the epitaxial structure 02 from one side of the source region 023 to form the source trench 03 (e.g., Figure 3 (As shown).

[0071] In this step, a hard mask is first formed on the side of the epitaxial structure 02 away from the substrate 01. Then, a pattern is formed on the hard mask using photolithography and dry etching processes. Finally, the photoresist is removed using dry and wet photoresist removal processes to obtain the first patterned mask layer 031 (e.g., ...). Figure 3 (As shown).

[0072] Then, based on the first patterned mask layer 031, a dry etching process is performed from one side of the source electrode 09 of the epitaxial structure 02 to the inside of the epitaxial structure 02 until the drift region 021 is exposed, forming the source trench 03.

[0073] Then remove the first patterned mask layer 031.

[0074] S40: A wide bandgap dielectric layer 04 is filled within the source trench 03 (e.g., ...). Figure 7 (As shown).

[0075] In this step, a wide bandgap dielectric layer 04 is filled in the source trench 03. The material of the wide bandgap dielectric layer 04 may include, but is not limited to, silicon carbide or silicon nitride.

[0076] The wide bandgap dielectric layer 04 can make the electric field more uniform and flat in the lateral and longitudinal directions, and can more finely modulate the electric field inside the device, especially the electric field peak at the bottom of the gate trench 05. This further reduces the maximum electric field stress on the gate oxide layer 061, thereby enhancing the long-term reliability of the gate oxide layer 061 and the device's withstand voltage capability.

[0077] S50: Etching is performed on one side of the source region 023 to form the epitaxial structure 02, forming the gate trench 05. The gate trench 05 is located between the source trenches 03 in a direction parallel to the substrate 01 (e.g., Figure 8 (As shown).

[0078] In this step, a hard mask is first formed on the side of the epitaxial structure 02 away from the substrate 01. Then, a pattern is formed on the hard mask using photolithography and dry etching processes. Finally, the photoresist is removed using dry and wet photoresist removal processes to obtain the second patterned mask layer 051 (e.g., ...). Figure 8 (As shown).

[0079] Then, based on the second patterned mask layer 051, a dry etching process is performed from one side of the source 09 of the epitaxial structure 02 to the inside of the epitaxial structure 02 until the drift region 021 is exposed, forming the gate trench 05.

[0080] It should be noted that, in the direction parallel to the substrate 01, the gate trench 05 is located between the source trenches 03.

[0081] S60: A gate structure 06 is formed within the gate trench 05. The gate structure 06 includes a gate oxide layer 061 and a gate 062. The gate oxide layer 061 is located between the gate 062 and the epitaxial structure 02 (e.g., ...). Figure 11 (As shown).

[0082] In this step, the gate structure 06 includes a gate oxide layer 061 and a gate 062. The material of the gate oxide layer 061 can be silicon dioxide, and the material of the gate 062 can be polysilicon.

[0083] When fabricating the gate oxide layer 061, a chemical vapor deposition process can be used to form the gate oxide material layer 0611 (e.g., Figure 9 As shown), gate oxide layer 061 covers the sidewalls and bottom of gate trench 05. Then, a gate material layer is filled into gate trench 05 using low-pressure chemical vapor deposition. When fabricating polycrystalline silicon, this can be done in a silane atmosphere at 620°C. Afterwards, the gate oxide layer 0611 and gate material layer outside the epitaxial structure 02 are removed by photolithography and dry etching processes. The gate oxide layer 0611 within gate trench 05 is retained as gate oxide layer 061, and the gate material layer within gate trench 05 is retained as gate 062 (as shown). Figure 10 (As shown).

[0084] In this embodiment, because a wide bandgap dielectric layer 04 is filled within the source trench 03, the electric field is distributed more uniformly and flatly in both the lateral and longitudinal directions. The wide bandgap dielectric layer 04 can more finely modulate the electric field inside the device, especially the electric field peak at the bottom of the gate trench 05. This further reduces the maximum electric field stress borne by the gate oxide layer 061, thereby enhancing the long-term reliability of the gate oxide layer 061 and the device's breakdown voltage capability. Simultaneously, it reduces the device's thermal resistance, increases power density, reduces thermal stress, and improves the device's mechanical robustness and lifespan under severe power cycling conditions.

[0085] In another embodiment of this application, before filling the source trench 03 with a wide bandgap dielectric layer 04, the following steps are included:

[0086] S400: A first dielectric material layer 071 is formed on the side of the epitaxial structure 02 and the source trench 03 away from the substrate 01 (e.g., Figure 5 (As shown).

[0087] A wide bandgap dielectric layer 04 is filled within the source trench 03, comprising:

[0088] S401: A wide bandgap dielectric material layer 041 is formed on the side of the first dielectric material layer 071 away from the substrate 01 (e.g., Figure 6 (As shown).

[0089] S402: Remove the wide bandgap dielectric material layer 041 and the first dielectric material layer 071 on the side of the epitaxial structure 02 away from the substrate 01. The remaining wide bandgap dielectric material layer 041 forms the wide bandgap dielectric layer 04, and the remaining first dielectric material layer 071 forms the first dielectric layer 07 (e.g., ...). Figure 7 (As shown).

[0090] Specifically, in step S400, the material of the first dielectric material layer 071 can be silicon dioxide.

[0091] The first dielectric material layer 071 can be formed by chemical vapor deposition, and the first dielectric material layer 071 covers the entire wafer surface.

[0092] In step S401, a wide bandgap dielectric material layer 041 is deposited on the side of the first dielectric material layer 071 away from the substrate 01. The material of the wide bandgap dielectric material layer 041 can be silicon carbide or gallium nitride, etc.

[0093] In step S402, the wide bandgap dielectric material layer 041 and the first dielectric material layer 071 on the side of the epitaxial structure 02 away from the substrate 01 are etched away by the back etching process. The remaining wide bandgap dielectric material layer 041 forms the wide bandgap dielectric layer 04, and the remaining first dielectric material layer 071 forms the first dielectric layer 07.

[0094] In another embodiment of this application, such as Figure 1 As shown, an epitaxial structure 02 is formed on one side of the substrate 01, including:

[0095] S200: An initial epitaxial material layer is formed on one side of substrate 01.

[0096] S201: The first ion implantation is performed on the initial epitaxial material layer from the side of the initial epitaxial material layer away from the substrate 01 to form the initial well region, and the remaining initial epitaxial material layer forms the drift region 021.

[0097] S202: A second ion implantation is performed on the initial well region from the side of the initial well region away from the drift region 021 to form the source region 023, and the remaining initial well region forms the well region 022.

[0098] In step S200, the initial epitaxial material layer can be a silicon carbide material layer.

[0099] In step S201, when performing ion implantation on the initial epitaxial material layer, silicon dioxide can be used as the implantation hard mask. A third patterned mask layer is formed through photolithography and dry etching processes. This third patterned mask layer blocks the terminal region of the device. First ion implantation is performed on the initial epitaxial material layer in the cell region from the side of the initial epitaxial material layer away from the substrate 01 to form the initial well region. The doping type of the first ion implantation is P-type. The remaining initial epitaxial material layer forms the drift region 021.

[0100] The first ion implantation is a high-temperature ion implantation, using aluminum as the dopant element, with a doping concentration range of 1E16cm. -3 ~1E17cm -3 This includes endpoint values; for example, the doping concentration can be 1E16cm. -3 Or the doping concentration can be 1E17cm -3 wait.

[0101] In step S202, the third patterned mask layer is still used to perform a second ion implantation on the side of the initial well region away from the substrate 01 in the cell region, forming the source region 023, and the remaining initial well region forms the well region 022. The doping type of the second ion implantation is N-type heavy doping.

[0102] The second ion implantation is a high-temperature ion implantation, using nitrogen as the dopant element, with a doping concentration range of 1E19cm. -3 ~1E21cm -3 This includes endpoint values; for example, the doping concentration can be 1E19cm. -3 wait.

[0103] After forming the source region 023, the third patterned mask layer is removed by wet etching.

[0104] In another embodiment of this application, after forming the source trench 03, the following is included:

[0105] A columnar doped region 024 is formed within the drift region 021 at the bottom of the source trench 03. The columnar doped region 024 extends from the source trench 03 to the drift region 021. The columnar doped region 024 has a second doping type (e.g., ...). Figure 4 (As shown).

[0106] Specifically, after forming the source trench 03, a third ion implantation is performed on the drift region 021 at the bottom of the source trench 03 based on the first patterned mask layer 031. At this time, the wafer can be tilted at 4° for room temperature ion channel implantation, utilizing the channel effect to form a doped region, namely the columnar doped region 024, at the bottom of the source trench 03. The doping type of the third ion implantation is P-type doping. The columnar doped region 024 extends from the source trench 03 to the drift region 021.

[0107] The third ion implantation can use aluminum as the dopant element, with a doping concentration range of 1E17cm⁻¹. -3 ~1E19cm -3 This includes endpoint values; for example, the doping concentration can be 1E18cm. -3 The energy injected is adjusted according to the actual depth requirements.

[0108] After the third ion implantation, the first patterned mask layer 031 is removed.

[0109] In another embodiment of this application, after forming the gate structure 06 within the gate trench 05, the process includes:

[0110] A second dielectric layer 08 is formed on the side of the gate structure 06 away from the epitaxial structure 02, and the second dielectric layer 08 exposes a wide bandgap dielectric layer 04 (e.g., Figure 11 (As shown).

[0111] Specifically, after forming the gate structure 06 in the gate trench 05, a second dielectric material layer (not shown) is formed on the side of the gate structure 06 away from the epitaxial structure 02 using chemical vapor deposition. Then, the second dielectric material layer is planarized by reflow to facilitate subsequent etching. The formation temperature of the second dielectric material layer can be 950°C, the time can be 60 minutes, and it can be performed in an N2 atmosphere. Afterwards, a photolithography process is used to etch and expose the wide bandgap dielectric layer 04 to form the second dielectric layer 08.

[0112] The second dielectric layer 08 can isolate the gate structure 06 from the subsequently formed source 09. It should be noted that the material of the second dielectric layer 08 can be silicon oxide.

[0113] In some embodiments, the second dielectric layer 08 can be a two-layer structure, including a first sublayer and a second sublayer. The first sublayer is located on the side closer to the gate structure 06, and the second sublayer is located on the side farther from the gate structure 06. The material of the first sublayer can be silicon dioxide. The material of the second sublayer can be p-doped silicon dioxide, or b- and p-doped silicon dioxide, without specific limitations.

[0114] In another embodiment of this application, a second dielectric layer 08 is formed on the side of the gate structure 06 away from the epitaxial structure 02. After the second dielectric layer 08 exposes the wide bandgap dielectric layer 04, it further includes:

[0115] An ohmic contact layer 11 is formed on one side of the epitaxial structure 02 exposed by the second dielectric layer 08 (e.g., ...). Figure 12 (As shown).

[0116] Specifically, an ohmic contact layer 11 is formed on one side of the epitaxial structure 02 exposed by the second dielectric layer 08. Before forming the source 09, a metal layer can be sputtered on the side of the epitaxial structure 02 exposed by the second dielectric layer 08 away from the substrate 01, and then the ohmic contact layer 11 is formed after two annealing processes. It should be noted that the temperature of the first annealing can be 750°C, the time can be 5 minutes, and it can be performed in an N2 atmosphere. After the first annealing, the unreacted metal can be removed by wet etching, and then a metal silicide with low contact resistance can be formed by a second annealing. The temperature of the second annealing can be 950°C, the time can be 3 minutes, and it can be performed in an N2 atmosphere.

[0117] The metal material can be Ni, Pt, nickel-platinum alloy, etc., and is not specifically limited; the above materials are only examples. After annealing, the metal forms a metal silicide on the silicon carbide surface, namely the ohmic contact layer 11. The low-resistance ohmic contact layer 11 can significantly reduce the heat dissipation generated by the semiconductor structure during operation, improve the efficiency and reliability of the semiconductor structure, and also help to reduce the size and weight of the semiconductor structure.

[0118] In another embodiment of this application, after forming an ohmic contact layer 11 on one side of the epitaxial structure 02 exposed by the dielectric layer, the method further includes:

[0119] A source electrode 09 is formed on the side of the second dielectric layer 08, the ohmic contact layer 11, and the wide bandgap dielectric layer 04 away from the substrate 01 (e.g. Figure 13 (as shown)

[0120] A drain 10 is formed on the side of substrate 01 away from epitaxial structure 02 (e.g. Figure 14 (As shown).

[0121] Specifically, after forming an ohmic contact layer 11 on one side of the epitaxial structure 02 exposed by the second dielectric layer 08, a source electrode 09 is formed on the side of the second dielectric layer 08, the ohmic contact layer 11, and the wide bandgap dielectric layer 04 away from the substrate 01. The source electrode 09 can be formed by physical vapor deposition (PVD), for example, by sequentially depositing a Ti layer, a TiN layer, and an Al layer as the source electrode 09.

[0122] In addition, the side of the substrate 01 away from the epitaxial structure 02 can be thinned first, and then nickel can be sputtered to form an ohmic contact. Then, metals such as titanium, nickel, and silver can be used for the evaporation of the drain electrode 10.

[0123] In another embodiment of this application, after forming the source 09 on the side of the second dielectric layer 08, the ohmic contact layer 11, and the wide bandgap dielectric layer 04 away from the substrate 01, the process includes:

[0124] A passivation layer is formed on the side of the source electrode 09 away from the epitaxial structure 02. The passivation layer includes a first passivation layer and a second passivation layer sequentially disposed in a direction perpendicular to the substrate 01.

[0125] Specifically, a first passivation layer is deposited on the side of the source electrode 09 away from the epitaxial structure 02 by plasma chemical vapor deposition. It should be noted that the material of the first passivation layer can be SiN. Then, photolithography and dry etching are used to form the required pattern.

[0126] Then, a second passivation layer is formed through processes such as coating, exposure, development, and curing. The second passivation layer can be a polyimide passivation layer.

[0127] In this embodiment, the passivation layer can protect the device and improve the yield.

[0128] In addition, the passivation layer can be removed where metal contact is required, and the specific removal location can be designed according to specific needs.

[0129] In another embodiment of this application, based on the above-described semiconductor structure fabrication method, refer to... Figures 2-14 A semiconductor structure is also provided, comprising:

[0130] Substrate 01, substrate 01 has a first doping type;

[0131] Epitaxial structure 02 is located on one side of substrate 01. Epitaxial structure 02 includes drift region 021, well region 022 and source region 023. Well region 022 is located on the side of drift region 021 away from substrate 01, and source region 023 is located on the side of well region 022 away from drift region 021. Drift region 021 and source region 023 have a first doping type, and well region 022 has a second doping type.

[0132] The source trench 03 is located within the epitaxial structure 02 and extends from the source region 023 to the drift region 021;

[0133] Wide bandgap dielectric layer 04, filled with source trench 03;

[0134] Gate trench 05 is located within epitaxial structure 02 and extends from source region 023 to drift region 021. Gate trench 05 is located between source trenches 03 in a direction parallel to substrate 01.

[0135] The gate structure 06 includes a gate oxide layer 061 and a gate 062, and is located within the gate trench 05.

[0136] Specifically, the first doping type is N-type doping, and the substrate 01 can be a silicon carbide substrate 01.

[0137] The material of the epitaxial structure 02 can be silicon carbide. The drift region 021 and the source region 023 in the epitaxial structure 02 have a first doping type, that is, they can have N-type doping. The well region 022 has a second doping type, which can be P-type doping.

[0138] In the epitaxial structure 02, the drift region 021, the well region 022, and the source region 023 are stacked sequentially from one side of the substrate 01 in a direction perpendicular to the substrate 01.

[0139] The source trench 03 extends from the source region 023 to the drift region 021. The wide bandgap dielectric layer 04 fills the source trench 03. The wide bandgap dielectric layer 04 can make the electric field more uniform and flat in the lateral and longitudinal directions, and can more finely modulate the electric field inside the device, especially the electric field peak at the bottom of the gate trench 05. This further reduces the maximum electric field stress borne by the gate oxide layer 061, thereby enhancing the long-term reliability of the gate oxide layer 061 and the device's withstand voltage capability.

[0140] A gate structure 06 is formed in the gate trench 05. The gate structure 06 includes a gate oxide layer 061 and a gate 062. The material of the gate oxide layer 061 can be silicon dioxide, and the material of the gate 062 can be polysilicon.

[0141] In this embodiment, because a wide bandgap dielectric layer 04 is filled within the source trench 03, the electric field is distributed more uniformly and flatly in both the lateral and longitudinal directions. The wide bandgap dielectric layer 04 can more finely modulate the electric field inside the device, especially the electric field peak at the bottom of the gate trench 05. This further reduces the maximum electric field stress borne by the gate oxide layer 061, thereby enhancing the long-term reliability of the gate oxide layer 061 and the device's breakdown voltage capability. Simultaneously, it reduces the device's thermal resistance, increases power density, reduces thermal stress, and improves the device's mechanical robustness and lifespan under severe power cycling conditions.

[0142] In another embodiment of this application, the wide bandgap dielectric layer 04 is made of silicon carbide or gallium nitride.

[0143] Specifically, the materials for the wide bandgap dielectric layer 04 include, but are not limited to, silicon carbide or gallium nitride.

[0144] In the description of this specification, references to terms such as "some embodiments," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0145] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a first doping type; An epitaxial structure is formed on one side of the substrate. The epitaxial structure includes a drift region, a well region, and a source region. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The drift region and the source region have a first doping type, and the well region has a second doping type. The epitaxial structure is etched from one side of the source region to form a source trench; A wide bandgap dielectric layer is filled within the source trench; The epitaxial structure is etched from one side of the source region to form a gate trench, which is located between the source trenches in a direction parallel to the substrate. A gate structure is formed within the gate trench, the gate structure including a gate oxide layer and a gate, the gate oxide layer being located between the gate and the epitaxial structure; Before filling the source trench with a wide bandgap dielectric layer, the process includes: A first dielectric material layer is formed on the side of the epitaxial structure and the source trench away from the substrate; The process of filling the source trench with a wide bandgap dielectric layer includes: A wide bandgap dielectric material layer is formed on the side of the first dielectric material layer away from the substrate; The wide bandgap dielectric material layer and the first dielectric material layer on the side of the epitaxial structure away from the substrate are removed, and the remaining wide bandgap dielectric material layer forms a wide bandgap dielectric layer, and the remaining first dielectric material layer forms a first dielectric layer.

2. The preparation method according to claim 1, characterized in that, The formation of an epitaxial structure on one side of the substrate includes: An initial epitaxial material layer is formed on one side of the substrate; A first ion implantation is performed on the initial epitaxial material layer from the side of the initial epitaxial material layer away from the substrate to form an initial well region, and the remaining initial epitaxial material layer forms the drift region; A second ion implantation is performed on the initial well region from the side of the initial well region away from the drift region to form the source region, and the remaining initial well region forms the well region.

3. The preparation method according to claim 1, characterized in that, After forming the source trench, the process includes: A columnar doped region is formed in the drift region at the bottom of the source trench, the columnar doped region extending from the source trench to the drift region, and the columnar doped region has a second doping type.

4. The preparation method according to claim 1, characterized in that, After forming the gate structure within the gate trench, the process includes: A second dielectric layer is formed on the side of the gate structure away from the epitaxial structure, and the second dielectric layer exposes the wide bandgap dielectric layer.

5. The preparation method according to claim 4, characterized in that, The second dielectric layer is formed on the side of the gate structure away from the epitaxial structure, and after the second dielectric layer exposes the wide bandgap dielectric layer, the method further includes: An ohmic contact layer is formed on one side of the epitaxial structure exposed by the second dielectric layer.

6. The preparation method according to claim 5, characterized in that, After forming an ohmic contact layer on one side of the epitaxial structure exposed by the dielectric layer, the method further includes: A source electrode is formed on the side of the second dielectric layer, the ohmic contact layer, and the wide bandgap dielectric layer away from the substrate; A drain electrode is formed on the side of the substrate away from the epitaxial structure.

7. The preparation method according to claim 6, characterized in that, After forming the source on the side of the second dielectric layer, the ohmic contact layer, and the wide bandgap dielectric layer away from the substrate, the process includes: A passivation layer is formed on the side of the source electrode away from the epitaxial structure. The passivation layer includes a first passivation layer and a second passivation layer sequentially disposed in a direction perpendicular to the substrate.

8. A semiconductor structure, characterized in that, include: Substrate, the substrate having a first doping type; An epitaxial structure is located on one side of the substrate. The epitaxial structure includes a drift region, a well region, and a source region. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The drift region and the source region have a first doping type, and the well region has a second doping type. A source trench is located within the epitaxial structure and extends from the source region to the drift region; The first dielectric layer is located at the bottom and sidewalls of the source trench. A wide bandgap dielectric layer covers the first dielectric layer and fills the source trench; A gate trench is located within the epitaxial structure and extends from the source region to the drift region. The gate trench is located between the source trenches in a direction parallel to the substrate. A gate structure, including a gate oxide layer and a gate, is located within the gate trench.

9. The semiconductor structure according to claim 8, characterized in that, The wide bandgap dielectric layer is made of silicon carbide or gallium nitride.

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