A vertical substrate-removing p-DBR red LED chip and a preparation method thereof

Abstract

The application discloses a vertical desubstrating p-DBR red LED chip and a preparation method, and adopts a vertical structure aiming at defects of AlGaInP red LED chip GaAs substrate light absorption, DBR insulation caused reflectivity and current distribution deterioration, electrode light shielding and low heat dissipation efficiency, a multilayer epitaxial structure containing a p-type DBR reflection layer is grown by MOCVD epitaxy, and the chip is formed by bonding a Si-based CMOS driving circuit, removing a GaAs substrate by a wet method, preparing a mesa, passivation isolation and electrode preparation; the chip removes substrate light absorption loss, p-DBR reflectivity is greater than 95% and has high conductivity, the vertical structure eliminates electrode light shielding, and the Si-based substrate optimizes heat dissipation; the application makes the light extraction efficiency higher than that of a traditional normal chip by more than 65%, a current density deviation is less than 5%, a thermal resistance is reduced to less than 6K / W, the structure is compatible with the Si-based driving, the process is feasible, and the application is suitable for display, illumination and other fields.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LED chip manufacturing, in particular to a vertical substrate-removing p-DBR red light LED chip and a preparation method thereof. BACKGROUND

[0002] AlGaInP-based red light LED chips have high luminous efficiency, good stability and long service life, and thus play an important role in many fields such as display, lighting and sensor; however, the AlGaInP red light LED chips in the prior art have three major technical defects, which seriously restrict their performance improvement and application expansion.

[0003] Firstly, the light absorption loss problem of the GaAs substrate: the absorption coefficient of the GaAs substrate in the 620-650 nm red light band is as high as 10 4 cm -1, which is 2-3 orders of magnitude higher than that of the GaN substrate. Therefore, more than 50% of the chip emitted light is absorbed by the substrate, which significantly reduces the light extraction efficiency (LEE), which is one of the key bottlenecks limiting the light efficiency improvement of the red light LED chip.

[0004] Secondly, the contradiction between the conductivity and reflectivity of the traditional high-reflective DBR: the conventional high-reflective DBR (such as / system) is an insulating material, and the DBR needs to be etched and windowed when preparing the electrode, which reduces the effective reflection area of the DBR to less than 70%; at the same time, the windowed structure destroys the uniformity of the current distribution, causing the current density deviation to exceed 30%, which not only affects the uniformity of light emission, but also reduces the long-term reliability of the chip.

[0005] Thirdly, the light-heat double defects of the traditional vertical LED structure: in the traditional vertical structure, the p-side electrode is directly arranged on the light emitting surface, and the metal electrode covers an area of more than 25%, causing serious light loss; in addition, the heat dissipation path is long and inefficient, and the heat generated by the chip during operation needs to penetrate the entire epitaxial layer and the low-thermal-conductivity GaAs substrate to be transmitted to the heat dissipation substrate, resulting in a high thermal resistance of more than 20 K / W, and high temperature will accelerate the aging of the chip, further reducing the luminous efficiency and service life.

[0006] In view of the above technical problems, there is an urgent need in the art to develop a new red light LED chip structure and a preparation method which can simultaneously solve the problems of substrate light absorption, DBR performance contradiction, electrode light shielding and low-efficiency heat dissipation. SUMMARY

[0007] The present application aims at overcoming the technical defects of GaAs substrate light absorption loss, DBR insulation causing reflectivity and current distribution deterioration, p-type electrode light shielding and long heat dissipation path of the AlGaInP red light LED chip in the prior art, and provides a vertical substrate-removed p-DBR red light LED chip and a preparation method, so as to realize the synergistic optimization of light extraction efficiency, current distribution uniformity and heat dissipation performance.

[0008] To solve the above technical problems, the technical scheme adopted by the present application is:

[0009] A vertical substrate-removed p-DBR red light LED chip comprises an epitaxial structure, a bonding assembly and an electrode structure.

[0010] The epitaxial structure comprises, from bottom to top, an n-type GaAs buffer layer, an n-type etching stop layer, an n-type GaAs ohmic contact layer, an n-type limiting layer, an InGaP / quantum well structure, a p-type spacer layer, a p-type electron blocking layer, a p-type / DBR reflection layer and a p-type GaP ohmic contact layer, wherein = = = =0.5, =0.1-0.4, =0.7-1, =0.6-0.9, =0.8-0.9, =0.5, =0.9-1, =0.1-0.3.

[0011] The bonding assembly comprises a bonding metal layer and a Si-based CMOS driving circuit, the epitaxial structure is bonded to the Si-based CMOS driving circuit through the bonding metal layer, and the n-type GaAs buffer layer is away from the Si-based CMOS driving circuit on one side without a GaAs substrate.

[0012] The electrode structure comprises a p-type ITO transparent conductive layer, an n-type ITO transparent conductive layer and an n-type electrode, the p-type ITO transparent conductive layer is arranged on one side of the p-type GaP ohmic contact layer away from the p-type / DBR reflection layer, the n-type ITO transparent conductive layer is electrically connected to the n-type GaAs ohmic contact layer, and the n-type electrode is arranged on the n-type ITO transparent conductive layer.

[0013] In a preferred scheme, the p-type / DBR reflection layer is 15-25 pairs, each layer thickness is 55nm and 45nm, surface resistance is < 0.1 ohm / square, reflectivity is > 95%.

[0014] In a preferred embodiment, the bonding metal layer is a Cr / Pt / Au multilayer structure with a total thickness of 800nm, wherein the Cr layer is 300nm thick, the Pt layer is 300nm thick, and the Au layer is 200nm thick.

[0015] In a preferred embodiment, the InGaP / AlGaInP quantum well structure is 1-5 pairs of quantum wells, the InGaP well layer is 1.5-4.5nm thick, and the AlGaInP barrier layer is 4-10nm thick. In a preferred embodiment, the InGaP / AlGaInP quantum well structure is 1-5 pairs of quantum wells, the InGaP well layer is 1.5-4.5nm thick, and the AlGaInP barrier layer is 4-10nm thick.

[0016] In a preferred embodiment, the epitaxial structure further comprises a sidewall passivation layer, wherein the sidewall passivation layer is arranged on the sidewall of the epitaxial structure and has a thickness of 10-100nm.

[0017] The application also provides a preparation method of a vertical substrate-removed p-DBR red LED chip, comprising the following steps:

[0018] S1, epitaxial growth: using an MOCVD system to epitaxially grow, on a GaAs substrate, an n-type GaAs buffer layer, an n-type AlGaInP / InGaP quantum well structure, a p-type AlGaInP / InGaP quantum well structure, a p-type GaP spacer layer, a p-type GaP electron blocking layer, a p-type GaP DBR reflection layer, and a p-type GaP ohmic contact layer in sequence, to obtain an epitaxial wafer; S2, electron beam evaporation deposition of an n-type ITO transparent conductive layer and annealing: electron beam evaporation deposition of an n-type ITO transparent conductive layer on the n-type GaAs buffer layer of the epitaxial wafer, followed by high-temperature annealing; S3, bonding and substrate removal: deposition of a bonding metal layer on the p-type ITO transparent conductive layer and the front surface of a Si-based CMOS driving circuit, bonding of the two, and removal of the GaAs substrate by wet etching; S4, preparation of a mesa structure: preparation of a Micro LED mesa structure on the epitaxial wafer by photolithography and ICP etching process; S5, passivation and isolation: deposition of a passivation layer on the epitaxial wafer by PECVD, and deposition of a separation layer on the passivation layer by ICP etching process;

[0019] S6, preparation of a Micro LED chip: deposition of a bonding metal layer on the separation layer, bonding of the two, and removal of the GaAs substrate by wet etching;

[0020] S7, preparation of a Micro LED chip: deposition of a bonding metal layer on the separation layer, bonding of the two, and removal of the GaAs substrate by wet etching;

[0021] S8, preparation of a Micro LED chip: deposition of a bonding metal layer on the separation layer, bonding of the two, and removal of the GaAs substrate by wet etching;

[0022] S9, preparation of a Micro LED chip: deposition of a bonding metal layer on the separation layer, bonding of the two, and removal of the GaAs substrate by wet etching;​​​​​​ Side wall passivation layer, device isolation by IBE etching;

[0023] S6, electrode preparation: n-type ITO transparent conductive layer and n-type electrode are prepared by PECVD deposition, photolithography, ICP etching, electron beam evaporation and lift-off process.

[0024] In a preferred scheme, in step S1, the MOCVD growth parameters are as follows:

[0025] n-type GaAs buffer layer: growth temperature 620-700℃, growth rate 0.2-0.7nm / s, growth source trimethylgallium and arsine, carrier gas hydrogen, doping source ethylsilane, doping concentration , thickness 100-300nm;

[0026] n-type Etching barrier layer: growth temperature 700-780℃, growth rate 0.2-0.7nm / s, growth source trimethylaluminum, trimethylgallium, trimethylindium and phosphine, carrier gas hydrogen, doping source ethylsilane, doping concentration , thickness 100-300nm;

[0027] n-type GaAs ohmic contact layer: growth temperature 620-700℃, growth rate 0.1-0.3nm / s, growth source trimethylgallium and arsine, carrier gas hydrogen, doping source ethylsilane, doping concentration , thickness 10-50nm;

[0028] n-type Restrictive layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source trimethylaluminum, trimethylgallium, trimethylindium and phosphine, carrier gas hydrogen, doping source ethylsilane, doping concentration , thickness 150-500nm;

[0029] InGaP / Quantum well structure: growth temperature 700-780℃, growth rate 0.1-0.2nm / s, growth source trimethylaluminum, trimethylgallium, trimethylindium and phosphine, carrier gas hydrogen;

[0030] p-type Spacer layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source trimethylaluminum, trimethylgallium, trimethylindium and phosphine, carrier gas hydrogen, doping source bis-magnesium, doping concentration , thickness 30-100nm;

[0031] p-type​ The electron blocking layer is grown at a growth temperature of 700-780 DEG C, a growth rate of 0.2-0.5 nm / s, a growth source of trimethylaluminum, trimethylindium and phosphine, a carrier gas of hydrogen and a doping source of dimethyl magnesium, and the doping concentration is , and the thickness is 200-900 nm.

[0032] The p-type / The DBR reflection layer is grown at a growth temperature of 700-780 DEG C, a growth rate of 0.2-0.5 nm / s, a growth source of trimethylaluminum, trimethylindium and arsine, a carrier gas of hydrogen and a doping source of dimethyl magnesium, and the doping concentration is ;

[0033] The p-type GaP ohmic contact layer is grown at a growth temperature of 700-780 DEG C, a growth rate of 0.2-0.5 nm / s, a growth source of trimethylgallium and phosphine, a carrier gas of hydrogen and a doping source of dimethyl magnesium and carbon tetrabromide, and the doping concentration is , and the thickness is 50-300 nm.

[0034] In a preferred solution, in step S3, the solution used for wet etching is 10% ammonia water and 10% hydrogen peroxide configured in a volume ratio of 4:1, and the etching time is 30-50 minutes; the bonding temperature is 400-700 DEG C, the bonding pressure is 3000-9000 kg, and the bonding time is 10-60 minutes.

[0035] In a preferred solution, in step S4, the etching gas used for ICP etching is + The photoresist used for photolithography is positive photoresist, the developing solution is aqueous solution of tetramethylammonium hydroxide, and the developing time is 100-140 s; the diameter of the Micro LED mesa structure is 1-50 microns, and the pixel pitch is 2-75 microns.

[0036] In a preferred solution, in step S6, the target material for electron beam evaporation deposition of the n-type electrode is chromium, platinum and gold, the deposition rate is 0.1-5 nm / s, the structure of the n-type electrode is a Cr / Pt / Au multilayer structure, and the total thickness is 800 nm, wherein the thickness of the Cr layer is 300 nm, the thickness of the Pt layer is 300 nm, and the thickness of the Au layer is 200 nm.

[0037] By means of the above technical solutions, the present application has the following beneficial effects compared with the prior art:

[0038] The present application solves the three core defects of the prior art by innovative integration of the vertical structure, the GaAs substrate and the p-type AlGaAs DBR reflection layer, and achieves the following remarkable beneficial effects:

[0039] 1. Light extraction efficiency is greatly improved: by wet etching to remove high light absorption GaAs substrate (absorption coefficient > 0.1 cm-1), the light power loss of red light band (620-650 nm) is reduced by more than 50%; p-type DBR reflection layer is directly integrated on the p-side of the active area, with reflectivity of more than 95%, which improves the utilization rate of downward emitted photons by 40%; at the same time, the vertical structure moves the p-type electrode out of the light path, completely eliminating the light loss of more than 25% of the light-emitting surface in the traditional normal structure, and the three synergies make the light extraction efficiency of the chip realize a qualitative leap.

[0040] 2. Current distribution uniformity is significantly optimized: p-type DBR reflection layer has high conductivity (surface resistance < 1000 Ω / sq), without etching window like traditional insulating DBR, achieving 100% reflection area coverage, so that the current density deviation of the chip is controlled within 5%, completely solving the current congestion and local overheating problem caused by windowing in traditional structure, improving the light-emitting uniformity and long-term reliability of the chip. 3. Heat dissipation performance is greatly enhanced: using vertical bonding technology to bond the epitaxial structure with high thermal conductivity Si-based CMOS driving circuit directly, combined with the removal of GaAs substrate, the heat dissipation path is greatly shortened, the thermal resistance of the chip is reduced to below 6K / W, which is much better than the traditional normal structure of more than 20K / W, effectively reducing the working temperature of the chip, delaying the aging of the device, and significantly improving the service life and working stability of the chip.

[0041] 4. High structural compatibility and process feasibility: the chip structure of the present application is highly compatible with the existing Si-based CMOS driving technology of Micro LED display, and the preparation process is based on mature MOCVD epitaxy, electron beam evaporation, ICP etching and other technologies, without the need to introduce special equipment, which is convenient for industrialized mass production and has good industrial application prospect.

[0042] BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0044] Figure 1 It is an epitaxial structure schematic diagram of a vertical substrate-removed p-DBR red light LED chip of the present application.

[0045] ​​​​Figure 2 A schematic diagram of a vertical substrate-removed p-DBR red LED chip according to the present application;

[0046] Figure 3 A flow chart of a method for preparing a vertical substrate-removed p-DBR red LED chip according to the present application;

[0047] 1, GaAs substrate; 2, n-type GaAs buffer layer; 3, n-type etching stop layer; 4, n-type GaAs ohmic contact layer; 5, n-type confinement layer; 6, InGaP quantum well structure; 7, p-type spacer layer; 8, p-type electron blocking layer; 9, p-type DBR reflection layer; 10, p-type GaP ohmic contact layer; 11, epitaxial wafer; 12, p-type ITO transparent conductive layer; 13, bonding metal layer; 14, Si-based CMOS driving circuit; 15, side wall passivation layer; 16, n-type ITO transparent conductive layer; 17, n-type electrode. DETAILED DESCRIPTION

[0048] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts should fall within the scope of protection of the present application.

[0049] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] ​In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0051] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0052] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0053] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0054] Example 1

[0055] Please see Figure 1 and Figure 2 This application provides a vertically substrate-free p-DBR red LED chip, which forms a synergistic high-performance system through innovative design of epitaxial structure, bonding components and electrode structure. The specific technical solution is as follows:

[0056] Epitaxial structure: The epitaxial structure consists of an n-type GaAs buffer layer 2 and an n-type layer 3, arranged sequentially from bottom to top. 3. Etching barrier layer; 4. n-type GaAs ohmic contact layer; Confinement layer 5, InGaP / Quantum well structure 6, p-type Spacer layer 7, p-type Electron blocking layer 8, p-type / DBR reflective layer 9, p-type GaP ohmic contact layer 10, wherein = = = =0.5, It is 0.1-0.4. It is 0.7-1. It is 0.6-0.9. It is 0.8-0.9. It is 0.5. It is 0.9-1. It is 0.1-0.3.

[0057] Functional synergistic design of each epitaxial layer: n-type GaAs buffer layer 2 provides a flat, high-quality lattice-matched substrate for subsequent epitaxial growth; n-type Etching barrier layer 3 protects the underlying epitaxial layer from corrosion during substrate removal; n-type GaAs ohmic contact layer 4 reduces the contact resistance between the electrode and the epitaxial layer; n-type Restriction layer 5 and p-type Spacer layer 7 forms a confinement of charge carriers, improving the recombination efficiency of electrons and holes in the quantum well; InGaP / Quantum well structure 6 is the core region for light emission. Highly efficient light emission in the 620-650nm red light band is achieved by precisely controlling the thickness and composition of the well and barrier layers; p-type Electron blocking layer 8 effectively prevents electrons from escaping from the quantum well to the p-side, increasing the carrier recombination probability; p-type / The DBR reflective layer 9 is one of the core innovations. Its high reflectivity can reflect downward-emitted photons back to the direction of light emission, while its high conductivity avoids the defect of traditional insulated DBRs requiring window openings. The p-type GaP ohmic contact layer 10 ensures good ohmic contact with the subsequent ITO transparent conductive layer.

[0058] Bonding components include a bonding metal layer 13 and a Si-based CMOS driving circuit 14. The epitaxial structure is tightly bonded to the Si-based CMOS driving circuit 14 through the bonding metal layer 13, and the n-type GaAs buffer layer 2 has no GaAs substrate 1 on the side away from the Si-based CMOS driving circuit 14. The bonding metal layer 13 adopts a Cr / Pt / Au multilayer structure with a total thickness of 800nm, of which the Cr layer is 300nm thick, the Pt layer is 300nm thick, and the Au layer is 200nm thick. This structure has good conductivity, thermal conductivity, and bonding stability, and can realize a reliable electromechanical connection between the epitaxial structure and the Si-based CMOS driving circuit 14. The Si-based CMOS driving circuit 14 not only provides driving signals for the chip, but its high thermal conductivity also provides an efficient path for heat dissipation. With the removal of the GaAs substrate 1, the heat dissipation problem of traditional structures is completely solved.

[0059] Electrode structure: includes a p-type ITO transparent conductive layer 12, an n-type ITO transparent conductive layer 16, and an n-type electrode 17; the p-type ITO transparent conductive layer 12 is disposed on the p-type GaP ohmic contact layer 10 away from the p-type electrode. / One side of the DBR reflective layer 9 is prepared using an ITO target with an indium-tin molar ratio of 9:1, which combines high light transmittance and high conductivity, enabling uniform current diffusion without obstructing the light emission path. The n-type ITO transparent conductive layer 16 is electrically connected to the n-type GaAs ohmic contact layer 4 to achieve n-type interconnection of multiple chip units. The n-type electrode 17 is disposed on the n-type ITO transparent conductive layer 16 and adopts a Cr / Pt / Au multilayer structure with a total thickness of 800nm, ensuring good ohmic contact and long-term stability between the electrode and the n-type ITO transparent conductive layer 16.

[0060] Auxiliary structures: also include A sidewall passivation layer 15 is disposed on the sidewall of the epitaxial structure, with a thickness of 10-100 nm. This passivation layer can repair sidewall damage caused during mesa etching, reduce surface recombination, and at the same time achieve electrical isolation between adjacent chip units, thereby improving the reliability and stability of the device.

[0061] Example 2

[0062] Please see Figure 3 This application provides a method for fabricating a vertically substrate-removed p-DBR red LED chip. The method is based on precise control of MOCVD epitaxial growth, bonding, etching, passivation, and other processes to achieve efficient fabrication of the aforementioned chip structure. The specific steps are as follows:

[0063] S1, Epitaxial Growth: Each functional layer was sequentially epitaxially grown on GaAs substrate 1 using an MOCVD system to obtain epitaxial wafer 11. Hydrogen was used as the uniform carrier gas during the growth process. The n-type layer used disilane as the doping source, the p-type layer used magnesia-dicyclopentadiene as the doping source, and carbon tetrabromide was additionally added as a doping auxiliary source for the p-type GaP ohmic contact layer 10. The growth parameters for each layer were precisely matched.

[0064] n-type GaAs buffer layer 2: Growth temperature 620-700℃, growth rate 0.2-0.7nm / s, doping concentration... The thickness is 100-300 nm, and the growth source is trimethylgallium and hydrogen arsine;

[0065] n-type Etching barrier layer 3 ( It is 0.1-0.4. =0.5): Growth temperature 700-780℃, growth rate 0.2-0.7nm / s, doping concentration , thickness 100-300 nm, growth source trimethylaluminum, trimethylgallium, trimethylindium and phosphine;

[0066] n-type GaAs ohmic contact layer 4: growth temperature 620-700°C, growth rate 0.1-0.3 nm / s, doping concentration , thickness 10-50 nm, growth source trimethylgallium and arsine;

[0067] n-type limiting layer 5 ( 0.7-1, =0.5): growth temperature 700-780°C, growth rate 0.2-0.5 nm / s, doping concentration , thickness 150-500 nm, growth source trimethylaluminum, trimethylgallium, trimethylindium and phosphine;

[0068] InGaP / quantum well structure 6 ( 0.6-0.9, =0.5): growth temperature 700-780°C, growth rate 0.1-0.2 nm / s, number of quantum well pairs 1-5 pairs, InGaP well layer thickness 1.5-4.5 nm, barrier layer thickness 4-10 nm, growth source trimethylaluminum, trimethylgallium, trimethylindium and phosphine;

[0069] p-type spacer layer 7 ( 0.8-0.9, =0.5): growth temperature 700-780°C, growth rate 0.2-0.5 nm / s, doping concentration , thickness 30-100 nm, growth source trimethylaluminum, trimethylgallium, trimethylindium and phosphine;

[0070] p-type electron blocking layer 8 ( 0.5): growth temperature 700-780°C, growth rate 0.2-0.5 nm / s, doping concentration , thickness 200-900 nm, growth source trimethylaluminum, trimethylindium and phosphine;

[0071] p-type / DBR reflection layer 9 ( 0.9-1, 0.1-0.3): growth temperature 700-780°C, growth rate 0.2-0.5 nm / s, doping concentration Log 15-25 pairs, each layer thickness of 55 nm and 45 nm, growth source of trimethylaluminum, trimethylgallium and arsine;

[0072] p-type GaP ohmic contact layer 10: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, doping concentration , thickness 50-300nm, growth source of trimethylgallium and phosphine.

[0073] S2, evaporate p-type ITO transparent conductive layer 12 and anneal: deposit p-type ITO transparent conductive layer 12 on the p-type GaP ohmic contact layer 10 of the epitaxial wafer 11 by electron beam evaporation process, deposition rate 1nm / s, thickness 150nm; then high temperature treatment is carried out by rapid thermal annealing (RTA) machine, treatment temperature 400℃, treatment time 180s, to optimize the crystalline quality and conductivity of the ITO layer.

[0074] S3, bonding and substrate removal: first, deposit Cr / Pt / Au multi-layer bonding metal layer 13 on the p-type ITO transparent conductive layer 12 and the front surface of the Si-based CMOS drive circuit 14 respectively by electron beam evaporation process, deposition rate 0.1-5nm / s (preferably 1nm / s); then align and paste the bonding metal layer 13 on the front surface of the epitaxial wafer 11 with the front surface of the Si-based CMOS drive circuit 14, bond at 400-700℃ (preferably 500℃), 3000-9000kg (preferably 4500kg) pressure for 10-60 minutes (preferably 30 minutes) by using a large pressure bonding machine, so that the metal layers are mutually fused to form a stable electrical-mechanical connection; finally, remove the GaAs substrate 1 by using a wet etching process, the etching solution is 10% concentration of ammonia and 10% concentration of hydrogen peroxide with a volume ratio of 4:1, and the etching time is 30-50 minutes (preferably 40 minutes), the solution can selectively etch the GaAs substrate 1, while the n-type GaAs buffer layer 2 and the n-type The etching stop layer 3 is not etched obviously.

[0075] S4, mesa structure preparation: spin 500-3000nm (preferably 1500nm) thick positive photoresist (preferably type 5214) on the epitaxial wafer 11 obtained in step S3, and after curing, ultraviolet exposure is carried out, and then develop for 100-140s (preferably 120s) by using tetramethylammonium hydroxide (TMAH) aqueous solution to form a mesa pattern mask; then, by using ICP etching process, the epitaxial layer in the patterned area is removed, and a Micro LED mesa structure with a diameter of 1-50μm and a pixel pitch of 2-75μm is prepared; finally, remove the remaining photoresist by using organic solvents such as acetone / isopropyl alcohol. +

[0076] ​S5, Passivation and Isolation: A 10-100 nm thick layer is deposited on the sample surface using plasma-enhanced chemical vapor deposition (PECVD). Sidewall passivation layer 15, deposition parameters are: Flow rate 1200 sccm The plasma flow rate was 300 sccm, the plasma source power was 100 W, the deposition temperature was 250 °C, and the deposition rate was 1 nm / s. Subsequently, the device isolation was achieved by etching with an ion beam etching (IBE) process with an etching power of 300 W, an etching rate of 2 nm / s, and an etching time of 600 s. The etching penetrated the ITO buffer layer and the bonding metal layer 13 to ensure electrical isolation between adjacent devices.

[0077] S6, Electrode fabrication: First, a 300nm thick electrode is deposited using PECVD process. The mask layer deposition parameters are consistent with those in step S5; subsequently, positive resist is spin-coated and subjected to UV exposure and development to form the electrode pattern window; an ICP etching process is then used. +Ar is the etching gas ( (Flow rate 25 sccm, Ar flow rate 0 sccm), etching time 400 s, etching through to the uncoated resist layer. A mask layer is used to expose the n-type ohmic contact layer. After removing the photoresist, an n-type ITO transparent conductive layer 16 is deposited to achieve n-type interconnection. Positive resist is spin-coated again, exposed, and developed to define the n-type electrode 17 pattern. Cr / Pt / Au multilayer n-type electrode 17 is deposited using an electron beam evaporation process (the target material is pure chromium, platinum, or gold target, and the deposition rate is 0.1-5 nm / s, preferably 1 nm / s). Finally, excess metal is removed by a lift-off process (acetone / isopropanol immersion and rinsing) to obtain the target n-type electrode 17 pattern.

[0078] Example 3

[0079] This application provides a method for fabricating a vertically substrate-free p-DBR red LED chip, comprising the following steps:

[0080] S1, Epitaxial Growth: A 4-inch, 500μm thick GaAs substrate 1 with a 10° bevel angle was selected. Epitaxial growth was performed using an MOCVD system. The growth parameters for each layer are as follows:

[0081] n-type GaAs buffer layer 2: Growth temperature 650℃, growth rate 0.5nm / s, doping source silane, doping concentration... Thickness 200nm;

[0082] n-type Etching barrier layer 3 ( =0.2, =0.5): growth temperature 750°C, growth rate 0.4 nm / s, doping source ethylsilane, doping concentration , thickness 200 nm;

[0083] n-type GaAs ohmic contact layer 4: growth temperature 650°C, growth rate 0.2 nm / s, doping source ethylsilane, doping concentration , thickness 30 nm;

[0084] n-type spacer layer 5 ( =0.8, =0.5): growth temperature 750°C, growth rate 0.3 nm / s, doping source ethylsilane, doping concentration , thickness 300 nm;

[0085] InGaP / quantum well structure 6 ( =0.7, =0.5): growth temperature 750°C, growth rate 0.15 nm / s, number of quantum well pairs 3 pairs, InGaP well layer thickness 3 nm, barrier layer thickness 7 nm;

[0086] p-type spacer layer 7 ( =0.85, =0.5): growth temperature 750°C, growth rate 0.3 nm / s, doping source bis-magnesium, doping concentration , thickness 60 nm;

[0087] p-type electron blocking layer 8 ( =0.5): growth temperature 750°C, growth rate 0.3 nm / s, doping source bis-magnesium, doping concentration , thickness 500 nm;

[0088] p-type / DBR reflection layer 9 ( =0.95, =0.2): growth temperature 750°C, growth rate 0.3 nm / s, doping source bis-magnesium, doping concentration , number of pairs 20, thickness of each layer 55 nm and 45 nm, respectively;

[0089] p-type GaP ohmic contact layer 10: growth temperature 750°C, growth rate 0.3 nm / s, doping source bis-magnesium + carbon tetrabromide, doping concentration , thickness 150 nm.

[0090] S2, vapor deposition of p-type ITO transparent conductive layer 12 and annealing: electron beam evaporation deposition of 150nm thick p-type ITO transparent conductive layer 12 (indium tin molar ratio 9:1), deposition rate 1nm / s; annealing at 400℃ for 180s.

[0091] S3, Bonding and Substrate Removal: Deposit a 300nm thick Cr / 300nm thick Pt / 200nm thick Au bonding metal layer 13 at a deposition rate of 1nm / s; bond at 500℃ and 4500kg pressure for 30 minutes; remove GaAs substrate 1 by etching with a 10% ammonia + 10% hydrogen peroxide (volume ratio 4:1) solution for 40 minutes.

[0092] S4, Mesa structure fabrication: Spin-coating 1500nm thick positive resist 5214, UV exposure followed by development with TMAH aqueous solution for 120s; ICP etching ( + A micro LED mesa structure with a diameter of 20 μm and a pixel pitch of 50 μm was prepared using gas; the photoresist was removed using acetone.

[0093] S5, Passivation and Isolation: 50nm Thick Layer Deposited by PECVD Sidewall passivation layer 15 ( 1200 sccm Flow rate 300 sccm, power 100 W, temperature 250 °C, speed 1 nm / s); IBE etching (300 W, 2 nm / s, 600 s) achieves device isolation.

[0094] S6, Electrode fabrication: PECVD deposition of a 300nm thick electrode Mask layer; after photolithography and development, ICP etching ( (Flow rate 25 sccm) 400s expose n-type ohmic contact layer; deposit n-type ITO transparent conductive layer 16; re-lithographically define electrode pattern, electron beam evaporation deposit 300nm thick Cr / 300nm thick Pt / 200nm thick Au electrode; lift-off process forms n-type electrode 17.

[0095] Specific methods for performance testing:

[0096] The following test methods are all formulated in accordance with the industry standards for semiconductor optoelectronic devices (GB / T 2423 series, JEDEC standards) and LED chip test specifications to ensure the scientific nature, repeatability and comparative validity of the test results. The test environment is uniformly set as follows: room temperature 25℃±2℃, relative humidity 50%±5%, and no electromagnetic interference.

[0097] I. Light extraction efficiency test.

[0098] 1. Testing equipment:

[0099] Integrating sphere (diameter 1 m, inner coating high diffuse reflection coating);

[0100] Spectrometer (wavelength range 380-1100 nm, spectral resolution 0.1 nm);

[0101] Probe station (precision ±1 μm, supporting direct current constant current drive);

[0102] Standard optical power meter (calibration certificate within the validity period).

[0103] 2. Sample preparation:

[0104] Inventive chip: vertical substrate removal p-DBR red LED chip (bare die, mesa diameter 20 μm) prepared in the example;

[0105] Comparative sample: conventional upright AlGaInP red LED chip (with GaAs substrate, insulating DBR, p-side light emitting surface electrode) of the same epitaxial system and mesa size;

[0106] Sample fixation: the two chips are respectively pasted on transparent quartz slides (low absorption), and the probe station is used to accurately contact the electrode (avoiding light shielding).

[0107] 3. Test steps:

[0108] (1) Integrating sphere calibration: place the standard optical power meter at the light outlet of the integrating sphere, input the known power of the 630 nm standard light source, and calibrate the light power measurement accuracy of the spectrometer;

[0109] (2) Sample test: place the two chips in the center of the integrating sphere in turn, apply a 20 mA forward constant current (rated working current), record the emission spectrum of 620-650 nm band, and integrate to calculate the total light power (inventive chip), (conventional chip);

[0110] (3) Light extraction efficiency calculation: light extraction efficiency η= (Ptotal / Pstandard) × 100%, calculate the efficiency improvement ratio.

[0111] II. DBR reflectivity test.

[0112] 1. Test equipment:

[0113] Ultraviolet-visible near-infrared spectrophotometer (with integrating sphere accessory, reflectivity test mode);

[0114] High-resolution photoetching machine (used for preparing test samples);

[0115] Wet etching workstation (same etching system as chip preparation).​​

[0116] 2. Sample preparation:

[0117] p-type DBR reflector sample: p-type DBR reflector (20 pairs, same parameters as in the example) was grown on a GaAs substrate using the same MOCVD process as for the chip, and the GaAs substrate was removed by wet etching (same substrate removal process as for the chip); DBR reflector sample: p-type DBR reflector (20 pairs, same parameters as in the example) was grown on a GaAs substrate using the same MOCVD process as for the chip, and the GaAs substrate was removed by wet etching (same substrate removal process as for the chip); DBR reflector sample: p-type DBR reflector (20 pairs, same parameters as in the example) was grown on a GaAs substrate using the same MOCVD process as for the chip, and the GaAs substrate was removed by wet etching (same substrate removal process as for the chip);

[0118] Sample fixation: The DBR film was flatly attached to a low-reflectivity black background slide, ensuring no wrinkles or bubbles.

[0119] 3. Test procedure:

[0120] (1) Baseline calibration: Use a high-reflectivity standard mirror (reflectivity known, ≥99%) as a reference to calibrate the reflectivity test baseline of the spectrophotometer;

[0121] (2) Sample testing: Place the DBR sample in the integrating sphere sample stage and test the diffuse reflectance spectrum in the 620-650 nm wavelength range, recording the reflectivity values at each wavelength;

[0122] (3) Result calculation: Take the average of the reflectivity in the 620-650 nm wavelength range, which is the DBR reflectivity.

[0123] III. Current density deviation test.

[0124] 1. Test equipment:

[0125] Semiconductor parameter analyzer (supports multi-channel current-voltage testing, accuracy ±1nA);

[0126] High-resolution infrared thermal imager (temperature measurement range -20~300℃, resolution 0.01℃);

[0127] Probe station (equipped with a micro-area positioning system, positioning accuracy ±0.5μm).

[0128] 2. Sample preparation:

[0129] Select a single Micro LED mesa (diameter 20μm) of the chip of the present application, ensuring that the mesa is undamaged and the electrode contact is good;

[0130] Comparison sample: A single mesa of the same size of a conventional flip-chip.

[0131] 3. Test procedure:

[0132] ​​(1) Apply current: 20mA forward constant current is applied to the chip by the probe station, and the test is performed after 5 minutes of stabilization;

[0133] (2) Micro-area current test: 9 test points (3x3 matrix, 5um spacing) are uniformly selected on the surface of the table by using the multi-channel probe of the parameter analyzer, and the current density (J=I / S, S is the area of the test point) of each point is measured respectively;

[0134] (3) Deviation calculation: current density deviation=(Jmax-Jmin) / Javgx100%, wherein Jmax is the maximum current density, Jmin is the minimum current density, and Javg is the average current density of the 9 points.

[0135] Four, thermal resistance test (steady state method).

[0136] 1. Test equipment:

[0137] T3ster thermal resistance tester (supports direct LED junction temperature test, precision ±0.1℃);

[0138] DC regulated power supply (output current 0-1A, precision ±1mA);

[0139] Heat dissipation substrate (Si-based CMOS drive circuit substrate bonded with the chip, thermal conductivity is known).

[0140] 2. Sample preparation:

[0141] Bond / pack the chip of the application and the conventional chip on the same size Si heat dissipation substrate (size 10mmx10mmx1mm) respectively, and ensure good heat dissipation contact (no air gap);

[0142] Sample aging: age for 1h under the rated current to eliminate initial thermal stress.

[0143] 3. Test steps:

[0144] (1) Cold state test: measure the surface temperature of the heat dissipation substrate when the chip is not powered on (Environmental temperature);

[0145] (2) Steady heating: 20mA forward constant current is applied to the chip, and the power is continuously turned on until the temperature is stable (temperature change≤0.1℃ within 10min), and the substrate surface temperature at this time is recorded ;

[0146] (3) Junction temperature test: measure the chip junction temperature by using the "voltage-temperature coefficient method" of T3ster tester (The forward voltage of AlGaInP material changes with temperature coefficient, about-1.5mV / ℃);

[0147] (4) Thermal resistance calculation: thermal resistance Rth= (V x I) / P, where V is the forward voltage of the chip, I is the working current, and P is the power. -

[0148] Five, 620-650 nm band luminous intensity test.

[0149] 1. Test equipment:

[0150] Integrating sphere spectrometer (same as light extraction efficiency test equipment);

[0151] Standard luminous intensity calibration lamp (630 nm, known luminous intensity).

[0152] 2. Sample preparation:

[0153] The chip of the present application and the conventional chip for light extraction efficiency test have the same packaging method (lensless bare packaging).

[0154] 3. Test steps:

[0155] (1) Instrument calibration: use the standard calibration lamp to calibrate the luminous intensity measurement accuracy of the spectrometer;

[0156] (2) Sample test: place the two chips in the integrating sphere respectively, apply 20 mA forward constant current, record the emission spectrum of 620-650 nm band, and extract the peak luminous intensity (the present application), (conventional chip);

[0157] (3) Improvement ratio calculation: luminous intensity improvement ratio = (I - ) / (I ) x 100%.

[0158] Six, long-term stability test (accelerated aging method).

[0159] 1. Test equipment:

[0160] High and low temperature and humidity test chamber (temperature range -40~150℃, humidity range 10%~95%RH);

[0161] Integrating sphere spectrometer (same as above);

[0162] Chip aging board (supports multiple chip constant current driving, current stability ±0.5%).

[0163] 2. Sample preparation:

[0164] Select 10 chips of the present application and package them in standard LED holders to ensure reliable electrical connection; ​

[0165] Initial testing: Testing the initial luminous intensity of each chip. .

[0166] 3. Testing steps:

[0167] (1) Aging conditions: The test chamber temperature was set to 85℃ and the relative humidity to 85%RH. A positive constant current of 20mA was applied to the aging plate, and the aging was carried out continuously for 1000h.

[0168] (2) Periodic testing: After aging for 100h, 500h, and 1000h, the samples were taken out and cooled to room temperature (25℃) to test the luminescence intensity. , , ;

[0169] (3) Calculation of attenuation rate: Attenuation rate of luminous intensity over 1000 hours = ( - ) / ×100%, take the average value of 10 chips as the final result.

[0170] The results of the performance testing using the methods described above are as follows:

[0171] Light extraction efficiency: more than 65% higher than traditional standard chips;

[0172] DBR reflectivity: 96.2%;

[0173] Current density deviation: 3.8%;

[0174] Thermal resistance: 5.2K / W;

[0175] Luminous intensity in the 620-650nm band: more than 70% higher than traditional chips;

[0176] After 1000 hours of continuous operation, the luminous intensity decay rate is <5%.

[0177] Example 4

[0178] This application provides a method for fabricating a vertically substrate-free p-DBR red LED chip, comprising the following steps:

[0179] S1, Epitaxial Growth: A 2-inch, 350μm thick GaAs substrate with a 2° bevel angle was selected. Epitaxial growth was performed using an MOCVD system. The growth parameters for each layer are as follows:

[0180] n-type GaAs buffer layer 2: Growth temperature 620℃, growth rate 0.2nm / s, doping source silane, doping concentration... Thickness 100nm;

[0181] n-type Etch stopper layer 3 (GaAs) = 0.1, = 0.5): growth temperature 700°C, growth rate 0.2 nm / s, doping source ethylsilane, doping concentration , thickness 100 nm;

[0182] n-type GaAs ohmic contact layer 4: growth temperature 620°C, growth rate 0.1 nm / s, doping source ethylsilane, doping concentration , thickness 10 nm;

[0183] n-type Confinement layer 5 (GaAs) = 0.7, = 0.5): growth temperature 700°C, growth rate 0.2 nm / s, doping source ethylsilane, doping concentration , thickness 150 nm;

[0184] InGaP / Quantum well structure 6 (InGaP / GaAs) = 0.6, = 0.5): growth temperature 700°C, growth rate 0.1 nm / s, number of quantum well pairs 1 pair, InGaP well layer thickness 1.5 nm, barrier layer thickness 4 nm;

[0185] p-type Spacer layer 7 (GaAs) = 0.8, = 0.5): growth temperature 700°C, growth rate 0.2 nm / s, doping source bis-magnesium, doping concentration , thickness 30 nm;

[0186] p-type Electron blocking layer 8 (GaAs) = 0.5): growth temperature 700°C, growth rate 0.2 nm / s, doping source bis-magnesium, doping concentration , thickness 200 nm;

[0187] p-type / DBR reflection layer 9 (GaAs) = 0.9, = 0.1): growth temperature 700°C, growth rate 0.2 nm / s, doping source bis-magnesium, doping concentration , number of pairs 15 pairs, thickness of each layer 55 nm and 45 nm, respectively;

[0188] p-type GaP ohmic contact layer 10: growth temperature 700°C, growth rate 0.2 nm / s, doping source bis-magnesium + carbon tetrabromide, doping concentration , thickness 50 nm.

[0189] S2, deposition of p-type ITO transparent conductive layer 12 and annealing: electron beam evaporation deposition of 150 nm thick p-type ITO transparent conductive layer 12 (molar ratio of indium and tin 9:1), deposition rate 1 nm / s; annealing at 400°C for 180 s.

[0190] S3, bonding and substrate removal: deposition of 300 nm thick Cr / 300 nm thick Pt / 200 nm thick Au bonding metal layer 13, deposition rate 0.1 nm / s; bonding at 400°C, 3000 kg pressure for 10 minutes; removal of GaAs substrate 1 by etching with 10% ammonia water + 10% hydrogen peroxide (volume ratio 4:1) solution for 30 minutes.

[0191] S4, preparation of mesa structure: spin coating of 500 nm thick positive resist 5214, UV exposure, and development with TMAH aqueous solution for 100 s; ICP etching (300 W, 25 sccm, 400 s) to prepare Micro LED mesa structure with a diameter of 1 μm and a pixel pitch of 2 μm; removal of photoresist by acetone. +

[0192] S5, passivation and isolation: PECVD deposition of 10 nm thick passivation layer 15 (SiO2, 1200 sccm, flow rate 300 sccm, power 100 W, temperature 250°C, rate 1 nm / s); IBE etching (300 W, 2 nm / s, 600 s) to achieve device isolation.

[0193] S6, electrode preparation: PECVD deposition of 300 nm thick mask layer; after photolithography and development, ICP etching (300 W, 25 sccm) to expose n-type ohmic contact layer for 400 s; deposition of n-type ITO transparent conductive layer 16; photolithography again to define electrode pattern, electron beam evaporation deposition of 300 nm thick Cr / 300 nm thick Pt / 200 nm thick Au electrode; Lift-off process to form n-type electrode 17.

[0194] Performance test results:

[0195] Light extraction efficiency: 65% higher than traditional flip chip;

[0196] DBR reflectivity: 95.0%;

[0197] Current density deviation: 4.8%;

[0198] Thermal resistance: 5.8 K / W;

[0199] ​​​620-650nm waveband luminous intensity: 70% higher than traditional chips;

[0200] 1000h continuous working luminous intensity decay rate: 4.9%.

[0201] Example Five

[0202] The application provides a preparation of a vertical debonding p-DBR red LED chip, comprising the following steps:

[0203] S1, epitaxial growth: select a 12-inch, 650-μm-thick, 15°-bevelled GaAs substrate 1, use a MOCVD system for epitaxial growth, and the growth parameters of each layer are as follows:

[0204] n-type GaAs buffer layer 2: growth temperature 700℃, growth rate 0.7nm / s, doping source ethylsilane, doping concentration , thickness 300nm;

[0205] n-type etching stop layer 3 ( =0.4, =0.5): growth temperature 780℃, growth rate 0.7nm / s, doping source ethylsilane, doping concentration , thickness 300nm;

[0206] n-type GaAs ohmic contact layer 4: growth temperature 700℃, growth rate 0.3nm / s, doping source ethylsilane, doping concentration , thickness 50nm;

[0207] n-type limiting layer 5 ( =1, =0.5): growth temperature 780℃, growth rate 0.5nm / s, doping source ethylsilane, doping concentration , thickness 500nm;

[0208] InGaP / quantum well structure 6 ( =0.9, =0.5): growth temperature 780℃, growth rate 0.2nm / s, quantum well pairs 5 pairs, InGaP well layer thickness 4.5nm, barrier layer thickness 10nm;

[0209] p-type spacer layer 7 ( =0.9, =0.5): growth temperature 780℃, growth rate 0.5nm / s, doping source metallocene, doping concentration , thickness 100nm;

[0210] p-type electron blocking layer 8 (p-type) =0.5): growth temperature 780℃, growth rate 0.5nm / s, doping source dimethyl magnesium, doping concentration , thickness 900nm;

[0211] p-type / DBR reflection layer 9 (p-type) =1, =0.3): growth temperature 780℃, growth rate 0.5nm / s, doping source dimethyl magnesium, doping concentration , 25 pairs of logarithm, each layer thickness is 55nm and 45nm respectively;

[0212] p-type GaP ohmic contact layer 10: growth temperature 780℃, growth rate 0.5nm / s, doping source dimethyl magnesium + carbon tetrabromide, doping concentration , thickness 300nm.

[0213] S2, evaporate p-type ITO transparent conductive layer 12 and anneal: electron beam evaporation deposition 150nm thick p-type ITO transparent conductive layer 12 (molar ratio of indium and tin 9:1), deposition rate 1nm / s; anneal at 400℃ for 180s.

[0214] S3, bonding and substrate removal: deposit 300nm thick Cr / 300nm thick Pt / 200nm thick Au bonding metal layer 13, deposition rate 5nm / s; bond at 700℃, 9000kg pressure for 60 minutes; remove GaAs substrate 1 by etching with 10% ammonia water + 10% hydrogen peroxide (volume ratio 4:1) solution for 50 minutes.

[0215] S4, mesa structure preparation: spin 3000nm thick positive resist 5214, develop with TMAH aqueous solution for 140s after ultraviolet exposure; ICP etching (O2+H2) + gas) to prepare Micro LED mesa structure with diameter 50μm and pixel pitch 75μm; remove photoresist with acetone.

[0216] S5, passivation and isolation: PECVD deposit 100nm thick side wall passivation layer 15 (p-type) 1200sccm, flow rate 300sccm, power 100W, temperature 250℃, rate 1nm / s); IBE etching (300W, 2nm / s, 600s) to achieve device isolation.

[0217] S6, electrode preparation: PECVD deposit 300nm thick Mask layer; after photolithography and development, ICP etching Flow 25sccm) 400s Exposure n-type ohmic contact layer; deposition of n-type ITO transparent conductive layer 16; photolithography to define electrode pattern again, electron beam evaporation deposition of 300nm thick Cr / 300nm thick Pt / 200nm thick Au electrode; Lift-off process to form n-type electrode 17.

[0218] Performance test results:

[0219] Light extraction efficiency: 72% higher than traditional flip chip;

[0220] DBR reflectivity: 97.5%;

[0221] Current density deviation: 3.2%;

[0222] Thermal resistance: 4.5K / W;

[0223] 620-650nm waveband luminous intensity: 78% higher than traditional chip;

[0224] 1000h continuous working luminous intensity attenuation rate: 3.8%.

[0225] The test results show that the chip of the present application is significantly better than the prior art in light efficiency, current uniformity, heat dissipation performance and stability, and achieves the expected technical effect.

[0226] Finally, it should be noted that the above is only the preferred embodiment of the present application and is not intended to limit the present application, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments or make equivalent replacement for part of the technical features, any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A vertical debonding p-DBR red LED chip, characterized in that, The application relates to an epitaxial structure, a bonding assembly and an electrode structure. The epitaxial structure is sequentially from bottom to top n-type GaAs buffer layer, n-type etching stop layer, n-type GaAs ohmic contact layer, n-type limiting layer, InGaP quantum well structure, p-type spacer layer, p-type electron blocking layer, p-type / DBR reflection layer, p-type GaP ohmic contact layer, wherein = = = = 0.5, = 0.1-0.4, = 0.7-1, = 0.6-0.9, = 0.8-0.9, = 0.5, = 0.9-1, = 0.1-0.3; The bonding assembly comprises a bonding metal layer and a Si-based CMOS driving circuit, the epitaxial structure is bonded with the Si-based CMOS driving circuit through the bonding metal layer, and the n-type GaAs buffer layer is away from the GaAs substrate on one side of the Si-based CMOS driving circuit. The electrode structure comprises a p-type ITO transparent conductive layer, an n-type ITO transparent conductive layer and an n-type electrode, the p-type ITO transparent conductive layer is arranged on the side of the p-type GaP ohmic contact layer far from the p-type / DBR reflection layer, the n-type ITO transparent conductive layer is electrically connected with the n-type GaAs ohmic contact layer, and the n-type electrode is arranged on the n-type ITO transparent conductive layer. 2.The vertical debonding p-DBR red LED chip according to claim 1, wherein, The p-type / The DBR reflective layer has 15-25 pairs of layers, with thicknesses of 55nm and 45nm respectively, and a sheet resistivity of < Reflectivity > 95%. 3.The vertical debonding p-DBR red LED chip according to claim 1, wherein, The bonding metal layer is a Cr / Pt / Au multilayer structure with a total thickness of 800 nm, wherein the thickness of the Cr layer is 300 nm, the thickness of the Pt layer is 300 nm, and the thickness of the Au layer is 200 nm. 4.The vertical debonding p-DBR red LED chip according to claim 1, wherein, The InGaP The quantum well structure has 1-5 pairs of quantum wells, and the InGaP well layer has a thickness of 1.5-4.5 nm, The barrier layer has a thickness of 4-10 nm. 5.The vertical debonding p-DBR red LED chip according to claim 1, wherein, Also includes Sidewall passivation layer, the The sidewall passivation layer is located on the sidewall of the epitaxial structure and has a thickness of 10-100 nm.

6. A method for preparing a vertical desorption p-DBR red LED chip, characterized in that, The application further discloses a preparation method of the epitaxial structure. S1, epitaxial growth: using MOCVD system, epitaxially growing n-type GaAs buffer layer, n-type etching stop layer, n-type GaAs ohmic contact layer, n-type limiting layer, InGaP / quantum well structure, p-type spacer layer, p-type electron blocking layer, p-type / DBR reflection layer, p-type GaP ohmic contact layer, to obtain an epitaxial wafer; S2, evaporating a p-type ITO transparent conductive layer and annealing: evaporating and depositing a p-type ITO transparent conductive layer on the p-type GaP ohmic contact layer of the epitaxial wafer by means of an electron beam, and then performing high-temperature annealing; S3, bonding and substrate removal: depositing a bonding metal layer on the p-type ITO transparent conductive layer and the front surface of the Si-based CMOS driving circuit respectively, bonding the two, and then removing the GaAs substrate by means of wet etching; S4, preparing a mesa structure: preparing a Micro LED mesa structure on the epitaxial wafer by means of a photoetching and ICP etching process; S5, passivation and isolation: PECVD deposition Side wall passivation layer, device isolation by IBE etching; S6, electrode preparation: deposition by PECVD Mask layer, photolithography, ICP etching, electron beam evaporation and lift-off process, preparation of n-type ITO transparent conductive layer and n-type electrode.

7. The method for fabricating a vertically substrate-removed p-DBR red LED chip according to claim 6, characterized in that, In step S1, the MOCVD growth parameters are as follows: The n-type GaAs buffer layer is grown at a temperature of 620-700℃, a growth rate of 0.2-0.7nm / s, a growth source of trimethyl gallium and arsine, a carrier gas of hydrogen, a doping source of disilane, and a doping concentration of 100-300nm in thickness. n-type Etching barrier layer: growth temperature 700-780℃, growth rate 0.2-0.7 nm / s, growth source is trimethylaluminum, trimethylgallium, trimethylindium and phosphine, carrier gas is hydrogen, doping source is silane, doping concentration is [missing information]. The thickness is 100-300nm; n-type GaAs ohmic contact layer: growth temperature 620-700℃, growth rate 0.1-0.3nm / s, growth source is trimethyl gallium and arsine, carrier gas is hydrogen, doping source is ethylsilane, doping concentration is 10 18 cm 3, thickness is 10-50nm; n-type Confinement layer: Growth temperature 700-780℃, growth rate 0.2-0.5 nm / s, growth source is trimethylaluminum, trimethylgallium, trimethylindium, and phosphine, carrier gas is hydrogen, doping source is silane, doping concentration is [missing information]. The thickness is 150-500 nm; InGaP Quantum well structure: growth temperature 700-780℃, growth rate 0.1-0.2 nm / s, growth source is trimethylaluminum, trimethylgallium, trimethylindium and phosphine, carrier gas is hydrogen; p-type Spacer layer: Growth temperature 700-780℃, growth rate 0.2-0.5 nm / s, growth source is trimethylaluminum, trimethylgallium, trimethylindium and phosphine, carrier gas is hydrogen, doping source is magnesia, doping concentration is [missing information]. The thickness is 30-100nm; p-type Electron blocking layer: growth temperature 700-780℃, growth rate 0.2-0.5 nm / s, growth source is trimethylaluminum, trimethylindium, and phosphine, carrier gas is hydrogen, doping source is magnesia, doping concentration is [missing information]. The thickness is 200-900 nm; p-type / DBR reflection layer: growth temperature 700-780°C, growth rate 0.2-0.5 nm / s, growth source trimethylaluminum, trimethylindium and arsine, carrier gas hydrogen, doping source dimethyl magnesium, doping concentration 1.0 x 1018cm"3 ; p-type GaP ohmic contact layer: growth temperature 700-780℃, growth rate 0.2-0.5 nm / s, growth source is trimethylgallium and phosphine, carrier gas is hydrogen, doping source is magnesia-dicenocene and carbon tetrabromide, doping concentration is [missing information]. The thickness is 50-300nm.

8. The method for fabricating a vertically substrate-removed p-DBR red LED chip according to claim 6, characterized in that, In step S3, the solution used for wet etching is 10% ammonia water and 10% hydrogen peroxide configured in a volume ratio of 4:1, the etching time is 30-50 minutes, the bonding temperature is 400-700 DEG C, the bonding pressure is 3000-9000 kg, and the bonding time is 10-60 minutes.

9. The method for fabricating a vertically substrate-removed p-DBR red LED chip according to claim 6, characterized in that, In step S4, the etching gas for ICP etching is + , the photoresist used for photolithography is positive photoresist, the developing solution is a tetramethylammonium hydroxide aqueous solution, and the developing time is 100-140s; the diameter of the Micro LED mesa structure is 1-50μm, and the pixel pitch is 2-75μm.

10. The method for fabricating a vertically substrate-removed p-DBR red LED chip according to claim 6, characterized in that, In step S6, the target material for evaporating and depositing the n-type electrode by means of an electron beam is chromium, platinum and gold, the deposition rate is 0.1-5 nm / s, the n-type electrode is a Cr / Pt / Au multilayer structure with a total thickness of 800 nm, wherein the thickness of the Cr layer is 300 nm, the thickness of the Pt layer is 300 nm, and the thickness of the Au layer is 200 nm.

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