A low-power four-phase distributed digital low-dropout linear voltage regulator

Abstract

The application relates to a low-power four-phase distributed digital low-voltage difference linear voltage stabilizer, belonging to the technical field of electronic circuits, comprising a four-phase clock circuit and four digital LDO subunits connected to the same load network; the four-phase clock circuit is used for converting an input clock signal into clock signals with the same frequency and different phases through a clock phase adjustment channel composed of four frequency dividers and three inverters, and outputting the clock signals to the connected four digital LDO subunits for time sharing and phase control; the digital LDO subunit is used for comparing the size of an output voltage of the subunit with two reference voltages through an internal voltage judgment circuit composed of double comparators and a fast trigger loop composed of a controller, and stably controlling the output voltage between the two reference voltages according to the voltage comparison. The application effectively optimizes the transient response speed and power consumption of the digital LDO.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a low-power four-phase distributed digital low-dropout linear regulator. Background Technology

[0002] With the increasing prevalence and complexity of portable electronic devices, their internal control chips need to integrate and manage more and more processing units, functional modules, and peripheral circuits, ultimately forming a complete System-on-a-Chip (SoC). Within a limited physical space, the SoC undertakes critical tasks such as computing, communication, and multimedia processing, and its performance directly determines the user experience of the terminal device. To meet the requirements of miniaturization, thinness, and long battery life, the performance of the power management system that powers the SoC becomes crucial. Specifically, the power management system must be low-power to extend battery life and highly efficient to reduce waste during energy conversion.

[0003] In SoC power management solutions, low-dropout linear regulators (LDOs) are widely used to provide clean and stable power supplies for noise-sensitive analog and digital modules due to their simple structure, low output ripple voltage, and fast response. LDOs are divided into analog LDOs and digital LDOs. Analog LDOs regulate voltage by adjusting the on-resistance of the power transistors through an error amplifier in a negative feedback loop. However, this structure has relatively high quiescent power consumption, especially under light load conditions, where efficiency drops significantly, making it difficult to meet the extreme energy efficiency requirements of modern portable devices. Digital LDOs use quantization control based on a single comparator and digital logic circuits (such as shift registers or state machines) to dynamically switch parallel power transistor arrays. Their power consumption is related to the load current, achieving extremely high efficiency under both light and heavy loads. However, existing digital LDO architectures face a key challenge: achieving a good trade-off between transient response speed and quiescent power consumption. To achieve fast transient response, a high sampling clock frequency and complex control logic are required, but this will lead to a sharp increase in power consumption under no-load or light-load conditions. Conversely, if a lower clock frequency and simpler control logic are used to reduce power consumption, the response will be slow when the load current changes abruptly, resulting in a large overshoot or undershoot of the output voltage, which threatens the stability and reliability of the SoC function. Summary of the Invention

[0004] Therefore, it is necessary to provide a low-power four-phase distributed digital low-dropout linear regulator to address the above-mentioned technical problems. This regulator can inherit the advantages of high efficiency and low power consumption of digital LDOs while ensuring that its transient response speed is not affected, thereby meeting the stringent requirements of SoCs for power management chips in advanced portable devices.

[0005] A low-power four-phase distributed digital low-dropout linear regulator includes a four-phase clock circuit and four digital LDO sub-units connected to the same load network.

[0006] The four-phase clock circuit is used to convert the input clock signal into a clock signal with the same frequency but different phases through a clock phase adjustment path consisting of four frequency dividers and three inverters, and outputs it to four connected digital LDO sub-units for time-division and phase-division control.

[0007] The digital LDO subunit is used to compare its own output voltage with two reference voltages through an internal voltage judgment circuit composed of dual comparators and a fast trigger loop composed of a controller, and quickly responds to control the output voltage to stabilize between the two reference voltages based on the voltage comparison.

[0008] Furthermore, the clock phase adjustment path, consisting of four frequency dividers and three inverters, includes frequency dividers DIV1 to DIV4 and the first inverter to the third inverter;

[0009] The clock input terminal of the frequency divider DIV1 directly receives the input clock signal CLKIN, and outputs the divided clock signal to the first digital LDO subunit via the non-inverting output terminal.

[0010] The clock input terminal of the frequency divider DIV2 receives the inverted CLKIN signal from the first inverter and outputs the divided clock signal to the second digital LDO subunit via the non-inverting output terminal.

[0011] The clock input terminal of the frequency divider DIV3 receives the CLKIN signal after it has been inverted by the first inverter and the second inverter in sequence, and outputs the divided clock signal to the third digital LDO subunit via the inverted output terminal.

[0012] The clock input of the frequency divider DIV4 receives the CLKIN signal after it has been inverted by the first inverter, the second inverter, and the third inverter in sequence, and outputs the divided clock signal to the fourth digital LDO subunit via the inverted output.

[0013] Furthermore, frequency dividers DIV1 to DIV4 are frequency divider circuits consisting of the inverted output terminal of a D-type flip-flop and the data input terminal short-circuited. The frequency of the output clock signal is 1 / 2 of the frequency of the input clock signal CLKIN.

[0014] Furthermore, the phases of the clock signals output by frequency dividers DIV1 to DIV4 are 90°, 180°, 270° and 360°, respectively.

[0015] Furthermore, the digital LDO subunit consists of a first comparator, a second comparator, a controller, a power transistor array, and fast-response power transistors;

[0016] The first comparator has its input connected to the lower limit reference voltage VrefL and its output connected to the controller's US input. The second comparator has its input connected to the upper limit reference voltage VrefH and its output connected to the controller's OS input. The controller's SR OUT output is connected to the gate of each power transistor in the power transistor array, and the controller's TRIG output is connected to the gate of the fast-response power transistor. The drains of each power transistor in the power transistor array and the fast-response power transistor are all connected to a unified input voltage VIN. The sources of each power transistor in the power transistor array and the fast-response power transistor are connected to the output voltage VOUT. The source of the fast-response power transistor is also connected to a grounded capacitor, and the output voltage VOUT is also connected to a grounded load.

[0017] Furthermore, when the output voltage VOUT of the digital LDO subunit is less than the lower reference voltage VrefL, the output CMPL of the first comparator changes from low to high, while the output CMPH of the second comparator remains low. The controller uses the high-level CMPL to control the fast-response power transistor and the power transistor array to control the output voltage VOUT until the output voltage VOUT is greater than or equal to the lower reference voltage VrefL. When the output voltage VOUT of the digital LDO subunit is greater than the upper reference voltage VrefH, the output CMPH of the second comparator changes from low to high, while the output CMPL of the first comparator remains low. The controller uses the high-level CMPH to control the power transistor array to control the output voltage VOUT until the output voltage VOUT is less than or equal to the upper reference voltage VrefH. When the output voltage VOUT of the digital LDO subunit is between the lower reference voltage VrefL and the upper reference voltage VrefH, both the output CMPL of the first comparator and the output CMPH of the second comparator remain low.

[0018] Furthermore, the clock input of the controller is also connected to the clock inputs of the first comparator and the second comparator to keep their operating clocks consistent.

[0019] Furthermore, the controller consists of a shift register, a counter, a trigger controller, and an XOR gate; among them, the fast trigger loop composed of the counter, the trigger controller, and the XOR gate is used to improve the transient response speed of the digital LDO subunit under light load conditions.

[0020] The shift register receives the OS signal from the controller's OS input terminal and the US signal from the US input terminal, and increments or decrements the data based on these signals. When the OS signal is high and the US signal is low, the data in the shift register decreases by 1 per clock cycle; when the US signal is high and the OS signal is low, the data in the shift register increases by 1 per clock cycle. The OS signal indicates a decrease in load current, causing the output voltage VOUT of the digital LDO subunit to rise and exceed the upper reference voltage VrefH; the US signal indicates an increase in load current, causing the output voltage VOUT of the digital LDO subunit to fall below the lower reference voltage VrefL.

[0021] The trigger controller receives the data value SR output from the shift register, determines the load state of the digital LDO subunit based on the magnitude of SR, and then controls the level of the enable signal CTEN output to the counter. It also receives the status signal CTON output from the counter and outputs the Trdown signal to the XOR gate. Specifically, when SR is less than 6, the current load state is determined to be lightly loaded, and the enable signal CTEN is high. In this case, the level of the Trdown signal is controlled by both the status signal CTON and the US signal. When SR is greater than or equal to 6, the current load state is determined to be medium or higher, and the enable signal CTEN is low. In this case, the level of the Trdown signal is controlled by the US signal and maintains the same level as the US signal.

[0022] The counter receives the US signal input from the US input terminal and the enable signal CTEN output from the trigger controller, and turns the counting on or off according to the levels of the US signal and the enable signal CTEN. Specifically, when both the US signal and the enable signal CTEN are high, the counting is started, and the counting is completed and turned off after four cycles. In the non-counting state, the status signal CTON output by the counter is low, and in the counting state, the status signal CTON output by the counter is high.

[0023] The XOR gate is used to receive the US signal input from the US input terminal and the Trdown signal output from the trigger controller. Based on the levels of the US signal and the Trdown signal, it controls the level of the trigger signal TRIG output from the TRIG output terminal of the controller. Specifically, when the levels of the US signal and the Trdown signal are different, the trigger signal TRIG is high; when the levels of the US signal and the Trdown signal are the same, the trigger signal TRIG is low.

[0024] Furthermore, the controller also includes a level converter array connected to the output of the shift register and a level converter connected to the output of the XOR gate. The level converter array and the level converter are used to convert the output levels of the shift register and the XOR gate from the core voltage to the IO voltage, respectively.

[0025] The aforementioned low-power four-phase distributed digital low-dropout linear regulator includes a four-phase clock circuit and four digital LDO sub-units connected to the same load network. By utilizing the four-phase clock circuit to perform time-division and phase-division control on the four digital LDO sub-units, the transient response speed of the digital LDOs can be improved while ensuring system stability. Through a voltage judgment circuit composed of dual comparators in the digital LDO sub-units, the output voltage can be stabilized between two reference voltages, eliminating the limit cycle oscillation (LCO) formed within the digital LDO and reducing its static power consumption. Furthermore, through a fast trigger loop composed of a controller in the digital LDO sub-units, the transient response speed of the digital LDO under light load conditions is improved. In summary, this application can improve the transient response speed of the digital LDO while ensuring low static power consumption, reducing the power consumption control pressure of the SOC. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the overall structure of a low-power four-phase distributed digital low-dropout linear regulator in one embodiment.

[0027] Figure 2 This is a schematic diagram of the controller's operating waveforms in one embodiment; wherein, Figure 2 (a) is a schematic diagram of the controller's operating waveforms under light load in the initial state; Figure 2 (b) is a schematic diagram of the controller's operating waveforms under medium load in the initial state.

[0028] Figure 3 This is a schematic diagram comparing the load response and power consumption of this application with that of a traditional digital LDO in one embodiment; wherein, Figure 3 (a) is a schematic diagram comparing load response; Figure 3 (b) is a schematic diagram comparing the power consumption composition. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0030] In one embodiment, such as Figure 1As shown, a low-power four-phase distributed digital low-dropout linear regulator is provided, including: a four-phase clock circuit and four digital LDO sub-units (DLDO PHASE1 to DLDO PHASE4) connected to the same load network.

[0031] The four-phase clock circuit is used to convert the input clock signal into a clock signal with the same frequency but different phases through a clock phase adjustment path consisting of four frequency dividers and three inverters, and outputs it to four connected digital LDO sub-units for time-division and phase-division control.

[0032] The digital LDO subunit is used to compare its own output voltage with two reference voltages through an internal voltage judgment circuit composed of dual comparators and a fast trigger loop composed of a controller, and quickly responds to control the output voltage to stabilize between the two reference voltages based on the voltage comparison.

[0033] It should be understood that the aforementioned low-power four-phase distributed digital low-dropout linear regulator uses a four-phase clock circuit to perform time-division and phase-division control on the four digital LDO sub-units, uses a voltage judgment circuit composed of dual comparators in the digital LDO sub-units to control the output voltage to stabilize between two reference voltages, and uses the fast system regulation capability brought by the fast trigger loop in the controller to improve the transient response speed of the digital LDO while ensuring that the digital LDO has low static power consumption, thus reducing the power consumption control pressure of the SOC.

[0034] Furthermore, such as Figure 1 As shown, the clock phase adjustment path, consisting of four frequency dividers and three inverters, includes frequency dividers DIV1 to DIV4 and the first inverter to the third inverter. Figure 1 A triangle with a circle inside represents an inverter.

[0035] The clock input terminal of frequency divider DIV1 directly receives the input clock signal CLKIN and outputs the divided clock signal to the first digital LDO subunit DLDO PHASE1 via the non-inverting output terminal; the clock input terminal of frequency divider DIV2 receives CLKIN after being inverted by the first inverter and outputs the divided clock signal to the second digital LDO subunit DLDOPHASE2 via the non-inverting output terminal; the clock input terminal of frequency divider DIV3 receives CLKIN after being inverted by the first and second inverters in sequence and outputs the divided clock signal to the third digital LDO subunit DLDO PHASE3 via the inverting output terminal; the clock input terminal of frequency divider DIV4 receives CLKIN after being inverted by the first, second, and third inverters in sequence and outputs the divided clock signal to the fourth digital LDO subunit DLDO PHASE4 via the inverting output terminal. Figure 1In the clock input, CLK is the clock input and OUT is the non-inverting output. The non-inverting output terminal is the inverting output terminal, and the phase difference between the non-inverting output terminal and the inverting output terminal is 180°.

[0036] Furthermore, such as Figure 1 As shown, frequency dividers DIV1 to DIV4 are connected by the inverting outputs of D-type flip-flops. The frequency divider circuit formed by shorting the data input terminal D outputs a clock signal with a frequency that is half the frequency of the input clock signal CLKIN. Figure 1 Q represents the non-inverting output of a D-type flip-flop.

[0037] Furthermore, the phases of the clock signals output by frequency dividers DIV1 to DIV4 are 90°, 180°, 270° and 360°, respectively.

[0038] It should be understood that using a four-phase clock circuit to perform time-division and phase-division control on the four digital LDO subunits has the following advantages: 1. The clock frequency of each digital LDO subunit is only half the frequency of the input clock signal CLKIN, making it easier for the digital LDO subunits to maintain system stability and prevent oscillations. 2. The four digital LDO subunits operate in different phases, making the system's detection frequency for output voltage changes twice the actual input frequency, improving the system's response speed to output voltage changes, and ultimately optimizing the system's transient performance. 3. The four-phase clock circuit can control the four digital LDO subunits to operate sequentially, simplifying the control logic of distributed digital LDOs and effectively reducing the problem of uneven operation of distributed digital LDOs.

[0039] Furthermore, such as Figure 1 As shown, the digital LDO subunit consists of a first comparator CMP1, a second comparator CMP2, a controller, a power transistor array Ma, and a fast-response power transistor MTR.

[0040] In this circuit, the input of the first comparator CMP1 is connected to the lower limit reference voltage VrefL, and its output is connected to the US input of the controller. The input of the second comparator CMP2 is connected to the upper limit reference voltage VrefH, and its output is connected to the OS input of the controller. The SR OUT output of the controller is connected to the gate of each power transistor in the power transistor array Ma, and the TRIG output of the controller is connected to the gate of the fast-response power transistor MTR. The drains of each power transistor in the power transistor array Ma and the fast-response power transistor MTR are all connected to a unified input voltage VIN. The sources of each power transistor in the power transistor array Ma and the fast-response power transistor MTR are connected to the output voltage VOUT. The source of the fast-response power transistor MTR is also connected to a grounded capacitor. The output voltage VOUT is also connected to the grounded load Load. Figure 1 The " / " on the center line indicates that the bit width of the signal line is greater than 1, meaning that multiple signals are transmitted on the line simultaneously.

[0041] Furthermore, the technical logic for output voltage control in the digital LDO subunit, which uses a voltage judgment circuit composed of dual comparators, is as follows: When the output voltage VOUT of the digital LDO subunit is less than the lower limit reference voltage VrefL, the output CMPL of the first comparator CMP1 changes from low to high, while the output CMPH of the second comparator CMP2 remains low. The controller controls the fast-response power transistor and the power transistor array through the high-level CMPL to control the output voltage VOUT until the output voltage VOUT is greater than or equal to the lower limit reference voltage VrefL; when the output voltage VOUT of the digital LDO subunit is less than the lower limit reference voltage VrefL, the output voltage VOUT changes from low to high. When T is greater than the upper reference voltage VrefH, the output CMPH of the second comparator CMP2 changes from low to high, and the output CMPL of the first comparator CMP1 remains low. The controller controls the power transistor array to control the output voltage VOUT through the high-level CMPH until the output voltage VOUT is less than or equal to the upper reference voltage VrefH. When the output voltage VOUT of the digital LDO subunit is between the lower reference voltage VrefL and the upper reference voltage VrefH, the output CMPL of the first comparator CMP1 and the output CMPH of the second comparator CMP2 both remain low.

[0042] It should be understood that the voltage judgment circuit composed of dual comparators in the digital LDO subunit can control the output voltage to be stable between two reference voltages, eliminating the limiting loop formed inside the digital LDO and reducing the static power consumption of the digital LDO.

[0043] Furthermore, the clock input of the controller is also connected to the clock inputs of the first comparator and the second comparator to keep their operating clocks consistent.

[0044] Furthermore, such as Figure 1 As shown, the controller consists of a shift register, a counter (CONTER), a trigger controller (TRCT), and an XOR gate. The fast trigger loop formed by the counter (CONTER), trigger controller (TRCT), and XOR gate is used to improve the transient response speed of the digital LDO subunit under light load conditions. The controller's operating waveform is shown below. Figure 2 As shown, Figure 2 (a) shows the controller operating waveform when the digital LDO subunit is initially under light load. Figure 2 (b) shows the controller operating waveform when the digital LDO subunit is initially in a medium-load state. Figure 2 In the middle, DC represents the data within the counter COUNTER.

[0045] The shift register receives the OS signal from the controller's OS input terminal and the US signal from the US input terminal, and increments or decrements the data based on the OS and US signals. When the OS signal is high and the US signal is low, the data in the shift register decreases by 1 per clock cycle; when the US signal is high and the OS signal is low, the data in the shift register increases by 1 per clock cycle. The OS signal indicates that a decrease in load current has occurred, which will cause the output voltage VOUT of the digital LDO subunit to rise and exceed the upper limit reference voltage VrefH; the US signal indicates that an increase in load current has occurred, which will cause the output voltage VOUT of the digital LDO subunit to fall below the lower limit reference voltage VrefL.

[0046] The trigger controller TRCT receives the data value SR output from the shift register, determines the load state of the digital LDO subunit based on the magnitude of SR, and then controls the level of the enable signal CTEN output to the counter CONTER. It also receives the status signal CTON output from the counter CONTER and outputs the Trdown signal to the XOR gate. Specifically, when SR is less than 6, the current load state is determined to be light, and the enable signal CTEN is high. In this case, the level of the Trdown signal is controlled by the status signal CTON and the US signal. When SR is greater than or equal to 6, the current load state is determined to be medium or higher, and the enable signal CTEN is low. In this case, the level of the Trdown signal is controlled by the US signal and maintains the same level as the US signal. The Trdown signal is an intermediate value in the controller's calculations and has no specific meaning; its main purpose is to work with the US signal to control the fast-response power transistor.

[0047] The counter CONTER receives the US signal input from the US input terminal and the enable signal CTEN output from the trigger controller TRCT. It turns the counting on or off based on the levels of the US signal and the enable signal CTEN. When both the US signal and the enable signal CTEN are high, the counting is turned on. After four cycles, the counting is completed and the counting is turned off. In the non-counting state, the status signal CTON output by the counter CONTER is low. In the counting state, the status signal CTON output by the counter CONTER is high.

[0048] The XOR gate is used to receive the US signal input from the US input terminal and the Trdown signal output from the trigger controller TRCT. Based on the levels of the US signal and the Trdown signal, it controls the level of the trigger signal TRIG output from the TRIG output terminal of the controller. Specifically, when the levels of the US signal and the Trdown signal are inconsistent, the trigger signal TRIG is high; when the levels of the US signal and the Trdown signal are consistent, the trigger signal TRIG is low.

[0049] Furthermore, the controller also includes a level shift array connected to the output of the shift register and a level shifter connected to the output of the XOR gate. The level shift array and the level shifter are used to convert the output levels of the shift register and the XOR gate from the core voltage to the I / O voltage, respectively. This allows for a reduction in the size of the power transistor array while ensuring high efficiency of the digital LDO.

[0050] It should be understood that the comparator's level controls the controller's output adjustment, and the controller's output controls the power transistors. The power transistor array is controlled by the shift register output SR in the controller via a level shifter array. The fast-response power transistors are controlled by the counter (COUNTER), trigger controller (TRCT), and XOR gate in the controller via level shifters. The fast-response power transistors are used to quickly adjust the output voltage when the load current increases in a digital LDO subunit under light load conditions, reducing the voltage drop caused by the increased load current. The power transistor array can also be used to quickly adjust the output voltage when the load current decreases in a digital LDO subunit under medium or heavy load conditions, preventing a voltage rise caused by the decreased load current; it also has the function of suppressing voltage drops caused by increased load current.

[0051] To verify the beneficial effects of this application, the performance of the low-power four-phase distributed digital low-dropout linear regulator provided in this application was compared with that of a traditional digital LDO (based on a single comparator). Figure 3 As shown, the evaluation metrics include load response and power consumption. Figure 3As shown in (a), when a traditional digital LDO is in a stable operating state, the discrete output of the power transistor array and the quantization error of the comparator can lead to a limit cycle in the system, which causes ripple in the system output. The low-power four-phase distributed digital low-dropout linear regulator proposed in this application utilizes the reference voltage dead time formed by dual comparators to effectively remove the limit cycle in the system, thereby eliminating output ripple. Furthermore, the fast trigger loop composed of the counter CONTER, counter controller TRCT, and XOR gate in this application effectively improves the transient response speed of the system under light load conditions and reduces Vdrop caused by load changes. Figure 3 As shown in (b), since the digital LDO sub-unit in this application does not have a limit cycle, the dynamic power consumption generated during data path oscillation is effectively avoided, thereby effectively reducing the total power consumption of the digital LDO system during stable operation. Therefore, compared with the prior art, this application can inherit the advantages of high efficiency and low power consumption of digital LDO, while ensuring that its transient response speed is not affected, thus meeting the stringent requirements of SoC for power management chips in advanced portable devices.

[0052] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A low power consumption four-phase distributed digital low-dropout linear voltage regulator, characterized in that, The four-phase clock circuit and four digital LDO subunits connected to the same load network are included. The four-phase clock circuit is used to convert the input clock signal into clock signals with the same frequency and different phases through a clock phase adjustment path composed of four frequency dividers and three inverters, and output to the connected four digital LDO subunits for time sharing and phase control; wherein the clock frequency of each digital LDO subunit is 1 / 2 of the input clock signal frequency, and the four digital LDO subunits work in different phases, and the detection frequency of the output voltage change reaches twice the actual input frequency. The digital LDO subunit is used to compare the size of its own output voltage with two reference voltages through an internal voltage judgment circuit composed of double comparators and a fast trigger loop composed of a controller, and quickly respond to control the output voltage to be stable between the two reference voltages according to the voltage comparison; The controller is composed of a shift register, a counter, a trigger controller and an XOR gate; wherein the fast trigger loop composed of the counter, the trigger controller and the XOR gate is used to improve the transient response speed of the digital LDO subunit in the light load state; The shift register is used to receive the OS signal input from the OS input end and the US signal input from the US input end of the controller, and increase or decrease the data according to the OS signal and the US signal; when the OS signal is high and the US signal is low, the data in the shift register decreases by 1 every clock cycle; when the US signal is high and the OS signal is low, the data in the shift register increases by 1 every clock cycle; wherein the OS signal indicates that a load current reduction event has occurred, which will cause the output voltage VOUT of the digital LDO subunit to rise and exceed the upper limit reference voltage VrefH; the US signal indicates that a load current increase event has occurred, which will cause the output voltage VOUT of the digital LDO subunit to drop below the lower limit reference voltage VrefL; The trigger controller is used to receive the data value SR output by the shift register, judge the load state of the digital LDO subunit according to the size of SR, and then control the level of the enable signal CTEN output to the counter, and output the Trdown signal to the XOR gate by receiving the state signal CTON output by the counter; wherein when SR is less than 6, it is judged that the current load state is light load, the enable signal CTEN is high, at this time the level of Trdown signal is controlled by the state signal CTON and the US signal; when SR is greater than or equal to 6, it is judged that the current load state is medium load and above, the enable signal CTEN is low, at this time the level of Trdown signal is controlled by the US signal and keeps consistent with the level of the US signal; The four-phase clock circuit and four digital LDO subunits connected to the same load network are included. The four-phase clock circuit is used to convert the input clock signal into clock signals with the same frequency and different phases through a clock phase adjustment path composed of four frequency dividers and three inverters, and output to the connected four digital LDO subunits for time sharing and phase control; wherein the clock frequency of each digital LDO subunit is 1 / 2 of the input clock signal frequency, and the four digital LDO subunits work in different phases, and the detection frequency of the output voltage change reaches twice the actual input frequency. The digital LDO subunit is used to compare the size of its own output voltage with two reference voltages through an internal voltage judgment circuit composed of double comparators and a fast trigger loop composed of a controller, and quickly respond to control the output voltage to be stable between the two reference voltages according to the voltage comparison; The controller is composed of a shift register, a counter, a trigger controller and an XOR gate; wherein the fast trigger loop composed of the counter, the trigger controller and the XOR gate is used to improve the transient response speed of the digital LDO subunit in the light load state; The shift register is used to receive the OS signal input from the OS input end and the US signal input from the US input end of the controller, and increase or decrease the data according to the OS signal and the US signal; when the OS signal is high and the US signal is low, the data in the shift register decreases by 1 every clock cycle; when the US signal is high and the OS signal is low, the data in the shift register increases by 1 every clock cycle; wherein the OS signal indicates that a load current reduction event has occurred, which will cause the output voltage VOUT of the digital LDO subunit to rise and exceed the upper limit reference voltage VrefH; the US signal indicates that a load current increase event has occurred, which will cause the output voltage VOUT of the digital LDO subunit to drop below the lower limit reference voltage VrefL; The trigger controller is used to receive the data value SR output by the shift register, judge the load state of the digital LDO subunit according to the size of SR, and then control the level of the enable signal CTEN output to the counter, and output the Trdown signal to the XOR gate by receiving the state signal CTON output by the counter; wherein when SR is less than 6, it is judged that the current load state is light load, the enable signal CTEN is high, at this time the level of Trdown signal is controlled by the state signal CTON and the US signal; when SR is greater than or equal to 6, it is judged that the current load state is medium load and above, the enable signal CTEN is low, at this time the level of Trdown signal is controlled by the US signal and keeps consistent with the level of the US signal; The counter is used for receiving the US signal input by the US input and the enable signal CTEN output by the trigger controller, and starting or stopping counting according to the levels of the US signal and the enable signal CTEN; when the US signal and the enable signal CTEN are both high levels, the counting is started, the counting is completed after four periods and the counting is stopped, and the state signal CTON output by the counter is a low level in the non-counting state and a high level in the counting state; The XOR gate is used for receiving the US signal input by the US input and the Trdown signal output by the trigger controller, and controlling the level of the trigger signal TRIG output by the TRIG output end of the controller according to the levels of the US signal and the Trdown signal; when the levels of the US signal and the Trdown signal are inconsistent, the trigger signal TRIG is a high level; and when the levels of the US signal and the Trdown signal are consistent, the trigger signal TRIG is a low level.

2. The low-power four-phase distributed digital low-dropout linear voltage regulator of claim 1, wherein, The clock phase adjustment path composed of four frequency dividers and three inverters includes the frequency dividers DIV1 to DIV4 and the first to third inverters; The clock input end of the frequency divider DIV1 directly receives the input clock signal CLKIN and outputs the frequency-divided clock signal to the first digital LDO subunit through the non-inverted output end; The clock input end of the frequency divider DIV2 receives the CLKIN inverted by the first inverter and outputs the frequency-divided clock signal to the second digital LDO subunit through the non-inverted output end; The clock input end of the frequency divider DIV3 receives the CLKIN inverted by the first inverter and the second inverter in sequence and outputs the frequency-divided clock signal to the third digital LDO subunit through the inverted output end; The clock input end of the frequency divider DIV4 receives the CLKIN inverted by the first inverter, the second inverter and the third inverter in sequence and outputs the frequency-divided clock signal to the fourth digital LDO subunit through the inverted output end.

3. The low power consumption four-phase distributed digital low-dropout linear voltage regulator of claim 2, wherein, The frequency dividers DIV1 to DIV4 are two-frequency division circuits composed of the inverted output end and the data input end of the D-type flip-flop, and the frequencies of the output clock signals are all 1 / 2 of the frequency of the input clock signal CLKIN.

4. The low-power four-phase distributed digital low-dropout linear voltage regulator according to claim 2 or 3, characterized in that, The phases of the clock signals output by the frequency dividers DIV1 to DIV4 are 90°, 180°, 270° and 360° respectively.

5. The low power consumption four-phase distributed digital low-dropout linear voltage regulator of claim 1, wherein, The digital LDO subunit is composed of the first comparator, the second comparator, the controller, the power transistor array and the fast-response power transistor. The input end of the first comparator is connected with a lower limit reference voltage VrefL, and the output end is connected with the US input end of the controller; the input end of the second comparator is connected with an upper limit reference voltage VrefH, and the output end is connected with the OS input end of the controller; the SR OUT output end of the controller is connected with the gate of each power transistor in the power transistor array, and the TRIG output end of the controller is connected with the gate of the fast response power transistor; the drain of each power transistor in the power transistor array and the fast response power transistor is connected with a unified input voltage VIN, and the source of each power transistor in the power transistor array and the fast response power transistor is connected with an output voltage VOUT, and the source of the fast response power transistor is also connected with a capacitor grounded, and the output voltage VOUT is also connected with a load grounded.

6. The low-power four-phase distributed digital low-dropout linear voltage regulator of claim 5, wherein, When the output voltage VOUT of the digital LDO subunit is less than the lower limit reference voltage VrefL, the output CMPL of the first comparator changes from low level to high level, the output CMPH of the second comparator remains low level, the controller controls the fast response power transistor and the power transistor array to control the output voltage VOUT through the high-level CMPL until the output voltage VOUT is greater than or equal to the lower limit reference voltage VrefL; when the output voltage VOUT of the digital LDO subunit is greater than the upper limit reference voltage VrefH, the output CMPH of the second comparator changes from low level to high level, the output CMPL of the first comparator remains low level, the controller controls the power transistor array to control the output voltage VOUT through the high-level CMPH until the output voltage VOUT is less than or equal to the upper limit reference voltage VrefH; when the output voltage VOUT of the digital LDO subunit is between the lower limit reference voltage VrefL and the upper limit reference voltage VrefH, the output CMPL of the first comparator and the output CMPH of the second comparator remain low level.

7. The low power consumption four-phase distributed digital low-dropout linear voltage regulator according to claim 5, wherein, The clock input end of the controller is also connected with the clock input ends of the first comparator and the second comparator, for keeping the working clock of the three consistent.

8. The low power consumption four-phase distributed digital low-dropout linear voltage regulator of claim 1, wherein, The controller further comprises a level converter array connected with the output end of the shift register and a level converter connected with the output end of the XOR gate, and the level converter array and the level converter are respectively used for converting the output level of the shift register and the XOR gate from a core voltage to an IO voltage.

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