Circuit schematic diagram generation method and device based on dual-channel graph learning model

Abstract

The application relates to a circuit schematic diagram generation method and device based on a double-channel graph learning model, wherein the method comprises the following steps: acquiring a circuit schematic diagram file, wherein the circuit schematic diagram file comprises file label information and core design information; constructing a graph structure transformation model based on the file label information and the core design information, and transforming the circuit schematic diagram file into a bill of materials file and a netlist file based on the graph structure transformation model; aligning the bill of materials file and the netlist file with the circuit schematic diagram file to obtain graph structure data; and predicting the graph structure data based on a pre-constructed double-channel graph node classification model to obtain a target node prediction result, and generating a circuit schematic diagram based on the target node prediction result, thereby solving the problems of weak circuit schematic diagram automatic design capability and low efficiency in related technical engineering design, improving the circuit schematic diagram automatic design capability, and improving the circuit design efficiency.

Description

Technical Field

[0001] This invention relates to the field of power electronics automation design technology, and in particular to a method and apparatus for generating circuit schematics based on a dual-channel graph learning model. Background Technology

[0002] Currently, new power systems are constantly generating diverse application scenarios and increasingly diversified performance requirements for power electronic equipment, necessitating the use of relevant computer-aided design or design automation software to complete detailed design and deliver it for production and testing.

[0003] Related technologies mainly employ deep learning and reinforcement learning methods, such as using reward mechanisms to ensure that key performance indicators meet the prescribed standards, thereby achieving reverse design optimization, or new auxiliary design methods based on Large Language Model (LLM) to obtain circuit design suggestions by interacting with intelligent agents through natural language.

[0004] However, research on related technologies mainly focuses on optimizing principle-based topologies, with limited attention paid to automating complete engineering schematics. This results in weak and inefficient automated design capabilities for circuit schematics in engineering design, which urgently needs to be addressed. Summary of the Invention

[0005] This invention provides a circuit schematic generation method and apparatus based on a dual-channel graph learning model to solve the problems of weak automated circuit schematic design capability and low efficiency in related technology engineering design, thereby improving the automated circuit schematic design capability and increasing the efficiency of circuit design.

[0006] A first aspect of the present invention provides a method for generating circuit schematics based on a dual-channel graph learning model, comprising the following steps: obtaining a circuit schematic file, the circuit schematic file including file tag information and core design information; constructing a graph structure conversion model based on the file tag information and the core design information, and converting the circuit schematic file into a bill of materials (BOM) file and a netlist file based on the graph structure conversion model, and aligning the BOM file and the netlist file with the circuit schematic file to obtain graph structure data; predicting the graph structure data based on a pre-constructed dual-channel graph node classification model to obtain target node prediction results, and generating a circuit schematic based on the target node prediction results.

[0007] Furthermore, in some embodiments, the step of constructing a graph structure conversion model based on the file tag information and the core design information, and converting the circuit schematic file into a bill of materials (BOM) file and a netlist file based on the graph structure conversion model, includes: identifying and deleting duplicate information in the file tag information and the core design information using a preset MD5 hash value identification method to obtain a preprocessed circuit schematic file; and classifying the preprocessed circuit schematic file based on a preset data processing method to obtain the BOM file and the netlist file.

[0008] Furthermore, in some embodiments, aligning the bill of materials file and the netlist file with the schematic file to obtain graph structure data includes: establishing a mapping function between the format features of the bill of materials file and the netlist file and the graphical elements in the schematic file; and aligning the bill of materials file and the netlist file with the schematic file based on the mapping function to generate the graph structure data.

[0009] Furthermore, in some embodiments, before predicting the graph structure data based on a pre-built dual-channel graph node classification model to obtain the target node prediction result, the method further includes: constructing a node information channel and a node type channel; and obtaining the dual-channel graph node classification model based on the node information channel and the node type channel.

[0010] Furthermore, in some embodiments, the step of predicting the graph structure data based on a pre-built dual-channel graph node classification model to obtain target node prediction results, and generating a circuit schematic based on the target node prediction results, includes: acquiring neighboring node information of the target node; capturing semantic associations and positional dependencies between neighboring nodes based on the node information channels, and outputting hidden features containing semantic and positional information; capturing nonlinear associations based on the node type channels, and outputting an aggregated representation of type features; calculating the probability that the target node belongs to various types of components based on the hidden features containing semantic and positional information and the aggregated representation of type features, and obtaining a prediction probability calculation result; and generating the circuit schematic based on the prediction probability calculation result.

[0011] The circuit schematic generation method based on a dual-channel graph learning model provided by the present invention obtains the original circuit schematic file, constructs a graph structure transformation model and converts it into a bill of materials and netlist file, aligns the bill of materials and netlist file with the original circuit schematic to obtain graph structure data, and then uses a dual-channel graph node classification model to predict and generate the circuit schematic. This solves the problems of weak automated design capability and low efficiency of circuit schematics in related technology engineering design, improves the automated design capability of circuit schematics, and enhances the efficiency of circuit design.

[0012] A second aspect of the present invention provides a circuit schematic generation apparatus based on a dual-channel graph learning model. The apparatus includes: an acquisition module for acquiring a circuit schematic file, the circuit schematic file including file tag information and core design information; a construction module for constructing a graph structure conversion model based on the file tag information and the core design information, and converting the circuit schematic file into a bill of materials (BOM) file and a netlist file based on the graph structure conversion model, and aligning the BOM file and the netlist file with the circuit schematic file to obtain graph structure data; and a generation module for predicting the graph structure data based on a pre-constructed dual-channel graph node classification model to obtain target node prediction results, and generating a circuit schematic based on the target node prediction results.

[0013] Furthermore, in some embodiments, the construction module is specifically used to: identify and delete duplicate information of the file tag information and the core design information using a preset MD5 hash value identification method to obtain a preprocessed circuit schematic file; and classify the preprocessed circuit schematic file based on a preset data processing method to obtain the bill of materials file and the netlist file.

[0014] Furthermore, in some embodiments, the construction module is also used to: establish a mapping function between the format features of the bill of materials file and the netlist file and the graphical elements in the circuit schematic file; and based on the mapping function, align the bill of materials file and the netlist file with the circuit schematic file to generate the graph structure data.

[0015] Furthermore, in some embodiments, before predicting the graph structure data based on a pre-built dual-channel graph node classification model to obtain the target node prediction result, the construction module is further configured to: construct a node information channel and a node type channel; and obtain the dual-channel graph node classification model based on the node information channel and the node type channel.

[0016] Furthermore, in some embodiments, the generation module is specifically used for: acquiring neighboring node information of the target node; capturing semantic associations and positional dependencies between neighboring nodes based on the node information channel, and outputting hidden features containing semantic and positional information; capturing nonlinear associations based on the node type channel, and outputting an aggregated representation of type features; calculating the probability that the target node belongs to various types of components based on the hidden features containing semantic and positional information and the aggregated representation of type features, and obtaining a predicted probability calculation result; and generating the circuit schematic based on the predicted probability calculation result.

[0017] The circuit schematic generation device based on a dual-channel graph learning model provided in this embodiment of the invention obtains the original circuit schematic file, constructs a graph structure conversion model and converts it into a bill of materials and netlist file, aligns the bill of materials and netlist file with the original circuit schematic to obtain graph structure data, and then uses a dual-channel graph node classification model to predict and generate a circuit schematic. This solves the problems of weak automated design capability and low efficiency of circuit schematics in related technology engineering design, improves the automated design capability of circuit schematics, and enhances the efficiency of circuit design.

[0018] A third aspect of the present invention provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the circuit schematic generation method based on the dual-channel graph learning model described in the above embodiments.

[0019] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, the program being executed by a processor to implement the circuit schematic generation method based on a dual-channel graph learning model as described in the above embodiments.

[0020] A fifth aspect of the present invention provides a computer program product, including a computer program that is executed to implement the circuit schematic generation method based on a dual-channel graph learning model as described in the above embodiments.

[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 This invention provides a circuit schematic generation method based on a dual-channel graph learning model, according to an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram of a data processing system structure according to a specific embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the proportions of circuit elements provided according to a specific embodiment of the present invention;

[0026] Figure 4 A schematic diagram of the circuit structure of a CLLC converter according to a specific embodiment of the present invention;

[0027] Figure 5This is a schematic diagram of the graph structure data of a CLLC converter according to a specific embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of a dual-channel graph node classification model structure provided according to a specific embodiment of the present invention;

[0029] Figure 7 This is a block diagram of a circuit schematic generation device based on a dual-channel graph learning model provided according to an embodiment of the present invention.

[0030] Figure 8 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present invention. Detailed Implementation

[0031] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0032] The following description, with reference to the accompanying drawings, illustrates a circuit schematic generation method and apparatus based on a dual-channel graph learning model according to embodiments of the present invention. Addressing the issues of weak automated circuit schematic design capabilities and low efficiency in engineering design mentioned in the background art, the present invention provides a circuit schematic generation method based on a dual-channel graph learning model. This method obtains the original circuit schematic file, constructs a graph structure conversion model, and converts it into a bill of materials (BOM) and netlist file. After aligning the BOM and netlist file with the original circuit schematic, graph structure data is obtained. Then, a dual-channel graph node classification model is used for prediction and generation of the circuit schematic. This solves the problem of weak automated circuit schematic design capabilities and low efficiency in related engineering design, improves the automated design capabilities of circuit schematics, and enhances the efficiency of circuit design.

[0033] Specifically, Figure 1 This invention provides a circuit schematic generation method based on a dual-channel graph learning model according to an embodiment of the present invention.

[0034] like Figure 1 As shown, the circuit schematic generation method based on the dual-channel graph learning model includes the following steps:

[0035] In step S101, a circuit schematic file is obtained, which includes file tag information and core design information.

[0036] Among them, circuit schematic files refer to graphical files that describe the circuit structure in power electronic equipment. File tag information refers to the identification information attached to the circuit schematic file itself, which does not involve specific circuit design content, such as file format, file size, etc. Core design information refers to the substantive design information in the circuit schematic file that reflects the circuit function, such as circuit components and their connection relationships.

[0037] Specifically, the file tag information of the circuit schematic file can be obtained through the computer system or the system's built-in file management tool. The core design information of the circuit schematic file can be extracted by calling the application programming interface through an automated program. The original schematic files are then associated through a data processing system to form structured core design data.

[0038] In step S102, a graph structure conversion model is constructed based on file tag information and core design information. Based on the graph structure conversion model, the circuit schematic file is converted into a bill of materials file and a netlist file. The bill of materials file and netlist file are then aligned with the circuit schematic file to obtain graph structure data.

[0039] Among them, the graph structure conversion model refers to the processing model that converts the graphical design information of the circuit schematic into graph structure data; the bill of materials (BOM) file refers to the structured list file that records the detailed attributes of all components in the circuit schematic, including information such as the type, specifications, quantity and unique identifier of each component in the schematic; and the netlist file refers to the structured file that records the electrical connection relationship between components in the circuit schematic, including a text description of the correspondence between component pins and connection nodes.

[0040] Specifically, in this embodiment of the invention, based on the tag information of the circuit schematic file, compliant files are selected. Then, by calling the industry standard software API through the constructed graph structure transformation model, the schematic is automatically extracted into a bill of materials file that records component attributes and a netlist file that records connection relationships. Subsequently, a mapping relationship is established between the bill of materials file, the netlist file, and the circuit schematic. Finally, the components in the bill of materials file are converted into graph nodes, and the connection relationships in the netlist file are converted into graph edges, forming graph structure data that integrates component attributes and connection semantics.

[0041] It should be noted that due to the significant differences in encoding formats between schematic files, directly parsing the detailed information in the files would require developing dedicated decomposition tools for each format, which would greatly increase technical complexity and processing costs, and would be difficult to be compatible with all formats. Therefore, the filtering process does not delve into the specific design content of the file, but instead utilizes the inherent attributes of the file that are independent of the encoding format to achieve rapid filtering.

[0042] In some embodiments, a graph structure conversion model is constructed based on file tag information and core design information. Based on the graph structure conversion model, the circuit schematic file is converted into a bill of materials (BOM) file and a netlist file. This includes: identifying and deleting duplicate information in the file tag information and core design information using a preset (Message-Digest Algorithm 5, MD5) hash value recognition method to obtain a preprocessed circuit schematic file; and classifying the preprocessed circuit schematic file based on a preset data processing method to obtain a BOM file and a netlist file.

[0043] The preset MD5 hash value recognition method refers to a method that quickly determines whether the contents of different files are completely consistent by calculating the MD5 hash value of the file (i.e., a 128-bit digital fingerprint that uniquely corresponds to the file content). The preset data processing method refers to a data processing method that integrates the preprocessed circuit schematic file into a bill of materials file and a netlist file.

[0044] Specifically, for the input circuit schematic file, the MD5 hash value of the circuit schematic file is calculated and used as an identifier of the circuit schematic file content. If two circuit schematic files have the same hash value, they are determined to be duplicates, and one file is kept while the other duplicate files are deleted. Then, based on the preset industry standard software API interface, the preprocessed circuit schematic file is formatted and adapted. Component information is extracted from the schematic and organized into a structured bill of materials (BOM) file. At the same time, the electrical connection relationship between components is parsed to generate a netlist file (NETLIST), generating BOM and NETLIST files that conform to specific format specifications.

[0045] For example, Figure 2 This is a schematic diagram of a data processing system structure according to a specific embodiment of the present invention, such as... Figure 2 As shown, in the data filtering system, the MD5 hash value recognition method is used to detect duplicate content in file tag information and core design information. The duplicate detection part can identify duplicate files with the same hash value and then delete these duplicate files to obtain the preprocessed circuit schematic file. After the preprocessing is completed, the preprocessed circuit schematic file is classified after format conversion. By extracting component information and topology from the schematic file, it is organized into bill of materials file and netlist file respectively.

[0046] Furthermore, in power electronics scenarios, passive components such as resistors and capacitors constitute a large proportion of all components in a power electronics schematic. However, other components that play a crucial role in circuit function have a relatively small share in the overall component distribution. The detailed classification within these less abundant components further reduces the proportion of each specific type, thereby amplifying the imbalance between passive and active components in the schematic data. Figure 3 This is a schematic diagram of circuit elements according to a specific embodiment of the present invention, such as... Figure 3 As shown, resistors and capacitors account for nearly 70%, while key components account for too small a proportion. In order to solve the problem of high proportion of passive components in power electronics schematics, this embodiment of the invention enhances node features by combining additional component information extracted from NETLIST.

[0047] Specifically, each element in the netlist partial list is treated as a tag, and the 4000 most frequently occurring tags are selected to construct a hot-coded dictionary.

[0048] It should be noted that although the dictionary size can theoretically be defined arbitrarily, the dimension of the resulting one-hot encoded feature matrix increases quadratically with the dictionary size, which significantly increases the computational complexity of the entire model. Therefore, to achieve a balance between model performance and computational efficiency, a dictionary size of 4000 is adopted.

[0049] Furthermore, in some embodiments, the bill of materials (BOM) file and netlist file are aligned with the circuit schematic file to obtain graph structure data, including: establishing a mapping function between the format features of the BOM file and netlist file and the graphical elements in the circuit schematic file; and aligning the BOM file and netlist file with the circuit schematic file based on the mapping function to generate graph structure data.

[0050] Specifically, by analyzing the graphical elements in the schematic diagram, such as component symbols and component connections, as well as the format characteristics in the bill of materials and netlist files, the correspondence rules between them are determined. After establishing the mapping function, the function is used to align the bill of materials file, netlist file, and circuit schematic diagram file. Through the mapping function, the information in the bill of materials and netlist is accurately matched with the graphical elements in the schematic diagram. This information is then integrated to generate graph structure data that can graphically display the component connection relationships and other information in the circuit.

[0051] For example, Figure 4 This is a schematic diagram of the circuit structure of a CLLC converter according to a specific embodiment of the present invention. Figure 5 This is a schematic diagram of the graph structure data of a CLLC converter according to a specific embodiment of the present invention, combined with... Figure 4 and Figure 5 As shown, the (Capacitor-Inductor-Inductor-Capacitor, CLLC) resonant DC-DC converter circuit is simplified, which is a transformation from the circuit system of practical engineering application to the principle topology. For example, the switching transistor is simplified to a switch, and the corresponding driving circuit is omitted. The current and voltage measurement and feedback parts in the circuit are also removed, and more emphasis is placed on showing the basic working principle of the circuit and the connection relationship of the components.

[0052] In step S103, based on the pre-built dual-channel graph node classification model, the graph structure data is predicted to obtain the target node prediction result, and a circuit schematic is generated based on the target node prediction result.

[0053] In some embodiments, before predicting the graph structure data based on a pre-built dual-channel graph node classification model to obtain the target node prediction result, the method further includes: constructing a node information channel and a node type channel; and obtaining a dual-channel graph node classification model based on the node information channel and the node type channel.

[0054] Specifically, the dual-channel graph node classification model models the semantic information of circuit elements and the structural relationships between them, thereby making full use of these two types of information to improve prediction accuracy. In order to ensure the consistency between the training process and the actual deployment scenario, when using the masking training mechanism, a target node is randomly selected and its feature information and category label are masked. Then, prediction is made only based on the information of adjacent nodes.

[0055] For example, Figure 6 This is a schematic diagram of a dual-channel graph node classification model structure provided according to a specific embodiment of the present invention, such as... Figure 6 As shown, for the node information channel, the entire computational pipeline mainly consists of a positional encoding component and an encoder module. In the node information channel, component attributes are treated as semantic tags, similar to the representations used in natural language processing (NLP) tasks. Triangular positional encoding is applied to distinguish positional relationships within component information vectors. This method assigns a unique positional identifier to each element in the sequence, enabling the model to capture sequence-related features. The adoption of positional encoding ensures that the positional structure of components is explicitly represented, which is crucial for learning accurate semantic relevance.

[0056] Furthermore, after positional encoding, the node information vector is processed by the encoder module of the Transformer architecture, such as the BERT encoder, to compute hidden representations containing semantic and positional information. In addition, the multi-head attention mechanism within the encoder enhances the model's ability to capture the interactions and correlations between circuit components, allowing the model to learn the latent structural dependencies embedded in the circuit topology, thereby improving the accuracy and reasonableness of node prediction.

[0057] Furthermore, in the node type channel, an embedding layer is first used to perform initial encoding and dimensionality transformation, thereby mitigating potential confusion and numerical instability when using raw integer values ​​to represent component types. After embedding, a graph aggregation layer is applied to aggregate node type features. The main model used in this layer is a Graph Attention Network (GAT). GAT uses a graph attention mechanism to dynamically assign different aggregation weights to neighboring nodes, thereby emphasizing information from more important neighbors. To address the limitation of the graph attention mechanism in modeling the nonlinear interactions between different components in power electronics schematics due to it being a linear operator, this embodiment of the invention adds a Multi-Layer Perceptron (MLP) after each GAT. The nonlinear activation function in the MLP introduces nonlinear transformations, enhancing the model's ability to capture complex component relationships.

[0058] Furthermore, in some embodiments, based on a pre-built dual-channel graph node classification model, graph structure data is predicted to obtain target node prediction results, and a circuit schematic is generated based on the target node prediction results. This includes: acquiring information about the neighboring nodes of the target node; capturing semantic associations and positional dependencies between neighboring nodes based on the node information channel, and outputting hidden features containing semantic and positional information; capturing nonlinear associations based on the node type channel, and outputting an aggregated representation of type features; calculating the probability that the target node belongs to various types of components based on the hidden features containing semantic and positional information and the aggregated representation of type features, and obtaining a prediction probability calculation result; and generating a circuit schematic based on the prediction probability calculation result.

[0059] Among them, the target node refers to the node where a resistor, capacitor or other component is located in the graph structure constructed by the circuit schematic. Semantic association refers to the inherent relationship between the components represented by adjacent nodes in terms of function, attributes, etc. Position dependence refers to the features that cannot be directly observed but can reflect the essential characteristics of the node after processing and analyzing the node information. Aggregated representation of type features refers to the comprehensive representation obtained after integrating and aggregating the features of different types of nodes. Predicted probability calculation result refers to the probability value of the target node belonging to various types of components obtained by calculating the aggregated representation of hidden features and type features.

[0060] Specifically, such as Figure 6 As shown, firstly, node information vectors (e.g., component parameters and connection relationships) and node type vectors (e.g., resistor, inductor, etc.) are extracted from the power electronics engineering diagram to construct the graph structure input. Based on the node information channel, semantic associations and positional dependencies between adjacent nodes are captured, and hidden features containing semantic and positional information are output. Specifically, position embedding and feature extraction techniques are used in the node information channel to capture the semantic and positional dependencies between adjacent nodes, and this information is integrated into hidden features. Specifically, a Transformer encoder is simulated through the node information channel, and positional encoding is used to distinguish the positional differences of components of the same type (e.g., capacitors at different locations on a circuit board have different functions). Multi-head attention is used to capture multi-dimensional component interactions, layer normalization is used to stabilize the training gradient, and a feedforward network is used to enhance nonlinear representations. For the node type channel, a specific network structure, such as the GAT network, is used to identify and obtain the adjacent nodes of the target node. Based on the node type channel, nonlinear associations are captured, and an aggregated representation of type features is output. That is, in the node type channel, an embedding layer and a graph aggregation layer are used. The structure (such as Layer) captures the nonlinear relationships between different types of nodes. Then, the hidden features and aggregated representations of semantic and positional information obtained earlier are integrated and input into subsequent network layers. Through the calculation of these network layers, the probability of the target node belonging to various types of components is obtained. Finally, based on the obtained prediction probability calculation results, the component type of the target node is determined, and this information is integrated into the design of the entire circuit to generate the final circuit schematic.

[0061] To verify the effectiveness of the circuit schematic generation method based on the dual-channel graph learning model in this embodiment of the invention, a comparative experiment was also conducted on a power electronic design task. Table 1 is a comparison table of experimental results of a power electronic design task provided according to a specific embodiment of the invention.

[0062] Table 1

[0063] Model TOP-5 Accuracy Hamming Loss Jaccard Score GCN 0.653 0.713 0.168 SAGE 0.666 0.618 0.236 GIN 0.566 0.751 0.142 Proposed Model 0.928 0.386 0.443

[0064] Among them, TOP-5Accuracy indicates the probability that the top five categories in the model's prediction results contain the correct category; Hamming Loss indicates the proportion of difference between the predicted label and the true label, with a smaller value indicating better model performance; Jaccard Score indicates the degree of overlap between the predicted result and the true result, with a larger value indicating better model performance. In the experiment, compared with GCN, Graphsage, and GIN methods, the circuit schematic generation method based on the dual-channel graph learning model in this embodiment of the invention outperforms the relevant methods in three aspects: candidate answer coverage, error rate in multi-label classification tasks, and degree of overlap between the predicted result and the true result, demonstrating the effectiveness of the circuit schematic generation method based on the dual-channel graph learning model of this invention.

[0065] The circuit schematic generation method based on a dual-channel graph learning model provided by the present invention obtains the original circuit schematic file, constructs a graph structure transformation model and converts it into a bill of materials and netlist file, aligns the bill of materials and netlist file with the original circuit schematic to obtain graph structure data, and then uses a dual-channel graph node classification model to predict and generate the circuit schematic. This solves the problems of weak automated design capability and low efficiency of circuit schematics in related technology engineering design, improves the automated design capability of circuit schematics, and enhances the efficiency of circuit design.

[0066] Next, referring to the accompanying drawings, a circuit schematic generation device based on a dual-channel graph learning model according to an embodiment of the present invention is described.

[0067] Figure 7 This is a block diagram of a circuit schematic generation device based on a dual-channel graph learning model according to an embodiment of the present invention.

[0068] like Figure 7 As shown, the circuit schematic generation device 10 based on the dual-channel graph learning model includes: an acquisition module 100, a construction module 200, and a generation module 300.

[0069] The acquisition module 100 is used to acquire circuit schematic files, which include file tag information and core design information. The construction module 200 is used to construct a graph structure conversion model based on the file tag information and core design information, and based on the graph structure conversion model, convert the circuit schematic files into bill of materials (BOM) files and netlist files, and align the BOM files and netlist files with the circuit schematic files to obtain graph structure data. The generation module 300 is used to predict the graph structure data based on a pre-built dual-channel graph node classification model, obtain the target node prediction results, and generate a circuit schematic based on the target node prediction results.

[0070] Furthermore, in some embodiments, the construction module 200 is specifically used to: identify and delete duplicate information of file tag information and core design information by using a preset MD5 hash value identification method to obtain a preprocessed circuit schematic file; and classify the preprocessed circuit schematic file based on a preset data processing method to obtain a bill of materials file and a netlist file.

[0071] Furthermore, in some embodiments, the construction module 200 is also used to: establish a mapping function between the format features of the bill of materials file and the netlist file and the graphical elements in the circuit schematic file; and based on the mapping function, align the bill of materials file and the netlist file with the circuit schematic file to generate graph structure data.

[0072] Furthermore, in some embodiments, before predicting the graph structure data based on the pre-built dual-channel graph node classification model to obtain the target node prediction result, the construction module 200 is also used to: construct a node information channel and a node type channel; and obtain a dual-channel graph node classification model based on the node information channel and the node type channel.

[0073] Furthermore, in some embodiments, the generation module 300 is specifically used for: acquiring neighboring node information of the target node; capturing semantic associations and positional dependencies between neighboring nodes based on node information channels, and outputting hidden features containing semantic and positional information; capturing nonlinear associations based on node type channels, and outputting an aggregated representation of type features; calculating the probability that the target node belongs to various types of components based on the hidden features containing semantic and positional information and the aggregated representation of type features, and obtaining a predicted probability calculation result; and generating a circuit schematic based on the predicted probability calculation result.

[0074] It should be noted that the above explanation of the circuit schematic generation method based on the dual-channel graph learning model also applies to the circuit schematic generation device based on the dual-channel graph learning model in this embodiment, and will not be repeated here.

[0075] The circuit schematic generation device based on a dual-channel graph learning model provided in this embodiment of the invention obtains the original circuit schematic file, constructs a graph structure conversion model and converts it into a bill of materials and netlist file, aligns the bill of materials and netlist file with the original circuit schematic to obtain graph structure data, and then uses a dual-channel graph node classification model to predict and generate a circuit schematic. This solves the problems of weak automated design capability and low efficiency of circuit schematics in related technology engineering design, improves the automated design capability of circuit schematics, and enhances the efficiency of circuit design.

[0076] Figure 8 This is a schematic diagram of an electronic device provided according to an embodiment of the present invention. The electronic device may include:

[0077] The memory 801, the processor 802, and the computer program stored on the memory 801 and capable of running on the processor 802.

[0078] When the processor 802 executes the program, it implements the circuit schematic generation method based on the dual-channel graph learning model provided in the above embodiments.

[0079] Furthermore, the electronic device also includes:

[0080] Communication interface 803 is used for communication between memory 801 and processor 802.

[0081] The memory 801 is used to store computer programs that can run on the processor 802.

[0082] The memory 801 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0083] If the memory 801, processor 802, and communication interface 803 are implemented independently, then the communication interface 803, memory 801, and processor 802 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 8 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0084] Optionally, in a specific implementation, if the memory 801, processor 802, and communication interface 803 are integrated on a single chip, then the memory 801, processor 802, and communication interface 803 can communicate with each other through an internal interface.

[0085] The processor 802 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0086] In addition, embodiments of the present invention also provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the circuit schematic generation method based on a dual-channel graph learning model as described above.

[0087] In addition, embodiments of the present invention also provide a computer program product, including a computer program, which is executed to implement the circuit schematic generation method based on the dual-channel graph learning model as described above.

[0088] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0089] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0090] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more N executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of the invention pertain.

[0091] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0092] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

Claims

1. A circuit schematic generation method based on a dual-channel graph learning model, characterized in that, Includes the following steps: Obtain the circuit schematic file, which includes file tag information and core design information; Based on the file tag information and the core design information, a graph structure conversion model is constructed. Based on the graph structure conversion model, the circuit schematic file is converted into a bill of materials file and a netlist file. The bill of materials file and the netlist file are then aligned with the circuit schematic file to obtain graph structure data. Based on a pre-built dual-channel graph node classification model, the graph structure data is predicted to obtain the target node prediction result, and a circuit schematic is generated based on the target node prediction result. This includes: acquiring information about the target node's neighboring nodes; capturing semantic associations and positional dependencies between neighboring nodes based on the node information channel, and outputting hidden features containing semantic and positional information; capturing nonlinear associations based on the node type channel, and outputting an aggregated representation of the type features; calculating the probability that the target node belongs to various types of components based on the hidden features containing semantic and positional information and the aggregated representation of the type features, and obtaining a predicted probability calculation result; and generating the circuit schematic based on the predicted probability calculation result.

2. The method according to claim 1, characterized in that, The process of constructing a graph structure conversion model based on the file tag information and the core design information, and converting the circuit schematic file into a bill of materials file and a netlist file based on the graph structure conversion model, includes: By using a preset MD5 hash value recognition method, duplicate information in the file tag information and the core design information is identified and deleted to obtain a preprocessed circuit schematic file. Based on a preset data processing method, the preprocessed circuit schematic file is classified to obtain the bill of materials file and the netlist file.

3. The method according to claim 1, characterized in that, The step of aligning the bill of materials file and the netlist file with the circuit schematic file to obtain graph structure data includes: Establish a mapping function between the format characteristics of the bill of materials file and the netlist file and the graphic elements in the circuit schematic file; Based on the mapping function, the bill of materials file and the netlist file are aligned with the circuit schematic file to generate the graph structure data.

4. The method according to claim 1, characterized in that, Before predicting the target node based on a pre-built dual-channel graph node classification model on the graph structure data, the method further includes: Construct node information channels and node type channels; The dual-channel graph node classification model is obtained based on the node information channel and the node type channel.

5. A circuit schematic generation device based on a dual-channel graph learning model, characterized in that, The device includes: The acquisition module is used to acquire circuit schematic files, which include file tag information and core design information. The construction module is used to construct a graph structure conversion model based on the file tag information and the core design information, and based on the graph structure conversion model, convert the circuit schematic file into a bill of materials file and a netlist file, and align the bill of materials file and the netlist file with the circuit schematic file to obtain graph structure data; A generation module is used to predict the graph structure data based on a pre-built dual-channel graph node classification model, obtain the target node prediction result, and generate a circuit schematic based on the target node prediction result. Specifically, the generation module is used to: acquire information about the neighboring nodes of the target node; capture the semantic associations and positional dependencies between neighboring nodes based on the node information channels, and output hidden features containing semantic and positional information; capture nonlinear associations based on the node type channels, and output an aggregated representation of the type features; calculate the probability that the target node belongs to various types of components based on the hidden features containing semantic and positional information and the aggregated representation of the type features, and obtain a prediction probability calculation result; and generate the circuit schematic based on the prediction probability calculation result.

6. The apparatus according to claim 5, characterized in that, The building module is specifically used for: By using a preset MD5 hash value recognition method, duplicate information in the file tag information and the core design information is identified and deleted to obtain a preprocessed circuit schematic file. Based on a preset data processing method, the preprocessed circuit schematic file is classified to obtain the bill of materials file and the netlist file.

7. An electronic device, characterized in that, include: The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the circuit schematic generation method based on a dual-channel graph learning model as described in any one of claims 1-4.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the circuit schematic generation method based on the dual-channel graph learning model as described in any one of claims 1-4.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the circuit schematic generation method based on the dual-channel graph learning model as described in any one of claims 1-4.

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