Error recording device, memory device, memory system and operating method thereof

Abstract

The invention relates to an error recording device, a memory device, a memory system and an operating method thereof. A memory device includes: a memory cell array including memory cells coupled to a plurality of rows; a fault detection circuit configured to generate first to third fault addresses according to a result of an error check operation for each of the plurality of rows, and sequentially output the first to third fault addresses together with a fault input signal; and a failure information management circuit configured to store the first failure address as a starting failure address and generate failure mode information defining a relationship between the stored starting failure address and the second and third failure addresses according to a failure input signal, and outputting error information including the initial fail address and the fail mode information.

Description

Cross-reference to related applications

[0001] This patent application claims the benefit of priority to U.S. Provisional Application No. 63 / 667,410, filed July 3, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] Various embodiments of this disclosure relate to semiconductor design technology, and more specifically, to a storage system and memory device for performing error recording operations in accordance with error checking operations. Background Technology

[0003] In the early days of the semiconductor memory industry, memory chips manufactured using advanced processes were pristine, undamaged dies with numerous defect-free memory cells. However, as the capacity of memory devices has increased, it has become increasingly difficult to manufacture memory devices completely free of defective memory cells; it is now practically impossible to produce memory devices without defective memory cells. Current solutions to this problem include methods that use redundant memory cells to repair defective memory cells or methods that use error-correcting circuitry to correct errors in the data within the memory cells.

[0004] Recently, various methods for efficiently performing error checking and error logging operations have been discussed. This disclosure describes a memory device that performs an error checking operation by using embedded error correction circuitry to check for errors in internal data to select regions with numerous errors, and performs an error logging operation based on the error checking operation to record error information about the selected regions. Summary of the Invention

[0005] Embodiments of this disclosure relate to a memory device and a method of operating the same, the memory device being able to provide information about multiple row (or multi-row) faults and a single row fault during an error recording operation based on an error checking operation.

[0006] According to one embodiment of the present disclosure, a memory device includes: a memory cell array including memory cells coupled to a plurality of rows; a fault detection circuit configured to generate a first fault address to a third fault address based on the result of an error checking operation for each of the plurality of rows, and to sequentially output the first fault address to the third fault address together with a fault input signal; and a fault information management circuit configured to store the first fault address as a starting fault address and generate fault mode information defining the relationship between the stored starting fault address and the second and third fault addresses based on the fault input signal, and to output error information including the starting fault address and the fault mode information.

[0007] According to one embodiment of this disclosure, an error recording device includes: a fault detection circuit configured to output a fault address together with a fault input signal; an address storage circuit configured to store the fault address as a starting fault address based on a reset signal and a fault input signal, store the fault address as a first comparison address based on fault input signals input in odd order, and store the fault address as a second comparison address based on fault input signals input in even order; a finite state machine (FSM) configured to update fault mode information based on the result of comparing the first comparison address and the second comparison address; and an error information output circuit configured to output error information including fault mode information and a starting fault address based on an error information request command.

[0008] According to an embodiment of this disclosure, an error recording method includes: initializing fault mode information according to a reset signal; storing a fault address as a starting fault address according to the first fault input signal input after initialization, and updating the fault mode information; storing a fault address as a first comparison address according to fault input signals input in odd order, storing a fault address as a second comparison address according to fault input signals input in even order, and updating the fault mode information according to the comparison result of the first comparison address and the second comparison address; and outputting error information including fault mode information and starting fault address according to an error information request command.

[0009] According to one embodiment of this disclosure, a storage system includes: a storage controller; and a memory device configured to perform a scrubbing operation on each of a plurality of rows under the control of the storage controller, and generate a reset signal based on the scrubbing operation. The storage controller includes: a fault detection circuit configured to generate a first fault address to a third fault address based on the scrubbing operation, and sequentially output the first fault address to the third fault address together with a fault input signal; and a fault information management circuit configured to store the first fault address as a starting fault address based on the fault input signal and the reset signal, generate fault mode information defining the relationship between the stored starting fault address and the second and third fault addresses, and output error information including the starting fault address and the fault mode information.

[0010] According to embodiments of the present invention, the memory device can provide information about multiple line failures during error recording operations. Therefore, optimized reliability, accessibility, and serviceability (RAS) operation can be provided.

[0011] These and other features and advantages of the embodiments of this disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0012] Figure 1This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0013] Figure 2A and Figure 2B It is used to describe embodiments according to this disclosure. Figure 1 A diagram of a storage cell array.

[0014] Figure 3 It is shown Figure 1 A block diagram showing the configuration of row and column addresses.

[0015] Figure 4 This is a diagram illustrating the arrangement of a sub-word line driver according to an embodiment of the present disclosure.

[0016] Figure 5 It is shown Figure 4 Detailed circuit diagram of the sub-word line driver.

[0017] Figure 6 This describes embodiments according to the present disclosure. Figure 1 The flowchart shows the operation of the fault detection circuit.

[0018] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 1 Detailed configuration diagram of the fault information management circuit.

[0019] Figure 8 It is used to describe Figure 7 A diagram illustrating the operation of the address storage circuit.

[0020] Figure 9 yes Figure 7 Detailed configuration diagram of the fault analysis circuit.

[0021] Figure 10 and Figure 11 It is used for definition Figure 9 The table and status diagram of the FSM's fault mode information.

[0022] Figure 12 It is a description Figure 7 The flowchart shows the operation of the fault information management circuit.

[0023] Figures 13 to 18 This is a flowchart describing the operation of a finite state machine according to embodiments of the present disclosure.

[0024] Figure 19 This is a block diagram illustrating a storage system according to an embodiment of the present disclosure.

[0025] Figure 20 This is a block diagram illustrating a storage system including a storage module according to an embodiment of the present disclosure.

[0026] Figure 21 This is a block diagram illustrating a storage system including stacked memory devices according to an embodiment of the present disclosure.

[0027] Figure 22 This is a block diagram illustrating a storage system according to another embodiment of the present disclosure. Detailed Implementation

[0028] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, embodiments of the present disclosure may take different forms and should not be construed as limited to those described herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same components in various figures and embodiments.

[0029] It should be understood that when an element is referred to as "coupled" or "connected" to another element, it may mean that the two are directly coupled or electrically connected to each other, with another circuit or element intervening between them. It should also be understood that the terms "comprising," "including," "having," etc., as used in this specification, specify the presence of the stated features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0030] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure. Figure 2A and Figure 2B It is used to describe embodiments according to this disclosure. Figure 1 A diagram of a storage cell array. Figure 3 It is shown Figure 1 A block diagram showing the configuration of row and column addresses.

[0031] refer to Figure 1 The memory device 100 may include a memory cell array 110, a row control circuit 112, a column control circuit 114, a command / address (CA) receiving circuit 120, a data input / output circuit 130, a command decoder 140, an address generation circuit 150, an erase control circuit 160, an error correction code (ECC) engine 170, and an error recording circuit 180.

[0032] The memory cell array 110 may include a plurality of memory cells MC arranged in an array type. The plurality of memory cells MC may be coupled to row control circuitry 112 via a plurality of word lines WL and to column control circuitry 114 via a plurality of bit lines BL. The plurality of word lines WL may extend along a first direction (e.g., row direction) and may be sequentially arranged in a second direction perpendicular to the first direction (e.g., column direction). The plurality of bit lines BL may extend along the column direction and may be sequentially arranged in the row direction. The memory cell array 110 may include at least one memory bank. The number of memory banks or the number of memory cells MC may be determined based on the capacity of the memory device 100. The memory cell array 110 may include a plurality of memory blocks (hereinafter referred to as "cell blocks"), each memory block including a plurality of memory cells MC.

[0033] refer to Figure 2A The memory cell array 110 may include a plurality of cell blocks MB arranged in an array along a first direction X1 and a second direction Y1 intersecting the first direction X1. Each cell block MB may include a plurality of memory cells MC connected between a plurality of word lines WL and a plurality of bit lines BL. Cell blocks MB arranged along the row direction X1 may be divided into a plurality of bit lines BL, and cell blocks MB arranged along the column direction Y1 may be divided into a plurality of word lines WL. Sub-word line driver regions SWB may be arranged between cell blocks MB arranged along the first direction X1. A plurality of sub-word line drivers may be disposed in the sub-word line driver regions SWB. Bit line sense amplifier regions BLSAB may be arranged between cell blocks MB arranged along the second direction Y1. A plurality of bit line sense amplifiers may be disposed in the bit line sense amplifier regions BLSAB. In one embodiment of this disclosure, a "cell block" may be defined as a group of memory cells sharing word lines WL and bit lines BL and arranged along the first direction X1 and the second direction Y1.

[0034] For reference, in order to reduce the propagation delay of word line voltage as the number of memory cells connected to the word line increases and the distance between word lines decreases, a main word line can be divided into multiple (e.g., 8) sub-word lines, which are driven by a sub-word line driver. In the following, the word line WL mentioned in this invention may correspond to a known sub-word line.

[0035] refer to Figure 2B , showed Figure 2A MA in part of the region.

[0036] The squares between unit blocks (MB) can represent subword line drivers (SWDs), and the lines extending to the left and right of the SWDs can represent word lines. In reality, there are a considerable number of subword line drivers (SWDs) and word lines, but for simplicity, only a portion of the lines are shown.

[0037] Each unit block MB may include odd-numbered lines (hereinafter referred to as "first word lines WLO") extending in a first direction X1 and alternating with each other in a second direction Y1, and even-numbered lines (hereinafter referred to as "second word lines WLE"). In odd-numbered unit blocks (e.g., Figure 2B In MB1), the first word line WLO can share the sub-word line driver SWD with adjacent cell blocks in the first direction X1, while the second word line WLE can share the sub-word line driver SWD with adjacent cell blocks in the opposite direction X2. Conversely, in even-numbered cell blocks (e.g., ... Figure 2B In MB2), the second word line WLE can share the sub-word line driver SWD with the adjacent cell block in the first direction X1, while the first word line WLO can share the sub-word line driver SWD with the adjacent cell block in the direction X2. That is, since the two adjacent cell blocks MB in the first direction X1 share the sub-word line driver SWD, one sub-word line driver SWD can be allocated to the two adjacent cell blocks MB in the first direction X1.

[0038] Each cell block MB may include a first bit line BLU and a second bit line BLL extending along a second direction Y1 and alternately arranged in a first direction X1. The first bit line BLU may share a bit line sense amplifier BLSA with an adjacent cell block (not shown) in the second direction Y1, and the second bit line BLL may share a bit line sense amplifier BLSA with an adjacent cell block (not shown) in the opposite direction Y2. That is, since two adjacent cell blocks MB in the second direction Y1 share a bit line sense amplifier BLSA, one bit line sense amplifier BLSA can be allocated to two adjacent cell blocks MB in the second direction Y1.

[0039] Return to reference Figure 1 The CA receiving circuit 120 can receive command / address signals C / A. Depending on the type of memory device 100, commands and addresses can be input through the same input terminal, or commands and addresses can be input through separate input terminals. Figure 1 The diagram shows that commands and addresses are input through the same input terminal. The command / address signal C / A can be formed by multiple bits.

[0040] Data input / output circuitry 130 can transmit data DQ to or receive data DQ from the memory controller (not shown). Data input / output circuitry 130 may include data input circuitry 132 and data output circuitry 134. Data input circuitry 132 can receive data DQ to be written to memory cell array 110 during a write operation. Data output circuitry 134 can output data DQ read from memory cell array 110 during a read operation.

[0041] Command decoder 140 can decode the command / address signal C / A received by CA receiving circuit 120 to generate activation command ACT, precharge command PCG, write command WT, read command RD, wipe command ECS, and error message request command ERR_OUT. Activation command ACT is the signal input when an activation operation is indicated, precharge command PCG is the signal input when a precharge operation is indicated, write command WT is the signal input when a write operation is indicated, and read command RD can be the signal input when a read operation is indicated. Furthermore, wipe command ECS can be the signal input when an error checking operation is indicated, and error message request command ERR_OUT can be the signal input when an error message is requested. For reference, an error checking operation, also known as an error checking and wiping (ECS) operation, can represent the operation of reading data DATA' from memory cell array 110 and checking for errors in the read data DATA' using error correction code (ECC) engine 170 and selecting regions with numerous errors.

[0042] Address generation circuit 150 can classify the internal address (ICA) received from command decoder 140 into row address (RADD) and column address (CADD). Row address (RADD) can be an address used to select one of multiple word lines (WL), and column address (CADD) can be an address used to select some bit lines (BL) from multiple bit lines to perform a read operation. Each of row address (RADD) and column address (CADD) can consist of multiple bits. According to embodiments, address generation circuit 150 can also generate block addresses for specifying multiple cell blocks, and can generate bank addresses, row addresses, and channel addresses according to the configuration of the memory device.

[0043] A row address (RADD) can be divided into a high-order group of bits used to specify a main word line from multiple main word lines and a low-order group of bits used to specify a sub-word line from multiple sub-word lines allocated to a main word line. Similarly, a column address (CADD) can consist of bits used to specify a column from multiple columns, with a predetermined number of bit lines selected when a column is selected. For example, refer to... Figure 3 The row address RAD can be divided into a 7-bit high-order group UP_B assigned to the 128 main word lines and a 3-bit low-order group DN_B assigned to the 8 sub-word lines (which are allocated to one main word line). Furthermore, the column address CADD consists of 7 bits assigned to the 128 columns, and when a column is specified, all 8 bit lines can be selected.

[0044] In the following text, the multiple word lines WL mentioned in this invention will be referred to as multiple lines.

[0045] Return to reference Figure 1The wipe control circuit 160 can generate a wipe activation signal ACT_E, a wipe precharge signal PCG_E, a wipe write signal WT_E, and a wipe read signal RD_E according to the wipe command ECS to perform an error checking operation. The wipe control circuit 160 can sequentially activate the wipe activation signal ACT_E, the wipe read signal RD_E, the wipe write signal WT_E, and the wipe precharge signal PCG_E according to the wipe command ECS to control the error checking operation to be performed, including the activation operation, the read operation, the write operation, and the precharge operation. For reference, the error checking operation can be performed through the activation operation, the read operation, the write operation, and the precharge operation, but according to the embodiment, the write operation can be omitted.

[0046] Furthermore, the scrubbing control circuit 160 can generate the scrubbing row address RADD_E and the scrubbing column address CADD_E according to the scrubbing command ECS. Whenever the scrubbing command ECS is input, the scrubbing control circuit 160 can increment the value of the scrubbing column address CADD_E by "+1", and when the value of the scrubbing column address CADD_E reaches its maximum value, the scrubbing control circuit 160 can increment the value of the scrubbing row address RADD_E by "+1". For example, when the value of the scrub row address RADD_E ranges from 0 to 3 and the value of the scrub column address CADD_E ranges from 0 to 3, the scrub control circuit 160 can generate the scrub address (RADD_E, CADD_E) to be changed whenever the scrub command ECS is input as follows: (0,0)->(0,1)->(0,2)->(0,3)->(1,0)->(1,1)->(1,2)->(1,3)->(2,0)->(2,1)->(2,2)->(2,3)->(3,0)->(3,1)->(3,2)->(3,3).

[0047] In an embodiment of the invention, the wipe control circuit 160 can generate a reset signal RST_E to initialize the error information E_INFO provided from the error recording circuit 180. In this embodiment, the wipe control circuit 160 can generate the reset signal RST_E, which is activated when an error check operation for rows included in at least two adjacent cell blocks is completed. At least two adjacent cell blocks can be... Figure 2A and Figure 2B The cell blocks MB arranged along the column direction Y1 as described herein are selected, that is, selected from cell blocks MB divided by multiple rows WL. For example, when there are 128 rows WL arranged in each cell block, the scrubbing control circuit 160 can activate the reset signal RST_E when the error checking operation for the 256 rows included in two adjacent cell blocks is completed.

[0048] The ECC engine 170 may include error correction circuitry 172 and ECC generation circuitry 174.

[0049] Error correction circuit 172 can use error correction code (ECC) read from memory cell array 110 during a read operation to correct errors in read data DATA', outputting error-corrected data DATA. Here, error correction can mean an error checking operation that uses error correction code (ECC) to check for errors in read data DATA' and an error correction operation that corrects errors in read data DATA' when an error is detected. Error correction circuit 172 can check and correct errors in error correction code (ECC) and data DATA'. When an error in data DATA' is detected and corrected, the data DATA' input to error correction circuit 172 and the data DATA output from error correction circuit 172 can be different from each other. Error correction circuit 172 can output an error signal ERR, which is activated when an error is detected during an error checking operation. In the following embodiments, the error signal ERR can be a signal activated as a logic high level.

[0050] ECC generation circuit 174 can generate error correction code (ECC) using data DATA during a write operation. During the write operation, since the error correction code (ECC) is generated using data DATA and errors in data DATA are not corrected, the data DATA input to ECC generation circuit 174 is the same as the data DATA' output from ECC generation circuit 174.

[0051] Error logging circuit 180 can record errors found during error checking operations. More specifically, error logging circuit 180 may include fault detection circuit 182 and fault information management circuit 184.

[0052] The fault detection circuit 182 can generate a fault address F_RADD based on the result of an error checking operation on each row of multiple rows WL. The fault detection circuit 182 can output the fault address F_RADD together with the fault input signal FIN. The fault detection circuit 182 can also generate the fault address F_RADD based on the error signal ERR activated during the error checking operation on each row of multiple rows WL. For example, the fault detection circuit 182 can count the number of errors in each row to generate the address (i.e., the row address) of the row whose error count exceeds a threshold as the fault address F_RADD. Since the fault detection circuit 182 receives the wipe row address RADD_E, the wipe column address CADD_E, and the error signal ERR, it can check which area of ​​the memory cell array 110 the error was found in. Detailed operation of the fault detection circuit 182 will be described in [reference needed]. Figure 6 Describe it.

[0053] The fault information management circuit 184 can store the fault address F_RADD, which is the first fault address input after the reset signal RST_E is activated, as the starting fault address S_FADD, based on the fault input signal FIN. The fault information management circuit 184 can generate fault mode information FSM_ST based on the fault input signal FIN. This fault mode information FSM_ST defines the fault mode as the relationship between the stored starting fault address S_FADD and the subsequently input fault address F_RADD. The fault information management circuit 184 can output error information E_INFO, including the starting fault address S_FADD and the fault mode information FSM_ST, based on the error information request command ERR_OUT. The fault information management circuit 184 can also transmit the error information E_INFO to the storage controller through the data output circuit 134 of the data input / output circuit 130, based on the error information request command ERR_OUT.

[0054] Furthermore, the fault information management circuit 184 can initialize the fault mode information FSM_ST based on the reset signal RST_E provided from the wipe control circuit 160. Since the memory controller can handle faults related to rows included in the two cell blocks, the fault information management circuit 184 can initialize the fault mode information FSM_ST based on the reset signal RST_E.

[0055] The fault mode information FSM_ST can be set to one of several state values ​​defining a fault associated with one or more rows of defects specified by the starting fault address S_FADD. The fault information management circuit 184 can change or maintain (i.e., update) the fault mode information F_ST to one of these state values ​​based on the fault input signal FIN by comparing the previously input fault address F_RADD with the currently input fault address F_RADD. The possible state values ​​of the fault mode information FSM_ST will be... Figure 11 As described in the text.

[0056] Depending on the embodiment, when a fault mode caused by two or more rows (hereinafter referred to as a multi-row fault mode) is specified according to the fault mode information FSM_ST, the fault information management circuit 184 can output an alarm signal ALT to the storage controller. For example, when the fault mode information FSM_ST notifies a multi-row fault mode that may lead to an uncorrectable error (UE), the fault information management circuit 184 can activate the alarm signal ALT. Although Figure 1 The alarm signal ALT is shown to be output externally via a separate pad, but the proposed invention is not limited thereto. Similar to the error message E_INFO, the alarm signal ALT can be provided to the memory controller via the data output circuit 134 of the data input / output circuit 130. Detailed configuration and operation of the fault information management circuit 184 will be discussed later. Figures 7 to 18As described in the text.

[0057] The row control circuit 112 can activate the row selected by the row address RADD in response to the activation command ACT, and can perform a pre-charge operation to pre-charge the activated row in response to the pre-charge command PCG. Furthermore, the row control circuit 112 can activate the row selected by the wipe row address RADD_E in response to the wipe activation signal ACT_E, and can perform a pre-charge operation to pre-charge the activated row in response to the wipe pre-charge signal PCG_E.

[0058] The column control circuit 114 can select some bit lines from the multiple bit lines BL of the memory cell array 110 according to the column address CADD. In response to the read command RD, it performs a read operation to read data DATA' and error correction code ECC from the memory cell MC through the selected bit lines, or in response to the write command WT, it performs a write operation to write data DATA' and error correction code ECC to the memory cell MC through the selected bit lines. Furthermore, the column control circuit 114 can select some bit lines from the multiple bit lines BL of the memory cell array 110 according to the erase column address CADD_E. In response to the erase read signal RD_E, it performs a read operation to read data DATA' and error correction code ECC from the memory cell MC through the selected bit lines, or in response to the erase write command WT_E, it performs a write operation to write data DATA' and error correction code ECC to the memory cell MC through the selected bit lines.

[0059] As described above, according to an embodiment of the present invention, the memory device 100 may store the fault address F_RADD first detected during an error checking operation for each row as a starting fault address S_FADD, and update the fault mode information FSM_ST, which defines the relationship between the starting fault address S_FADD and subsequent fault addresses F_RADD, whenever a fault address is subsequently detected. Thereafter, the memory device 100 may provide the memory controller with error information E_INFO, including both the fault mode information FSM_ST and the starting fault address S_FADD, according to the error information request command ERR_OUT. Conventionally, memory controllers struggle to effectively perform error management because the memory device only provides information about one or more defective rows. In this invention, however, the memory device can provide information about defective rows as well as information defining the faults of one or more rows associated with the defective row. Therefore, the memory controller can identify possible fault modes based on the defective row specified by the starting fault address, thereby effectively managing errors and performing optimized reliability, accessibility, and serviceability (RAS) operations.

[0060] Figure 4 This is a diagram illustrating the arrangement of a sub-word line driver according to an embodiment of the present disclosure. Figure 5 It is shown Figure 4 Detailed circuit diagram of the sub-word line driver.

[0061] refer to Figure 4 The diagram shows the first cell block MB0 and the second cell block MB1 that are adjacent to each other in the row direction. Figure 4 The diagram shows two main word lines arranged in each unit block and eight sub-word lines arranged in each main word line. That is, the first to sixteenth sub-word lines (i.e., rows WL0 to WL15) can extend in the row direction and can be arranged alternately in the column direction in the first unit block MB0 and the second unit block MB1, respectively.

[0062] The first sub-word line drivers D0 to the sixteenth sub-word line drivers D15, used to drive the first sub-word line WL0 to the sixteenth sub-word line WL15, can be alternately arranged on opposite sides of each cell block. For example, the odd-numbered sub-word line drivers arranged on one side of each cell block can drive the odd-numbered sub-word lines, while the even-numbered sub-word line drivers arranged on the other side can drive the even-numbered sub-word lines.

[0063] The first sub-word line drivers D0 to D7 can jointly receive the first main word line drive signal MWLB0, the corresponding signals of the first word line selection signal FX<0:7> and the second word line selection signal FXB<0:7>, and drive the first sub-word lines WL0 to WL7. The ninth sub-word line drivers D8 to D15 can jointly receive the second main word line drive signal MWLB1, the corresponding signals of the first word line selection signal FX<0:7> and the second word line selection signal FXB<0:7>, and drive the ninth sub-word lines WL8 to WL15. Here, the main word line drive signals MWLB0 and MWLB1 can represent the drive signals transmitted through the main word lines.

[0064] refer to Figure 5 , showed Figure 4 The sub-word line drivers D0, D2, D4, D6, D8, D10, D12, and D14 are arranged on one side of the first unit block MB0. Since each sub-word line driver has the same configuration, the first sub-word line driver D0 will be used as an example for description.

[0065] The first sub-word line driver D0 may include a PMOS transistor P11 and NMOS transistors N11 and N12. PMOS transistor P11 and NMOS transistor N11 are connected in series between the input terminal of the first word line select signal FX0 and the reverse bias voltage (VBBW) (or ground voltage VSS) terminal, and receive the main word line drive signal MWLB0 through their common gate. NMOS transistor N12 is connected between the sub-word line WL0 and the reverse bias voltage (VBBW) terminal, and receives the second word line select signal FXB0 through its gate.

[0066] Figure 6 This describes embodiments according to the present disclosure. Figure 1 The flowchart shows the operation of the fault detection circuit.

[0067] refer to Figure 6 The wipe control circuit 160 can initialize the wipe row address RADD_E and the wipe column address CADD_E according to the wipe command ECS (in S110). Furthermore, the wipe control circuit 160 can sequentially activate the wipe activation signal ACT_E, the wipe read signal RD_E, the wipe write signal WT_E, and the wipe precharge signal PCG_E according to the wipe command ECS. Therefore, error checking operations can be performed on the first row and the first column (in S120).

[0068] When an error is detected during the error checking operation and the error correction circuit 172 activates the error signal ERR ("Yes" in S130), the fault detection circuit 182 can increment the error count for the first row by "+1" (in S140), and then the wipe control circuit 160 can increment the wipe column address CADD_E by "+1" (in S160). Therefore, an error checking operation can be performed on the first row and the second column (in S120).

[0069] Repeat the operations from S120 to S160. When the error checking operation for all columns of the first row is completed and the wipe column address CADD_E reaches its maximum value ("Yes" in S150), the fault detection circuit 182 can check whether the error count for the first row exceeds the threshold. If the error count for the first row exceeds the threshold, the fault detection circuit 182 can generate the wipe row address RADD_E of the first row as the fault address F_RADD, and provide the fault address F_RADD together with the fault input signal FIN to the fault information management circuit 184 (in S170). When the wipe row address RADD_E reaches its maximum value ("Yes" in S180), the error checking operation for all rows can be completed.

[0070] When the wipe row address RADD_E has not reached its maximum value ("No" in S180), the wipe control circuit 160 can initialize the wipe column address CADD_E and increment the wipe row address RADD_E by "+1" (in S190). The above operations from S120 to S190 can be repeated. Therefore, error checking operations can be performed on the second row and the first column (in S120).

[0071] As described above, when a fault address F_RADD is detected based on the error checking operation of each line, the fault detection circuit 182 can provide the detected fault address F_RADD together with the fault input signal FIN to the fault information management circuit 184.

[0072] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 1 Detailed configuration diagram of the fault information management circuit.

[0073] refer to Figure 7 The fault information management circuit 184 may include an address storage circuit 310 and a fault analysis circuit 330.

[0074] The address storage circuit 310 can store the fault address F_RADD as the initial fault address S_FADD according to the reset signal RST_E and the fault input signal FIN, store the fault address F_RADD as the first comparison address FADD1 according to the fault input signal FIN input in odd order, and store the fault address F_RADD as the second comparison address FADD2 according to the fault input signal FIN input in even order.

[0075] More specifically, the address storage circuit 310 may include a storage device controller 312 and a first address storage device S1 to a third address storage device S3.

[0076] The storage device controller 312 can output a fault address F_RADD as a starting fault address S_FADD based on the reset signal RST_E and the fault input signal FIN, and output the fault address F_RADD as a first comparison address FADD1 or a second comparison address FADD2 according to the input order of the fault input signals FIN. The storage device controller 312 may include an initial signal generator 312A, a selection signal generator F1, a first selector M1, and a second selector M2.

[0077] The initial signal generator 312A can generate the initial input signal FIRST_FIN by detecting the fault input signal FIN initially input after the reset signal RST_E is activated. The selection signal generator F1 can generate a logic-low selection signal SEL based on fault input signals FIN input in odd-numbered order, and a logic-high selection signal SEL based on fault input signals FIN input in even-numbered order. For example, the selection signal generator F1 can be implemented as a flip-flop that receives the inverted signal of the selection signal SEL through an input terminal, receives the fault input signal FIN through a clock terminal, and outputs the selection signal SEL through an output terminal.

[0078] The first selector M1 can output the fault address F_RADD as the starting fault address S_FADD when the initial input signal FIRST_FIN is activated. For example, the first selector M1 can be implemented using logic gates that perform a logical AND operation on the initial input signal FIRST_FIN and the fault address F_RADD. Although Figure 7 The diagram shows an AND gate, but a number of gates corresponding to the number of bits in the fault address F_RADD can be provided. The second selector M2 can output the first comparison address FADD1 by selecting the fault address F_RADD according to the logic low selection signal SEL, and output the second comparison address FADD2 by selecting the fault address F_RADD according to the logic high selection signal SEL. For example, the second selector M2 can be implemented using a known multiplexer.

[0079] The first address storage device S1 can store the starting fault address S_FADD output from the first selector M1, the second address storage device S2 can store the first comparison address FADD1 output from the second selector M2, and the third address storage device S3 can store the second comparison address FADD2 output from the second selector M2.

[0080] The fault analysis circuit 330 can update the fault mode information FSM_ST by comparing the first comparison address FADD1 stored in the second address storage device S2 with the second comparison address FADD2 stored in the third address storage device S3, based on the fault input signal FIN. The fault analysis circuit 330 can output error information E_INFO, including the starting fault address S_FADD and the fault mode information FSM_ST, based on the error information request command ERR_OUT. According to an embodiment, when multiple fault modes are specified according to the fault mode information FSM_ST, the fault analysis circuit 330 can output an alarm signal ALT. The fault analysis circuit 330 can initialize the fault mode information FSM_ST to a default value (e.g., a first status value "000") based on the reset signal RST_E.

[0081] Figure 8 It is used to describe Figure 7 A diagram illustrating the operation of the address storage circuit.

[0082] refer to Figure 8When the fault address F_RADD "A1" is input according to the fault input signal FIN, which is input first after the reset signal RST_E is activated (①), the initial input signal FIRST_FIN is activated. In this case, since the fault input signal FIN is input in odd order, a logic low-level selection signal SEL is generated. Therefore, the first address storage device S1 and the second address storage device S2 can store the fault address F_RADD "A1" as the starting fault address S_FADD and the first comparison address FADD1, respectively.

[0083] Subsequently, when the fault address F_RADD "A2" is input according to the fault input signal FIN input in even-numbered order (②), a logic high-level selection signal SEL is generated. Therefore, the third address storage device S3 can store the fault address F_RADD "A2" as the second comparison address FADD2.

[0084] Subsequently, when the fault address F_RADD "A3" is input according to the fault input signal FIN input in odd order (③), a low-level selection signal SEL is generated. Therefore, the second address storage device S2 can store the fault address F_RADD "A3" as the first comparison address FADD1.

[0085] Subsequently, when the fault address F_RADD "A4" is input according to the fault input signal FIN input in even-numbered order (④), a logic high-level selection signal SEL is generated. Therefore, the third address storage device S3 can store the fault address F_RADD "A4" as the second comparison address FADD2.

[0086] As described above, the address storage circuit 310 can store the fault address F_RADD as the starting fault address S_FADD based on the first fault input signal FIN after initialization. Furthermore, the address storage circuit 310 can store the fault address F_RADD as a first comparison address FADD1 based on an odd-numbered fault input signal FIN, and store the fault address F_RADD as a second comparison address FADD2 based on an even-numbered fault input signal FIN. Therefore, the address storage circuit 310 can store two consecutive fault addresses F_RADD as the first comparison address FADD1 and the second comparison address FADD2, respectively.

[0087] Figure 9 for Figure 7 Detailed configuration diagram of the fault analysis circuit.

[0088] refer to Figure 9 The fault analysis circuit 330 may include a finite state machine (FSM) 332 and an information output circuit 334.

[0089] The FSM 332 can update the fault mode information FSM_ST by comparing the first comparison address FADD1 and the second comparison address FADD2 based on the fault input signal FIN. The FSM 332 can initialize the fault mode information FSM_ST to the first status value "000" based on the reset signal RST_E.

[0090] The information output circuit 334 can output error information E_INFO, including the starting fault address S_FADD and fault mode information FSM_ST, based on the error information request command ERR_OUT. Depending on the configuration, when multiple fault modes are specified according to the fault mode information FSM_ST, the information output circuit 334 can output an alarm signal ALT.

[0091] Figure 10 and Figure 11 It is used for definition Figure 9 The table and status diagram of the FSM 332's fault mode information FSM_ST.

[0092] refer to Figure 10 The fault mode information FSM_ST can be configured as 3 bits and set to one of the first state value F1 to the eighth state value F8.

[0093] When no fault address is detected, the first state value F1 "NRFLT" can be set to the default value "000". When a fault address is initially detected, the second state value F2 "ROW" can be set to the value "001". When a fault address is detected in an odd-numbered or even-numbered sub-word line of a main word line, the third state value F3 "MWLE, MWLO" can be set to the value "010". When a fault address is detected only in a sub-word line coupled to a main word line, the fourth state value F4 "MWL" can be set to the value "011". When a fault address is detected in sub-word lines of the same order coupled to two adjacent main word lines, the fifth state value F5 "EAWL" can be set to the value "100". Here, when the first to sixteenth sub-word lines are assigned to two adjacent master word lines, the first and ninth sub-word lines are configured in the same order, the second and tenth sub-word lines are configured in the same order, and so on, with the eighth and sixteenth sub-word lines configured in the same order. When a fault address is repeatedly detected among sub-word lines in the same order coupled to multiple master word lines, the sixth state value F6 "EEWL" can be set to the value "101". When a fault address is repeatedly detected among odd or even sub-word lines, the seventh state value F7 "EWL, OWL" can be set to the value "110". When the conditions of the first state values ​​F1 to the seventh state values ​​F7 are not met, the eighth state value F8 "ETC" can be set to the value "111". The eighth state value F8 can be set when no relationship is found between fault addresses.

[0094] In addition, Figure 5 In the sub-word line driver structure described herein, when a defect occurs in a contact shared by the sub-word line drivers, the sub-word line driven by the corresponding sub-word line driver may be defective. For example, when a defect occurs in the contact of the reverse bias voltage VBBW shared by the first sub-word line driver D0 and the ninth sub-word line driver D8, the first sub-word line WL0 and the ninth sub-word line WL8 may be defective. That is, when a sub-word line in the same order among the eight sub-word lines coupled to each of two adjacent main word lines is defective, a defect in the contact shared by the corresponding sub-word line driver may be the cause.

[0095] In addition, Figure 5In the sub-word line driver structure described herein, when a defect occurs in the signal path used to apply the word line selection signal, the sub-word line driven by the sub-word line driver receiving the corresponding word line selection signal may be defective. For example, when a defect occurs in the signal path used to apply the first word line selection signal FX0, the first sub-word line WL0 and the ninth sub-word line WL8 driven by the first sub-word line driver D0 and the ninth sub-word line driver D8 may be defective. That is, when sub-word lines in the same order among the eight sub-word lines coupled to each of the multiple main word lines are defective, the defect in the signal path collectively provided to the corresponding sub-word line driver may be the cause.

[0096] refer to Figure 11 The FSM 332 can initialize the fault mode information FSM_ST to a first state value "000". When a first fault address is input, the FSM 332 can update the fault mode information FSM_ST from the first state value "000" to a second state value "001". Whenever a subsequent fault address is input, the FSM 332 can compare the first comparison address FADD1 with the second comparison address FADD2 to update the fault mode information FSM_ST to one of the third to eighth state values. For example, when the fault mode information FSM_ST is set to the second state value "001", if a subsequent fault address is detected in an odd-numbered or even-numbered subword line coupled to a main word line as a result of the comparison between the first comparison address FADD1 and the second comparison address FADD2, the FSM 332 can update the fault mode information FSM_ST from the second state value "001" to a third state value "010". (See reference...) Figures 13 to 18 describe Figure 11 The transition (i.e., update) between state values.

[0097] The following will refer to Figures 7 to 12 The operation of the fault information management circuit 184 according to an embodiment of the present disclosure is described.

[0098] Figure 12 It is a description Figure 7 The flowchart shows the operation of the fault information management circuit.

[0099] refer to Figure 12 When a reset signal RST_E is input from the wiping control circuit 160 (in S210), the fault analysis circuit 330 can initialize the fault mode information FSM_ST (in S212). For example, the fault analysis circuit 330 can initialize the fault mode information FSM_ST to the first state value "000".

[0100] Furthermore, the fault address F_RADD can be input from the fault detection circuit 182 along with the fault input signal FIN (in S220). When the fault input signal FIN is input for the first time after the reset signal RST_E is input ("Yes" in S230), the address storage circuit 310 can store the fault address F_RADD as the starting fault address S_FADD in the first address storage device S1. At the same time, the address storage circuit 310 can store the fault address F_RADD as the first comparison address FADD1 in the second address storage device S2 (in S232). As the starting fault address S_FADD is stored, the FSM 332 can update the fault mode information FSM_ST from the first state value "000" to the second state value "001" (in S250).

[0101] On the other hand, when the fault input signal FIN is not initially input after the reset signal RST_E is input ("No" in S230), the address storage circuit 310 can store the fault address F_RADD as either the first comparison address FADD1 or the second comparison address FADD2 according to the input order of the fault input signals FIN. When the fault input signal FIN is input in an odd-numbered order ("Yes" in S240), the address storage circuit 310 can store the fault address F_RADD as the first comparison address FADD1 in the second address storage device S2 (in S242). On the other hand, when the fault input signal FIN is input in an even-numbered order ("No" in S240), the address storage circuit 310 can store the fault address F_RADD as the second comparison address FADD2 in the third address storage device S3 (in S244). The FSM 332 can update the fault mode information FSM_ST to one of the third to eighth status values ​​(in S250) based on the current fault mode information FSM_ST status value and the result of comparing the first comparison address FADD1 with the second comparison address FADD2.

[0102] The error message request command ERR_OUT can be input from the storage controller (in S260). The information output circuit 334 can output error message E_INFO including the starting fault address S_FADD and update the fault mode information FSM_ST (in S262). According to an embodiment, when a multi-row fault mode of two or more rows is specified according to the fault mode information FSM_ST, the information output circuit 334 can selectively output an alarm signal ALT (in S264).

[0103] Figures 13 to 18 This is a flowchart describing the operation of a finite state machine according to an embodiment of the present disclosure.

[0104] Before describing each operation, such as Figure 3Each of the first comparison address FADD1 and the second comparison address FADD2 can be divided into a high-order byte group UP_B for specifying the main word line and a low-order byte group DN_B for specifying the eight sub-word lines. A finite state machine (FSM 332) can compare the high-order byte group UP_B and the low-order byte group DN_B of the first comparison address FADD1 with the high-order byte group UP_B and the low-order byte group DN_B of the second comparison address FADD2, and determine the relationship between the current fault address and subsequent fault addresses as follows.

[0105] (1) When the high-order byte UP_B of the first comparison address FADD1 and the second comparison address FADD2 is the same: it is determined that the current fault address and the subsequent fault address exist in the same main word line.

[0106] (2) When the difference between the values ​​of the high-order group UP_B is 1, it is determined that the current fault address and the subsequent fault address exist in the adjacent main word line.

[0107] (3) When the difference between the values ​​of the high-order group UP_B is greater than or equal to 2: it is determined that the current fault address and the subsequent fault address do not exist on the same main word line or adjacent main word lines.

[0108] (4) When the low-order group DN_B of the first comparison address FADD1 and the second comparison address FADD2 is the same: determine that the current fault address and the subsequent fault address exist in the same order of the eight sub-word lines coupled to each main word line.

[0109] (5) When the least significant bit (LSB) of the low-order group DN_B is the same: determine that the current fault address and the subsequent fault address are both in the odd subword line or the even subword line.

[0110] refer to Figure 13 This illustrates the operation of FSM 332 when the fault mode information FSM_ST has been set to the second status value "001" after the first fault address has been detected.

[0111] When the subsequent fault address and the previous (i.e., the first) fault address are detected only in odd or even subwords coupled to the same main word line ("Yes" in S310 and "Yes" in S312), the FSM 332 can change the fault mode information FSM_ST from the second state value "001" to the third state value "010". Figure 11 ③). On the other hand, when the subsequent fault address and the previous fault address are detected in the same main word line rather than in the same order of sub-word lines ("Yes" in S310 and "No" in S312), the FSM 332 can change the fault mode information FSM_ST from the second state value "001" to the fourth state value "011". Figure 11 (④).

[0112] Furthermore, when a subsequent fault address and a previous fault address are detected in sub-word lines of the same order coupled to two adjacent main word lines ("Yes" in S320 and "Yes" in S322), the FSM 332 can change the fault mode information FSM_ST from the second state value "001" to the fifth state value "100". Figure 11 (⑤). On the other hand, when the subsequent fault address and the previous fault address are detected only in the odd or even number of sub-word lines coupled to two adjacent main word lines ("Yes" in S320, "No" in S322, and "Yes" in S324), the FSM 332 can change the fault mode information FSM_ST from the second state value "001" to the seventh state value "110" ( ). Figure 11 (⑦). When a subsequent fault address and a previous fault address are detected in two adjacent main word lines instead of in sub-word lines of the same order ("Yes" in S320, "No" in S322, and "No" in S324), the FSM 332 can change the fault mode information FSM_ST from the second state value "001" to the eighth state value "111". Figure 11 (⑧).

[0113] Furthermore, when the subsequent fault address and the previous fault address are not present in adjacent main word lines, but are detected in sub-word lines of the same order ("No" in S310, "No" in S320, and "Yes" in S330), the FSM 332 can change the fault mode information FSM_ST from the second state value "001" to the sixth state value "101". Figure 11 (⑥). On the other hand, when the subsequent fault address and the previous fault address do not exist in adjacent main word lines, but are only detected in odd or even sub-word lines ("No" in S330 and "Yes" in S324), the FSM 332 can change the fault mode information FSM_ST from the second state value "001" to the seventh state value "110" (⑥). Figure 11 (⑦). When the subsequent fault address and the previous fault address are not detected in the same order of subword lines ("No" in S330 and "No" in S324), the FSM 332 can change the fault mode information FSM_ST from the second state value "001" to the eighth state value "111". Figure 11 (⑧).

[0114] As described above, when the current fault mode information FSM_ST is set to the second state value "001", FSM 332 can set the fault mode information FSM_ST to one of the third to eighth state values.

[0115] refer to Figure 14This illustrates the operation of the FSM 332 when the fault mode information FSM_ST has been set to the third state value "010" after a fault address is detected in an odd or even sub-word line coupled to a main word line.

[0116] When the subsequent fault address and the previous fault address are detected only in the odd or even number of sub-words coupled to the same main word line ("Yes" in S410 and "Yes" in S412), the FSM 332 can maintain the fault mode information FSM_ST in the third state value "010". Figure 11 (③). On the other hand, when a subsequent fault address and a previous fault address are detected in the same main word line rather than in the same order of sub-word lines ("Yes" in S410 and "No" in S412), the FSM 332 can change the fault mode information FSM_ST from the third state value "010" to the fourth state value "011". Figure 11 (④).

[0117] Furthermore, when the subsequent fault address and the previous fault address do not exist in adjacent main word lines, but are only detected in odd or even sub-word lines ("No" in S410 and "Yes" in S420), the FSM 332 can change the fault mode information FSM_ST from the third state value "010" to the seventh state value "110". Figure 11 (⑦). When the subsequent fault address and the previous fault address are not detected in the same order of subword lines ("No" in S410 and "No" in S420), the FSM 332 can change the fault mode information FSM_ST from the third state value "010" to the eighth state value "111". Figure 11 (⑧).

[0118] refer to Figure 15 This illustrates the operation of the FSM 332 when the fault mode information FSM_ST has been set to the fourth state value "011" after a fault address is detected only in a sub-word line coupled to a main word line.

[0119] When a subsequent fault address and a previous fault address are detected in the same main word line ("Yes" in S510), the FSM332 can maintain the fault mode information FSM_ST in the fourth state value "011" ( Figure 11 (④). On the other hand, when the subsequent fault address and the previous fault address are detected in different main word lines ("No" in S510), the FSM 332 can change the fault mode information FSM_ST from the fourth state value "011" to the eighth state value "111" ( ). Figure 11 (⑧).

[0120] refer to Figure 16This illustrates the operation of the FSM 332 when the fault mode information FSM_ST has been set to the fifth state value "100" after a fault address has been detected in the same order of sub-word lines coupled to two adjacent main word lines.

[0121] When a subsequent fault address and a previous fault address are repeatedly detected in the same order of subword lines ("Yes" in S610), the FSM 332 can change the fault mode information FSM_ST from the fifth state value "100" to the sixth state value "101". Figure 11 (⑥).

[0122] On the other hand, when subsequent fault addresses and previous fault addresses are detected only in odd or even subword lines ("No" in S610 and "Yes" in S620), the FSM 332 can change the fault mode information FSM_ST from the fifth state value "100" to the seventh state value "110". Figure 11 (⑦). When neither the subsequent fault address nor the previous fault address is detected from a specific subword line ("No" in S610 and "No" in S620), the FSM 332 can change the fault mode information FSM_ST from the fifth state value "100" to the eighth state value "111". Figure 11 (⑧).

[0123] refer to Figure 17 This illustrates the operation of the FSM 332 when the fault mode information FSM_ST has been set to the sixth state value "101" after the fault address has been repeatedly detected in the same order of sub-word lines coupled to multiple master word lines.

[0124] When a subsequent fault address and a previous fault address are repeatedly detected in the same sequence of subword lines (S710 "Yes"), the FSM 332 can maintain the fault mode information FSM_ST in the sixth state value "101". Figure 11 (⑥).

[0125] On the other hand, when subsequent fault addresses and previous fault addresses are detected only in odd or even subword lines ("No" in S710 and "Yes" in S720), the FSM 332 can change the fault mode information FSM_ST from the sixth state value "101" to the seventh state value "110". Figure 11 (⑦). When the subsequent fault address and the previous fault address are not detected in the same order of subword lines ("No" in S710 and "No" in S720), the FSM 332 can change the fault mode information FSM_ST from the sixth state value "101" to the eighth state value "111". Figure 11 (⑧).

[0126] refer to Figure 18 This illustrates the operation of the FSM 332 when the fault mode information FSM_ST has been set to the seventh state value "110" after the fault address has been repeatedly detected in either the odd or even subword line.

[0127] When both the subsequent fault address and the previous fault address are detected only in odd or even subword lines (S810 "Yes"), the FSM 332 can maintain the fault mode information FSM_ST at the seventh state value "110". Figure 11 (⑦). On the other hand, when the subsequent fault address and the previous fault address are not detected in a specific sub-word line (S810 "No"), the FSM 332 can change the fault mode information FSM_ST from the seventh state value "110" to the eighth state value "111". Figure 11 (⑧).

[0128] like Figures 12 to 18 According to the present disclosure, the memory device 100 can store the fault address F_RADD first detected during the error checking operation for each row as the starting fault address S_FADD, and update the fault mode information FSM_ST that defines the relationship between the starting fault address S_FADD and the subsequent fault address F_RADD whenever a fault address is subsequently detected.

[0129] ] Figure 19 This is a block diagram illustrating a storage system according to an embodiment of the present disclosure.

[0130] See Figure 19 The storage system 1000 may include a storage device 1100 and a storage controller 1200.

[0131] Storage controller 1200 can control the overall operation of storage system 1000 and control data exchange between host and memory device 1100. Storage controller 1200 can generate command / address signals C / A in response to a request REQ from the host and provide the command / address signals C / A to memory device 1100. Storage controller 1200 can provide command / address signals C / A to memory device 1100 indicating activation operations, precharge operations, read operations, write operations, error checking operations, error message request operations, etc. Storage controller 1200 can provide data DQ to memory device 1100 corresponding to the request REQ provided from the host. Storage controller 1200 can provide data DQ read from memory device 1100 to the host. Storage controller 1200 may include ECC engine 1210 to provide error-correcting data by correcting errors in data DQ read from memory device 1100. When the number of error bits in data DQ exceeds the error correction capability of ECC engine 1210, storage controller 1200 can notify the host that an uncorrectable error (UE) has occurred.

[0132] The memory device 1100 may have the same as Figure 1 The memory device 1100 has a configuration substantially the same as that of the memory device 100. The memory device 1100 may include an ECC engine 1110. The memory device 1100 may also include wipe control circuitry and error recording circuitry (not shown). The memory device 1100 may store the fault address F_RADD first detected during an error checking operation for each row as a starting fault address S_FADD, and update the fault mode information FSM_ST, which defines the relationship between the starting fault address S_FADD and subsequent fault addresses F_RADD, whenever a fault address is subsequently detected. The memory device 1100 may provide the memory controller 1200 with error information E_INFO, including the fault mode information FSM_ST and the starting fault address S_FADD, according to the error information request command ERR_OUT. According to an embodiment, when multiple row fault modes are specified by the fault mode information FSM_ST, the memory device 1100 may output an alarm signal ALT to the memory controller 1200.

[0133] Figure 20 This is a block diagram illustrating a storage system including a storage module according to an embodiment of the present disclosure.

[0134] refer to Figure 20 The storage system 2000 may include a storage module 2100 and a storage controller 2200.

[0135] Storage controller 2200 can control the overall operation of storage system 2000 and control data exchange between the host and storage module 2100. Storage controller 2200 can generate a command / address signal C / A based on a request REQ from the host and provide the command / address signal C / A to storage module 2100, provide data DQ corresponding to the request REQ from the host to storage module 2100, and provide data DQ read from storage module 2100 to the host. Storage controller 2200 may include an ECC engine 2210 to provide error-correcting data by correcting errors in data DQ read from storage module 2100. When the number of error bits in data DQ exceeds the error-correcting capability of ECC engine 2210, storage controller 2200 can notify the host that an uncorrectable error (UE) has occurred.

[0136] Storage module 2100 may include a plurality of memory devices 2100_0 to 2100_10. Each of memory devices 2100_0 to 2100_10 may include an ECC engine 2110. Each of memory devices 2100_0 to 2100_10 may correspond to the above reference. Figure 1 The memory device 100 is described. Each of the memory devices 2100_0 to 2100_10 may further include an erase control circuit and an error recording circuit. Each of the memory devices 2100_0 to 2100_10 may store the fault address F_RADD first detected during an error checking operation for each row as a starting fault address S_FADD, and update the fault mode information FSM_ST that defines the relationship between the starting fault address S_FADD and subsequent fault addresses F_RADD whenever a fault address is subsequently detected. Each of the memory devices 2100_0 to 2100_10 may provide the memory controller 2200 with error information E_INFO including the fault mode information FSM_ST and the starting fault address S_FADD, according to the error information request command ERR_OUT. According to an embodiment, when multiple row fault modes are specified by the fault mode information FSM_ST, each of the memory devices 2100_0 to 2100_10 may output an alarm signal ALT to the memory controller 2200.

[0137] Figure 21 This is a block diagram illustrating a storage system including stacked memory devices according to an embodiment of the present disclosure.

[0138] refer to Figure 21 The storage system 3000 may include a package board / substrate 3140, an interposer 3130, one or more stacked memory devices 3110 and a processor 3120.

[0139] The package board / substrate 3140 may include a printed circuit board (PCB). The package board / substrate 3140 may be electrically connected to an external system board, motherboard, or module board via bumps.

[0140] Interposer 3130 can be formed on package board / substrate 3140. Interposer 3130 can be a silicon substrate with only wiring formed on it.

[0141] The stacked memory device 3110 and processor 3120 can be formed on the interposer layer 3130. The stacked memory device 3110 and processor 3120 can be disposed on the interposer layer 3130 with spacing between them. Furthermore, although... Figure 21 A stacked memory device 3110 is shown, but the invention is not limited thereto, and one or more stacked memory devices may be formed on the interposer layer 3130.

[0142] Processor 3120 may include a memory controller (MC) 3121 and a physical interface circuit (PHY) 3122. The memory controller 3121 may be configured to control a stacked memory device 3110. The physical interface circuit 3122 may interface between the memory controller 3121 and the stacked memory device 3110. The physical interface circuit 3122 may be an interface circuit that converts signals transmitted from the memory controller 3121 into signals suitable for use in the stacked memory device 3110 and outputs signals transmitted from the stacked memory device 3110 into signals suitable for use in the memory controller 3121. Processor 3120 may be one of a variety of processors, such as a microprocessor unit (MPU), a central processing unit (CPU), a general-purpose processing unit (GPU), and a host processing unit (HPU).

[0143] The stacked memory device 3110 may include a lower chip 3114 and one or more upper chips 3112_0 to 3112_3 vertically stacked on an interposer layer 3130. As described above, an example of the stacked memory device 3110 formed by stacking multiple chips may be a high-bandwidth memory (HBM). A through-electrode (TSV) is formed between the lower chip 3114 and the upper chips 3112_0 to 3112_3, through which signals (i.e., commands, addresses, and data) can be transmitted between the chips.

[0144] The lower chip 3114 may include a physical interface circuit (PHY) 3116 for interfacing with the memory controller 3121. Each of the upper chips 3112_0 to 3112_3 may correspond to Figure 1The memory device 100 described herein. Specifically, each of the upper chips 3112_0 to 3112_3 may further include an erase control circuit and an error recording circuit. Each of the upper chips 3112_0 to 3112_3 may store the fault address F_RADD first detected during an error checking operation for each row as a starting fault address S_FADD, and update the fault mode information FSM_ST, which defines the relationship between the starting fault address S_FADD and subsequent fault addresses F_RADD, whenever a fault address is subsequently detected. Each of the upper chips 3112_0 to 3112_3 may provide the memory controller 3121 with error information E_INFO, including the fault mode information FSM_ST and the starting fault address S_FADD, according to the error information request command ERR_OUT. According to an embodiment, when a multi-row fault mode is specified according to the fault mode information FSM_ST, each of the upper chips 3112_0 to 3112_3 may output an alarm signal ALT to the memory controller 3121.

[0145] In the above embodiments, the memory device includes an ECC engine and performs error checking and error logging operations, but the present invention is not limited thereto. According to an embodiment, when the memory device does not have an ECC engine, the memory controller can perform error checking and error logging operations. For example, the memory controller can transmit row and column addresses along with an erase command to the memory device, the memory device can read data from the corresponding rows and columns, and the memory controller can perform error checking and error logging operations on each row based on the read data.

[0146] Figure 22 This is a block diagram illustrating a storage system according to another embodiment of the present disclosure.

[0147] refer to Figure 22 The storage system 4000 may include a storage device 4100 and a storage controller 4200.

[0148] The storage controller 4200 can control the overall operation of the storage system 4000 and control the data exchange between the host and the memory device 4100. The storage controller 4200 can generate a command / address signal C / A in response to a request REQ from the host and provide the command / address signal C / A to the memory device 4100. The storage controller 4200 can provide the memory device 4100 with command / address signals C / A indicating activation operations, precharge operations, read operations, write operations, error checking operations, error message request operations, etc. The storage controller 4200 can provide the memory device 4100 with data DQ corresponding to the request REQ provided from the host. The storage controller 4200 can provide the data DQ read from the memory device 4100 to the host.

[0149] Memory device 4100 may include dynamic random access memory (DRAM), which includes dynamic memory cells. Memory device 4100 may be double data rate 4 (DDR4) synchronous DRAM (SDRAM), DDR5 SDRAM, low power DDR4 (LPDDR4) SDRAM, LPDDR5 SDRAM, or others. Memory device 4100 may include a memory cell array in which multiple memory cells coupled to multiple rows and multiple columns are arranged in an array.

[0150] The storage controller 4200 may include a host interface 4210, a scheduler 4220, an error correction code (ECC) engine 4230, an erase control module 4240, an error logging module 4250, and a memory interface 4260.

[0151] The host interface 4210 can be an interface used for communication between the host and the storage controller 4200.

[0152] Scheduler 4220 can receive requests (REQs) from the host via host interface 4210. Scheduler 4220 can generate various commands (e.g., activation command, precharge command, read command, write command, repair command, etc.) and addresses based on the requests (REQs). Scheduler 4220 can set the order of requests to be directed to memory device 4100 in the requests (REQs) from the host, and generate commands to be applied to memory device 4100 according to a predetermined order of operations. To improve the performance of memory device 4100, scheduler 4220 can change the order in which requests (REQs) are received from the host and the order of operations to be directed to memory device 4100. For example, even if the host requests a read operation from memory device 4100 first and then a write operation, scheduler 4220 can adjust the order so that the write operation is performed before the read operation.

[0153] The ECC engine 4230 can correct errors in the data DQ read from the memory device 4100 and provide the corrected data to the host. Error correction may include error checking operations for checking for errors in the data DQ, and error correction operations for correcting errors in the data DQ when errors are found.

[0154] The scrubbing control module 4240 can provide the addresses of the rows and columns to be scrubbed, along with a scrubbing command instructing the scrubbing operation, to the memory device 4100 during the scrubbing period. The memory device 4100 can perform a scrubbing operation on the memory cells connected between the rows and columns selected by the addresses, according to the scrubbing command. The memory device 4100 can perform a scrubbing operation, which includes: a read operation for reading data from the selected memory cell and providing the read data to the memory controller 4200; and / or a write operation for rewriting error-corrected data provided by the memory controller 4200 to the selected memory cell.

[0155] The ECC engine 4230 can perform an error checking operation to check for errors in the data DQ read from the memory device 4100 during the wipe operation, and generate an error signal ERR when an error is detected.

[0156] Error logging module 4250 can record errors found during error checking operations according to the scrubbing command. Error logging module 4250 can generate error information based on the recording results to provide the error information to the host. According to an embodiment, error logging module 4250 can correspond to... Figure 1 The error recording circuit 180. That is, the error recording module 4250 may include a fault detection circuit and a fault information management circuit.

[0157] Memory device 4100 may include multiple cell blocks, each cell block including multiple memory cells MC, as referenced above. Figure 2A and Figure 2B The memory device 4100 may provide a reset signal RST_E to the memory controller 4200, which is activated when an erase operation is completed on rows included in at least two adjacent cell blocks of a plurality of cell blocks.

[0158] Therefore, when a fault address is generated based on the wiping operation for each row, the fault detection circuit can output a fault address and a fault input signal. The fault information management circuit can store the first fault address input after activation by the reset signal RST_E as the starting fault address and generate fault mode information defining the relationship between the stored starting fault address and subsequently input fault addresses. The fault information management circuit can provide error information to the host, including the starting fault address and fault mode information. The fault information management circuit can initialize the fault mode information based on the reset signal RST_E. According to an embodiment, when a fault mode involving two or more rows is specified according to the fault mode information, the fault information management circuit can provide an alarm signal to the host.

[0159] The memory interface 4260 can be configured to communicate with the memory device 4100. For example, the memory interface 4260 can transmit command / address signals C / A and data DQ to the memory device 4100 and receive data DQ read from the memory device 4100.

[0160] As described above, in the embodiments, even if the memory device 4100 does not embed an ECC engine, the error logging module 4250 of the storage controller 4200 can generate error information including the starting fault address and fault mode information to identify possible fault modes based on the fault line specified by the starting fault address, thereby effectively managing errors and performing optimized reliability, accessibility and serviceability (RAS) operations.

[0161] While this disclosure has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A memory device comprising: an array of memory cells including memory cells coupled to a plurality of rows; a failure detection circuit that: generates first through third failure addresses from results of error check operations for each of the plurality of rows, and sequentially outputs the first through third failure addresses with a failure input signal; and a failure information management circuit that: stores the first failure address as a start failure address and generates failure pattern information defining a relationship between the start failure address and the second and third failure addresses from the failure input signal; and outputs error information including the start failure address and the failure pattern information.

2. The memory device of claim 1, wherein, the failure information management circuit: sequentially compares the start failure address with the second and third failure addresses from the failure input signal to update the failure pattern information to one of a plurality of state values defining a failure of one or more rows related to a defective row specified by the start failure address.

3. The memory device of claim 1, wherein, the failure information management circuit: outputs an alarm signal when a failure pattern caused by two or more rows is specified from the failure pattern information.

4. The memory device of claim 1, further comprising: a scrub control circuit that: generates a reset signal that is activated when the error check operations for rows included in at least two adjacent cell blocks of a plurality of cell blocks divided from the plurality of rows are completed, wherein the first failure address is input for the first time after the reset signal is activated.

5. The memory device of claim 4, wherein, the failure information management circuit: initializes the failure pattern information from the reset signal.

6. The memory device of claim 1, wherein, the failure information management circuit includes: an address storage circuit that: stores the first failure address as the start failure address from a reset signal and the failure input signal; stores the second failure address as a first comparison address from the failure input signal input in odd order; and stores the third failure address as a second comparison address from the failure input signal input in even order; and a failure analysis circuit that: updates the failure pattern information from a result of comparison of the first and second comparison addresses; and outputs the error information including the start failure address and the failure pattern information from an error information request command.

7. The memory device of claim 6, wherein, the address storage circuit includes: a memory device controller that: outputs the first failure address as the start failure address from the failure input signal input for the first time after the reset signal is activated; and outputs the second and third failure addresses as the first and second comparison addresses, respectively, from an input order of the failure input signal; a first address storage device that stores the start failure address; a second address storage device that stores the first comparison address; and a third address storage device that stores the second comparison address.

8. The memory device of claim 6, wherein, the failure analysis circuit includes: a finite state machine that: updates the failure mode information according to a result of the comparison, and initializes the failure mode information according to the reset signal; and an information output circuit that outputs the error information including the start failure address and the failure mode information according to the error information request command.

9. An error recording apparatus comprising: a failure detection circuit that outputs a failure address with a failure input signal; an address storage circuit that stores the failure address as a start failure address according to a reset signal and the failure input signal, stores the failure address as a first comparison address according to the failure input signal input in odd-numbered order, and stores the failure address as a second comparison address according to the failure input signal input in even-numbered order; a FSM that updates failure mode information according to a result of comparison of the first comparison address and the second comparison address, the FSM indicating a finite state machine; and an error information output circuit that outputs error information including the failure mode information and the start failure address according to an error information request command.

10. The error recording apparatus of claim 9, wherein, The address storage circuit includes: a storage device controller that outputs a first failure address as the start failure address according to the failure input signal input for the first time after the reset signal is activated, and outputs the second failure address and the third failure address as the first comparison address and the second comparison address, respectively, according to the input order of the failure input signal; a first address storage device that stores the start failure address; a second address storage device that stores the first comparison address; and a third address storage device that stores the second comparison address.

11. The error recording apparatus according to claim 9, wherein the reset signal is provided from a memory device including a storage unit coupled to a plurality of rows, and wherein the memory device generates the reset signal that is activated when an error check operation for rows included in at least two adjacent cell blocks among a plurality of cell blocks divided by the plurality of rows is completed.

12. The error recording apparatus according to claim 9, wherein each of the first comparison address and the second comparison address includes a first bit group for specifying a main word line and a second bit group for specifying a sub word line, and wherein the FSM updates the failure mode information by comparing the first bit group and the second bit group of the first comparison address and the second comparison address, respectively.

13. The error recording apparatus according to claim 12, wherein the FSM: sets the failure mode information to a first state value according to the reset signal, and updates the failure mode information from the first state value to a second state value when the start failure address is stored.

14. The error logging apparatus of claim 12, wherein, the failure mode information is set to the second state value, and the FSM: in a state where the first bit group is identical, the fault mode information is updated to a third state value when LSBs of the second bit group are identical, and the fault mode information is updated to a fourth state value when the LSBs of the second bit group are different from each other, LSB indicating least significant bit, in a state where a difference between values of the first bit group is 1, the fault mode information is updated to a fifth state value when the second bit group is identical, in a state where the difference is greater than or equal to 2, the fault mode information is updated to a sixth state value when the second bit group is identical, and in a state where the difference is greater than or equal to 1, the fault mode information is updated to a seventh state value when only the LSBs of the second bit group are identical.

15. The error logging apparatus of claim 12, wherein, the fault mode information is set to a third state value, and the FSM: in a state where the first bit group is identical, the fault mode information is maintained as the third state value when LSBs of the second bit group are identical, and the fault mode information is updated to a fourth state value when the LSBs of the second bit group are different from each other, LSB indicating least significant bit, and in a state where a difference between values of the first bit group is greater than or equal to 1, the fault mode information is updated to a seventh state value when only the LSBs of the second bit group are identical.

16. The error logging apparatus of claim 12, wherein, the fault mode information is set to a fourth state value, and the FSM: the fault mode information is maintained as the fourth state value when the first bit group is identical.

17. The error logging apparatus of claim 12, wherein, the fault mode information is set to a fifth state value, and the FSM: the fault mode information is updated to a sixth state value when the second bit group is identical, and the fault mode information is updated to a seventh state value when LSBs of the second bit group are identical, LSB indicating least significant bit.

18. The error logging apparatus of claim 12, wherein, the fault mode information is set to a sixth state value, and the FSM: the fault mode information is maintained as the sixth state value when the second bit group is identical, and the fault mode information is updated to a seventh state value when LSBs of the second bit group are identical, LSB indicating least significant bit.

19. The error logging apparatus of claim 12, wherein, the fault mode information is set to a seventh state value, and the FSM: the fault mode information is maintained as the seventh state value when LSBs of the second bit group are identical, LSB indicating least significant bit.

20. An error recording method, comprising: initializing fault mode information according to a reset signal; storing a fault address as a start fault address according to a fault input signal inputted for the first time after initialization, and updating the fault mode information; storing the fault address as a first comparison address according to the fault input signal inputted in odd number order, storing the fault address as a second comparison address according to the fault input signal inputted in even number order, and updating the fault mode information according to a result of comparison of the first comparison address and the second comparison address; and output error information including the failure mode information and the start failure address according to an error information request command.

21. The error logging method of claim 20, further comprising: receiving the reset signal from a memory device including memory cells coupled with a plurality of rows, wherein the reset signal is activated when an error check operation for rows included in at least two adjacent cell blocks among a plurality of cell blocks divided by the plurality of rows is completed.

22. The error logging method of claim 20, further comprising: outputting an alarm signal when a failure mode caused by two or more rows is designated by the failure mode information.

23. A memory system, comprising: a memory controller; and a memory device which performs a scrub operation for each of a plurality of rows under control of the memory controller and generates a reset signal according to the scrub operation, wherein the memory controller includes: a failure detection circuit which generates first to third failure addresses according to the scrub operation and sequentially outputs the first to third failure addresses together with a failure input signal; and a failure information management circuit which stores the first failure address as a start failure address and generates failure mode information defining a relationship between the start failure address and the second and third failure addresses according to the failure input signal and the reset signal, and outputs error information including the start failure address and the failure mode information.

24. The storage system of claim 23, wherein, the memory device generates the reset signal activated when the scrub operation for rows included in at least two adjacent cell blocks among a plurality of cell blocks divided by the plurality of rows is completed.

25. The storage system of claim 23, wherein, the failure information management circuit: outputs an alarm signal when a failure mode caused by two or more rows is designated by the failure mode information, and initializes the failure mode information according to the reset signal.

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