Switching power supply oscillator with frequency jittering function

Abstract

The application discloses a switching power supply oscillator with frequency jitter function, which comprises a reference circuit, an operational amplifier EA, a bias current source, PMOS tubes P1-P3, an oscillator capacitor Cosc and a frequency jitter control circuit, wherein the frequency jitter control circuit comprises a comparator Comp, a logic control circuit, NMOS tubes N1-N5 and resistors R0-R5; the frequency jitter control circuit controls the charging and discharging of the Cosc to form an oscillator, and the oscillator signal CLK controls the logic control circuit to continuously flip the level, short-circuit or connect the resistors R1-R5, so as to make the frequency jitter control voltage linearly rise or fall, and further realize the wide frequency change in the 64 gears and 256 switching frequency ranges, so that the interference energy is distributed in each frequency band, and the peak spectrum of the frequency signal is effectively reduced. The application realizes the oscillator with the frequency jitter function, is easy to be monolithically integrated, and can significantly reduce the chip area and cost.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to power management, specifically a switching power supply oscillator with frequency dithering function. Background Technology

[0002] With the rapid development of semiconductor technology and the communications and automotive electronics industries, the application areas of switching power supplies are constantly expanding. Most switching-mode power supplies operate at a fixed and fast switching frequency; however, such a switching frequency and its associated harmonics generate strong noise, causing significant electromagnetic interference (EMI). EMI consists of two parts: the switching frequency and its harmonics (multiples of the switching frequency). EMI varies periodically with the switching frequency. If the interference energy is concentrated at discrete switching frequencies, it is difficult to meet EMI standards and comply with international or regional electromagnetic compatibility (EMC) standards, thus avoiding interference with other equipment. Many methods exist to suppress EMI, such as increasing filter capacitors or reducing leakage inductance and distributed capacitance. Frequency dithering is also an effective method for reducing EMI. Dithering or jittering the switching frequency can distribute noise energy over a wide bandwidth, thereby suppressing noise and improving the conduction performance of EMI. Figure 1 As shown, frequency dithering technology disperses harmonic interference energy by periodically changing the operating frequency of the switching power supply. Harmonic energy originally concentrated at a specific frequency fc is dispersed over a wider frequency range, generating a series of discrete sidebands fm. This expands the interference spectrum, distributing the interference energy across various frequency bands, effectively reducing the peak frequency spectrum and making it easier to meet EMI standards. However, the frequency dithering techniques commonly used in switching power supplies are exponential modulation or triangular modulation, both of which have limited and unsatisfactory EMI reduction effects. Pseudo-random dithering techniques are also used, but these have complex circuit structures and high costs. Therefore, designing a circuit with a simple structure that effectively reduces EMI in switching power supplies is a problem that those skilled in the art must solve.

[0003] In response to this, existing technologies include US Patent 6,249,876, which discloses a frequency dithering control circuit that adjusts the charging and discharging current in the power supply oscillation circuit to change the switching frequency of the power supply, thereby reducing EMI radiation. However, this solution requires a large capacitor for charging and discharging, which is detrimental to reducing costs and chip circuit integration. US Patent 7701305, on the other hand, uses a discontinuous reference voltage signal to control frequency changes, resulting in limited accuracy in predicting frequency variations.

[0004] The Chinese patent CN113422507B discloses a frequency jitter control circuit and a switching power supply, comprising: a frequency generation circuit for generating a clock signal; a frequency jitter circuit for generating a pseudo-random code and decoding the pseudo-random code to generate a control signal; and a voltage selector for selecting different reference voltages fed back to the frequency generation circuit according to the control signal generated by the frequency jitter circuit to obtain different clock signals. The scheme adopts a pseudo-random frequency jitter technology, and the circuit is relatively complex. The voltage selector uses a reference voltage to control the frequency of the oscillator. The frequency of the oscillator is changed by changing the reference voltage. Different reference voltages are realized by dividing the voltage with a resistor string. Different reference voltages are sampled by controlling the switch, so as to output the reference voltage for the oscillator. If the number of resistors in series is small, the sampling range is small; if the number of resistors in series is large, the size of the sampling circuit is significantly increased. Therefore, high precision, wide range and low cost cannot be considered at the same time.

[0005] The Chinese patent CN102647087B discloses a pulse width modulation controller. The current sensing signal of a power switch is obtained, and the gain or level of the signal is adjusted according to the switching frequency to adjust the working time of the power switch and reduce the output ripple. The specific method includes changing the gain of the current sensing signal by using a programmable amplifier or changing the level of the current sensing signal by using a counter and a frequency jitter modulator to adjust the working time Ton and improve the output ripple problem. A series of signal processing such as pulse width modulation, clock signal counting and programmable amplifier gain is required in the circuit, but the control signal system is complex and not conducive to single-chip integration.

[0006] Therefore, there is a need for a smaller, more cost-effective and independent frequency jitter circuit to change the switching frequency of the power supply. SUMMARY

[0007] The technical problem to be solved by the present application is that the existing technology has a complex circuit and insufficient precision, which is not conducive to integration.

[0008] The technical solution of the present application is: a switching power supply oscillator with frequency jitter function, comprising a reference circuit, an operational amplifier EA, a bias current source, PMOS tubes P1-P3, an oscillator capacitor Cosc and a frequency jitter control circuit,

[0009] The frequency jitter control circuit comprises a comparator Comp, a logic control circuit, NMOS tubes N1-N5 and resistors R0-R5, wherein the resistances of R1-R5 are proportional;

[0010] The reference circuit outputs connect the negative phase end of the operational amplifier EA, the output of the operational amplifier EA connects the gate of P1, P2, P3, the positive phase end of the operational amplifier EA and the drain of P1 connect the ground through the bias resistor Rbias; the source and body of P1, P2, P3 connect the power supply end VIN of the switching power supply, the drain of P2 connects the ground through Cosc, the reference circuit, the operational amplifier EA, the bias resistor Rbias and P1 provide the bias current for P2 and P3, P2 charges Rbias, the drain of P2 also connects the drain of an NMOS N0 and the positive end of the comparator Comp, the source and body of N0 connect the ground together; the drain of P3 outputs the dithering frequency control voltage V1 to the negative end of the comparator Comp, and connects the ground through the series connection of R0-R5, and the voltage division is formed on R0-R5;

[0011] The output end of the comparator Comp outputs the oscillator signal CLK to the gate of N0 and the input end of the control logic circuit, the control logic circuit is a frequency divider, which outputs the control signals A, B, C, D, E after frequency division, and the level is continuously flipped in a period, the control signals control the gates of N1, N2, N3, N4, N5, and the high level is continuously turned on from E to A, R5, R4, R3, R2, R1 are continuously short-circuited through N1, N2, N3, N4, N5, the voltage V1 continuously linearly decreases, the frequency of the oscillator continuously increases, and the high level is continuously turned from A to E to low level in a period, R5, R4, R3, R2, R1 are continuously connected to R0, the voltage V1 continuously linearly increases, the frequency of the oscillator continuously decreases, the frequency is periodically modulated, the interference energy is distributed on each frequency band, and the peak spectrum of the frequency signal is reduced.

[0012] Further, in the dithering frequency control circuit, R0 is a fixed resistance, R1-R5 are trimming resistors, and the ratio of R1:R2:R3:R4:R5 is 16:8:4:2:1.

[0013] Further, the control logic circuit outputs the signals A, B, C, D, E to the gates of N1, N2, N3, N4, N5, the drain of N1 is connected between R0 and R1, the source and body of N1 and the drain of N2 are connected between R1 and R2, the source and body of N2 and the drain of N3 are connected between R2 and R3, the source and body of N3 and the drain of N4 are connected between R3 and R4, the source and body of N4 and the drain of N5 are connected between R4 and R5, and the source and body of N5 are connected to the ground.

[0014] Further, the operational amplifier EA includes 4 PMOS transistors PE1-PE4, 3 NMOS transistors NE1-NE3, a compensation resistor Rc1 and a compensation capacitor Cc1, the source and body terminals of PE1 and PE2 are connected to VIN, the drain of PE1 is connected to the source and body terminals of PE3 and PE4, the gates of PE1 and PE2 are connected to the bias current source control signal B+, the gate of PE3 is the negative phase terminal of the operational amplifier, the gate of PE4 is the positive phase terminal of the operational amplifier, the drain of PE3 is connected to the drain and gate of NE1 and the gate of NE2, the source and body terminals of NE1, NE2 and NE3 are connected to ground, the drain of PE4, the drain of NE2 and the gate of NE3 are connected to ground through the series connection of Rc1 and Cc1, the drain of PE2 is connected to the drain of NE3 and outputs the signal OP_out.

[0015] Further, the comparator Comp includes 4 PMOS transistors PC1-PC4 and 3 NMOS transistors NC1-NC3, the source and body terminals of PC1 and PC2 are connected to VIN, the drain of PC1 is connected to the source and body terminals of PC3 and PC4, the gates of PC1 and PC2 are connected to the bias current source control signal B+, the gate of PC3 is the negative phase terminal of the comparator, the gate of PC4 is the positive phase terminal of the comparator, the drain of PC3 is connected to the drain and gate of NC1 and the gate of NC2, the source and body terminals of NC1, NC2 and NC3 are connected to ground, the drain of PC4 is connected to the drain of NC2 and the gate of NC3, the drain of PC2 is connected to the drain of NC3 and outputs the output signal Comp_out of the comparator.

[0016] Further, the logic control circuit includes 8 D flip-flops DFF1-DFF8, a group of inverters inv*, a group of NOR gates nor*, a group of NAND gates nand*, PMOS transistors P1L and P2L and NMOS transistors N1L and N2L, and * indicates the number of corresponding devices.

[0017] The D end and the Q end of each of DFF1-DFF8 are connected together, the signal CLK is input to the clock end clk of DFF1, then the output Q of the previous stage D flip-flop drives the clock clk of the next stage D flip-flop, the output Q end of the last stage DFF8 is connected to the input end of the inverter inv5, the input end of the inverter inv3 and the source ends of P1L and N2L, the body ends of P1L and P2L are connected to VIN, the body ends of N1L and N2L are connected to the ground GND; the output end of inv5 is connected to the source ends of N1L and P2L, the Q end of DFF7 is connected to the input end of inv4, the gate ends of N2L and P2L, the output end of inv4 is connected to the gate ends of P1L and N1L, the output end of inv1 is connected to the input end 1 of nor1A, the input end 1 of nor1B, the input end 1 of nor1C and the input end 1 of nor1D; the output end of inv2 is connected to the input end 1 of nor2A, the input end 1 of nor2B, the input end 1 of nor2C and the input end 1 of nor2D, the Q end of DFF6 is connected to the input end of inv3A and the input end 2 of nor2A, the Q end of DFF5 is connected to the input end of inv3B and the input end 2 of nor2B, the Q end of DFF4 is connected to the input end of inv3C and the input end 2 of nor2C, the Q end of DFF3 is connected to the input end of inv3D and the input end 2 of nor2D; the output end of inv3A is connected to the input end 2 of nor1A, the output end of inv3B is connected to the input end 2 of nor1B, the output end of inv3C is connected to the input end 2 of nor1C, the output end of inv3D is connected to the input end 2 of nor1D,

[0018] inv3 outputs a control signal A; the output of nor1A and the output of nor2A are input to nand1A after being inverted by inv1A and invA2 respectively, outputting a control signal B; the output of nor1B and the output of nor2B are input to nand1B after being inverted by inv1B and inv2B respectively, outputting a control signal C; the output of nor1C and the output of nor2C are input to nand1C after being inverted by inv1C and inv2C respectively, outputting a control signal D; the output of nor1D and the output of nor2D are input to nand1D after being inverted by inv1D and inv2D respectively, outputting a control signal E.

[0019] Further, after the oscillator signal CLK is divided by DFF1-DFF8, the periods are 2:4:8:16:32:64:128:256 respectively, the control R1-R5 generates 32 continuous resistance value changes in the range of 0-31, combined with the resistance of R0, the V1 voltage is continuously changed on the basis of the R0 voltage division, the oscillator frequency formed based on the V1 voltage is continuously changed around the center frequency with a change of 1 / 32, forming the spread spectrum effect.

[0020] The present application can realize the frequency jitter control through simple oscillator circuit and logic control circuit. Compared with the exponential modulation method or the triangle modulation method, the effect of reducing EMI is more ideal; compared with the pseudo-random frequency jitter technology, the circuit structure is simple. At the same time, the small bias current in the control is not required to use the large charge and discharge capacitor; the sampling resistance continuously changes, and the precision of the discontinuous frequency change is avoided; the proportional resistance 16:8:4:2:1 is adopted, 32 resistance value gears are generated in the wide range of 0-31, the resistance increases from 0 to 31 and then decreases from 31 to 0 in the whole oscillator period, the oscillator frequency increases from low to high and then decreases from high to low, 32+32=64 gears are continuously changed, and the cycle is repeated, the proportional change range of the traditional linear resistance can be larger, so that the high-precision continuous output voltage in a wide range is realized; at the same time, the digital logic is simple and clear, easy to integrate, and external signals are avoided to realize the control.

[0021] Therefore, the present application can realize the high-precision and wide-range frequency jitter control through the small-scale circuit structure, is easy to integrate, can save the chip area, and reduces the cost. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 For the frequency jitter prior art example, the noise energy is distributed to a wide band, and the EMI characteristics are improved.

[0023] Figure 2 The oscillator circuit with frequency jitter control function of the present application.

[0024] Figure 3 The operational amplifier EA circuit used in the present application.

[0025] Figure 4 The comparator Comp circuit used in the present application.

[0026] Figure 5 The logic control circuit used in the present application.

[0027] Figure 6 The effect schematic diagram of the embodiment of the circuit of the present application, the oscillator frequency periodically changes, has a wide range and high precision. DETAILED DESCRIPTION

[0028] The specific implementation of the present application will be described below in combination with the drawings.

[0029] The specific circuit of the oscillator with frequency jitter function of the present application is as follows Figure 2As shown, it comprises reference circuit, operational amplifier EA, bias current source, PMOS tubes P1-P3, oscillator capacitor Cosc and dithering control circuit, the dithering control circuit comprises comparator Comp, logic control circuit, NMOS tubes N1-N5 and resistors R0-R5, R0 is a fixed resistor, R1-R5 are proportional in resistance value, all are trimming resistors. As an embodiment, the ratio of R1:R2:R3:R4:R5 is 16:8:4:2:1. Cosc is the oscillator capacitor, Rbias is the bias resistor, used to generate the bias current for charging the capacitor. VIN is the power supply terminal, and GND is the ground. The reference is a conventional reference voltage circuit, the bias current source is a conventional reference current source circuit, providing bias voltage B+ and B-, output to operational amplifier EA and comparator Comp. EA is the error amplifier, i.e. operational amplifier. Comp is the comparator. The control logic is the digital logic circuit of dithering control, outputting signals A / B / C / D / E. CLK is the oscillator signal with dithering.

[0030] The negative phase terminal of the operational amplifier EA is connected with the output of the reference circuit, the output of the operational amplifier EA is connected with the gate of P1, P2 and P3, the positive phase terminal of the operational amplifier EA and the drain of P1 are connected with the ground through the bias resistor Rbias; the source and body of P1, P2 and P3 are connected together and connected with the power supply terminal VIN of the switching power supply, the drain of P2 is connected with the ground through Cosc, the reference circuit, the operational amplifier EA, the bias resistor Rbias and P1 provide bias current for P2 and P3, P2 charges Rbias, the drain of P2 is also connected with the drain of NMOS tube N0 and the positive terminal of comparator Comp, the source and body of N0 are connected with the ground together; the drain of P3 outputs dithering control voltage V1 to the negative terminal of Comp, and is connected with the ground through the series connection of R0-R5, forming a voltage division on R0-R5; the output terminal of the comparator Comp outputs the oscillator signal CLK to the gate of N0 and the input terminal of the control logic circuit, the control logic circuit is a frequency divider, outputting control signals A, B, C, D and E after dividing the frequency of CLK, continuously flipping the level in a period, the control signals control the gates of N1, N2, N3, N4 and N5, continuously turning on the high level from E to A, controlling R5, R4, R3, R2 and R1 to be continuously short-circuited through N1, N2, N3, N4 and N5, continuously linearly reducing the voltage of V1, continuously rising the frequency of the oscillator, and then continuously turning from high level to low level from A to E in a period, connecting R5, R4, R3, R2 and R1 to R0 in sequence, continuously linearly rising the voltage of V1, continuously reducing the frequency of the oscillator, realizing the periodic modulation of the frequency, distributing the interference energy on each frequency band, and reducing the peak spectrum of the frequency signal.

[0031] Figure 3The connection circuit of the operational amplifier EA used in the application, B+ is a bias current source control signal, OP_out is an output signal, VIN is a power supply, and GND is a ground. PE1, PE2, PE3, and PE4 are PMOS tubes, NE1, NE2, and NE3 are NMOS tubes, Rc1 is a compensation resistor, and Cc1 is a compensation capacitor.

[0032] The source and body terminals of PE1 and PE2 are connected to VIN. The drain terminal of PE1 is connected to the source and body terminals of PE3 and PE4. The gate terminals of PE1 and PE2 are connected to the B+ signal. The gate terminal of PE3 is the input negative terminal of the operational amplifier, and the gate terminal of PE4 is the input positive terminal of the operational amplifier. The drain terminal of PE3 is connected to the drain terminal and the gate terminal of NE1, and the gate terminal of NE2. The source and body terminals of NE1, NE2, and NE3 are connected to the ground together. The drain terminal of PE4, the drain terminal of NE2, and the gate terminal of NE3 are connected to the ground through the series connection of Rc1 and Cc1, and the drain terminal of PE2 is connected to the drain terminal of NE3 and outputs the signal OP_out.

[0033] Figure 4 The connection circuit of the comparator Comp used in the application: B+ is a bias current source control signal, Comp_out is an output signal, VIN is a power supply, and GND is a ground. PC1, PC2, PC3, and PC4 are PMOS tubes, and NC1, NC2, and NC3 are NMOS tubes.

[0034] The source and body terminals of PC1 and PC2 are connected to VIN. The drain terminal of PC1 is connected to the source and body terminals of PC3 and PC4. The gate terminals of PC1 and PC2 are connected to the B+ signal. The gate terminal of PC3 is the input negative terminal of the comparator, and the gate terminal of PC4 is the input positive terminal of the comparator. The drain terminal of PC3 is connected to the drain terminal and the gate terminal of NE1, and the gate terminal of NC2. The source and body terminals of NC1, NC2, and NC3 are connected to the ground together. The drain terminal of PC4 is connected to the drain terminal of NC2 and the gate terminal of NC3. The drain terminal of PC2 is connected to the drain terminal of NC3 and outputs the signal Comp_out.

[0035] Figure 5The connection mode of the logic control circuit used in the application is shown: CLK is the input terminal of the logic control circuit, A, B, C, D, E are its output signals. VIN is the power supply, GND is the ground. DFF1, DFF2, DFF3, DFF4, DFF5, DFF6, DFF7, DFF8 are conventional D flip-flops, respectively having clk, D, Q and -Q ports. Inv1, inv2, inv3, inv4, inv5, inv1A, inv2A, inv3A, inv1B, inv2B, inv3B, inv1C, inv2C, inv3C, inv1C, inv2C, inv3C, inv1D, inv2D, inv3D are inverters. Nor1A, nor2A, nor1B, nor2B, nor1C, nor2C, nor1D, nor2D are NOR gates. Nan1A, nand1B, nand1C, nand1D are NAND gates.

[0036] The respective D terminals and -Q terminals of DFF1-DFF8 are connected together, the signal CLK is input to the clock terminal clk of DFF1, and then the output Q of the previous stage D flip-flop drives the clock clk of the next stage D flip-flop.

[0037] The output Q terminal of DFF8 is connected to the input terminal of inverter inv5, the input terminal of inv3 and the source terminals of P1L and N2L, the body terminals of P1L and P2L are connected to VIN, the body terminals of N1L and N2L are connected to the ground GND; the output terminal of inv5 is connected to the source terminals of N1L and P2L, the Q terminal of DFF7 is connected to the input terminal of inv4, the gate terminals of N2L and P2L, the output terminal of inv4 is connected to the gate terminals of P1L and N1L, the output terminal of inv1 is connected to the input terminal 1 of nor1A, the input terminal 1 of nor1B, the input terminal 1 of nor1C and the input terminal 1 of nor1D; the output terminal of inv2 is connected to the input terminal 1 of nor2A, the input terminal 1 of nor2B, the input terminal 1 of nor2C and the input terminal 1 of nor2D, the Q terminal of DFF6 is connected to the input terminal of inv3A and the input terminal 2 of nor2A, the Q terminal of DFF5 is connected to the input terminal of inv3B and the input terminal 2 of nor2B, the Q terminal of DFF4 is connected to the input terminal of inv3C and the input terminal 2 of nor2C, the Q terminal of DFF3 is connected to the input terminal of inv3D and the input terminal 2 of nor2D; the output terminal of inv3A is connected to the input terminal 2 of nor1A, the output terminal of inv3B is connected to the input terminal 2 of nor1B, the output terminal of inv3C is connected to the input terminal 2 of nor1C, and the output terminal of inv3D is connected to the input terminal 2 of nor1D.

[0038] The output of nor1A and the output of nor2A are inputted into nand1A after being inverted by inv1A and inv2A respectively, and output control signal B; the output of nor1B and the output of nor2B are inputted into nand1B after being inverted by inv1B and inv2B respectively, and output control signal C; the output of nor1C and the output of nor2C are inputted into nand1C after being inverted by inv1C and inv2C respectively, and output control signal D; the output of nor1D and the output of nor2D are inputted into nand1D after being inverted by inv1D and inv2D respectively, and output control signal E.

[0039] The working principle of the circuit is that the reference, the operational amplifier, the Rbias resistor and P1 generate a bias current, and at the same time, provide a bias current for the oscillator charging tube P2 and the frequency jitter voltage control circuit P3. The P1 bias current is the reference voltage divided by the resistance Rbias. P2, Cosc, N0, the comparator Comp and the V1 voltage jointly constitute an oscillator circuit. P3, R0, R1, R2, R3, R4, R5 and switches N1, N2, N3, N4, N5, and control logic together, constitute a reference voltage circuit continuously variable with the oscillator, and output a continuously changing reference voltage V1.

[0040] As an oscillator, when the application takes effect, P2 charges Cosc, when the voltage of Cosc reaches V1, the output of Comp flips to high level, and N0 is turned on to discharge Cosc to 0. After that, the voltage of Cosc is lower than V1, the output of Comp is low level, N0 is turned off, and Cosc starts to charge again. The above process is repeated, and the oscillator signal CLK is output. It should be noted that as the voltage of V1 rises, the oscillator charging period becomes longer, and the frequency decreases; as the voltage of V1 decreases, the oscillator charging period becomes shorter, and the frequency increases.

[0041] The principle of generating V1 voltage is that the ratio of R1:R2:R3:R4:R5 is 16:8:4:2:1, and R0, R1, R2, R3, R4 and R5 are connected to R0 by N1, N2, N3, N4 and N5 to generate V1 voltage. For example, R5 is set to r, and the combination of R1-R5 can form 1r, 2r, 3r,..., 30r and 31r different schemes, which can generate 32 continuous resistance value gears in the range of 0-31, combined with R0 resistance, which can form the state that V1 voltage continuously rises on the basis of R0 voltage, continuously changes, and then controls the frequency of the oscillator to change continuously by 1 / 32 of the maximum change amount, forming the frequency spread effect. The oscillator frequency is realized based on V1, and the small range change of V1 voltage is realized, and then the small range fluctuation of the oscillator frequency around the center frequency is realized, and the maximum change amount of V1 is 31r / R0. In actual operation, the change amount can be 10%, for example, the minimum change of V1 voltage is 1V, and the maximum 1.1V after connecting R1-R5 to increase the resistance, and then the change amount of ±5% around 1.05V is realized, from 1 to 1.1, and then from 1.1 to 1V, and continuously changes around 1.05V. Corresponding to the oscillator frequency, for example, the frequency 1Mhz is increased to 1.001, 1.002, 1.003, and decreased to 0.999, 0.998, 0.997, etc. All changes from low to high are 32 gears, and then from high to low are 32 gears, and a cycle of 64 gears is changed.

[0042] The working principle of the logic control circuit in the circuit of the application is that DFF1-DFF8 are connected by D and-Q to form a frequency divider, i.e. the period is multiplied. Therefore, after the CLK signal is input into the logic control circuit, it is divided by DFF1-DFF8, and the period is increased to 2:4:8:16:32:64:128:256 respectively. Since DFF7 and DFF8 are combined, DFF7 starts to flip after the period ends, so the corresponding periods are E:D:C:B:A=8:16:32:64:128, for example, from E to A, the high level is continuously turned on. At the same time, after the 128th oscillator period, the state is flipped, for example, from A to E, the high point starts to flip to low level.

[0043] Comprehensive Figure 2 And Figure 5Together, the oscillator and logic control circuit of the present application are combined, and the oscillator CLK signal is used to control the logic control circuit to continuously flip. After the oscillator signal CLK is divided by DFF1-DFF8, the period is changed to 2:4:8:16:32:64:128:256, and the output signal E:D:C:B:A=8:16:32:64:128, for example, from E to A, the high level is continuously turned on, and R5, R4, R3, R2, R1 are continuously short-circuited through switches N5, N4, N3, N2, N1, and the V1 voltage is continuously and linearly reduced, resulting in a continuous and small increase in the oscillator frequency, as shown on the left side of Figure 6 At the same time, after 128 oscillator periods, the highest point is reached Figure 6 , the state flips, for example, from A to E, and the high level starts to flip to low level, and R5, R4, R3, R2, R1 are continuously connected to R0, and the V1 voltage is continuously and linearly increased, resulting in a continuous and small decrease in the oscillator frequency, as shown on the right side of Figure 6 . All adjustments are achieved within 256 oscillation periods, so the modulation frequency is 1 / 256 of the oscillator. At the same time, since the ratio of R1:R2:R3:R4:R5 is 16:8:4:2:1, the resistance change range is 0-31, and 32 voltage steps are achieved, and within 256 oscillator control periods, 64 steps are achieved, with 32 steps up and 32 steps down, so high-precision changes can be achieved within a wide range, and the interference energy is distributed in each frequency band, effectively reducing the peak spectrum of the frequency signal, which makes it easier to meet the EMI standard.

[0044] In summary, the present application uses 5 switch-controlled resistance steps combined with 8 D flip-flops to achieve a wide frequency change within 64 steps and 256 switch frequency ranges, and high-precision changes within a wide range, which distributes the interference energy in each frequency band and effectively reduces the peak spectrum of the frequency signal, making it easier to meet the EMI standard. The simple circuit realizes an oscillator with a frequency jitter function, which is easy to integrate into a single chip, and the chip area and cost can be significantly reduced.

Claims

1. A switching power supply oscillator with frequency dithering function, characterized in that: This includes a reference circuit, operational amplifier EA, bias current source, PMOS transistors P1-P3, oscillator capacitor Cosc, and frequency dithering control circuit. The frequency dithering control circuit includes a comparator Comp, a logic control circuit, NMOS transistors N1 to N5, and resistors R0 to R5, wherein the resistance values ​​of R1 to R5 are proportional. The reference circuit output is connected to the negative input of operational amplifier EA. The output of operational amplifier EA is connected to the gates of P1, P2, and P3. The positive input of operational amplifier EA and the drain of P1 are grounded through the bias resistor Rbias. The sources and bodies of P1, P2, and P3 are connected together and connected to the power supply VIN of the switching power supply. The drain of P2 is grounded through Cosc. The reference circuit, operational amplifier EA, bias resistor Rbias, and P1 provide bias current for P2 and P3. P2 charges Rbias. The drain of P2 is also connected to the drain of an NMOS transistor N0 and the positive input of comparator Comp. The source and body of N0 are grounded together. The drain of P3 outputs a frequency dithering control voltage V1 to the negative input of Comp and is grounded through the series resistors R0 to R5, forming a voltage divider across R0 to R5. The output of comparator Comp outputs the oscillator signal CLK to the gate of N0 and the input of the control logic circuit. The control logic circuit is a frequency divider, which divides CLK and outputs control signals A, B, C, D, and E. The level is continuously flipped periodically. The control signals control the gates of N1, N2, N3, N4, and N5 respectively. From E to A, the gates are continuously turned on with a high level. Through N1, N2, N3, N4, and N5, R5, R4, R3, R2, and R1 are continuously shorted. The voltage of V1 decreases continuously and linearly, causing the oscillator frequency to increase continuously. After the cycle, the gates are continuously flipped from high level to low level from A to E. R5, R4, R3, R2, and R1 are continuously connected to R0. The voltage of V1 increases continuously and linearly, causing the oscillator frequency to decrease continuously. This achieves periodic frequency modulation, which distributes interference energy across various frequency bands and reduces the peak spectrum of the frequency signal.

2. The switching power supply oscillator with frequency dithering function according to claim 1, characterized in that: In the frequency dithering control circuit, R0 is a fixed resistance resistor, and R1 to R5 are adjustment resistors. The ratio of R1:R2:R3:R4:R5 is 16:8:4:2:

1.

3. The switching power supply oscillator with frequency dithering function according to claim 1, characterized in that: The control logic circuit outputs signals A, B, C, D, and E to the gates of N1, N2, N3, N4, and N5. The drain of N1 is connected between R0 and R1, and the source and body of N1 and the drain of N2 are connected between R1 and R2. The source and body of N2 and the drain of N3 are connected between R2 and R3. The source and body of N3 and the drain of N4 are connected between R3 and R4. The source and body of N4 and the drain of N5 are connected between R4 and R5. The source and body of N5 are grounded.

4. A switching power supply oscillator with frequency dithering function according to claim 1, characterized in that: The operational amplifier EA includes four PMOS transistors PE1-PE4, three NMOS transistors NE1-NE3, a compensation resistor Rc1, and a compensation capacitor Cc1. The sources and bodies of PE1 and PE2 are connected to VIN. The drain of PE1 is connected to the sources and bodies of PE3 and PE4. The gates of PE1 and PE2 are connected to the bias current source control signal B+. The gate of PE3 is the negative input of the operational amplifier, and the gate of PE4 is the positive input. The drain of PE3 is connected to the drain and gate of NE1 and the gate of NE2. The sources and bodies of NE1, NE2, and NE3 are grounded together. The drain of PE4, the drain of NE2, and the gate of NE3 are grounded after passing through Rc1 and Cc1 in series. The drain of PE2 is connected to the drain of NE3, and the output signal OP_out is provided.

5. A switching power supply oscillator with frequency dithering function according to claim 1, characterized in that: The comparator Comp includes four PMOS transistors PC1 to PC4 and three NMOS transistors NC1 to NC3. The sources and bodies of PC1 and PC2 are connected to VIN. The drain of PC1 is connected to the sources and bodies of PC3 and PC4. The gates of PC1 and PC2 are connected to the bias current source control signal B+. The gate of PC3 is the negative terminal of the comparator. The gate of PC4 is the positive terminal of the comparator. The drain of PC3 is connected to the drain and gate of NC1 and the gate of NC2. The sources and bodies of NC1, NC2, and NC3 are grounded together. The drain of PC4 is connected to the drain of NC2 and the gate of NC3. The drain of PC2 is connected to the drain of NC3. The comparator outputs the output signal Comp_out.

6. A switching power supply oscillator with frequency dithering function according to claim 1, characterized in that: The logic control circuit includes eight D flip-flops DFF1 to DFF8, a set of inverters inv*, a set of NOR gates nor*, a set of NAND gates nand*, PMOS transistors P1L and P2L, and NMOS transistors N1L and N2L. * indicates the corresponding device number. The D and -Q terminals of DFF1-DFF8 are connected together. The CLK signal is input to the clock terminal clk of DFF1. Then, the output Q of the previous stage D flip-flop drives the clock clk of the next stage D flip-flop. The output Q terminal of the last stage DFF8 is connected to the input terminals of inverter inv5 and inv3, as well as the sources of P1L and N2L. The bodies of P1L and P2L are connected to VIN, and the bodies of N1L and N2L are grounded to GND. The output terminal of inv5 is connected to the source of N1L and P2L. The Q terminal of DFF7 is connected to the input terminal of inv4, the gates of N2L and P2L, and the output terminal of inv4 is connected to the gates of P1L and N1L. The output terminal of inv1 is connected to the input terminal of inv2, input terminal 1 of nor1A, input terminal 1 of nor1B, and nor1C. The input terminals of DFF1, DFF2, and DFF3 are connected to the input terminals of DFF4, DFF5, DFF6, DFF6, DFF4, and DFF3. The output terminals of DFF3, DFF4, DFF5, DFF6, DFF3, and DFF3 are connected to the input terminals of DFF3 and DFF2. The output terminals of DFF3A, DFF3B, DFF3C, and DFF3 are connected to the input terminals of DFF3 and DFF2. The output terminals of DFF3A, DFF3B, DFF3C, and DFF3 are connected to the input terminals of DFF1 and DFF2. The output control signal A is generated by inv3; the outputs of nor1A and nor2A are inverted by inv1A and invA2 respectively and then input into nand1A, outputting control signal B; the outputs of nor1B and nor2B are inverted by inv1B and inv2B respectively and then input into nand1B, outputting control signal C; the outputs of nor1C and nor2C are inverted by inv1C and inv2C respectively and then input into nand1C, outputting control signal D; the outputs of nor1D and nor2D are inverted by inv1D and inv2D respectively and then input into nand1D, outputting control signal E.

7. A switching power supply oscillator with frequency dithering function according to claim 1, characterized in that: After the oscillator signal CLK is divided by the control logic circuit, the period becomes 2:4:8:16:32:64:128:256 respectively. This controls R1-R5 to generate 32 continuous resistance value changes within the range of 0-31. Combined with the resistor R0, the voltage V1 changes continuously based on the voltage division of R0. The oscillator frequency based on the voltage V1 changes continuously around the center frequency by a increment of 1 / 32, forming a spread spectrum effect.

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