Message processing method and device, computer equipment and storage medium
By using a hash-linked list segmented lookup method for IPv6 address lookup, the problem of low efficiency in IPv6 address lookup is solved, and a more efficient rule matching process is achieved.
Patent Information
- Application Number
- CN202511296550.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-10
- Publication Date
- 2026-01-06
AI Technical Summary
Existing technologies, especially the longest prefix matching method, suffer from low lookup efficiency in IPv6 address lookup, particularly when the IPv6 prefix length is long, requiring traversal of hash tables of all lengths, leading to performance degradation.
Multiple hash lists are used, each corresponding to a predecessor length. The list is divided according to the prefix range of IPv6. First, the longest prefix length is determined for hash matching. If no match is found, the prefix length is decreased and the search continues until the target predecessor node is found, and then packet rule lookup is performed.
By using segmented lookup, the number of hash calculations and lookups is reduced, improving the efficiency of IPv6 address lookup and enhancing the performance of rule matching.
Smart Images
Figure CN121283945A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a message processing method, apparatus, computer equipment, and storage medium. Background Technology
[0002] With the rapid development of network technology, network devices need to efficiently identify and filter data packets. To improve matching flexibility, matching can be based on the longest prefix matching rule, similar to a routing lookup process, prioritizing the matching of IP network segments with the longest mask length. For example, a hash table algorithm can be used for the lookup. This algorithm requires maintaining 32 hash tables of different lengths, calculating hash values sequentially in descending order of mask length (e.g., from 32 bits to 1 bit) until a match is found.
[0003] However, the lookup performance of this method is greatly affected by the number of routing table entries and the distribution of mask length. In the worst case, it is necessary to traverse hash tables of all lengths. Especially for IPv6, the prefix length is relatively long (96 bits), which makes the lookup process more cumbersome and results in low lookup efficiency. Summary of the Invention
[0004] In view of this, this application provides a message processing method, apparatus, computer equipment, and storage medium that can reduce the number of rule lookups and improve the efficiency of rule matching.
[0005] According to a first aspect of this application, a message processing method is provided, the method comprising:
[0006] The message is acquired and parsed to extract the destination Internet Protocol (IP) address; the message is an Internet Protocol version 6 (IPv6) message.
[0007] For the prefix of the destination IP address, the target predecessor length and the hash value corresponding to the destination IP address are determined according to the longest prefix length. Then, the predecessor node is matched in the hash table according to the target predecessor length and the hash value. The hash table consists of multiple hash chains, each hash chain corresponding to a predecessor length. Each predecessor length is obtained by dividing according to the prefix range of IPv6. Each hash chain includes multiple predecessor nodes. Predecessor nodes with different hash values correspond to different hash chains, and predecessor nodes with the same hash value correspond to the same hash chain.
[0008] If no predecessor node is matched, a new prefix length is determined by decreasing the preset length, and the new prefix length is used as the longest prefix length. The process then returns to the step of determining the target predecessor length corresponding to the destination IP and the hash value corresponding to the destination IP address based on the longest prefix length, until the prefix length is the shortest.
[0009] If a predecessor node is matched, a message rule query and matching is performed, and if a corresponding message processing rule is found, the message is processed according to the message processing rule.
[0010] In some possible embodiments, each predecessor node also corresponds to multiple cascaded successor nodes; if a predecessor node is matched, then a message rule query matching is performed, including:
[0011] If a predecessor node is matched, determine whether the target predecessor node has a corresponding first-level successor node.
[0012] If the target predecessor node does not have a corresponding first-level successor node, then a message rule query matching is performed on the target predecessor node.
[0013] In some possible embodiments, each successor node includes multiple entries, and the address of each entry is determined based on the base address of the preceding node and the data corresponding to the entry; the method further includes:
[0014] If the target predecessor node has a corresponding first-level successor node, a preset number of bits are taken from the high-order bits of the target successor length of the target IP address; the target successor length of the target IP address is the network segment length that is the difference between the current longest prefix length and the predecessor length corresponding to the target predecessor node.
[0015] Based on the preset number of bits and the base address of the target predecessor node, the target entry address is determined, and message rule query matching is performed based on the target entry address.
[0016] In some possible embodiments, the message rule query matching based on the target entry address includes:
[0017] Determine whether a subsequent generation node exists within the target entry indicated by the target entry address;
[0018] If the target entry does not contain the next-level successor node, then a message rule query and matching is performed on the target entry.
[0019] In some possible embodiments, the method further includes:
[0020] If the target entry contains the subsequent successor node, the data range is shifted to the lower end by the preset number of bits, and the process returns to the step of determining the target entry address based on the preset number of bits of data and the base address of the target predecessor node.
[0021] In some possible embodiments, the method further includes:
[0022] If the target predecessor node has a corresponding successor node, determine whether there is a corresponding message processing rule within the target predecessor node; if so, record the message processing rule within the target predecessor node; and / or,
[0023] If the target entry contains the next-level successor node, determine whether there is a corresponding entry message processing rule in the target entry; if so, record the message processing rule in the entry.
[0024] In some possible embodiments, the method further includes:
[0025] If no message processing rule is found in the target table entry, the message processing rule with the longest prefix length among the recorded message processing rules will be identified as the found message processing rule.
[0026] According to a second aspect of this application, a message processing apparatus is provided, the apparatus comprising:
[0027] The message acquisition module is used to acquire and parse the message, and extract the destination Internet Protocol (IP) address from the message; the message is an Internet Protocol version 6 (IPv6) message;
[0028] The hash calculation module is used to determine the target predecessor length and the hash value corresponding to the destination IP address based on the longest prefix length of the destination IP address, and to perform predecessor node matching in the hash table according to the target predecessor length and the hash value. The hash table consists of multiple hash chains, each hash chain corresponding to a predecessor length. Each predecessor length is obtained by dividing according to the prefix range of IPv6. Each hash chain includes multiple predecessor nodes. Predecessor nodes with different hash values correspond to different hash chains, and predecessor nodes with the same hash value correspond to the same hash chain.
[0029] The length adjustment module is used to determine a new prefix length by decreasing the preset length if no predecessor node is matched, and to use the new prefix length as the longest prefix length. Then, it returns to the step of determining the target predecessor length corresponding to the destination IP and the hash value corresponding to the destination IP address according to the longest prefix length, until the prefix length is the shortest.
[0030] The message query module is used to perform message rule query matching if a predecessor node is matched, and to perform corresponding actions on the message based on the message processing rules if the corresponding message processing rules are found.
[0031] In some possible embodiments, each predecessor node also corresponds to multiple cascaded successor nodes; the message query module is specifically used for:
[0032] If a predecessor node is matched, determine whether the target predecessor node has a corresponding first-level successor node.
[0033] If the target predecessor node does not have a corresponding first-level successor node, then a message rule query matching is performed on the target predecessor node.
[0034] In some possible embodiments, each successor node includes multiple entries, and the address of each entry is determined based on the base address of the preceding node and the data corresponding to the entry; the message query module is specifically used for:
[0035] If the target predecessor node has a corresponding first-level successor node, a preset number of bits are taken from the high-order bits of the target successor length of the target IP address; the target successor length is the network segment length that is the difference between the current longest prefix length and the predecessor length corresponding to the target predecessor node.
[0036] Based on the preset number of bits and the base address of the target predecessor node, the target entry address is determined, and message rule query matching is performed based on the target entry address.
[0037] In some possible embodiments, the message query module is specifically used for:
[0038] Determine whether a subsequent generation node exists within the target entry indicated by the target entry address;
[0039] If the target entry does not contain the next-level successor node, then a message rule query and matching is performed on the target entry.
[0040] In some possible embodiments, the message query module is further configured to:
[0041] If the target entry contains the subsequent successor node, the data range is shifted to the lower level by a preset number of bits, and the process returns to the step of determining the target entry address based on the preset number of bits and the base address of the target predecessor node.
[0042] In some possible embodiments, the message query module is further configured to:
[0043] If the target predecessor node has a corresponding successor node, determine whether there is a corresponding message processing rule within the target predecessor node; if so, record the message processing rule within the target predecessor node; and / or,
[0044] If the target entry contains the next-level successor node, determine whether there is a corresponding entry message processing rule in the target entry; if so, record the message processing rule in the entry.
[0045] In some possible embodiments, the message query module is further configured to:
[0046] If no message processing rule is found in the target table entry, the message processing rule with the longest prefix length among the recorded message processing rules will be identified as the found message processing rule.
[0047] According to a third aspect of this application, a computer device is provided, comprising: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor communicates with the memory via the bus, and when the machine-readable instructions are executed by the processor, the message processing method described in the first aspect is performed.
[0048] According to a fourth aspect of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, performs the message processing method described in the first aspect above.
[0049] The message processing method, apparatus, computer equipment, and storage medium provided in this application utilize a hash table with multiple hash linked lists, each hash linked list corresponding to a predecessor length, and each predecessor length being determined based on the prefix range of IPv6. Thus, when performing rule matching on received messages, the target predecessor length can be determined first from the longest prefix, and then rule matching can be performed in the hash linked list corresponding to that target predecessor length. If no matching rule is found, the longest prefix is reduced by a preset length, and hash calculation and table lookup are performed again, and so on. In other words, segmented searching is used instead of sequentially traversing the table, thereby reducing the number of hash calculations and searches and improving search efficiency.
[0050] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this application and, together with the specification, serve to explain the technical solutions of this application. It should be understood that the following drawings only show some embodiments of this application and should not be considered as limiting the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.
[0052] Figure 1 This is a schematic diagram of the structure of a network device shown in an exemplary embodiment of this application.
[0053] Figure 2 This is a flowchart illustrating a message processing method in an exemplary embodiment of this application.
[0054] Figure 3 This is a schematic diagram illustrating the configuration of a predecessor node according to an exemplary embodiment of this application.
[0055] Figure 4 This is a schematic diagram illustrating the configuration of a successor node according to an exemplary embodiment of this application.
[0056] Figure 5 This is a schematic diagram illustrating a message processing method according to an exemplary embodiment of this application.
[0057] Figure 6 This is a schematic diagram of the structure of a message processing apparatus shown in an exemplary embodiment of this application.
[0058] Figure 7 This is a schematic diagram of the structure of a computer device shown in an exemplary embodiment of this application. Detailed Implementation
[0059] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0060] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0061] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0062] Unless otherwise specified, all embodiments mentioned herein can be combined to form new technical solutions. Furthermore, unless otherwise specified, all technical features and preferred features mentioned herein can be combined to form new technical solutions.
[0063] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.
[0064] First, the terminology used in this application will be explained:
[0065] A network segment is a portion of a computer network that allows computers using the same physical layer devices (such as transmission media, repeaters, and hubs) to communicate directly. A network segment is a range of IP addresses that share the same network identifier, enabling computers within the same segment to communicate directly without needing to go through a router.
[0066] Hash: Hash, generally translated as hashing, is a function that transforms an input of arbitrary length (also called a pre-image) into a fixed-length output using a hash algorithm. This output is the hash value. This transformation is a compression mapping, meaning that the space of hash values is usually much smaller than the space of inputs. Different inputs may hash to the same output, so it is impossible to determine a unique input value from the hash value. Simply put, it is a function that compresses a message of arbitrary length into a message digest of a fixed length.
[0067] CRC (Cyclic Redundancy Check) is a fast algorithm that generates a short, fixed-length check code based on data such as network packets or computer files. It is primarily used to detect or verify errors that may occur during data transmission or storage. CRC utilizes the principles of division and remainders to achieve error detection, and has advantages such as clear principles and simple implementation.
[0068] An array is a collection of elements of the same data type stored in a contiguous space. If a collection of a finite number of variables of the same type is named, then this name is called the array name. The individual variables that make up an array are called array components, also known as array elements, and sometimes subscript variables. The numerical identifier used to distinguish each element of the array is called the subscript. In programming, an array is a way to organize several elements of the same type in an ordered manner for ease of processing. This ordered collection of similar data elements is called an array.
[0069] A linked list is a non-contiguous, non-sequential storage structure in physical memory. The logical order of data elements is achieved through the linking order of pointers within the linked list. A linked list consists of a series of nodes (each element in the linked list is called a node), which can be dynamically generated at runtime. Each node includes two parts: a data field that stores the data element and a pointer field that stores the address of the next node. Compared to the sequential structure of a linear list, linked lists are more complex to operate. Because they do not necessarily need to be stored sequentially, linked lists can achieve a time complexity of O(1) for insertion, which is much faster than sequential lists. However, searching for a node or accessing a node with a specific number requires O(n) time, while the time complexities of linear lists and sequential lists are O(logn) and O(1), respectively.
[0070] IP, short for Internet Protocol, is a network layer protocol in the TCP / IP architecture. The purpose of IP design is to improve network scalability: firstly, to solve the problems of the Internet, enabling large-scale, heterogeneous network interconnection; and secondly, to separate the coupling between top-level network applications and underlying network technologies, facilitating their independent development. Based on end-to-end design principles, IP provides hosts with only a connectionless, unreliable, best-effort packet transmission service.
[0071] IPv6, short for "Internet Protocol Version 6," is the next-generation IP protocol designed by the Internet Engineering Task Force (IETF) to replace IPv4. Its address space is said to be enough to assign an address to every grain of sand in the world. IPv6 addresses are 128 bits long, four times the length of IPv4 addresses. Therefore, the dotted decimal notation of IPv4 is no longer applicable, and hexadecimal representation is used instead.
[0072] A message is a data unit exchanged and transmitted in a network; that is, a block of data that a station sends at one time. A message contains complete data information to be sent, and its length varies greatly, being unlimited and variable.
[0073] With the rapid development of network technology, network devices need to efficiently identify and filter data packets. Taking aggregation and distribution devices as an example, these devices can issue rules for IPv6 network segments, specifying the types of packets to be processed. If the IP address of a packet is within the corresponding network segment, then that packet type matches the rule. Specifically, the aggregation and distribution device can match the traffic on the inbound interface with the rules. If a matching rule is found, the packet is processed accordingly, such as forwarding it through a specified port or dropping it.
[0074] Aggregation and distribution equipment refers to network devices that can filter, screen, encapsulate, and modify network traffic.
[0075] An IPv6 address is 128 bits long. The first N bits of an IPv6 address are called the prefix, and the address family that conforms to this prefix length and value is called a network segment. For example, assuming a specified prefix length of 64 bits and a prefix of 1111:2222:3333:4444::, then all packets with the first 64 bits of 1111:2222:3333:4444:: meet the requirement. Therefore, the IPv6 address 1111:2222:3333:4444:5555:6666:7777:8888 belongs to this network segment. The IPv6 address family that meets the requirement can be called the network segment with a prefix length of 64 bits and a prefix of 1111:2222:3333:4444::.
[0076] This application mainly relates to the storage of IPv6 network segment rules with prefix lengths between 32 bits and 96 bits on network devices (such as aggregation and distribution devices), and the packet matching process for IPv6 network segment rules. The network segment rules include prefixes, lengths, actions, etc., and the information contained in the rules needs to be stored on the device in a certain format.
[0077] See Figure 1 The diagram shown is a schematic representation of a network device provided in an embodiment of this application. The network device 100 includes a main control board 10 and service boards 20. The main control board 10 can manage each service board 20 through channels. Figure 1 As shown, the main control board 10 can realize data communication and control, system coordination and management, and signal processing and conversion. The service board 20 can implement different service functions depending on the target scenario.
[0078] For example, the main control board 10 may include a CPU (Central Processing Unit) board responsible for rule management. The service board 20 may include an FPGA (Field Programmable Gate Array) board responsible for rule matching.
[0079] In this embodiment, network device 100 is an aggregation and distribution device. In other embodiments, network device 100 may also include switches, routers, firewalls, bridges, hubs, gateways, VPN (Virtual Private Network) servers, network interface controllers (NICs), wireless access points (WAPs), modems, 5G base stations, optical transceivers, fiber optic transceivers, and other network devices. This application does not specifically limit the types of devices included.
[0080] In some embodiments, the main control board 10 and the service board 20 may include multiple ports. For example... Figure 1 As shown, port 0 and port 2 form a channel link 1, and port 1 and port 3 form a channel link 2. Understandably, the ports used for channel link communication are called channel ports. When there are problems with the channel ports, it will affect inter-board communication, resulting in problems such as configuration data loss and traffic interruption.
[0081] It should be noted that, Figure 1 The channel link configuration shown is merely illustrative. In other embodiments, the network device 100 may also include multiple main control boards 10 and multiple service boards 20, resulting in more link combinations.
[0082] In this embodiment, the main control board 10 can distribute the managed and optimized longest prefix rules to the storage space of the service board 20. The service board 20 generates a lookup index based on the destination IP address, retrieves the stored table entries, completes the rule lookup based on the longest prefix matching, and performs corresponding subsequent processing actions on the data packet according to the matched packet processing rules. Furthermore, any additions, deletions, or modifications to rules on the main control board 10 need to be mirrored and distributed to the service board 20.
[0083] The message processing method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0084] To facilitate understanding of this embodiment, the executing entity of the message processing method provided in this application embodiment will first be described in detail. The executing entity of the message processing method provided in this application embodiment is a computer device. This computer device can be the aforementioned network device 100. In some embodiments, the computer device can also be a terminal device or a server. The terminal device can be a mobile device, a user terminal, a handheld device, a computing device, or a wearable device, etc. The server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud storage, big data, and artificial intelligence platforms.
[0085] In other embodiments, the message processing method can also be implemented by the processor calling computer-readable instructions stored in memory.
[0086] See Figure 2 The diagram shown is a flowchart of a message processing method provided in an embodiment of this application. The method includes the following steps S101 to S104:
[0087] S101, Obtain the message and parse the message to extract the destination Internet Protocol (IP) address from the message; the message is an Internet Protocol version 6 (IPL) message.
[0088] For example, after receiving an IPv6 packet to be processed, the device can first parse the packet and extract the destination IP address field in the packet header.
[0089] S102, for the prefix of the destination IP address, determine the target predecessor length corresponding to the destination IP and the hash value corresponding to the destination IP address according to the longest prefix length, and perform predecessor node matching in the hash table according to the target predecessor length and the hash value; the hash table has multiple hash chains, each hash chain corresponds to a predecessor length, each predecessor length is obtained according to the prefix range of IPv6, each hash chain includes multiple predecessor nodes, predecessor nodes with different hash values correspond to different hash chains, and predecessor nodes with the same hash value correspond to the same hash chain.
[0090] The construction method of hash tables will be explained in detail later.
[0091] S103, if no predecessor node is matched, a new prefix length is determined by decreasing the preset length, and the new prefix length is used as the longest prefix length. Then, the process returns to the step of determining the target predecessor length corresponding to the destination IP and the hash value corresponding to the destination IP address according to the longest prefix length, until the prefix length is the shortest.
[0092] S104, if a predecessor node is matched, a message rule query and matching is performed, and if a corresponding message processing rule is found, the message is processed according to the message processing rule.
[0093] For example, if a corresponding message processing rule is found, the message can be processed accordingly. For instance, if the message processing rule is "forward to port 1", the message will be output to port 1; if the rule is "discard", the message will be discarded and not forwarded further. Other actions can also be performed, such as rate limiting or QoS tagging, depending on the specific requirements.
[0094] The packet processing method provided in this application uses a hash table with multiple hash chains, each hash chain corresponding to a predecessor length, and each predecessor length is divided according to the prefix range of IPv6. Thus, when performing rule matching on received packets, the target predecessor length can be determined first from the longest prefix, and then rule matching can be performed in the hash chain corresponding to that target predecessor length. If no matching rule is found, the longest prefix is reduced by a preset length, and hash calculation and table lookup are performed again, and so on. That is, segmented searching is used instead of sequentially traversing the table, thereby reducing the number of hash calculations and searches and improving search efficiency.
[0095] The following section provides a detailed explanation of how hash tables are constructed.
[0096] Specifically, the IPv6 prefix range can be divided into multiple intervals, each interval corresponding to a predecessor length, that is, each interval corresponds to a hash linked list. For example, the 32-bit to 96-bit range can be divided into four intervals: 32-48, 48-64, 64-80, and 80-96. The storage of network segment rules (i.e., packet processing rules) can be based on network segments with prefix lengths of 32, 48, 64, 80, and 96. In this embodiment, these five network segment lengths are the predecessor lengths, and the stored nodes are the predecessor nodes. The predecessor length for a network segment with a prefix length between 32 and 48 is 32, the predecessor length for a network segment with a prefix length between 48 and 64 is 48, and so on, with the predecessor length for a network segment with a prefix length between 80 and 96 being 80.
[0097] In this example, each interval includes 16 bits. It is understood that in other embodiments, each interval may also include more (e.g., 32 bits) or fewer (e.g., 8 bits) data bits. When the number of data bits in each interval is less, it can be divided into more intervals; when the number of data bits in each interval is more, it can be divided into fewer intervals, as long as the intervals are consecutive and the number of data bits in each interval is the same.
[0098] It should be noted that each interval includes the lower boundary but excludes the upper boundary. For example, for network segments with prefix lengths between 32 and 48, 32 is included, but 48 is excluded. That is, 48 is assigned to network segments with prefix lengths between 48 and 64. In addition, for the longest prefix length of 96, the corresponding predecessor length is 96. Regardless of how it is divided, the predecessor length corresponding to the longest prefix of 96 is fixed and is always 96.
[0099] Here, when issuing any rule for a network segment, the data of the predecessor length of that network segment needs to be extracted and stored in the predecessor node.
[0100] See Figure 3 As shown, Figure 3This is a schematic diagram of a hash linked list provided in an embodiment of this application. The hash linked list can correspond to a predecessor length as described above. The hash linked list can include a hash head and a hash tail. The hash head can be in array form, with indices representing calculated hash values. The hash tail can be attached to the hash chain as a linked list.
[0101] For example, if a rule for a network segment with a prefix length of 34 (predecessor length of 32) is issued, the first 32 bits need to be stored in the predecessor node. Then, the hash of the first 32 bits of the network segment is calculated, and the predecessor node is added to the hash chain. Similarly, to issue a rule for a network segment with a prefix length of 88 (predecessor length of 80), the first 80 bits need to be stored in the predecessor node. Then, the hash of the first 80 bits of the network segment is calculated, and the predecessor node is added to the hash chain. Here, the hash value is an index calculated from the original data; different nodes with the same hash value have different data stored in their memory.
[0102] It is understood that the above embodiments only discussed the predecessor length. In reality, in addition to the predecessor length, there may be extra data bits. For example, in the network segment rule with a prefix length of 34 bits mentioned above, after removing 32 bits, there are still 2 bits remaining. Therefore, each predecessor node can correspond to multiple cascaded successor nodes. Here, if the prefix length is exactly 32 bits, 48 bits, 64 bits, 80 bits, or 96 bits, then there is no corresponding successor node, only a predecessor node is needed.
[0103] The number of successor nodes can be determined based on the number of data bits in the interval and the division length. In this embodiment, the length remaining after subtracting the predecessor length from the prefix length of the network segment rule is the successor length. Combining the aforementioned interval division, each interval includes 16 data bits. Therefore, the range of the successor length (excluding the lower boundary) is [1, 15]. This is divided into three segments, each with a length of 5 bits.
[0104] It should be noted that when dividing the rear drive length, the specific number of segments and the number of data bits in each segment can be adjusted appropriately according to requirements, and this application does not impose specific limitations on this. For example, it can be divided into 5 segments, each segment being 3 bits long.
[0105] See Figure 4 As shown, if the prefix length of the issued network segment rule is not exactly equal to the predecessor length, a successor length will definitely be generated. If the successor length is between [1, 5], then only one successor node needs to be created, called the first successor node. Figure 4The first successor node (1) has its base address stored within the predecessor node. This node contains 32 entries, and the addresses of these 32 entries are calculated by adding the base address of the successor node to all the values 0b00000 to 0b11111 (sub-addresses: 0 to 31) after expanding the 5 bits. Traversing these 32 entries, if the sub-address prefix length matches the issued rule length (i.e., only the rule prefix length is considered), the sub-address represents a network segment equal to the rule's IP address, and there is no rule information with a longer prefix length in the entry, then the entry stores the rule information. The address of each entry is calculated as: successor node base address + 5 bits. If the successor length is between [5, 10], then two successor nodes need to be created. Figure 4 In the case of successor node 2), the base address of the second successor node is stored in an entry within the first successor node, and the calculation method for the rules of the second successor node is consistent with that of the first successor node. If the successor length is between [10, 15], then 3 successor nodes need to be allocated. Figure 4 In the middle successor node 3), the base address of the third successor node is stored in the table entry within the second successor node, and the calculation method for the distribution of rules for the third successor node is consistent with that of the first two successor nodes.
[0106] For example, if a network segment rule is issued with a prefix length of 34 bits, and the prefix is 1111:2222:c000::, then the 32 bits of data stored in the predecessor node will be 1111:2222::. Since the remaining two bits are between 1 and 5 bits in length, it is only necessary to find or request one successor node. By traversing the 32 entries in successor node 1, we can reach 8 entries with a sub-address range of 0b11000 to 0b11111. As long as there is no network segment rule with a longer prefix length in these 8 entries, the network segment rule can be issued to these 8 entries. In this way, the hash index construction and the storage of various rule information (message processing rules) are completed.
[0107] In this embodiment of the application, since the network segment rules are stored using a hash linked list plus data expansion storage method, the memory space occupied by the rules can be reduced and the resource utilization rate can be improved.
[0108] The following section provides a detailed explanation of how to perform message rule query and matching in step S104 when a predecessor node is matched.
[0109] In some embodiments, during the rule query process, if a predecessor node is matched, then a message rule query matching is performed, which may include:
[0110] If a predecessor node is matched, it is determined whether the target predecessor node has a corresponding first-level successor node; if the target predecessor node does not have a corresponding first-level successor node, a message rule query and matching is performed on the target predecessor node.
[0111] Here, for network segments with prefix lengths of exactly 32, 48, 64, 80, and 96 bits, since there are no corresponding successor nodes, the rule query only performs packet rule matching on the predecessor node, which can further improve the search efficiency.
[0112] In some embodiments, the method further includes:
[0113] If the target predecessor node has a corresponding first-level successor node, a preset number of bits are taken from the high-order bits of the target successor length of the target IP address; the target successor length of the target IP address is the network segment length that is the difference between the current longest prefix length and the predecessor length corresponding to the target predecessor node.
[0114] Based on the preset number of bits and the base address of the target predecessor node, the target entry address is determined, and message rule query matching is performed based on the target entry address.
[0115] Here, when a rule is issued, the successor length is between [1, 15]. When searching for a rule, the target successor length is 15. This preset number of bits can be 5 bits, consistent with the aforementioned construction. For example, when matching a rule, the target successor length is 15 bits, and the first 5 bits are calculated first, then the second 5 bits are calculated after finding the match, and so on. Furthermore, when a successor node exists, using hash lookup and direct lookup (address traversal lookup) not only improves the efficiency of the search but also its accuracy.
[0116] Specifically, when performing message rule query matching based on the target entry address, it may include:
[0117] Determine whether a subsequent generation node exists within the target entry indicated by the target entry address;
[0118] If the target entry does not contain the next-level successor node, then perform a message rule query and matching on the target entry.
[0119] If the target entry contains the next-level successor node, the data range is shifted to the lower end by the preset number of bits, and the process returns to the step of determining the target entry address based on the preset number of bits and the base address of the target predecessor node. This process continues until the last-level successor node is found.
[0120] It is understandable that during the query process, for the query step targeting the target predecessor node, if the target predecessor node has a corresponding successor node, it can be determined whether there is a corresponding message processing rule within the target predecessor node; if so, the message processing rule within the target predecessor node is recorded. For the query step targeting a table entry, if the target table entry contains the subsequent successor node, it can be determined whether there is a corresponding table entry message processing rule within the target table entry; if so, the message processing rule within the table entry is recorded. In this way, if a subsequent successor node is found but no message processing rule is found, the message processing rule corresponding to the longest prefix length among the previously recorded message processing rules can be used, thereby improving search performance. If no rule was previously recorded, the default rule is executed.
[0121] The search process for this application will be explained in detail below with specific examples.
[0122] See Figure 5 As shown, when external traffic enters the service board 20 of the aggregation and distribution device, the IP of the traffic can be resolved. Then, the IP is used as an IP with a prefix length of 96 to calculate the hash. If it cannot match the predecessor node (the target predecessor node in the aforementioned lookup process), the prefix length is reduced by 16, and the hash is calculated again as an IP with a prefix length of 80. This process continues until the hash is calculated as an IP with a prefix length of 32, and if it still cannot match the predecessor node, the default action is executed.
[0123] If a predecessor node is matched, check if the predecessor node has a successor node and if the successor node contains a matching rule. If there is no successor node, the rules within the predecessor node are matched. If there is a successor node, look up the rules in the successor node's table. Specifically, the first 5 bits of the target successor length (e.g., 15 bits) of the IP are extracted. Combined with the base address of the first successor node stored in the predecessor node, the corresponding entry address is calculated. The entry is then checked for rule information (packet processing rules). If a rule exists, its rule ID is recorded. Next, the entry is checked for the base address of the second successor node. If a second successor node exists, the entry address is calculated using the same method. The entry is then checked for rule information. If a rule exists, its rule ID is recorded. The entry is then checked for the base address of the third successor node. If a third successor node exists, the entry address is calculated using the same method. If a rule exists, the rule in that entry is matched. If no rule exists, the previously recorded rule information is checked, and the rule with the longest prefix length is matched. If no match is found, the default action is executed. The default action can be determined according to actual needs; for example, it could be a "discard" action.
[0124] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.
[0125] Based on the same technical concept, this application also provides a message processing device corresponding to the message processing method. Since the principle of the device in this application is similar to the message processing method described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.
[0126] Reference Figure 6 The diagram shown is a schematic representation of a message processing apparatus provided in an embodiment of this application. The message processing apparatus 600 includes:
[0127] The message acquisition module 601 is used to acquire a message and parse the message to extract the destination Internet Protocol (IP) address from the message; the message is an Internet Protocol version 6 (IPv6) message.
[0128] The hash calculation module 601 is used to determine the target predecessor length and the hash value corresponding to the target IP address based on the longest prefix length of the prefix of the target IP address, and to perform predecessor node matching in the hash table according to the target predecessor length and the hash value; the hash table consists of multiple hash chains, each hash chain corresponds to a predecessor length, and each predecessor length is obtained by dividing according to the prefix range of IPv6. Each hash chain includes multiple predecessor nodes, and predecessor nodes with different hash values correspond to different hash chains, while predecessor nodes with the same hash value correspond to the same hash chain.
[0129] The length adjustment module 603 is used to determine a new prefix length by decreasing the preset length if no predecessor node is matched, and to use the new prefix length as the longest prefix length, and return to the step of determining the target predecessor length corresponding to the destination IP and the hash value corresponding to the destination IP address according to the longest prefix length, until the prefix length is the shortest.
[0130] The message query module 604 is used to perform message rule query matching if a predecessor node is matched, and to perform corresponding actions on the message based on the message processing rules if a corresponding message processing rule is found.
[0131] In some possible embodiments, each predecessor node also corresponds to multiple cascaded successor nodes; the message query module 604 is specifically used for:
[0132] If a predecessor node is matched, determine whether the target predecessor node has a corresponding first-level successor node.
[0133] If the target predecessor node does not have a corresponding first-level successor node, then a message rule query matching is performed on the target predecessor node.
[0134] In some possible embodiments, each successor node includes multiple entries, and the address of each entry is determined based on the base address of the preceding node and the data corresponding to the entry; the message query module 604 is specifically used for:
[0135] If the target predecessor node has a corresponding first-level successor node, a preset number of bits are taken from the high-order bits of the target successor length of the target IP address; the target successor length is the network segment length that is the difference between the current longest prefix length and the predecessor length corresponding to the target predecessor node.
[0136] Based on the preset number of bits and the base address of the target predecessor node, the target entry address is determined, and message rule query matching is performed based on the target entry address.
[0137] In some possible embodiments, the message query module 604 is specifically used for:
[0138] Determine whether a subsequent generation node exists within the target entry indicated by the target entry address;
[0139] If the target entry does not contain the next-level successor node, then a message rule query and matching is performed on the target entry.
[0140] In some possible embodiments, the message query module 604 is further configured to:
[0141] If the target entry contains the subsequent successor node, the data range is shifted to the lower end by the preset number of bits, and the process returns to the step of determining the target entry address based on the preset number of bits of data and the base address of the target predecessor node.
[0142] In some possible embodiments, the message query module 604 is further configured to:
[0143] If the target predecessor node has a corresponding successor node, determine whether there is a corresponding message processing rule within the target predecessor node; if so, record the message processing rule within the target predecessor node; and / or,
[0144] If the target entry contains the next-level successor node, determine whether there is a corresponding entry message processing rule in the target entry; if so, record the message processing rule in the entry.
[0145] In some possible embodiments, the message query module 604 is further configured to:
[0146] If no message processing rule is found in the target table entry, the message processing rule with the longest prefix length among the recorded message processing rules will be identified as the found message processing rule.
[0147] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.
[0148] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0149] Corresponding to the above-described message processing method, this disclosure also provides a computer device, such as... Figure 7 The diagram shown is a structural schematic of a computer device provided in an embodiment of this disclosure, including:
[0150] Computer device 700 includes a processor 710, an internal bus 720, memory 730, a network interface 740, and non-volatile memory 750, and may also include other hardware required for its functions. One or more embodiments of this specification can be implemented in software, for example, the processor 710 reads the corresponding computer program from the non-volatile memory 750 into the memory 730 and then runs it. Of course, besides software implementation, one or more embodiments of this specification do not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. That is to say, the execution entity of the following processing flow is not limited to individual logic units, but can also be hardware or logic devices.
[0151] The memory 730, also known as internal memory, is used to temporarily store the computational data in the processor 710, as well as the data exchanged with non-volatile memory 750 such as hard disk. The processor 710 exchanges data with the non-volatile memory 750 through the memory 730.
[0152] In this embodiment, memory 730 is specifically used to store application code that executes the solution of this application, and its execution is controlled by processor 710. That is, when the computer device is running, processor 710 communicates with network interface 740, memory 730 and non-volatile memory 750 through internal bus 720, so that processor 710 executes the application code stored in memory 730 and non-volatile memory 750, thereby executing the message processing method described in the above method embodiment.
[0153] Processor 710 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor.
[0154] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the computer device 700. In other embodiments of this application, the computer device 700 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
[0155] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the message processing method described in the above method embodiments. The storage medium can be either volatile or non-volatile computer-readable storage.
[0156] This application also provides a computer program product carrying program code. The program code includes instructions that can be used to execute the steps of the message processing method in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.
[0157] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.
[0158] Furthermore, embodiments of the subject matter and functional operation described in this specification can be implemented in the following ways: digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. Alternatively or additionally, program instructions may be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiving device for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or combinations thereof.
[0159] The processing and logic flow described in this specification can be executed by one or more programmable computers that execute one or more computer programs to perform corresponding functions by operating on input data and generating output. The processing and logic flow can also be executed by dedicated logic circuitry—such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and the device can also be implemented as dedicated logic circuitry.
[0160] Suitable computers for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as disks, magneto-optical disks, or optical disks, or the computer will be operatively coupled to such mass storage devices to receive data from or transfer data to them, or both. However, a computer is not required to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.
[0161] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. Processors and memory may be supplemented by or incorporated into dedicated logic circuitry.
[0162] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather are primarily intended to describe features of specific embodiments of a particular invention. Certain features described in the various embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in various embodiments or in any suitable sub-combination. Furthermore, while features may function in certain combinations as described above and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and a claimed combination may refer to a sub-combination or a variation thereof.
[0163] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
[0164] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings are not necessarily shown in a specific order or sequence to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.
[0165] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A message processing method, characterized in that, include: Acquire the message and parse the message to extract the destination Internet Protocol (IP) address from the message; The message is an Internet Protocol version 6 (IPv6) message; For the prefix of the destination IP address, the target predecessor length and the hash value corresponding to the destination IP address are determined according to the longest prefix length. Then, the predecessor node is matched in the hash table according to the target predecessor length and the hash value. The hash table includes multiple hash chains, each hash chain corresponds to a predecessor length, and each predecessor length is obtained according to the prefix range of IPv6. Each hash chain includes multiple predecessor nodes. Predecessor nodes with different hash values correspond to different hash chains, and predecessor nodes with the same hash value correspond to the same hash chain. If no predecessor node is matched, a new prefix length is determined by decreasing the preset length, and the new prefix length is used as the longest prefix length. The process then returns to the step of determining the target predecessor length corresponding to the destination IP and the hash value corresponding to the destination IP address based on the longest prefix length, until the prefix length is the shortest. If a predecessor node is matched, a message rule query and matching is performed, and if a corresponding message processing rule is found, the message is processed according to the message processing rule.
2. The method according to claim 1, characterized in that, Each predecessor node also corresponds to multiple cascaded successor nodes; if a predecessor node is matched, a message rule query and matching is performed, including: If a predecessor node is matched, determine whether the target predecessor node has a corresponding first-level successor node. If the target predecessor node does not have a corresponding first-level successor node, then a message rule query matching is performed on the target predecessor node.
3. The method according to claim 2, characterized in that, Each successor node includes multiple entries, and the address of each entry is determined based on the base address of the preceding node and the data corresponding to the entry; the method further includes: If the target predecessor node has a corresponding first-level successor node, a preset number of bits are taken from the high-order bits of the target successor length of the target IP address; the target successor length of the target IP address is the network segment length that is the difference between the current longest prefix length and the predecessor length corresponding to the target predecessor node. Based on the preset number of bits and the base address of the target predecessor node, the target entry address is determined, and message rule query matching is performed based on the target entry address.
4. The method according to claim 3, characterized in that, The message rule query and matching based on the target entry address includes: Determine whether a subsequent generation node exists within the target entry indicated by the target entry address; If the target entry does not contain the next-level successor node, then a message rule query and matching is performed on the target entry.
5. The method according to claim 4, characterized in that, The method further includes: If the target entry contains the subsequent successor node, the data range is shifted to the lower end by the preset number of bits, and the process returns to the step of determining the target entry address based on the preset number of bits of data and the base address of the target predecessor node.
6. The method according to claim 4, characterized in that, The method further includes: If the target predecessor node has a corresponding successor node, determine whether there is a corresponding message processing rule within the target predecessor node; if so, record the message processing rule within the target predecessor node; and / or, If the target entry contains the next-level successor node, determine whether there is a corresponding entry message processing rule in the target entry; if so, record the message processing rule in the entry.
7. The method according to claim 6, characterized in that, The method further includes: If no message processing rule is found in the target table entry, the message processing rule with the longest prefix length among the recorded message processing rules will be identified as the found message processing rule.
8. A message processing apparatus, characterized in that, The device includes: The message acquisition module is used to acquire and parse the message, and extract the destination Internet Protocol (IP) address from the message; the message is an Internet Protocol version 6 (IPv6) message; The hash calculation module is used to determine the target predecessor length and the hash value corresponding to the destination IP address based on the longest prefix length of the destination IP address, and to perform predecessor node matching in the hash table according to the target predecessor length and the hash value. The hash table consists of multiple hash chains, each hash chain corresponding to a predecessor length. Each predecessor length is obtained by dividing according to the prefix range of IPv6. Each hash chain includes multiple predecessor nodes. Predecessor nodes with different hash values correspond to different hash chains, and predecessor nodes with the same hash value correspond to the same hash chain. The length adjustment module is used to determine a new prefix length by decreasing the preset length if no predecessor node is matched, and to use the new prefix length as the longest prefix length. Then, it returns to the step of determining the target predecessor length corresponding to the destination IP and the hash value corresponding to the destination IP address according to the longest prefix length, until the prefix length is the shortest. The message query module is used to perform message rule query matching if a predecessor node is matched, and to perform corresponding actions on the message based on the message processing rules if the corresponding message processing rules are found.
9. A computer device, characterized in that, include: The computer device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the message processing method as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the message processing method as described in any one of claims 1-7.