Highly reliable split-plane silicon carbide VDMOS and method of making same

Abstract

The application provides a high-reliability separation plane gate silicon carbide VDMOS and a preparation method thereof. The method comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, etching, ion implanting to form a first P-type well region, a P+ well region, an N-type source region, a low-resistance region, a second P-type well region and a Schottky region; depositing to form a gate dielectric layer; depositing metal to form a gate metal layer; depositing metal to form a first source metal layer and a second source metal layer; removing the barrier layer; and completing the preparation. The device switching speed can be effectively improved, the on-resistance during short circuit can be increased, the short circuit current density can be effectively reduced, the short circuit resistance of the device can be improved, and the reliability of the device can be improved.

Description

Technical Field

[0001] This invention relates to a highly reliable discrete planar gate silicon carbide VDMOS and its fabrication method. Background Technology

[0002] Silicon carbide MOSFETs are a typical example of silicon carbide power devices, widely used in electric vehicles, aerospace, power conversion, and other fields. While the performance requirements for silicon carbide power MOSFETs vary across different applications, the overall requirements generally include higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage surge reliability, and short-circuit reliability), and lower body diode conduction loss.

[0003] In high-reliability applications such as aerospace and electric vehicles, external environmental disturbances can cause short circuits in devices. These short circuits can lead to overheating of the devices, which can result in device burnout or even fires in peripheral circuits. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-reliability discrete planar gate silicon carbide VDMOS and its fabrication method, which can effectively improve the switching speed of the device, increase the on-resistance during short circuit, effectively reduce the short-circuit current density, improve the short-circuit withstand capability of the device, and improve the reliability of the device.

[0005] In a first aspect, the present invention provides a method for fabricating a highly reliable discrete planar gate silicon carbide VDMOS, comprising the following steps:

[0006] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; grow an epitaxial layer on the upper side of the silicon carbide substrate to form a drift layer;

[0007] Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form a via, and implant ions to form the first P-type well region;

[0008] Step 3: Ion implantation to form a P+ trap region;

[0009] Step 4: Ion implantation to form an N-type source region;

[0010] Step 5: Ion implantation to form a low-resistivity region;

[0011] Step 6: Ion implantation to form a second P-type well region;

[0012] Step 7: Ion implantation to form Schottky regions;

[0013] Step 8: Deposition to form the gate dielectric layer;

[0014] Step 9: Deposit metal to form a gate metal layer;

[0015] Step 10: Deposit metal to form the first source metal layer and the second source metal layer, remove the barrier layer, and complete the fabrication;

[0016] Before steps 3 to 10, the barrier layer from the previous step needs to be removed, a new barrier layer needs to be formed, and the barrier layer needs to be etched to form a via.

[0017] Secondly, the present invention provides a high-reliability discrete planar gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the preparation method of the high-reliability discrete planar gate silicon carbide VDMOS described in the first aspect.

[0018] The advantages of this invention are:

[0019] I. This invention reduces the area directly overlapping the drain and gate below the gate by constructing a gate metal layer in the device, thereby reducing the gate-drain capacitance (i.e., Miller capacitance) of the device and effectively improving the switching speed of the device.

[0020] 2. The present invention constructs a lateral distribution region of low resistance region - second P-type well region - Schottky region in the middle region of the gate metal layer. The Schottky region can construct the parasitic Schottky diode of the device, thereby reducing the body diode freewheeling loss of the device. The second P-type well region, the low resistance region and the Schottky region respectively form a pn junction to form a depletion layer. The depletion layer extends into the JFET region. When the short-circuit current is close to the JFET region, the on-resistance during short circuit increases, effectively reducing the short-circuit current density, improving the short-circuit withstand capability of the device and improving the reliability of the device.

[0021] 3. The Schottky region and the second source metal layer of this invention have equal widths and are in direct contact. However, due to process errors, the intermediate source metal may come into contact with the second P-type well region. In reverse voltage withstand (when reverse voltage withstand occurs, the second P-type well region has a voltage withstand capability comparable to the first P-type well region, and the Schottky junction also has a voltage withstand capability, so it does not affect the voltage withstand capability), forward conduction (when forward conduction occurs, the current flows through the N-type source region to the low-resistance region and then to the device drain, and the second P-type well region and the N-type Schottky region have no effect on it), or body diode freewheeling (the voltage drop of the Schottky region < the voltage drop of the P+ well region < the voltage drop of the second P-type well region, and the current finally flows through the second P-type well region. When the P+ well region of the device cannot meet the body diode freewheeling requirements, the device is easily burned out), the current capability and reliability of the device are not affected.

[0022] Fourth, the low-resistance region of this invention completely encapsulates the Schottky region and the second P-type well region. This is to avoid the influence of the second P-type well region on the conduction characteristics of the device. At the same time, when the device is turned on, when the current flows laterally from the N-type source region downwards, the current distribution can be redistributed to the middle region, thereby reducing the on-resistance of the device. Attached Figure Description

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This is a schematic diagram of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention.

[0025] Figure 2 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0026] Figure 3 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0027] Figure 4 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0028] Figure 5 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0029] Figure 6 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0030] Figure 7 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0031] Figure 8 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0032] Figure 9 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0033] Figure 10 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0034] Figure 11 This is a cross-sectional view of the process of a high-reliability discrete planar gate silicon carbide VDMOS according to the present invention. Figure 10 . Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0039] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0040] like Figures 1 to 11 As shown in the embodiments of this application, a method for fabricating a highly reliable discrete planar gate silicon carbide VDMOS is provided, comprising the following steps:

[0041] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 112; epitaxially grow on the upper side of silicon carbide substrate 101 to form drift layer 102;

[0042] Step 2: Form a barrier layer 113 above the drift layer 102, etch the barrier layer 113 to form a via, and implant ions to form the first P-type well region 103;

[0043] Step 3: Ion implantation to form P+ well region 104;

[0044] Step 4: Ion implantation to form the N-type source region 1041;

[0045] Step 5: Ion implantation to form a low-resistivity region 105;

[0046] Step 6: Ion implantation to form the second P-type well region 106;

[0047] Step 7: Ion implantation to form the Schottky region 107;

[0048] Step 8: Deposition to form the gate dielectric layer 108;

[0049] Step 9: Deposit metal to form gate metal layer 109;

[0050] Step 10: Deposit metal to form a first source metal layer 110 and a second source metal layer 111, remove the barrier layer 113, and complete the preparation.

[0051] Before steps 3 to 10, the barrier layer 113 from the previous step needs to be removed, the barrier layer 113 needs to be reformed, and the barrier layer 113 needs to be etched to form a through hole.

[0052] In this embodiment, preferably, the silicon carbide substrate 101, drift layer 102, low-resistivity region 105, and Schottky region 107 are all N-type.

[0053] In this embodiment, preferably, the doping concentration of the low-resistivity region 105 is greater than the doping concentration of the drift layer 102.

[0054] In this embodiment, preferably, the doping concentration of the Schottky region 107 is equal to the doping concentration of the second P-type well region 106.

[0055] In this embodiment, preferably, the lower side of the low-resistivity region 105 and the lower side of the first P-type well region 103 are located on the same plane.

[0056] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0057] Silicon carbide substrate 101,

[0058] A drift layer 102 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 101. A protrusion 1021 is provided on the drift layer 102, and a first groove (not shown in the figure) is provided in the protrusion 1021.

[0059] The first P-type well region 103 has its inner side connected to the outer side of the protrusion 1021 and its lower side connected to the drift layer 102.

[0060] P+ well region 104, the lower side of P+ well region 104 is connected to the first P-type well region 103, and an N-type source region 1041 is provided in P+ well region 104. One side of the N-type source region 1041 and one side of P+ well region 104 are both connected to the first P-type well region 103.

[0061] Low resistance region 105, the low resistance region 105 is disposed in the first groove, and a second groove (not shown in the figure) is provided in the low resistance region 105.

[0062] The second P-type well region 106 is disposed in the second groove, and the second P-type well region 106 is provided with a perforation (not shown in the figure).

[0063] Schottky region 107 is disposed within the perforation, and the lower side of Schottky region 107 is connected to the low-resistivity region 105;

[0064] Gate dielectric layer 108, the lower side of which is connected to N-type source region 1041, first P-type well region 103, protrusion 1021, low-resistivity region 105 and second P-type well region 106 respectively.

[0065] A gate metal layer 109 is connected to the gate dielectric layer 108;

[0066] The first source metal layer 110 is connected to the P+ well region 104 and the N-type source region 1041 respectively;

[0067] The second source metal layer 111 is connected to the Schottky region 107;

[0068] And a drain metal layer 112, which is connected to the lower side of the silicon carbide substrate 101.

[0069] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 102 is 5-9e16cm. -3 The doping concentration of the N-type low-resistivity region 105 is 5-9e17cm. -3 The doping concentration of both the first P-type well region 103 and the second P-type well region 106 is 1-6e17cm. -3 The doping concentration of the P+ well region 104 is 1-5e18cm. -3 The doping concentration of the N-type Schottky region 107 is 1-6e17cm. -3 The gate dielectric layer 108 can be made of silicon dioxide, and the doping concentration of the N-type source region 1041 is 2-8e18cm. -3 ;

[0070] The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 112; the doping concentration of the first P-type well region 103 is to form a gradually changing junction at the reverse breakdown voltage of the N-type drift layer 102 and the first P-type well region 103, avoiding device reliability issues caused by sudden changes in electric field strength; the doping concentration of the second P-type well region 106 is to improve the device's short-circuit current withstand capability in the structure directly below the second source metal layer 111 while avoiding affecting the device's parasitic Schottky diode and conduction characteristics. The P+ well region 104 is designed to protect the device from drain-source breakdown during reverse breakdown while simultaneously forming an ohmic contact with the source metal, reducing the conduction loss of the parasitic pn junction body diode. The doping concentration of the N-type Schottky region 107 is to form the parasitic Schottky body diode, reducing the conduction loss of the body diode. The doping concentration of the N-type drift layer 102 represents a trade-off between the reverse breakdown voltage and on-resistance. The doping concentration of the N-type source region 1041 is to reduce the source contact resistance and thus the on-resistance of the device.

[0071] The thickness of the N-type silicon carbide substrate 101 is 2 μm to provide support during fabrication. The thickness of the N-type drift layer 102 is 50-100 μm, adjusted within this range according to different requirements for the device's breakdown voltage characteristics. The width of the N-type source region 1041 is 1 μm-4 μm, and the width of the P+ well region 104 is twice that of the N-type source region 1041. This is to ensure that the device's reverse breakdown voltage capability and forward conduction resistance meet design requirements. The width of the first P-type well region 103 is 300 nm wider than that of the P+ well region 104 to form the device's gate control structure. The thickness of the N-type source region 1041 is 200 nm, the thickness of the P+ well region 104 is 400 nm, the thickness of the first P-type well region 103 is 600 nm, and the thickness of the first P-type well region located below the P+ well region 104 is... The width of the N-type Schottky region 107 is 1 μm, which is equal to the width of the second source metal layer 111. This is to form a Schottky junction. The thickness of the N-type Schottky region 107 is 400 nm. This is to ensure the Schottky reverse breakdown voltage of the device. The width of the second P-type well region 106 is 300 nm and the thickness is 400 nm. This is to form a reverse space charge region, which improves the short-circuit current withstand capability of the device while avoiding affecting the conduction characteristics of the device. The thickness of the low-resistance region 105 located at the bottom of the N-type Schottky region 107 is 200 nm. This is to avoid the short-circuit withstand structure of the device affecting the conduction characteristics of the device. The thickness of the gate dielectric layer 108 is 50 nm. The thickness of the first source metal layer 110 and the second source metal layer 111 is 200 nm. The thickness of the gate metal layer 109 is 150 nm.

[0072] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a high-reliability discrete planar gate silicon carbide VDMOS, characterized in that: Includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; grow an epitaxial layer on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form a via, and implant ions to form the first P-type well region; Step 3: Ion implantation to form a P+ trap region; Step 4: Ion implantation to form an N-type source region; Step 5: Ion implantation to form a low-resistivity region; Step 6: Ion implantation to form a second P-type well region; Step 7: Ion implantation to form Schottky regions; Step 8: Deposition to form the gate dielectric layer; Step 9: Deposit metal to form a gate metal layer; Step 10: Deposit metal to form the first source metal layer and the second source metal layer, remove the barrier layer, and complete the fabrication; Before steps 3 to 10, the barrier layer from the previous step needs to be removed, a new barrier layer needs to be formed, and the barrier layer needs to be etched to form a via. The lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and the drift layer has a protrusion, and the protrusion has a first groove. The inner side of the first P-type well region is connected to the outer side of the protrusion, and the lower side of the first P-type well region is connected to the drift layer. The lower side of the P+ well region is connected to the first P-type well region. An N-type source region is provided in the P+ well region. One side of the N-type source region and one side of the P+ well region are both connected to the first P-type well region. The low-resistance region is located within the first groove, and a second groove is provided within the low-resistance region; The second P-type well region is located in the second groove, and the second P-type well region is provided with a perforation; The Schottky region is disposed within the perforation, and the lower side of the Schottky region is connected to the low-resistivity region; The lower side of the gate dielectric layer is connected to the N-type source region, the first P-type well region, the protrusion, the low-resistivity region and the second P-type well region, respectively. The gate metal layer is connected to the gate dielectric layer; The first source metal layer is connected to both the P+ well region and the N-type source region. The second source metal layer is connected to the Schottky region; The drain metal layer is connected to the lower side of the silicon carbide substrate.

2. The method for fabricating a high-reliability discrete planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The silicon carbide substrate, drift layer, low-resistivity region, and Schottky region are all N-type.

3. The method for fabricating a high-reliability discrete planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration in the low-resistivity region is greater than that in the drift layer.

4. The method for fabricating a high-reliability discrete planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the Schottky region is equal to the doping concentration of the second P-type well region.

5. The method for fabricating a high-reliability discrete planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The lower side of the low-resistivity region is located on the same plane as the lower side of the first P-type well region.

6. A high-reliability discrete planar gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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