3C / 4H-SiC heterojunction tunneling field effect transistor device and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor device manufacturing, in particular to a 3C / 4H-SiC heterojunction tunneling field effect transistor device with excellent third quadrant characteristics and a manufacturing method of the 3C / 4H-SiC heterojunction tunneling field effect transistor device. A 4H-SiC drift region, wherein the 4H-SiC drift region is arranged above the 4H-SiC substrate; the shallow trench gate electrode structure is arranged in the 4H-SiC drift region, and the shallow trench gate electrode structure is a split gate electrode structure; a source metal and a drain metal; the 3C-SiC epitaxial layer is arranged above the 4H-SiC drift region, the 3C-SiC epitaxial layer is in contact with the 4H-SiC drift region to form a heterojunction, and the heterojunction is located below the source electrode metal, electrically connected with the source electrode metal and used as a source electrode injection end. According to the 3C / 4H-SiC heterojunction tunneling field effect transistor device, the multiple problems that a traditional SiC MOSFET body diode is poor in reliability, high in on resistance, weak in gate oxide reliability and poor in dynamic performance are solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a 3C / 4H-SiC heterojunction tunneling field-effect transistor device with excellent third-quadrant characteristics and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC), as a representative of third-generation wide-bandgap semiconductor materials, possesses excellent properties such as high breakdown field strength, high thermal conductivity, and high electron saturation drift velocity, making it particularly suitable for power semiconductor devices operating under harsh conditions such as high power, high frequency, and high temperature. Among various SiC-based power switching devices, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted widespread attention from academia and industry due to their inherent leakage current-free characteristics, which significantly reduces energy loss during switching and reduces heat sink size, thereby effectively improving the power density of the entire power electronic system.

[0003] However, the parasitic body diode present in SiC MOSFET devices brings a series of serious problems in practical applications: this body diode not only has a high forward voltage drop (V... F Furthermore, the large reverse recovery current generated during the reverse recovery process leads to significant switching losses. More critically, during the body diode's conduction period, the injected minority carriers induce the proliferation and expansion of lattice defects, causing the so-called "bipolar degradation" phenomenon, which severely reduces the long-term reliability of the device. These issues limit the possibility of directly using the SiC MOSFET body diode as a commutation circuit, thus restricting further improvements in the overall performance of SiC power systems.

[0004] To overcome the inherent defects of parasitic body diodes, various solutions have been proposed in existing technologies, with the mainstream approach being the integration of Schottky barrier diodes (SBDs) into the SiC MOSFET cell structure. For example, existing technologies have reported structures integrating SBD cells between two split P-wells in a planar SiC MOSFET; other literature proposes a planar device scheme with a built-in SBD in the region between split gates; and research has also proposed a method using a split-gate trench SiC MOSFET and integrating an SBD. Although these methods can bypass the body diode to some extent and reduce reverse recovery losses, the introduction of the SBD cell requires additional chip area, leading to an increase in the device's specific on-resistance (Ron). on , sp ) and the forward voltage drop of the body diode (V F The trade-offs between these factors are difficult to reconcile, often resulting in increased cell size or deteriorated conduction characteristics, which restricts the optimization of device performance.

[0005] Therefore, in order to resolve the contradiction between area and performance caused by the integrated SBD scheme in the existing technology, and to fundamentally suppress the conduction problem of the body diode and the resulting reliability degradation, there is an urgent need for a new device structure that can effectively suppress the conduction of the body diode and strengthen its reliability while maintaining a compact cell size.

[0006] In view of this, the present invention is proposed. Summary of the Invention

[0007] The purpose of this invention is to provide a 3C / 4H-SiC heterojunction tunneling field-effect transistor device, which solves multiple problems of traditional SiC MOSFETs, such as poor body diode reliability, high on-resistance, weak gate oxide reliability, and poor dynamic performance.

[0008] In a first aspect, the present invention provides a 3C / 4H-SiC heterojunction tunneling field-effect transistor device, comprising a 4H-SiC substrate; A 4H-SiC drift region is disposed above the 4H-SiC substrate; A shallow trench gate structure is disposed in the 4H-SiC drift region, and the shallow trench gate structure is a split gate structure. Source metal and drain metal; A 3C-SiC epitaxial layer is disposed above the 4H-SiC drift region, and the 3C-SiC epitaxial layer and the 4H-SiC drift region are in contact to form a heterojunction. The heterojunction is located below the source metal and is electrically connected to the source metal, serving as the source injection terminal.

[0009] As a preferred embodiment of this technical solution, the split gate structure includes two split gate shallow trenches, each of which has a gate dielectric layer formed on its sidewall and bottom, and is filled with a gate.

[0010] As a preferred embodiment of this technical solution, a current extension region is provided in the 4H-SiC drift region, and the current extension region is located below the shallow trench gate structure. Preferably, the current extension region is an N+ current extension layer.

[0011] As a preferred embodiment of this technical solution, an electric field modulation region is provided in the 4H-SiC drift region, and the electric field modulation region is semi-enclosed on both sides and the inner upper surface of the current extension region; Preferably, the electric field modulation region includes a P-injection region and a P+injection region, wherein the P-injection region is disposed on the upper surface of the 4H-SiC drift region and located on both sides of the N+ current extension layer, and the P+injection region is disposed on the upper surface of the N+ current extension layer and located between adjacent gates.

[0012] As a preferred embodiment of this technical solution, it further includes an interlayer dielectric, which is disposed between the gate and the source metal.

[0013] In a preferred embodiment of this technical solution, the width of the P-implantation region is 0.8~1.2 μm, and the uniform doping concentration is 6e16~5e17 cm⁻¹. -3 The junction depth is 0.2~2.5 μm.

[0014] In a preferred embodiment of this technical solution, the uniform doping concentration of the N+ current spreading layer is 1e¹⁶~5e¹⁶ cm⁻¹. -3 The junction depth is 0.3~1.0 μm, and the junction depth of the N+ current extension layer is 0.1~1.5 μm less than the junction depth of the P- injection region.

[0015] In a preferred embodiment of this technical solution, the distance between the lower limit of the P+ injection region and the lower limit of the split gate shallow trench does not exceed 0.2 μm, and the lower limit of the P+ injection region does not exceed the lower limit of the N+ current extension layer.

[0016] As a preferred embodiment of this technical solution, the depth of the split gate shallow trench is 0.3~0.5 μm, the width is 0.3~0.6 μm, and the lower limit of the split gate shallow trench does not exceed the lower limit of the N+ current extension layer.

[0017] Secondly, the present invention also discloses a method for fabricating the above-mentioned 3C / 4H-SiC heterojunction tunneling field-effect transistor device, comprising the following steps: The 4H-SiC drift region is formed on a 4H-SiC substrate; P-injection regions are formed at both ends of the upper surface of the 4H-SiC drift region; An N+ current spread layer is formed between the two P-injection regions; Two split gate shallow trenches are formed within the N+ current extension layer; A P+ injection region is formed between adjacent split gate shallow trenches; A 3C-SiC epitaxial layer is formed on the surface of the 4H-SiC drift region; A gate dielectric layer is formed at the bottom, sidewalls, and surface of the 3C-SiC epitaxial layer of the split gate shallow trench; A gate is formed inside the shallow trench of the split gate; An interlayer dielectric is formed over the gate and the gate dielectric layer; The source and drain are formed to obtain a 3C / 4H-SiC heterojunction tunneling field-effect transistor device.

[0018] The 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention has at least the following beneficial effects: 1. The 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention has a 3C-SiC epitaxial layer disposed above the 4H-SiC drift region. The 3C-SiC material in the 3C-SiC epitaxial layer contacts the 4H-SiC material in the 4H-SiC drift region to form a heterojunction (3C / 4H-SiC). The forward conduction voltage drop of the 3C / 4H-SiC heterojunction diode is much lower than that of the body diode. Therefore, the 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention has lower freewheeling loss, and since it is unipolar conduction, the reverse recovery loss is also greatly reduced. 2. In the 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention, the heterojunction formed by 3C-SiC material and 4H-SiC material is located below the source metal and electrically connected to the source metal, serving as the source injection terminal and generating a forward tunneling current. This replaces the inversion layer channel of the traditional SiC MOSFET, and the mobility is not limited by the gate oxide interface quality of the traditional MOS channel, overcoming the problem of low channel field-effect mobility and reducing the overall on-resistance of the device. 3. The 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention uses the heterojunction interface formed by 3C-SiC and 4H-SiC materials as the source. Based on the tunneling mechanism, it conducts electricity and can directly select a shallow trench gate structure. Compared with the traditional 4H-SiC trench MOSFET structure, it greatly reduces the gate trench depth and reduces the process difficulty. 4. The 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention uses the heterojunction interface formed by 3C-SiC and 4H-SiC materials as the source. It conducts electricity based on the tunneling mechanism and is not affected by the gate oxide interface quality of traditional MOSFETs, thereby improving the gate oxide reliability of the device. 5. In the 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention, the shallow trench gate structure adopts a split gate structure. The split gate structure can reduce the gate capacitance and reduce the Miller effect caused by the gate capacitance, thereby enhancing the dynamic characteristics of the device. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the cross-sectional structure of a traditional UMOSFET device; Figure 2 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S1). Figure 3 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S2). Figure 4 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S3). Figure 5 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S4). Figure 6 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S5). Figure 7 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S6). Figure 8 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S7). Figure 9 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S8). Figure 10 This is a schematic diagram of the fabrication process of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S9). Figure 11 This is a schematic cross-sectional view of the 3C / 4H-SiC heterojunction tunneling field-effect transistor of the present invention (S10). Figure 12 This diagram illustrates the on-state voltage drop in the third quadrant for a conventional UMOSFET device and the 3C / 4H-SiC heterojunction tunneling field-effect transistor device of this invention.

[0021] Explanation of reference numerals in the attached figures: 1: Source metal; 2: Gate dielectric layer; 3: Interlayer dielectric; 4: Gate; 5: P+ source region; 6: N+ source region; 7: P-base region; 8: 4H-SiC drift region; 9: 4H-SiC substrate; 10: Drain metal; 11: P- implantation region; 12: N+ current spread layer; 13: P+ implantation region; 14: 3C-SiC epitaxial layer; 15: Split gate shallow trench. Detailed Implementation

[0022] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0025] Example 1 like Figure 11 As shown, this embodiment provides a 3C / 4H-SiC heterojunction tunneling field-effect transistor device, including a 4H-SiC substrate 9; 4H-SiC drift region 8, wherein the 4H-SiC drift region 8 is disposed above the 4H-SiC substrate 9; A shallow trench gate structure is disposed in the 4H-SiC drift region 8, and the shallow trench gate structure is a split gate structure. Source metal 1 and drain metal 10; A 3C-SiC epitaxial layer 14 is disposed above the 4H-SiC drift region 8, and the 3C-SiC epitaxial layer 14 contacts the 4H-SiC drift region 8 to form a heterojunction. The heterojunction is located below the source metal 1 and is electrically connected to the source metal 1, serving as the source injection terminal.

[0026] In this embodiment, a 4H-SiC drift region 8 is disposed above the 4H-SiC substrate 9, and a 3C-SiC epitaxial layer 14 is disposed above the 4H-SiC drift region 8. The 3C-SiC material in the 3C-SiC epitaxial layer 14 contacts the 4H-SiC material in the 4H-SiC drift region 8 to form a heterojunction (3C / 4H-SiC). The forward conduction voltage drop of the 3C / 4H-SiC heterojunction diode is much lower than that of the body diode. Therefore, the 3C / 4H-SiC heterojunction tunneling field-effect transistor device in this embodiment has lower freewheeling loss, and since it is unipolar conduction, the reverse recovery loss is also greatly reduced. Furthermore, the heterojunction formed by 3C-SiC and 4H-SiC materials is located below the source metal 1 and electrically connected to the source metal 1, serving as the source injection terminal. A forward tunneling current is generated at the heterojunction interface inside the bulk material. Electrons tunnel through the high-quality crystal interface, passing through instantaneously with extremely high efficiency. This replaces the inversion layer channel of the traditional SiC MOSFET. In other words, by integrating the 3C / 4H-SiC heterojunction, this invention fundamentally changes the current flow path in the third quadrant. The mobility is not limited by the gate oxide interface quality of the traditional MOS channel. This not only reduces the risk of gate oxide breakdown and improves gate oxide reliability, but also overcomes the problem of low mobility due to channel field effect and reduces the overall on-resistance of the device.

[0027] In the 3C / 4H-SiC heterojunction tunneling field-effect transistor device of this embodiment, since the heterojunction interface formed by 3C-SiC and 4H-SiC materials is used as the source, and conduction is achieved based on the tunneling mechanism, a shallow trench gate structure can be directly selected. There is no need to rely on a huge trench depth to obtain an ultra-wide channel to reduce resistance. Therefore, compared with the traditional 4H-SiC trench MOSFET structure, the gate trench depth is greatly reduced, the process difficulty is reduced, and it is not affected by the gate oxide interface quality of the traditional MOSFET. It fundamentally alleviates the terrible electric field concentration problem at the bottom corner of the deep trench, further protects the gate oxide, and improves the gate oxide reliability of the device.

[0028] Finally, the shallow trench gate structure in this embodiment adopts a split gate structure. The split gate structure reduces the critical gate capacitance (Miller capacitance) by physical means, thereby improving the switching performance (dynamic characteristics) of the device.

[0029] Therefore, the 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention combines a 3C / 4H-SiC heterojunction tunneling source with a split gate structure, which not only reduces static losses but also dynamic losses, and solves multiple problems of traditional SiC MOSFET body diodes such as poor reliability, high on-resistance, weak gate oxide reliability, and poor dynamic performance.

[0030] Based on the above technical solution, the split gate structure further includes two split gate shallow trenches 15, each of which has a gate dielectric layer 2 formed on its sidewall and bottom, and a gate 4 is disposed in the split gate shallow trench 15.

[0031] In the split gate structure, the regions between multiple gates 4 are isolated by an insulating dielectric, which physically separates the gate conductor from the drain region below. Therefore, the bottom area of ​​each split gate is greatly reduced, and capacitance is formed only through the sidewalls and the drain region, thus greatly reducing the Miller capacitance value.

[0032] In a specific embodiment of the present invention, the split gate structure includes two split gate shallow trenches 15, and each split gate shallow trench 15 is provided with a gate dielectric layer 2 and a gate 4.

[0033] Based on the above technical solution, a current extension region is further provided in the 4H-SiC drift region 8. The current extension region is located below the shallow trench gate structure to reduce the on-resistance and allow the current to extend and flow more uniformly in a direction parallel to the surface.

[0034] Based on the above technical solution, and more preferably, the current extension region is an N+ current extension layer 12.

[0035] Based on the above technical solution, the 4H-SiC drift region 8 is further provided with an electric field modulation region. The electric field modulation region is semi-enclosed on both sides and the inner upper surface of the current extension region to modulate the electric field, improve the withstand voltage and reliability, and thus solve the problem of electric field concentration at the bottom corner of the gate 4.

[0036] Based on the above technical solution, and further preferably, the electric field modulation region includes a P-injection region 11 and a P+ injection region 13. The P-injection region 11 is located on the upper surface of the 4H-SiC drift region 8 and on both sides of the N+ current extension layer 12. When the device is in the off state (withstanding high voltage), the main electric field is vertically distributed in the 4H-SiC drift region 8. The P-injection region 11 forms a PN junction with the surrounding N-type regions (such as the N+ current extension layer 12), and its depletion region expands laterally, thus "holding back" and "dispersing" the vertical electric field lines, preventing excessive concentration of the electric field at a certain point. The configuration of the P-injection region 11, acting as a "heterojunction" and a "shallow trench gate," provides an electrically "quieter" and more stable operating environment, ensuring that the device can reliably withstand high voltage in the off state. The P+ injection region 13 is located on the upper surface of the N+ current extension layer 12 and between adjacent gates 4. When the device is turned off and a high voltage is applied, the high potential of the drain will deplete the PN junction of the P+ injection region 13 / N+ current extension layer 12, forming a depletion layer region. This depletion layer acts like an "electrostatic shield" to physically separate the high-potential drain region from the bottom of the split gate shallow trench 15 above, thereby effectively absorbing and terminating the electric field lines and preventing the strong electric field from extending upward and impacting the weakest part of the gate oxide layer, the bottom corner of the split gate shallow trench 15.

[0037] Based on the above technical solution, it further includes an interlayer dielectric 3, which is disposed between the gate 4 and the source metal 1.

[0038] In another specific embodiment of the present invention, the width of the P-implantation region 11 is any value between 0.8 and 1.2 μm, and preferably 1 μm, with a uniform doping concentration of 6e16 to 5e17 cm⁻¹. -3 Any value between, preferably 1e17cm -3 The junction depth can be any value between 0.2 and 2.5 μm, and is preferably 2 μm.

[0039] Based on the above technical solution, the uniform doping concentration of the N+ current extension layer 12 is further specified as 1e16~5e16 cm⁻¹. -3 Any value between, preferably 2e16 cm -3 The junction depth is any value between 0.3 and 1.0 μm, and preferably 1 μm. The junction depth of the N+ current extension layer 12 is less than any value between 0.1 and 1.5 μm of the junction depth of the P- injection region 11, and preferably 1 μm.

[0040] Based on the above technical solution, the distance between the lower limit of the P+ injection region 13 and the lower limit of the split gate shallow trench 15 does not exceed 0.2 μm, and the lower limit of the P+ injection region 13 does not exceed the lower limit of the N+ current extension layer 12.

[0041] Based on the above technical solution, the depth of the split gate shallow trench 15 is any value between 0.3 and 0.5 μm, preferably 0.3 μm, and the width is any value between 0.3 and 0.6 μm, preferably 0.5 μm. Furthermore, the lower limit of the split gate shallow trench 15 does not exceed the lower limit of the N+ current extension layer 12.

[0042] In this embodiment, the layout of the P-injection region 11, the N+ current extension layer 12 and the P+ injection region 13 can be square, hexagonal, lattice array, etc., and the present invention does not impose strict limitations on this.

[0043] The core idea of ​​this invention, which involves forming a heterojunction in the semiconductor drift region as a highly efficient conductive or freewheeling channel, can also be applied to metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and junction barrier Schottky diodes (JBSs). In MOSFETs, a heterojunction replaces the traditional source to address issues such as body diode degradation, high on-resistance, and gate oxide reliability. In IGBTs, the heterojunction is integrated into the cathode, providing a low-loss carrier injection path and reducing on-state voltage drop or improving turn-off characteristics. In JBSs, the heterojunction is integrated into the anode, forming a superior heterojunction Schottky contact, further reducing on-state voltage drop and leakage current.

[0044] Furthermore, the core concept of integrating heterojunctions in this invention can be applied not only to SiC-based devices, but also to power devices on other semiconductor material platforms (such as Si silicon and GaN gallium nitride), which will not be elaborated here.

[0045] Example 2 This embodiment provides a method for fabricating the most preferred 3C / 4H-SiC heterojunction tunneling field-effect transistor device, specifically including the following steps: S1, such as Figure 2 As shown, an N-type 4H-SiC epitaxial layer was formed on an N-type heavily doped 4H-SiC substrate 9 using an epitaxial process, resulting in a 4H-SiC drift region 8. The resistivity of the N-type heavily doped 4H-SiC substrate 9 is 0.01–0.03 Ω·cm, and its thickness is 100–500 μm. The doping concentration of the N-type 4H-SiC drift region 8 is 5e¹⁴–5e¹⁶ cm⁻¹. -3 The thickness is 10~20 μm; S2, such as Figure 3 As shown, P-implantation regions 11 are formed at both ends of the upper surface of the 4H-SiC drift region 8 using photolithography and ion implantation processes. The junction depth of the P-implantation regions 11 is 0.2~2.5 μm, the width is 0.8~1.2 μm, and the uniform doping concentration of the P-implantation regions 11 is 6e16~5e17 cm⁻¹. -3 ; S3, such as Figure 4 As shown, an N+ current extension layer 12 is formed between two P- implantation regions 11 using photolithography and ion implantation processes. The junction depth of the N+ current extension layer 12 is 0.3~1.0 μm, and the uniform doping concentration is 1e16~5e16 cm⁻¹. -3 Furthermore, the junction depth of the N+ current extension layer 12 is 0.1~1.5 μm less than the junction depth of the P- injection region 11; S4, such as Figure 5 As shown, two split gate shallow trenches 15 are formed in the N+ current extension layer 12 between the P-injection regions 11 using photolithography and etching processes. The depth of the split gate shallow trenches 15 is 0.3~0.5 μm and the width is 0.3~0.6 μm. The lower limit of the split gate shallow trenches 15 does not exceed the lower limit of the N+ current extension layer 12. S5, such as Figure 6 As shown, P+ implantation regions 13 are formed between the shallow trenches 15 of the split gate using photolithography and ion implantation processes. The junction depth of the P+ implantation regions 13 is 0.2~0.5 μm, the implantation width is 1.2~2.0 μm, and the uniform doping concentration is 5e18~1e19 cm⁻¹. -3 Furthermore, the distance between the lower limit of the split gate shallow trench 15 and the lower limit of the P+ injection region 13 does not exceed 0.2 μm, and the lower limit of the P+ injection region 13 does not exceed the lower limit of the N+ current extension layer 12. S6, such as Figure 7 As shown, an N-type 3C-SiC epitaxial layer 14 is formed on the surface of the 4H-SiC drift region 8 using a high-temperature liquid phase method or a chemical vapor deposition method. The doping concentration of the N-type 3C-SiC epitaxial layer 14 is 1e19~1e20 cm⁻¹. -3 The thickness is 0.5~1.0 μm. Further, excess 3C-SiC is removed by photolithography and etching. An N-type 3C-SiC epitaxial layer 14 is generated on the surface of the 4H-SiC drift region 8 by high-temperature liquid phase method or chemical vapor deposition method. This allows the 3C-SiC epitaxial layer 14 to form an atomically tightly bonded crystal interface with the 4H-SiC drift region 8. This interface is the physical basis for all the subsequent excellent electrical properties.

[0046] S7, such as Figure 8As shown, a gate dielectric layer 2 is generated on the bottom and sidewalls of the split gate shallow trench 15 and the surface of the 3C-SiC epitaxial layer 14 using thermal oxidation or deposition processes, wherein the thickness of the gate dielectric layer 2 is 10~100 nm. S8, such as Figure 9 As shown, polysilicon is filled inside the split gate shallow trench 15 and above the gate dielectric layer 2 using deposition, photolithography and etching processes, and excess polysilicon and gate dielectric layer 2 are removed by photolithography and etching. S9, such as Figure 10 As shown, deposition, photolithography and etching processes are used to deposit interlayer dielectric 3 on polysilicon and gate dielectric layer 2, and excess interlayer dielectric 3 and gate dielectric layer 2 are removed by photolithography and etching. S10, such as Figure 11 As shown, source metal 1 is deposited on the front side of the device, and the source on the front side of the device is formed by photolithography and etching processes; drain metal 10 is deposited on the back side of the device, and the drain on the back side of the device is formed by laser annealing, metal thickening and other processes; finally, protective adhesive is deposited on the front side to obtain a 3C / 4H-SiC heterojunction tunneling field-effect transistor device.

[0047] This invention further tested the on-state voltage drop V0 of the 3C / 4H-SiC heterojunction tunneling field-effect transistor device prepared above in the third quadrant. F The size was compared with that of a conventional UMOSFET device, and the results are as follows: Figure 12 As shown.

[0048] Depend on Figure 12 It is known that the 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention integrates a heterojunction diode formed of 3C-SiC and 4H-SiC materials. The forward conduction voltage drop of the 3C / 4H-SiC heterojunction diode is much lower than that of the body diode of a traditional UMOSFET device. Figure 1 The forward conduction voltage drop is lower, resulting in lower follow current loss, and the reverse recovery loss is also significantly reduced due to the unipolar conduction.

[0049] In summary, the 3C / 4H-SiC heterojunction tunneling field-effect transistor device of the present invention solves multiple problems of traditional SiC MOSFETs, such as poor body diode reliability, high on-resistance, weak gate oxide reliability, and poor dynamic performance. Moreover, the fabrication method of this device is highly compatible with the fabrication process of traditional SiC MOSFET devices, and mass production can be achieved without special adjustments to the SiC process.

[0050] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to create the same structure, those skilled in the art can design methods that are not entirely identical to those described above.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 3C / 4H-SiC heterojunction tunneling field effect transistor device, characterized by, comprising a 4H-SiC substrate; a 4H-SiC drift region disposed above the 4H-SiC substrate; a shallow trench gate structure disposed in the 4H-SiC drift region, and the shallow trench gate structure is a split gate structure; a source metal and a drain metal; a 3C-SiC epitaxial layer disposed above the 4H-SiC drift region, and the 3C-SiC epitaxial layer forms a heterojunction with the 4H-SiC drift region, the heterojunction is below and electrically connected with the source metal as a source injection end.

2. The 3C / 4H-SiC heterojunction tunneling field effect transistor device of claim 1, wherein, The split gate structure comprises split gate shallow trenches, the sidewalls and bottom of each split gate shallow trench are formed with a gate dielectric layer, and a gate is disposed in the split gate shallow trench.

3. The 3C / 4H-SiC heterojunction tunneling field effect transistor device of claim 2, wherein, A current spreading region is disposed in the 4H-SiC drift region, and the current spreading region is disposed below the shallow trench gate structure; Preferably, the current spreading region is an N+ current spreading layer.

4. The 3C / 4H-SiC heterojunction tunneling field effect transistor device of claim 3, wherein, An electric field modulation region is disposed in the 4H-SiC drift region, and the electric field modulation region is semi-surrounded on both sides and the upper surface of the inside of the current spreading region; Preferably, the electric field modulation region comprises a P- injection region and a P+ injection region, wherein the P- injection region is disposed on the upper surface of the 4H-SiC drift region and is located on both sides of the N+ current spreading layer, and the P+ injection region is disposed on the upper surface of the N+ current spreading layer and is located between adjacent gates.

5. The 3C / 4H-SiC heterojunction tunneling field effect transistor device of claim 2, wherein, An interlayer dielectric is further included, and the interlayer dielectric is disposed between the gate and the source metal.

6. The 3C / 4H-SiC heterojunction tunneling field effect transistor device of claim 4, wherein, The width of the P-injection region is 0.8-1.2 μm, the uniform doping concentration is 6e16-5e17 cm -3 , and the junction depth is 0.2-2.5 μm.

7. The 3C / 4H-SiC heterojunction tunneling field effect transistor device of claim 4, wherein, The uniform doping concentration of the N+ current spreading layer is 1e16~5e16 cm -3 The junction depth of the N+ current spreading layer is 0.3~1.0 μm, and the junction depth of the N+ current spreading layer is less than the junction depth of the P- injection region by 0.1~1.5 μm.

8. The 3C / 4H-SiC heterojunction tunneling field effect transistor device of claim 4, wherein, The lower limit of the P+ injection region is spaced apart from the lower limit of the split gate shallow trench by no more than 0.2 μm, and the lower limit of the P+ injection region is no more than the lower limit of the N+ current spreading layer.

9. The 3C / 4H-SiC heterojunction tunneling field effect transistor device of claim 3, wherein, The depth of the split gate shallow trench is 0.3-0.5 μm, the width is 0.3-0.6 μm, and the lower limit of the split gate shallow trench is no more than the lower limit of the N+ current spreading layer.

10. A method of fabricating a 3C / 4H-SiC heterojunction tunneling field effect transistor device, characterized by, comprising the following steps: forming the 4H-SiC drift region on a 4H-SiC substrate; forming a P- injection region at both ends of the upper surface of the 4H-SiC drift region; forming an N+ current spreading layer between the two P- injection regions; forming two split gate shallow trenches in the N+ current spreading layer; forming a P+ injection region between adjacent split gate shallow trenches; forming a 3C-SiC epitaxial layer on the surface of the 4H-SiC drift region; forming a gate dielectric layer on the bottom, sidewall of the split gate shallow trench and the surface of the 3C-SiC epitaxial layer; forming a gate in the inside of the split gate shallow trench; forming an interlayer dielectric above the gate and the gate dielectric layer; forming a source and a drain to obtain a 3C / 4H-SiC heterojunction tunneling field effect transistor device; wherein the 3C-SiC epitaxial layer is prepared by a high-temperature liquid phase method or a chemical vapor deposition method.

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