Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are disclosed. The display device includes a circuit layer including: a light emitting pixel driver; a first shared line adjacent to a first boundary between the first light emitting pixel driver and the second light emitting pixel driver adjacent to each other, and electrically connected to the first light emitting pixel driver and the second light emitting pixel driver; a first semiconductor layer on the substrate; and a second semiconductor layer on the first intermediate insulating layer. Each of the light emitting pixel drivers includes a first transistor, a channel portion of which, a first electrode, and a second electrode are disposed in the second semiconductor layer. The first semiconductor layer and the second semiconductor layer of the first light-emitting pixel driver and the first semiconductor layer and the second semiconductor layer of the second light-emitting pixel driver are symmetrical relative to the first boundary.

Description

Technical Field

[0001] The disclosure relates to a display device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being used in a variety of electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light-emitting display device. Here, the light-emitting display device can include an organic light-emitting display device that includes an organic light-emitting element, an inorganic light-emitting display device that includes an inorganic light-emitting element such as an inorganic semiconductor, and a micro light-emitting display device or a nano light-emitting display device that includes a micro light-emitting element or a nano light-emitting element.

[0004] Organic light-emitting display devices use light-emitting elements, each comprising a light-emitting layer made of organic light-emitting materials, to display images. Thus, because organic light-emitting display devices use self-emissive elements to display images, they can offer superior performance in terms of power consumption, response speed, emission efficiency, brightness, and wide viewing angle compared to other display devices.

[0005] One surface of the display device can be a display area comprising a display area for displaying an image and a non-display area surrounding the display area. A light-emitting area emitting light with corresponding brightness and color can be arranged within the display area. Summary of the Invention

[0006] The display device may include light-emitting elements respectively disposed in light-emitting areas and light-emitting pixel drivers electrically connected to the light-emitting elements. Each of the light-emitting pixel drivers can supply driving current to each of the light-emitting elements.

[0007] Each of the light-emitting pixel drivers may include a first transistor for generating drive current and a second transistor electrically connected between the first transistor and a data line for transmitting data signals, and may also include transistors for optional electrical connection, initialization or reset of some nodes.

[0008] In addition, when the channel portion of the first transistor includes an oxide semiconductor, the width of the first transistor can be increased beyond a critical value to ensure the current characteristics of the first transistor, thereby increasing the width of each of the light-emitting pixel drivers.

[0009] As a result, there may be limitations in increasing the resolution of display devices.

[0010] The disclosed features provide a display device that can be advantageous in increasing resolution by improving the integration of the light-emitting pixel drivers.

[0011] However, the features of the disclosure are not limited to those set forth herein. These and other features of the disclosure will become more apparent to a person skilled in the art by referring to the detailed description of the disclosure given below.

[0012] In a disclosed embodiment, a display device is provided, comprising: a substrate including a display area in which a light-emitting region is disposed and a non-display area disposed around the display area; a circuit layer disposed on the substrate; and an element layer disposed on the circuit layer, including light-emitting elements all disposed in the light-emitting region. The circuit layer includes: a light-emitting pixel driver electrically connected to the light-emitting elements and disposed in a first direction and a second direction; a first shared line extending in the second direction, adjacent to a first boundary between a first light-emitting pixel driver and a second light-emitting pixel driver that are adjacent to each other in the first direction, and electrically connected to the first light-emitting pixel driver and the second light-emitting pixel driver; a first semiconductor layer disposed on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed on the second gate insulating layer; a first intermediate insulating layer covering the second gate conductive layer; and a second semiconductor layer disposed on the first intermediate insulating layer. One of the light-emitting pixel drivers includes a first transistor that generates a drive current for one of the light-emitting elements. The channel portion, first electrode, and second electrode of the first transistor are disposed in the second semiconductor layer. The first semiconductor layer and the second semiconductor layer of the first light-emitting pixel driver are symmetrical with respect to the first boundary as are the first semiconductor layer and the second semiconductor layer of the second light-emitting pixel driver.

[0013] In an embodiment, the light-emitting pixel driver further includes: a third light-emitting pixel driver adjacent to the second light-emitting pixel driver in a first direction; a fourth light-emitting pixel driver adjacent to the first light-emitting pixel driver in a second direction; a fifth light-emitting pixel driver adjacent to the second light-emitting pixel driver in a second direction; and a sixth light-emitting pixel driver adjacent to the third light-emitting pixel driver in a second direction. The first and second semiconductor layers of the second and third light-emitting pixel drivers are symmetrical with respect to a second boundary between the second and third light-emitting pixel drivers. The first and second semiconductor layers of the first and fourth light-emitting pixel drivers are symmetrical with respect to a third boundary between the first and fourth light-emitting pixel drivers. The first and second semiconductor layers of the second and fifth light-emitting pixel drivers are symmetrical with respect to an extension of the third boundary. A first shared line is also electrically connected to the fourth and fifth light-emitting pixel drivers.

[0014] In an embodiment, the circuit layer further includes: a data line for transmitting data signals to a light-emitting pixel driver; a reference voltage line for transmitting a reference voltage to a light-emitting pixel driver; an initialization voltage line for transmitting an initialization voltage to a light-emitting pixel driver; a first power line for transmitting a first power to a light-emitting pixel driver; a scan write line for transmitting a scan write signal to a light-emitting pixel driver; a reset control line for transmitting a reset control signal to a light-emitting pixel driver; a bias control line for transmitting a bias control signal to a light-emitting pixel driver; a first transmit control line for transmitting a first transmit control signal to a light-emitting pixel driver; and a second transmit control line for transmitting a second transmit control signal to a light-emitting pixel driver.

[0015] In an embodiment, the circuit layer further includes: a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer disposed on the third gate insulating layer; a second intermediate insulating layer covering the third gate conductive layer; a first source-drain conductive layer disposed on the second intermediate insulating layer; a first planarization layer covering the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer. One of the light-emitting pixel drivers in the light-emitting pixel driver further includes: a second transistor electrically connected between the gate electrode of the first transistor and one of the data lines; a third transistor electrically connected between the gate electrode of the first transistor and a reference voltage line; a fourth transistor electrically connected between a light-emitting element and an initialization voltage line; a fifth transistor electrically connected between the first electrode of the first transistor and a first power line; a sixth transistor electrically connected between the second electrode of the first transistor and a light-emitting element; a first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; and a second capacitor electrically connected between the first power line and the second electrode of the first transistor.

[0016] In one embodiment, the first power line includes: a first main power line disposed in a third gate conductive layer and extending in a first direction; and a first sub-power line disposed in a second source-drain conductive layer and extending in a second direction. The first shared line includes the first sub-power line.

[0017] In an embodiment, the circuit layer further includes: an electrode extension extending from the first electrode of the sixth transistor; a first capacitor electrode disposed in the first gate conductive layer, stacked with a portion of the electrode extension, and electrically connected to the gate electrode of the first transistor; a second capacitor electrode disposed in the second gate conductive layer, stacked with the first capacitor electrode, and electrically connected to the second electrode of the first transistor; a third capacitor electrode disposed in the first gate conductive layer, separated from the first capacitor electrode, stacked with another portion of the electrode extension and the second capacitor electrode, and electrically connected to the first power line; a first power connection auxiliary electrode disposed in the first source-drain conductive layer and electrically connected to the third capacitor electrode and the first power line; and a second power connection auxiliary electrode disposed in the first source-drain conductive layer and electrically connected to the first electrode of the fifth transistor and the first power line. The third capacitor electrode of the first light-emitting pixel driver and the third capacitor electrode of the second light-emitting pixel driver are connected to each other at a first boundary. The second power connection auxiliary electrode of the first light-emitting pixel driver and the second power connection auxiliary electrode of the second light-emitting pixel driver are connected to each other at a first boundary. The first capacitor is configured as a stacked region between each of the electrode extension and the second capacitor electrode and the first capacitor electrode. The second capacitor is configured as an overlapping area between the electrode extension and each of the second capacitor electrodes and the third capacitor electrode.

[0018] In one embodiment, the first power connection auxiliary electrode of the second light-emitting pixel driver and the first power connection auxiliary electrode of the third light-emitting pixel driver are connected to each other at the second boundary and are electrically connected to the first electrode of the fifth transistor of the first semiconductor layer.

[0019] In an embodiment, the circuit layer further includes at least one second shared line, which extends in a first direction, is adjacent to (adjacent to) the third boundary, and is electrically connected to the first light-emitting pixel driver, the second light-emitting pixel driver, the fourth light-emitting pixel driver, and the fifth light-emitting pixel driver.

[0020] In one embodiment, the fourth transistor is turned on by a bias control signal of a bias control line. The bias control line is disposed in the third gate conductive layer, extends in the first direction, and overlaps with the third boundary. At least one second shared line includes the bias control line.

[0021] In one embodiment, an initialization voltage line is disposed in a first source-drain conductive layer, extends in a first direction, and overlaps with a third boundary. At least one second shared line includes the initialization voltage line.

[0022] In one embodiment, the fifth transistor is turned on by a first emitt control signal of the first emitt control line. The sixth transistor is turned on by a second emitt control signal of the second emitt control line. The second emitt control line includes: an emitt control main line disposed in the first gate conductive layer, extending in a first direction and stacked with the fourth and fifth light-emitting pixel drivers; an emitt control protrusion line protruding from the emitt control main line and extending in a second direction; and a reset control extension line connected to the emitt control protrusion line, extending in the first direction and stacked with the fifth and sixth light-emitting pixel drivers. At least one second shared line includes the second emitt control line.

[0023] In one embodiment, the light-emitting pixel driver further includes: a seventh light-emitting pixel driver, adjacent to the fourth light-emitting pixel driver in a second direction; and an eighth light-emitting pixel driver, adjacent to the fifth light-emitting pixel driver in a second direction. The first and second semiconductor layers of the seventh light-emitting pixel driver are symmetrical with respect to the extensions of the first and second semiconductor layers of the eighth light-emitting pixel driver relative to a first boundary. The first and second semiconductor layers of the seventh light-emitting pixel driver are symmetrical with respect to the first and second semiconductor layers of the fourth light-emitting pixel driver relative to a fourth boundary between the fourth and seventh light-emitting pixel drivers. The first and second semiconductor layers of the eighth light-emitting pixel driver are symmetrical with respect to the extensions of the first and second semiconductor layers of the fifth light-emitting pixel driver relative to a fourth boundary. The circuit layer also includes at least one third shared line extending in the first direction, adjacent to the fourth boundary, and electrically connected to the fourth, fifth, seventh, and eighth light-emitting pixel drivers.

[0024] In one embodiment, the third transistor is turned on by a reset control signal from a reset control line. The reset control line includes: a reset control main line disposed in the third gate conductive layer, extending in a first direction and stacked with the fourth and fifth light-emitting pixel drivers; a reset control protrusion line protruding from the reset control main line and extending in a second direction; and a reset control extension line connected to the reset control protrusion line, extending in the first direction and stacked with the seventh and eighth light-emitting pixel drivers. At least one third shared line includes the reset control line.

[0025] In one embodiment, the reference voltage line includes: a reference voltage main line disposed in the second gate conductive layer, extending in a first direction and overlapping with a fourth boundary; and a reference voltage sub-line disposed in the second source-drain conductive layer, extending in a second direction, adjacent to the second boundary, and electrically connected to the reference voltage main line. At least one third shared line includes the reference voltage main line.

[0026] In a disclosed embodiment, a display device is provided, comprising: a substrate including a display area in which a light-emitting region is disposed and a non-display area disposed around the display area; a circuit layer disposed on the substrate; and an element layer disposed on the circuit layer and including light-emitting elements all disposed in the light-emitting region. The circuit layer includes: a light-emitting pixel driver electrically connected to the light-emitting elements and disposed in a first direction and a second direction; a data line extending in the second direction and transmitting data signals to the light-emitting pixel driver; a first bypass auxiliary line extending in the first direction and electrically connected to a first data line in the data line that is adjacent to the non-display area in the first direction; a second bypass auxiliary line extending in the second direction, adjacent to a second data line in the data line that is further apart from the non-display area in the first direction than the first data line, and electrically connected to the first bypass auxiliary line; and a first shared line extending in the second direction, adjacent to a boundary between two light-emitting pixel drivers that are adjacent to each other in the first direction, and electrically connected to the two light-emitting pixel drivers. The circuit layer includes a first semiconductor layer disposed on the substrate and a second semiconductor layer disposed on one or more insulating layers covering the first semiconductor layer. Two light-emitting pixel drivers include a first semiconductor layer and a second semiconductor layer that are symmetrical about each other with respect to the boundary between the two light-emitting pixel drivers. Two other light-emitting pixel drivers that are adjacent to each other in a second direction include a first semiconductor layer and a second semiconductor layer that are symmetrical about each other with respect to the boundary between the other two light-emitting pixel drivers.

[0027] In an embodiment, the circuit layer further includes: a first semiconductor layer; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed on the second gate insulating layer; a first intermediate insulating layer covering the second gate conductive layer; a second semiconductor layer disposed on the first intermediate insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer disposed on the third gate insulating layer; a second intermediate insulating layer covering the third gate conductive layer; a first source-drain conductive layer disposed on the second intermediate insulating layer; a first planarization layer covering the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer. Each of the light-emitting pixel drivers includes: a first transistor; a second transistor electrically connected between a data line transmitting a data signal and the gate electrode of the first transistor; a third transistor electrically connected between a reference voltage line transmitting a reference voltage and the gate electrode of the first transistor; a fourth transistor electrically connected between an initialization voltage line transmitting an initialization voltage and the light-emitting element; a fifth transistor electrically connected between a first power line transmitting a first power and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and the light-emitting element; a first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; and a second capacitor electrically connected between the first power line and the second electrode of the first transistor. The channel portion, first electrode, and second electrode of each of the first, second, third, and fourth transistors are disposed in a second semiconductor layer. The channel portion, first electrode, and second electrode of each of the fifth and sixth transistors are disposed in the first semiconductor layer. The third transistor is turned on by a reset control signal of a reset control line. The fourth transistor is turned on by a bias control signal of a bias control line. The fifth transistor is turned on by a first emitt control signal of a first emitt control line. The sixth transistor is turned on by a second emitt control signal of a second emitt control line.

[0028] In an embodiment, the light-emitting pixel driver includes: a first light-emitting pixel driver; a second light-emitting pixel driver adjacent to the first light-emitting pixel driver in a first direction; a third light-emitting pixel driver adjacent to the second light-emitting pixel driver in the first direction; a fourth light-emitting pixel driver adjacent to the first light-emitting pixel driver in a second direction; a fifth light-emitting pixel driver adjacent to the second light-emitting pixel driver in a second direction; a sixth light-emitting pixel driver adjacent to the third light-emitting pixel driver in a second direction; a seventh light-emitting pixel driver adjacent to the fourth light-emitting pixel driver in a second direction; and an eighth light-emitting pixel driver adjacent to the fifth light-emitting pixel driver in a second direction. The first power line includes: a first power main line disposed in a third gate conductive layer and extending in a first direction; and a first power sub-line disposed in a second source-drain conductive layer and extending in a second direction. A first shared line is adjacent to the boundary between the first and second light-emitting pixel drivers and includes the first power sub-line.

[0029] In an embodiment, each of the light-emitting pixel drivers further includes: an electrode extension extending from a first electrode of the sixth transistor; a first capacitor electrode disposed in a first gate conductive layer, stacked with a portion of the electrode extension, and electrically connected to the gate electrode of the first transistor; a second capacitor electrode disposed in a second gate conductive layer, stacked with the first capacitor electrode, and electrically connected to a second electrode of the first transistor; and a third capacitor electrode disposed in the first gate conductive layer, separated from the first capacitor electrode, stacked with another portion of the electrode extension and the second capacitor electrode, and electrically connected to a first power line. The first capacitor is configured as a stacked region between each of the electrode extension and the second capacitor electrode and the first capacitor electrode. The second capacitor is configured as a stacked region between each of the electrode extension and the second capacitor electrode and the third capacitor electrode.

[0030] In an embodiment, the circuit layer further includes at least one second shared line, which extends in a first direction, is adjacent to (adjacent to) the boundary between the second and third light-emitting pixel drivers, and is electrically connected to the second, third, fifth, and sixth light-emitting pixel drivers. The second emission control line includes: an emission control main line disposed in the first gate conductive layer, extending in the first direction, and superimposed on the fourth and fifth light-emitting pixel drivers; an emission control protrusion line protruding from the emission control main line and extending in the second direction; and a reset control extension line connected to the emission control protrusion line, extending in the first direction, and superimposed on the fifth and sixth light-emitting pixel drivers. The at least one second shared line includes at least one of a bias control line, an initialization voltage line, and a second emission control line.

[0031] In an embodiment, the circuit layer further includes at least one third shared line extending in a first direction, adjacent to (adjacent to) the boundary between the fourth and seventh light-emitting pixel drivers, and electrically connected to the fourth, fifth, seventh, and eighth light-emitting pixel drivers. The reference voltage line includes: a reference voltage main line disposed in the second gate conductive layer and extending in the first direction; and a reference voltage sub-line disposed in the second source-drain conductive layer, extending in the second direction, and electrically connected to the reference voltage main line. The reset control line includes: a reset control main line extending in the first direction and superimposed on the fourth and fifth light-emitting pixel drivers; a reset control protrusion line protruding from the reset control main line and extending in the second direction; and a reset control extension line connected to the reset control protrusion line, extending in the first direction, and superimposed on the seventh and eighth light-emitting pixel drivers. The at least one third shared line includes at least one of the reference voltage main line and the reset control line.

[0032] In one embodiment, the display device includes a circuit layer and a component layer disposed on a substrate.

[0033] In an embodiment, the element layer may include light-emitting elements respectively disposed in the light-emitting areas.

[0034] In an embodiment, the circuit layer may include: a light-emitting pixel driver, a light-emitting element electrically connected to the element layer, and arranged in a first direction and a second direction; and a first shared line extending in the second direction, adjacent to a first boundary between the first and second light-emitting pixel drivers that are adjacent to each other in the first direction, and electrically connected to the first and second light-emitting pixel drivers. The circuit layer may include a first semiconductor layer disposed on a substrate and a second semiconductor layer disposed on one or more insulating layers covering the first semiconductor layer. Each of the light-emitting pixel drivers may include a first transistor that generates a drive current for each of the light-emitting elements, and the channel portion, first electrode, and second electrode of the first transistor may be disposed in the second semiconductor layer.

[0035] In an embodiment, the first semiconductor layer and the second semiconductor layer of the first light-emitting pixel driver may be symmetrical with respect to the first semiconductor layer and the second semiconductor layer of the second light-emitting pixel driver with respect to the first boundary.

[0036] In this way, each of the first shared lines arranged in the display area can be electrically connected to two adjacent (adjacent) pixel columns in the first direction within a pixel column in the display area, which is composed of light-emitting pixel drivers arranged parallel in the second direction. Therefore, the total number of first shared lines arranged in the display area can be reduced to half the number of pixel columns arranged in the display area.

[0037] As a result, since the width of the display area consumed by arranging the first shared line can be reduced, it can be advantageous in increasing the resolution of the display device.

[0038] In an embodiment, the first shared line may include a first power sub-line that transmits first power and is disposed in a second source-drain conductive layer.

[0039] In an embodiment, the light-emitting pixel driver may include: a third light-emitting pixel driver, which is parallel to the second light-emitting pixel driver in a first direction; a fourth, a fifth, and a sixth light-emitting pixel driver, which are adjacent to the first, second, and third light-emitting pixel drivers respectively in a second direction; and a seventh and an eighth light-emitting pixel driver, which are adjacent to the fourth and fifth light-emitting pixel drivers respectively in a second direction.

[0040] In an embodiment, the circuit layer may further include at least one second shared line, which extends in a first direction, is adjacent to (adjacent to) a third boundary between the first light-emitting pixel driver and the fourth light-emitting pixel driver, and is electrically connected to the first light-emitting pixel driver, the second light-emitting pixel driver, the fourth light-emitting pixel driver, and the fifth light-emitting pixel driver.

[0041] At least one second shared line may include at least one of the following: a bias control line disposed in the third gate conductive layer and transmitting a bias control signal; an initialization voltage line disposed in the first source-drain conductive layer and transmitting an initialization voltage; and a light emission control main line disposed in the first gate conductive layer and transmitting a second light emission control signal.

[0042] In this way, any one of the second shared lines disposed in the display area can be electrically connected to two pixel rows that are adjacent to each other in the second direction among the pixel rows in the display area, which are all composed of light-emitting pixel drivers arranged parallel in the first direction. Therefore, the number of second shared lines disposed in the display area can be reduced to half the number of pixel rows disposed in the display area.

[0043] As a result, since the width of the display area consumed by arranging the second shared line can be reduced, it can be advantageous in increasing the resolution of the display device.

[0044] In an embodiment, the circuit layer may further include at least one third shared line, which extends in a first direction, is adjacent to (adjacent to) a fourth boundary between the fourth and seventh light-emitting pixel drivers, and is electrically connected to the fourth, fifth, seventh, and eighth light-emitting pixel drivers.

[0045] In an embodiment, at least one third shared line may include at least one of a reference voltage main line for transmitting a reference voltage and a second reset control line for transmitting a second reset control signal.

[0046] In this way, any one of the third shared lines in the display area can be electrically connected to two pixel rows that are adjacent to each other in the second direction. Therefore, the number of third shared lines in the display area can be reduced to half the number of pixel rows in the display area.

[0047] As a result, since the width of the display area consumed by arranging the third shared line can be reduced, it can be advantageous in increasing the resolution of the display device.

[0048] However, the effects of the embodiments are not limited to those described herein. The above and other effects of the embodiments will become more apparent to those skilled in the art upon which the embodiments pertain by referring to the claims. Attached Figure Description

[0049] The above and other advantages and features of the disclosure will become more apparent from the detailed description of the disclosed embodiments with reference to the accompanying drawings, in which: Figure 1 This is a perspective view illustrating an embodiment of the display device; Figure 2 It is shown Figure 1 A plan view of the display device; Figure 3 It is along Figure 2 A sectional view taken by line A-A'; Figure 4 It is shown Figure 2 A partial plan view of section B; Figure 5 It is shown Figure 4 An equivalent circuit diagram of an embodiment of a light-emitting pixel driver; Figure 6 It is shown Figure 5 A cross-sectional view of the first transistor, the second transistor, the sixth transistor, the first capacitor, the second capacitor, and the light-emitting element; Figure 7 It is shown Figure 3 A plan view of an embodiment of the substrate; Figure 8 It is shown Figure 7 A partial plan view of the circuit layer of D; Figure 9 It is shown Figure 7 A partial circuit layer plan view of E; Figure 10 It is shown Figure 8 A plan view of a portion of the embodiment of F; Figure 11 It is shown Figure 8 A plan view of a portion of an embodiment of G; Figure 12 It is shown Figure 4 A plan view of an embodiment of the first and second semiconductor layers of part C; Figure 13 It is shown Figure 12 A plan view of the first semiconductor layer, the first gate conductive layer and the second gate conductive layer of part H; Figure 14 It is shown Figure 12 A partial plan view of the second semiconductor layer and the third gate conductive layer of H; Figure 15It is shown Figure 12 A partial plan view of the first source-drain conductive layer of H; Figure 16 It is shown Figure 12 A partial plan view of the second source-drain conductive layer of H; Figure 17 It is shown Figure 12 A plan view of an embodiment of the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer of part I; Figure 18 It is shown Figure 12 A plan view of the first semiconductor layer, the first gate conductive layer and the second gate conductive layer of part J; Figure 19 This is a block diagram illustrating an embodiment of an electronic device; and Figure 20 This shows what is implemented as a smartphone. Figure 19 A view of an embodiment of an electronic device. Detailed Implementation

[0050] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0051] In order to describe the disclosed embodiments, some parts (components) that are not associated with the description may not be provided.

[0052] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on said other layer or substrate, or an intermediary layer may be present. Conversely, when an element is referred to as being "directly on" another element, no intermediary element is present.

[0053] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting the portion of the object from the side. The terms "overlapping" or "coinciding" mean that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping" can include layering, stacking, facing or confronting, extending over (overgoing), covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separated from," "offset from," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "confronting" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, although the first and second objects still face each other, the first and second objects can be understood as being indirectly opposite each other.

[0054] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are intended to also cover different orientations of the device during use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned “below” or “under” another device may be placed “above” another device. Thus, the exemplary term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore spatial relative terms may be interpreted differently depending on orientation.

[0055] When an element is referred to as being “connected” or “joined” to another element, the element may be “directly connected” or “directly joined” to the other element, or “electrically connected” or “electrically joined” to the other element with one or more intermediary elements disposed therebetween. It will also be understood that when the terms “comprising,” “having,” “including,” and / or variations thereof are used, they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combinations thereof.

[0056] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or for the convenience of its description and explanation. For example, when “first element” is discussed in the description, it may be named “second element” or “third element,” and “second element” and “third element” may be named in a similar manner without departing from the teaching herein.

[0057] As used herein, the terms “about” or “approximately” include the stated value and mean: within an acceptable deviation of the particular value, as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0058] In the specification and claims, the term "and / or" is intended, for the purposes of its meaning and interpretation, to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended, for the purposes of its meaning and interpretation, to include the meaning of "at least one of the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0059] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0060] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0061] Figure 1 This is a perspective view showing an embodiment of the display device. Figure 2 It is shown Figure 1 A plan view of the display device. Figure 3 It is along Figure 2 A sectional view taken by line A-A'.

[0062] Reference Figure 1 and Figure 2The display device 100 is a device for displaying moving or still images and can be used as a display screen for each of various products such as televisions, laptops, monitors, billboards and Internet of Things (“IoT”) devices and portable electronic devices such as mobile phones, smartphones, tablet PCs (“PCs”), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (“PMPs”), navigation devices and ultra-mobile PCs (“UMPCs”).

[0063] Display device 100 can be an organic light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes (OLEDs), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, or a micro light-emitting display device using micro LEDs or nano LEDs (micro-LEDs or nano-LEDs). In the following description, it will be based primarily on the fact that display device 100 is an organic light-emitting display device. However, the disclosure is not limited thereto, and can be applied to display devices including organic insulating materials, organic light-emitting materials, and metallic materials.

[0064] The display device 100 may be flat, but is not limited thereto. In embodiments, for example, the display device 100 may include curved surface portions formed at its left and right distal ends and having a constant or variable curvature. Additionally, the display device 100 may be flexibly shaped as curved, bent, folded, or rolled up.

[0065] like Figure 1 , Figure 2 and Figure 3 As shown, the display device 100 includes a substrate 110.

[0066] The substrate 110 may include a main region MA corresponding to the display surface of the display device 100 and a sub-region SBA protruding from one side of the main region MA.

[0067] like Figure 2 As shown, the main area MA may include a display area DA located in the center and a non-display area NDA located around the display area DA.

[0068] The display area DA can be formed in a quadrilateral plane (e.g., a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1). The corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be rounded to have a predetermined curvature, or it can be formed at a right angle. The planar shape of the display area DA is not limited to a quadrilateral shape, and the display area DA can be formed in other polygonal shapes, circular shapes, or elliptical shapes.

[0069] The non-display area NDA can be set at the edge of the main area MA to surround the display area DA.

[0070] The subregion SBA can be a part of the side of the main region MA that extends in the first direction DR1 and extends in the second direction DR2.

[0071] Subregion SBA can include curved regions that are deformed into curved shapes. Figure 8 BA).

[0072] Figure 2 and Figure 3 A curved portion of the sub-region SBA is shown in the display device 100.

[0073] like Figure 3 As shown, the sub-region SBA may include a curved region BA deformed into a curved shape (see reference). Figure 8 The first sub-region SB1 is located between one side of the main region MA and one side of the curved region BA (refer to...). Figure 8 ) and the second sub-region SB2 extending from the opposite side of the curved region BA (see reference) Figure 8 ).

[0074] When the curved region BA is deformed into a curved shape, the second sub-region SB2 can be disposed on the rear surface of the display device 100 and can be superimposed on the main region MA.

[0075] A display driver circuit 200 configured as an integrated circuit chip (“IC”) may be configured (e.g., mounted) in the second sub-region SB2.

[0076] Circuit board 300 can be attached to one side of the second sub-region SB2.

[0077] The touch driver circuit 400, configured as an integrated circuit chip (“IC”), can be set (e.g., mounted) on the circuit board 300.

[0078] Reference Figure 3 The display device 100 in the embodiment includes a substrate 110, a circuit layer 120 disposed on the substrate 110, and a component layer 130 disposed on the circuit layer 120.

[0079] The display device 100 in the embodiment may further include a sealing layer 140 disposed on the component layer 130 and a touch sensor layer 150 disposed on the sealing layer 140.

[0080] Additionally, the display device 100 in the embodiment may also include a polarization layer 160 disposed on the touch sensor layer 150 to reduce the reflection of external light.

[0081] The substrate 110 may include or be composed of an insulating material such as a polymeric resin. In embodiments, for example, the substrate 110 may include or be composed of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, and rolled up.

[0082] In an alternative embodiment, the substrate 110 may include or be composed of an insulating material such as glass.

[0083] The substrate 110 may include a main region MA and a sub-region SBA. The main region MA may include a display region DA and a non-display region NDA.

[0084] Component layer 130 may include components disposed in light-emitting areas ( Figure 4 The light-emitting element in EA) Figure 5 and Figure 6 (LE in the middle).

[0085] Circuit layer 120 may include light-emitting pixel drivers that are electrically connected to light-emitting elements LE of element layer 130. Figure 4 EPD in the middle).

[0086] The sealing layer 140 is disposed on the element layer 130 and may have a structure in which at least one organic membrane is disposed between two or more inorganic membranes.

[0087] The touch sensor layer 150 may include touch electrodes for detecting signals that change according to the touch of a person or object and for sensing the point in the main area MA where the touch of a person or object occurs.

[0088] The polarization layer 160 is used to prevent image visibility degradation due to reflection of external light by blocking external light reflected from the touch sensor layer 150, sealing layer 140, component layer 130 and circuit layer 120 and the interface therebetween.

[0089] In an embodiment, the display device 100 may further include a display driver circuit 200 configured as an integrated circuit chip (“IC”) and disposed (e.g., mounted) in a sub-region SBA of the substrate 110.

[0090] The display driver circuit 200 can transmit data signals ( Figure 5 The Vdata in the circuit layer 120 is supplied to the data line (Vdata). Figure 5 and Figure 6 (DL in the text).

[0091] In an embodiment, the display device 100 may further include a circuit board 300 bonded to a sub-region SBA of the substrate 110. The circuit board 300 may be bonded to a pad (or "soldering pad") disposed in the sub-region SBA of the substrate 110 using a low-resistance, high-reliability material such as anisotropic conductive film or sintered silver adhesive paste ("SAP").

[0092] The touch driver circuit 400 can be set (e.g., mounted) on the circuit board 300.

[0093] When the touch sensor layer 150 includes capacitive touch electrodes and sensing electrodes, the touch driving circuit 400 can sense a touch based on whether the capacitance changes. However, this is only one embodiment. Figure 3 The touch sensor layer 150 and touch driving circuit 400 can be configured using touch sensing methods other than capacitive methods.

[0094] Figure 4 It is shown Figure 2 Plan view of part B.

[0095] Reference Figure 4 In this embodiment, the display area DA of the display device 100 may include a light-emitting area EA. Additionally, the display area DA may also include a non-light-emitting area disposed in the intervals between the light-emitting areas EA.

[0096] The light-emitting pixel drivers EPDs, each corresponding to the light-emitting area EA, can be arranged in the display area DA so that they are parallel to each other in the first direction DR1 and the second direction DR2. The light-emitting pixel drivers EPDs can be electrically connected to the light-emitting elements (LEDs) of the element layer 130, which are all disposed in the light-emitting area EA. Figure 5 and Figure 6 (LE in the middle).

[0097] The light-emitting region EA can have a rhomboid planar shape or a quadrilateral (e.g., rectangular) planar shape. However, this is merely an illustrative embodiment, and the planar shape of the light-emitting region EA in the embodiment is not limited to this. Figure 4 The planar shape shown. That is, the luminous area EA can have a polygonal planar shape such as a square, pentagon or hexagon, or a circular or elliptical planar shape including curved edges.

[0098] The light-emitting region EA may include a first light-emitting region EA1 that emits light in a first wavelength band, a second light-emitting region EA2 that emits light in a second wavelength band lower than the first wavelength band, and a third light-emitting region EA3 that emits light in a third wavelength band lower than the second wavelength band.

[0099] In an embodiment, the first band may correspond to red and may be, for example, from about 600 nanometers (nm) to about 750 nm. The second band may correspond to green and may be from about 480 nm to about 560 nm. The third band may correspond to blue and may be from about 370 nm to about 460 nm.

[0100] The first light-emitting area EA1 and the third light-emitting area EA3 can be arranged alternately in the first direction DR1 or the second direction DR2.

[0101] The second light-emitting region EA2 can be arranged to be parallel to each other in the first direction DR1 or the second direction DR2.

[0102] In addition, the second light-emitting region EA2 can be adjacent to the first light-emitting region EA1 and the third light-emitting region EA3 on the diagonal directions DR4 and DR5 that intersect the first direction DR1 and the second direction DR2.

[0103] The pixels PX that display each brightness and color can be provided by the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 that are adjacent to each other in the light-emitting area EA.

[0104] In other words, a pixel (PX) can be the basic unit for displaying various colors, including white, at a predetermined brightness.

[0105] Each pixel PX may include at least one first light-emitting region EA1, at least one second light-emitting region EA2, and at least one third light-emitting region EA3 that are adjacent to each other. Therefore, each pixel PX can display various colors by mixing the light emitted from the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 that are adjacent to each other.

[0106] Figure 5 It is shown Figure 4 An equivalent circuit diagram of an embodiment of a light-emitting pixel driver.

[0107] Reference Figure 5 Circuit layer ( Figure 3 120 in the formula may include a first power line VDL that transmits a first power ELVDD to the light-emitting pixel driver EPD, a second power line that transmits a second power ELVSS to the light-emitting element LE, a reference voltage line VRL that transmits a reference voltage VREF to the light-emitting pixel driver EPD, and an initialization voltage line VAIL that transmits an initialization voltage VAINT.

[0108] Component layer ( Figure 3 The light-emitting element LE of (130) can be electrically connected between the light-emitting pixel driver EPD and the second power line.

[0109] In other words, one of the light-emitting elements LE can be electrically connected between one of the light-emitting pixel drivers EPD in circuit layer 120 and the second power line.

[0110] The second power supply, ELVSS, can have a lower voltage level than the first power supply, ELVDD.

[0111] In other words, the anode electrode of the light-emitting element LE can be electrically connected to the light-emitting pixel driver EPD, and a second power ELVSS with a voltage level lower than the first power ELVDD can be applied to the cathode electrode of the light-emitting element LE.

[0112] The capacitor Cel connected in parallel with the light-emitting element LE represents the parasitic capacitance between the anode and cathode electrodes.

[0113] The circuit layer 120 may include a scan write line GWL for transmitting a scan write signal GW, a reset control line GRL for transmitting a reset control signal GR, a bias control line GBL for transmitting a bias control signal GB, a first transmit control line ECL1 for transmitting a first transmit control signal EC1, and a second transmit control line ECL2 for transmitting a second transmit control signal EC2.

[0114] A light-emitting pixel driver EPD of circuit layer 120 may include a first transistor T1 that generates a drive current for driving the light-emitting element LE, two or more transistors T2 to T6 electrically connected to the first transistor T1, and one or more capacitors C1 and C2.

[0115] The second transistor T2 can be electrically connected between the gate electrode of the first transistor T1 and the data line DL.

[0116] The second transistor T2 can be turned on by the scan write signal GW of the scan write line GWL.

[0117] When the second transistor T2 is turned on, the data signal Vdata of the data line DL can be transmitted to the gate electrode of the first transistor T1.

[0118] When the data signal Vdata applied to the gate electrode of the first transistor T1 causes the voltage difference between the gate electrode and the second electrode of the first transistor T1 to be equal to or greater than the threshold voltage of the first transistor T1, the first transistor T1 can be turned on. Therefore, a drain-source current of the first transistor T1 corresponding to the magnitude of the data signal Vdata can be generated.

[0119] The third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the reference voltage line VRL.

[0120] The third transistor T3 can be turned on by the reset control signal GR of the reset control line GRL.

[0121] When the third transistor T3 is turned on, the potential of the gate electrode of the first transistor T1 can be reset to the reference voltage VREF of the reference voltage line VRL.

[0122] The fourth transistor T4 can be electrically connected between the light-emitting element LE and the initialization voltage line VAIL.

[0123] The fourth transistor T4 can be turned on by the bias control signal GB of the bias control line GBL.

[0124] When the fourth transistor T4 is turned on, the potential of the anode electrode of the light-emitting element LE can be initialized to the initial voltage VAINT of the initial voltage line VAIL.

[0125] The fifth transistor T5 can be electrically connected between the first electrode of the first transistor T1 and the first electric field line VDL.

[0126] The fifth transistor T5 can be turned on by the first transmit control signal EC1 of the first transmit control line ECL1.

[0127] When the fifth transistor T5 is turned on, the first power ELVDD of the first power line VDL can be transmitted to the first electrode of the first transistor T1.

[0128] The sixth transistor T6 can be electrically connected between the second electrode of the first transistor T1 and the light-emitting element LE.

[0129] The sixth transistor T6 can be turned on by the second emit control signal EC2 of the second emit control line ECL2.

[0130] When the sixth transistor T6 is turned on, the drain-source current of the first transistor T1, which is of the same magnitude as the data signal Vdata, can be transmitted to the light-emitting element LE through the sixth transistor T6.

[0131] As a result, the light-emitting element LE can emit light with a brightness corresponding to the data signal Vdata.

[0132] The first capacitor C1 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0133] Therefore, the first capacitor C1 can be charged with the data signal Vdata applied to the gate electrode of the first transistor T1, and due to the voltage charged to the first capacitor C1, the first transistor T1 can be kept on for a predetermined period of time.

[0134] The second capacitor C2 can be electrically connected between the second electrode of the first transistor T1 and the first power line VDL.

[0135] The voltage of the first capacitor C1 corresponds to the potential difference between the gate electrode and the second electrode of the first transistor T1, can be changed by the data signal Vdata, and can be divided by the second capacitor C2. Therefore, the threshold voltage of the first transistor T1 can be compensated.

[0136] In an embodiment, the first transistor T1 may include a gate electrode and a gate supplement electrode on opposite sides of the channel portion.

[0137] The gate electrode of the first transistor T1 can be electrically connected to the second transistor T2.

[0138] The gate electrode of the first transistor T1 can be electrically connected to the second electrode of the first transistor T1.

[0139] Therefore, when the first transistor T1 is turned on by applying the data signal Vdata to the gate electrode, another part of the channel portion of the first transistor T1 adjacent to the gate electrode may not be activated, compared to a part of the channel portion of the first transistor T1 adjacent to the gate electrode.

[0140] Therefore, since the electron mobility in the channel portion of the first transistor T1 decreases, the slope of the current curve representing the relationship between the gate voltage and the source-drain current of the first transistor T1 can become flatter. Thus, since the driving voltage range of the first transistor T1 can be widened, the ease of brightness control can be improved.

[0141] like Figure 5 As shown, the first transistor T1 can be an N-type metal-oxide-semiconductor field-effect transistor (“MOSFET”). Additionally, at least some of the second transistors T2 through the sixth transistor T6 can be P-type MOSFETs. In an embodiment, the fifth transistor T5 and the sixth transistor T6 can be P-type MOSFETs, and the second transistor T2, the third transistor T3, and the fourth transistor T4 can be N-type MOSFETs.

[0142] Therefore, in an embodiment, circuit layer 120 may include a first semiconductor layer for fabricating a P-type MOSFET. Figure 6 CH6, E16, and E26 in the middle) and the second semiconductor layer used to fabricate the N-type MOSFET ( Figure 6 CH1, E11, E21, CH2, E12, and E22 (in the following).

[0143] Figure 6 It is shown Figure 5A cross-sectional view of the first transistor, the second transistor, the sixth transistor, the first capacitor, the second capacitor, and the light-emitting element.

[0144] Reference Figure 6 The display device 100 in the embodiment includes a substrate 110, a circuit layer 120 on the substrate 110, and a component layer 130 on the circuit layer 120.

[0145] The display device 100 may also include a sealing layer 140 on the component layer 130.

[0146] In an embodiment, circuit layer 120 may include a first semiconductor layer SEL1 disposed on substrate 110, a first gate insulating layer 122 covering the first semiconductor layer SEL1, a first gate conductive layer GCDL1 disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer GCDL1, a second gate conductive layer GCDL2 disposed on the second gate insulating layer 123, a first intermediate insulating layer 124 covering the second gate conductive layer GCDL2, and a second semiconductor layer SEL2 disposed on the first intermediate insulating layer 124. The third gate insulating layer 125 covering the second semiconductor layer SEL2, the third gate conductive layer GCDL3 disposed on the third gate insulating layer 125, the second intermediate insulating layer 126 covering the third gate conductive layer GCDL3, the first source-drain conductive layer SDCDL1 disposed on the second intermediate insulating layer 126, the first planarization layer 127 covering the first source-drain conductive layer SDCDL1, the second source-drain conductive layer SDCDL2 disposed on the first planarization layer 127, and the second planarization layer 128 covering the second source-drain conductive layer SDCDL2.

[0147] In an embodiment, circuit layer 120 may further include a buffer layer 121 covering substrate 110. In this case, first semiconductor layer SEL1 may be disposed on buffer layer 121.

[0148] As shown above (refer to the reference) Figure 5 As described, the light-emitting pixel driver EPD may include a first transistor T1 and two or more transistors T2 to T6 electrically connected to the first transistor T1.

[0149] The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be N-type MOSFETs, and the fifth transistor T5 and the sixth transistor T6 can be P-type MOSFETs.

[0150] The fifth transistor T5 and the sixth transistor T6, configured as P-type MOSFETs, may include a channel portion disposed in the first semiconductor layer SEL1. Figure 12 CH5 and CH6 in the first electrode ( Figure 12 E15 and E16 in the middle) and the second electrode ( Figure 12 E25 and E26 in the first gate conductive layer GCDL1 and the gate electrode disposed in the first gate conductive layer and stacked with the channel portions CH5 and CH6 ( Figure 13 (G5 and G6 in the middle).

[0151] In an embodiment, the first semiconductor layer SEL1 may include a silicon semiconductor material such as polycrystalline silicon or amorphous silicon.

[0152] In other words, the sixth transistor T6 may include a channel portion CH6 disposed in the first semiconductor layer SEL1, a first electrode E16 disposed in the first semiconductor layer SEL1 and connected to one side of the channel portion CH6, a second electrode E26 disposed in the first semiconductor layer SEL1 and connected to the opposite side of the channel portion CH6, and a gate electrode G6 disposed in the first gate conductive layer GCDL1 and superimposed on the channel portion CH6.

[0153] Since the fifth transistor T5 is the same P-type MOSFET as the sixth transistor T6, redundant descriptions will be omitted below.

[0154] The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4, configured as N-type MOSFETs, may include a channel portion disposed in the second semiconductor layer SEL2. Figure 12 CH1, CH2, CH3 and CH4 in the first electrode ( Figure 12 E11, E12, E13 and E14 in the middle) and the second electrode ( Figure 12 E21, E22, E23, and E24 in the third gate conductive layer GCDL3 and the gate electrode disposed in the third gate conductive layer and stacked with the channel portions CH1, CH2, CH3, and CH4. Figure 14 G1 and G4 in Figure 17 (G2 and G3 in the middle).

[0155] In an embodiment, the second semiconductor layer SEL2 may include an oxide semiconductor material.

[0156] That is, the first transistor T1 may include a channel portion CH1 disposed in the second semiconductor layer SEL2, a first electrode E11 disposed in the second semiconductor layer SEL2 and connected to one side of the channel portion CH1, a second electrode E21 disposed in the second semiconductor layer SEL2 and connected to the opposite side of the channel portion CH1, and a gate electrode G1 disposed in the third gate conductive layer GCDL3 and superimposed on the channel portion CH1.

[0157] The upper surface of the channel portion CH1 of the first transistor T1 can face the gate electrode G1.

[0158] In addition, the lower surface of the channel portion CH1 of the first transistor T1 can face the second capacitor electrode CAE2, which is electrically connected to the second electrode E21 of the first transistor T1.

[0159] In other words, the second capacitor electrode CAE2 can be an additional electrode of the gate of the first transistor T1.

[0160] The second transistor T2 may include a channel portion CH2 disposed in the second semiconductor layer SEL2, a first electrode E12 disposed in the second semiconductor layer SEL2 and connected to one side of the channel portion CH2, a second electrode E22 disposed in the second semiconductor layer SEL2 and connected to the opposite side of the channel portion CH2, and a gate electrode G2 disposed in the third gate conductive layer GCDL3 and stacked with the channel portion CH2.

[0161] The first electrode E12 of the second transistor T2 can be electrically connected to the data line DL via the data connection electrode DCE.

[0162] The data connection electrode DCE can be disposed on the second intermediate insulating layer 126 in the first source-drain conductive layer SDCDL1, and can be electrically connected to the first electrode E12 of the second transistor T2 through the data connection hole DCH.

[0163] The data connection hole DCH can penetrate the second intermediate insulating layer 126 and the third gate insulating layer 125.

[0164] The data line DL can be disposed on the first planarization layer 127 in the second source-drain conductive layer SDCDL2, and can be electrically connected to the data connection electrode DCE through the data attachment connection hole DCAH that penetrates the first planarization layer 127.

[0165] The second electrode E22 of the second transistor T2 can be electrically connected to the gate electrode G1 of the first transistor T1 through the first node connection electrode NCE1.

[0166] The first node connecting electrode NCE1 can be disposed on the second intermediate insulating layer 126 within the first source-drain conductive layer SDCDL1.

[0167] The first node connection electrode NCE1 can be electrically connected to the gate electrode G1 of the first transistor T1 through the first node connection hole NCH1, can be electrically connected to the first capacitor electrode CAE1 through the second node connection hole NCH2, and can be electrically connected to the second electrode E22 of the second transistor T2 through the third node connection hole NCH3.

[0168] The first capacitor electrode CAE1 can be disposed on the first gate insulating layer 122 within the first gate conductive layer GCDL1.

[0169] The second electrode E21 of the first transistor T1 can be electrically connected to the first electrode E16 of the sixth transistor T6 through the second node connection electrode NCE2.

[0170] The second node connecting electrode NCE2 can be disposed on the second intermediate insulating layer 126 within the first source-drain conductive layer SDCDL1.

[0171] The second node connection electrode NCE2 can be electrically connected to the second electrode E21 of the first transistor T1 through the fourth node connection hole NCH4, can be electrically connected to the second capacitor electrode CAE2 through the fifth node connection hole NCH5, and can be electrically connected to the first electrode E16 of the sixth transistor T6 through the sixth node connection hole NCH6.

[0172] The second capacitor electrode CAE2 can be disposed on the second gate insulating layer 123 within the second gate conductive layer GCDL2.

[0173] Since the first capacitor electrode CAE1 is electrically connected to the gate electrode G1 of the first transistor T1 and the second capacitor electrode CAE2 is electrically connected to the second electrode E21 of the first transistor T1, the first capacitor C1 can be provided by the region where the first capacitor electrode CAE1 and the second capacitor electrode CAE2 are superimposed on each other.

[0174] A portion of the first electric field line VDL can be disposed on the first planarization layer 127 within the second source-drain conductive layer SDCDL2.

[0175] In order to apply the first power line ELVDD with a relatively uniform resistance throughout the display area DA, the first power line VDL can be set as a mesh line in the display area DA.

[0176] In other words, the first power line VDL may include a first main power line disposed in the third gate conductive layer GCDL3 and extending in the first direction DR1. Figure 15 VDMNL) and the first power sub-line disposed in the second source-drain conductive layer SDCDL2 and extending in the second direction DR2 ( Figure 16 VDSBL in (the text is incomplete and cannot be translated).

[0177] Each of the light-emitting pixel drivers EPD in circuit layer 120 may also include a third capacitor electrode CAE3, which is disposed in the first gate conductive layer GCDL1, separated from the first capacitor electrode CAE1, and electrically connected to the first power line VDL.

[0178] The second capacitor electrode CAE2 can be stacked with the first capacitor electrode CAE1 and the third capacitor electrode CAE3.

[0179] In addition, the electrode extension E16' protruding from the first electrode E16 of the sixth transistor T6 can be stacked with the first capacitor electrode CAE1 and the third capacitor electrode CAE3.

[0180] Therefore, the first capacitor C1 can also be provided by the area where the electrode extension E16' and the first capacitor electrode CAE1 overlap each other.

[0181] Additionally, the second capacitor C2 can be provided by each of the second capacitor electrode CAE2 and the electrode extension E16', which overlap with the third capacitor electrode CAE3.

[0182] The second electrode E26 of the sixth transistor T6 can be electrically connected to the anode electrode 131 of the light-emitting element LE through the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2.

[0183] The first anode connection electrode ANCE1 can be disposed on the second intermediate insulating layer 126 in the first source-drain conductive layer SDCDL1, and can be electrically connected to the second electrode E26 of the sixth transistor T6 through the first anode contact hole ANCH1.

[0184] The first anode contact hole ANCH1 can penetrate the second intermediate insulating layer 126, the third gate insulating layer 125, the first intermediate insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0185] The second anode connection electrode ANCE2 can be disposed on the first planarization layer 127 in the second source-drain conductive layer SDCDL2, and can be electrically connected to the first anode connection electrode ANCE1 through the second anode contact hole ANCH2 penetrating the first planarization layer 127.

[0186] The anode electrode 131 can be disposed on the second planarization layer 128 and can be electrically connected to the second anode connection electrode ANCE2 through the third anode contact hole ANCH3 penetrating the second planarization layer 128.

[0187] The component layer 130 can be disposed on the circuit layer 120 and can include light-emitting elements LE corresponding to the light-emitting regions EA respectively.

[0188] Each of the light-emitting elements LE may include an anode electrode 131 and a cathode electrode 134 facing each other, and a light-emitting layer 133 disposed therebetween.

[0189] In other words, the element layer 130 may include an anode electrode 131 disposed in the light-emitting region EA, a pixel limiting layer 132 disposed in the non-light-emitting region and covering the edge of the anode electrode 131, a light-emitting layer 133 disposed on the anode electrode 131, and a cathode electrode 134 disposed on the light-emitting layer 133 and the pixel limiting layer 132.

[0190] The pixel defining layer 132 may include a first pixel defining layer 1321 disposed on the second planarization layer 128, a second pixel defining layer 1322 disposed on the first pixel defining layer 1321, and a spacer layer 1323 disposed on a portion of the second pixel defining layer 1322.

[0191] In an embodiment, the first pixel defining layer 1321 may include a light-absorbing insulating material that absorbs light or a light-blocking insulating material that blocks light.

[0192] In an optional embodiment, each of the light-emitting elements LE may further include a first common layer disposed between the anode electrode 131 and the light-emitting layer 133 and a second common layer disposed between the light-emitting layer 133 and the cathode electrode 134.

[0193] Anode electrode 131 can be disposed in each of the light-emitting regions EA and can be electrically connected to a light-emitting pixel driver EPD of circuit layer 120. This anode electrode 131 can also be referred to as a pixel electrode.

[0194] The light-emitting layer 133 may include an organic light-emitting material that converts electron-hole pairs into light.

[0195] Cathode electrode 134 can be disposed in display area DA, including light-emitting area EA. Second power ( Figure 5 The ELVSS in the cathode electrode 134 can be applied together. Such a cathode electrode 134 can also be referred to as a common electrode.

[0196] The sealing layer 140 can be disposed on the circuit layer 120 and cover the component layer 130.

[0197] In an embodiment, the sealing layer 140 may include a first sealing layer, a second sealing layer, and a third sealing layer. The first sealing layer is disposed on the element layer 130 and includes or is composed of an inorganic insulating material. The second sealing layer is disposed on the first sealing layer, stacked with the element layer 130, and includes or is composed of an organic insulating material. The third sealing layer is disposed on the second sealing layer, covers the second sealing layer, and includes or is composed of an inorganic insulating material.

[0198] Figure 7 It is shown Figure 3 A plan view of an embodiment of the substrate.

[0199] Reference Figure 7 The substrate 110 of the display device 100 in the embodiment may include a main region MA corresponding to the display surface and a sub-region SBA protruding from a portion of one side of the main region MA.

[0200] The main area MA includes the display area DA located in the center and the non-display area NDA located at the edge and surrounding the display area DA.

[0201] The display area DA may include a bypass area BYA located on the side adjacent to (adjacent to) the sub-area SBA, and a general area GA located in the remaining areas excluding the bypass area BYA.

[0202] The bypass region BYA may include a bypass intermediate region BMA located at the center of the first direction DR1, a first bypass side region BSA1 parallel to the bypass intermediate region BMA and in contact with the non-display region NDA in the first direction DR1, and a second bypass side region BSA2 located between the bypass intermediate region BMA and the first bypass side region BSA1.

[0203] Compared to the intermediate bypass region BMA and the second bypass side region BSA2, the first bypass side region BSA1 may be adjacent to the curved edge of the base 110.

[0204] The first bypass side region BSA1 and the second bypass side region BSA2 can be set between each side of the bypass middle region BMA in the first direction DR1 and the non-display region NDA.

[0205] The general area GA may include a general intermediate area GMA extending from the bypass intermediate area BMA to the bypass area BYA in the second direction DR2, a first general side area GSA1 extending from the first bypass side area BSA1 to the bypass area BYA in the second direction DR2, and a second general side area GSA2 extending from the second bypass side area BSA2 to the bypass area BYA in the second direction DR2.

[0206] The non-display area NDA may include the gate drive circuit area GDRA, which is provided with gate drive circuitry.

[0207] The gate drive circuit region GDRA can be located in the non-display area NDA on the side extending in the second direction DR2 opposite to the display area DA. However, this is only one embodiment, and the gate drive circuit region GDRA can be located separately in the display area DA instead of the non-display area NDA.

[0208] The gate drive circuit in the gate drive circuit region (GDRA) can sequentially transmit gate signals to the gate lines. Here, the gate lines may include transmission scan write signals (…). Figure 5 The scan write line of GW in ( Figure 5 GWL in the middle), transmit reset control signal ( Figure 5 The reset control line of GR in ( Figure 5 GRL in the middle), transmission bias control signal ( Figure 5 The bias control line of GB in ( Figure 5 GBL in the middle), transmit the first transmit control signal ( Figure 5 The first launch control line of EC1 in the middle ( Figure 5 ECL1 in the middle) and the transmission of the second transmit control signal ( Figure 5 The second launch control line of EC2 (in the middle) Figure 5 (ECL2 in the middle).

[0209] The sub-region SBA may include a curved region BA that is deformed into a curved shape, a first sub-region SB1 disposed between one side of the curved region BA and the main region MA, and a second sub-region SB2 connected to the opposite side of the curved region BA.

[0210] When the curved region BA deforms into a curved shape, the second sub-region SB2 is positioned below the base 110 and superimposed on the main region MA.

[0211] The display driver circuit 200 can be set in the second sub-region SB2.

[0212] Joined to the circuit board ( Figure 3 The signal pad SPD (300) in the middle can be placed at one edge of the second sub-region SB2.

[0213] Figure 8 It is shown Figure 7 A plan view of an embodiment of the circuit layer of part D. Figure 9 It is shown Figure 7 A partial plan view of the circuit layer of E. Figure 10 It is shown Figure 8 A plan view of an embodiment of part F. Figure 11 It is shown Figure 8 A plan view of an embodiment of part G.

[0214] Reference Figure 8 and Figure 9 The circuit layer of the display device 100 in the embodiment ( Figure 3 120 in the text may include electrical connections to the component layer ( Figure 3 The light-emitting element (130) in the middle Figure 5The LE in the middle) and the light-emitting pixel driver EPD arranged parallel to each other in the first direction DR1 and the second direction DR2, extending in the second direction DR2 and transmitting data signals ( Figure 5 The data line DL (Vdata) is transmitted to the light-emitting pixel driver EPD, the first auxiliary line ASL1 extends in the first direction DR1, and the second auxiliary line ASL2 extends in the second direction DR2 and is adjacent to the data line DL.

[0215] The first auxiliary line ASL1 may include a first bypass auxiliary line BASL1 electrically connected to the first data line DL1 in the first direction DR1 and adjacent to the non-display area NDA, and the remaining first transmission auxiliary lines TASL1 other than the first bypass auxiliary line BASL1.

[0216] The second auxiliary line ASL2 may include a second bypass auxiliary line BASL2 electrically connected to the first bypass auxiliary line BASL1, and the remaining second transmission auxiliary line TASL2 other than the second bypass auxiliary line BASL2.

[0217] The second bypass auxiliary line BASL2 can be adjacent to the second data line DL2 in the data line DL, which is farther apart from the first data line DL1 and the non-display area NDA in the first direction DR1.

[0218] The first data line DL1 can be set in the first bypass side area BSA1.

[0219] The second data line DL2 and the second bypass auxiliary line BASL2 can be set in the second bypass side area BSA2.

[0220] The first bypass auxiliary line BASL1 can be set in the first bypass side area BSA1 and the second bypass side area BSA2.

[0221] like Figure 8 As shown in the embodiment, the circuit layer 120 may further include a data supply line DSPL disposed in the non-display area NDA and electrically connected between the display driving circuit 200 and the data line DL.

[0222] The data supply line DSPL can extend to the bypass middle area BMA and the second bypass side area BSA2.

[0223] The data supply line DSPL may include a first data supply line DSPL1 that transmits data signals of a first data line DL1 and a second data supply line DSPL2 that transmits data signals of a second data line DL2.

[0224] The first data supply line DSPL1 can extend to the second bypass auxiliary line BASL2 of the second bypass side region BSA2, and can be electrically connected to the first data line DL1 through the second bypass auxiliary line BASL2 and the first bypass auxiliary line BASL1.

[0225] The second data supply line DSPL2 can extend to the second bypass side area BSA2 and be directly electrically connected to the second data line DL2.

[0226] In this way, since the first data supply line DSPL1 extends to the second bypass auxiliary line BASL2 of the second bypass side region BSA2, instead of the first data line DL1 extending to the first bypass side region BSA1, the extension length of the first data supply line DSPL1 can be shortened. As a result, the width of the area required to arrange the data supply line DSPL can be reduced, and therefore the width of the non-display area NDA can be reduced.

[0227] In addition, since the data supply line DSPL is not located in some areas adjacent to the curved edge of the substrate 110 in the non-display area NDA, the width of the non-display area NDA can be further reduced.

[0228] The data line DL may also include a third data line DL3 disposed in the bypass intermediate region BMA. Additionally, the data supply line DSPL may also include a third data supply line DSPL3 that transmits the data signal of the third data line DL3.

[0229] The third data supply line DSPL3 can be extended to the bypass intermediate area BMA and can be directly electrically connected to the third data line DL3.

[0230] The first bypass auxiliary line BASL1 can be set between the first data line DL1 and the second bypass auxiliary line BASL2.

[0231] The second bypass auxiliary line BASL2 can be set in the non-display area NDA between the first data supply line DSPL1 and the first bypass auxiliary line BASL1.

[0232] In this way, since the first bypass auxiliary line BASL1 and the second bypass auxiliary line BASL2 are specifically set in the bypass area BYA, and the ends of the first bypass auxiliary line BASL1 and the ends of the second bypass auxiliary line BASL2 are set in the display area DA, the visibility of the first bypass auxiliary line BASL1 and the second bypass auxiliary line BASL2 is improved.

[0233] To prevent this situation, the first auxiliary line ASL1 may include a first transmission auxiliary line TASL1 in addition to the first bypass auxiliary line BASL1. Similarly, the second auxiliary line ASL2 may include a second transmission auxiliary line TASL2 in addition to the second bypass auxiliary line BASL2.

[0234] Two of the first transmission auxiliary lines TASL1 can extend from opposite ends of the first bypass auxiliary line BASL1 to the non-display area NDA.

[0235] One of the second transmission auxiliary lines TASL2 can extend from one end of the second bypass auxiliary line BASL2 into the non-display area NDA in a direction away from the sub-region SBA.

[0236] Since the second bypass auxiliary line BASL2 is only set in the second bypass side area BSA2, each of the first data line DL1 in the first bypass side area BSA1 and the third data line DL3 in the bypass middle area BMA can be completely adjacent to the second transmission auxiliary line TASL2.

[0237] In an embodiment, each of the first transmission auxiliary line TASL1 and the second transmission auxiliary line TASL2 can be electrically connected to transmit the first power ( Figure 5 The first power line of ELVDD (in the middle) Figure 5 VDL in the middle), transmitting the second power ( Figure 5 The second power line of ELVSS in the transmission initialization voltage ( Figure 5 The initial voltage line of VAINT in (in the text) Figure 5 VAIL in the middle) and transmission reference voltage ( Figure 5 The reference voltage line of VREF in ( Figure 5 One of the VRLs in the system. In this way, the resistance of the path for transmitting power or constant voltage can be reduced by using the first transmission auxiliary line TASL1 and the second transmission auxiliary line TASL2.

[0238] In an embodiment, circuit layer 120 may further include a first power line VDSPL and a second power line VSSPL disposed in the non-display area NDA and extending to the sub-area SBA.

[0239] The first power line VDSPL transmits the first power ( Figure 5 In the ELVDD), and the second power line VSSPL transmits the second power ( Figure 5 (ELVSS in the middle).

[0240] The first power line VDSPL can be electrically connected to the signal pad located in the second sub-region SB2. Figure 7 The SPD in the middle is used to transmit the first power ( Figure 5 The first power pad in ELVDD).

[0241] The second power line VSSPL can be electrically connected to the signal pad located in the second sub-area SB2. Figure 7 The SPD in the middle is used to transmit the second power ( Figure 5 The second power pad of ELVSS in the middle.

[0242] In an embodiment, at least some of the first transmission auxiliary lines TASL1 may be electrically connected to the second power line VSSPL.

[0243] Additionally, at least some of the second transmission auxiliary lines TASL2 can be electrically connected to at least some of the first transmission auxiliary lines TASL1 and electrically connected to the second power line VSSPL.

[0244] In an embodiment, circuit layer 120 may further include a first power ( Figure 5 The ELVDD in the light-emitting pixel driver is transmitted to the first power line VDL of the light-emitting pixel driver EPD.

[0245] The first power line VDL can extend in the second direction DR2 and be electrically connected to the first power line VDSPL.

[0246] The first power line VDL can be set between two second auxiliary lines ASL2 that are adjacent to each other along the first direction DR1.

[0247] In an embodiment, circuit layer 120 may further include a reference voltage ( Figure 5 The VREF in the light-emitting pixel driver is transmitted to the reference voltage line VRL of the light-emitting pixel driver EPD.

[0248] The reference voltage line VRL can be extended in the second direction DR2.

[0249] The reference voltage line VRL can be set between two data lines DL that are adjacent to each other along the first direction DR1.

[0250] like Figure 9 As shown, the first transmission auxiliary line TASL1 of the first auxiliary line ASL1 and the second transmission auxiliary line TASL2 of the second auxiliary line ASL2 can be set in the general area GA.

[0251] Each of the first transmission auxiliary lines TASL1 can be electrically connected to at least some of the second transmission auxiliary lines TASL2.

[0252] like Figure 8 and Figure 9As shown, in an embodiment, two of the first auxiliary lines ASL1 may be adjacent to the boundary between two light-emitting pixel drivers EPDs that are adjacent to each other on the first direction DR1.

[0253] like Figure 10 and Figure 11 As shown, the second source-drain conductive layer SDCDL2 may include a data line DL and a second auxiliary line ASL2.

[0254] The data line DL may include a first data line DL1 in the first bypass side region BSA1 and a second data line DL2 in the second bypass side region BSA2.

[0255] The second auxiliary line ASL2 may include a second bypass auxiliary line BASL2 for transmitting data signals from the first data line DL1, and the remaining second transmission auxiliary line TASL2 other than the second bypass auxiliary line BASL2.

[0256] The second bypass auxiliary line BASL2 can be adjacent to the second data line DL2.

[0257] The second source-drain conductive layer SDCDL2 may also include a portion of the first electric field line VDL.

[0258] The first source-drain conductive layer SDCDL1 may include a first auxiliary line ASL1.

[0259] The first auxiliary line ASL1 may include a first bypass auxiliary line BASL1 for transmitting the data signal of the first data line DL1, and the remaining first transmission auxiliary lines TASL1 other than the first bypass auxiliary line BASL1.

[0260] The first source-drain conductive layer SDCDL1 may also include a data connection electrode DCE superimposed on the protrusion of the data line DL and an auxiliary connection electrode ACE superimposed on the protrusion of the second auxiliary line ASL2.

[0261] The data connection electrode DCE and the auxiliary connection electrode ACE can be separated from the first auxiliary line ASL1.

[0262] The data connection electrode DCE, which is superimposed on one of the data lines DL, can be connected through each data attachment hole. Figure 6 The DCAH in the middle is electrically connected to a data line DL.

[0263] At least one auxiliary connection electrode ACE, which is superimposed on one of the second auxiliary lines ASL2, can be electrically connected to a second auxiliary line ASL2 through an auxiliary connection hole.

[0264] The first source-drain conductive layer SDCDL1 may also include a first direction DR1 that extends and transmits scan write signals. Figure 5 The scan write line GWL in GW).

[0265] like Figure 10 As shown, the first source-drain conductive layer SDCDL1 may further include a first auxiliary connection line ACL1, which extends from a first bypass auxiliary line BASL1 in the second direction DR2 and is connected to a data connection electrode DCE that is superimposed on a first data line DL1.

[0266] Therefore, a first data line DL1 can be electrically connected to a first bypass auxiliary line BASL1 via a first auxiliary connection line ACL1, a data connection electrode DCE, and a data additional connection hole DCAH.

[0267] The first source-drain conductive layer SDCDL1 may also include a second auxiliary connection line ACL2, which extends from a first bypass auxiliary line BASL1 in the second direction DR2 and connects to an auxiliary connection electrode ACE that is superimposed on a second bypass auxiliary line BASL2.

[0268] Therefore, a second bypass auxiliary line BASL2 can be electrically connected to a first bypass auxiliary line BASL1 via a second auxiliary connection line ACL2, an auxiliary connection electrode ACE, and an auxiliary connection hole.

[0269] In addition, such as Figure 10 and Figure 11 As shown in the embodiment, the third gate conductive layer GCDL3 may further include the gate electrode G2 of the second transistor T2 and the reset control line GRL.

[0270] The gate electrode G2 of the second transistor T2 can be electrically connected to the scan write line GWL disposed in the first source-drain conductive layer SDCDL1 through a connection hole.

[0271] Figure 12 It is shown Figure 4 A plan view of an embodiment of the first and second semiconductor layers of part C.

[0272] like Figure 12 As shown, in an embodiment, the circuit layer 120 may include a light-emitting pixel driver EPD arranged on a first direction DR1 and a second direction DR2, and a substrate ( Figure 6 The first semiconductor layer SEL1 on the 110) and one or more insulating layers disposed covering the first semiconductor layer SEL1 Figure 6The second semiconductor layer SEL2 is located on the first gate insulating layer 122, the second gate insulating layer 123 and the first intermediate insulating layer 124.

[0273] The light-emitting pixel driver EPD may include a first pixel driver (hereinafter also referred to as "first light-emitting pixel driver") EPD1 and a second pixel driver (hereinafter also referred to as "second light-emitting pixel driver") EPD2 that are adjacent to each other in the first direction DR1.

[0274] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the first light-emitting pixel driver EPD1 can be symmetrical with the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the second light-emitting pixel driver EPD2 based on the first boundary BDRY1 between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0275] The light-emitting pixel driver EPD may further include a third light-emitting pixel driver EPD3 that is adjacent to the second light-emitting pixel driver EPD2 in the first direction DR1, a fourth light-emitting pixel driver EPD4 that is adjacent to the first light-emitting pixel driver EPD1 in the second direction DR2, a fifth light-emitting pixel driver EPD5 that is adjacent to the second light-emitting pixel driver EPD2 in the second direction DR2, and a sixth light-emitting pixel driver EPD6 that is adjacent to the third light-emitting pixel driver EPD3 in the second direction DR2.

[0276] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the second light-emitting pixel driver EPD2 can be symmetrical with the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the third light-emitting pixel driver EPD3 based on the second boundary BDRY2 between the second light-emitting pixel driver EPD2 and the third light-emitting pixel driver EPD3.

[0277] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the first light-emitting pixel driver EPD1 can be symmetrical with the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the fourth light-emitting pixel driver EPD4 based on the third boundary BDRY3 between the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4.

[0278] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the second light-emitting pixel driver EPD2 can be symmetrical with the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the fifth light-emitting pixel driver EPD5 based on the extension line of the third boundary BDRY3.

[0279] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the third light-emitting pixel driver EPD3 can be symmetrical with the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the sixth light-emitting pixel driver EPD6 based on the extension line of the third boundary BDRY3.

[0280] Therefore, the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the fourth light-emitting pixel driver EPD4 can be symmetrical with the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the fifth light-emitting pixel driver EPD5 based on the extension line of the first boundary BDRY1.

[0281] In addition, the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the fifth light-emitting pixel driver EPD5 can be symmetrical with the first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the sixth light-emitting pixel driver EPD6 based on the extension line of the second boundary BDRY2.

[0282] The first semiconductor layer SEL1 may include the channel CH5 of the fifth transistor T5, the first electrode E15 and the second electrode E25, and the channel CH6 of the sixth transistor T6, the first electrode E16 and the second electrode E26.

[0283] The second semiconductor layer SEL2 may include the channel CH1, first electrode E11 and second electrode E21 of the first transistor T1, the channel CH2, first electrode E12 and second electrode E22 of the second transistor T2, the channel CH3, first electrode E13 and second electrode E23 of the third transistor T3, and the channel CH4, first electrode E14 and second electrode E24 of the fourth transistor T4.

[0284] The first electrode E11 of the first transistor T1 can be connected to one side of the channel CH1 of the first transistor T1, and can be adjacent to the first electrode E15 of the fifth transistor T5.

[0285] The second electrode E21 of the first transistor T1 can be connected to the opposite side of the channel CH1 of the first transistor T1, and can be adjacent to the first electrode E16 of the sixth transistor T6.

[0286] The second electrode E22 of the second transistor T2 can be connected to the second electrode E23 of the third transistor T3.

[0287] The second electrode E24 of the fourth transistor T4 can be adjacent to the second electrode E26 of the sixth transistor T6.

[0288] In the second light-emitting pixel driver EPD2 and the third light-emitting pixel driver EPD3, which are adjacent to each other along the first direction DR1, the fifth transistor T5 may include the first electrode E15 interconnected at the second boundary BDRY2.

[0289] Figure 13 It is shown Figure 12 A plan view of the first semiconductor layer, the first gate conductive layer and the second gate conductive layer of part H. Figure 14 It is shown Figure 12 A plan view of the second semiconductor layer and the third gate conductive layer of part H. Figure 15 It is shown Figure 12 A plan view of the first source-drain conductive layer of part H. Figure 16 It is shown Figure 12 A partial plan view of the second source-drain conductive layer of H.

[0290] Figure 13 , Figure 14 , Figure 15 and Figure 16 The diagram shows the portion of each of the first light-emitting pixel drivers EPD1, the second light-emitting pixel driver EPD2, the third light-emitting pixel driver EPD3, the fourth light-emitting pixel driver EPD4, the fifth light-emitting pixel driver EPD5, and the sixth light-emitting pixel driver EPD6 that is adjacent to the point where each of the second and third boundaries BDRY1 intersects with the third boundary BDRY3.

[0291] In an embodiment, circuit layer 120 may include a first shared line that is adjacent to (adjacent to) a first boundary BDRY1 between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 and extends in a second direction DR2. Figure 16 CMML1 in (the text is incomplete and cannot be translated).

[0292] The first shared line CMML1 can be electrically connected to the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, as well as the fourth light-emitting pixel driver EPD4 and the fifth light-emitting pixel driver EPD5, which are parallel to the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 in the second direction DR2.

[0293] In this embodiment, the first power is transmitted ( Figure 5 The first power line of ELVDD (in the middle) Figure 5 The VDL in the third gate conductive layer may include a layer disposed in the third gate conductive layer. Figure 14 In GCDL3) and the first power main line extending in the first direction DR1 ( Figure 14 VDMNL in the middle) and disposed in the second source and drain conductive layer ( Figure 16The first power sub-line (SDCDL2) in the second direction DR2 and extending therein ( Figure 16 VDSBL in (the text is incomplete and cannot be translated).

[0294] The first shared line CMML1 may include a first power sub-line superimposed on the first boundary BDRY1. Figure 16 VDSBL in (the text is incomplete and cannot be translated).

[0295] In an optional embodiment, circuit layer 120 may include an additional shared line that is adjacent to (adjacent to) the second boundary BDRY2 between the second light-emitting pixel driver EPD2 and the third light-emitting pixel driver EPD3 and extends in the second direction DR2. Figure 16 (in ACMML).

[0296] The additional shared line ACMML can be electrically connected to the second light-emitting pixel driver EPD2 and the third light-emitting pixel driver EPD3, as well as the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6, which are parallel to the second light-emitting pixel driver EPD2 and the third light-emitting pixel driver EPD3 in the second direction DR2.

[0297] In the embodiment, the transmission reference voltage ( Figure 5 The reference voltage line of VREF in ( Figure 5 The VRL in the second gate conductive layer may include a layer disposed in the second gate conductive layer. Figure 17 The reference voltage main line extending in the first direction DR1 in GCDL2) Figure 17 VRMNL in the middle) and disposed in the second source and drain conductive layer ( Figure 16 The reference voltage sub-line (SDCDL2) extending in the second direction DR2) Figure 16 VRSBL in (the context of VRSBL).

[0298] The additional shared line ACMML may include a reference voltage sub-line superimposed on the second boundary BDRY2. Figure 16 VRSBL in (the context of VRSBL).

[0299] In an embodiment, circuit layer 120 may include at least one second shared line that is adjacent to (adjacent to) the third boundary BDRY3 between the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4 and extends in the first direction DR1. Figure 14 CMML2 in (the text is incomplete and cannot be translated).

[0300] The second shared line CMML2 can be electrically connected to the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4, as well as the second light-emitting pixel driver EPD2, the third light-emitting pixel driver EPD3, the fifth light-emitting pixel driver EPD5, and the sixth light-emitting pixel driver EPD6, which are parallel to the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4 in the first direction DR1.

[0301] In an embodiment, at least one second shared line CMML2 may include a third gate conductive layer ( Figure 14 In GCDL3) and transmit bias control signals ( Figure 5 The bias control line of GB in ( Figure 14 GBL in the middle) and disposed in the first source and drain conductive layer ( Figure 15 In SDCDL1) and transmit the initialization voltage ( Figure 5 The initial voltage line of VAINT in (in the text) Figure 15 At least one of the VAIL in the table.

[0302] In the embodiment, when the bias control line GBL or the initialization voltage line ( Figure 15 When VAIL is at least one second shared line CMML2, the bias control line GBL or the initialization voltage line ( Figure 15 The VAIL in the middle can be overlaid with the third boundary BDRY3.

[0303] like Figure 13 As shown, the first semiconductor layer SEL1 may include the channel portion CH5 of the fifth transistor T5, the first electrode E15 and the second electrode E25, the channel portion CH6 of the sixth transistor T6, the first electrode E16 and the second electrode E26, and the electrode extension portion E16' extending from the first electrode E16 of the sixth transistor T6.

[0304] In an embodiment, the remaining portion of the first semiconductor layer SEL1, excluding the channel portion CH5 of the fifth transistor T5 and the channel portion CH6 of the sixth transistor T6, can be made conductive by performing a process of implanting dopant using a separate mask prior to the process of setting the first gate conductive layer GCDL1.

[0305] The first gate conductive layer GCDL1 may include a first emitter control line ECL1 extending in the first direction DR1 and intersecting with the channel portion CH5 of the fifth transistor T5, a second emitter control line ECL2 extending in the first direction DR1 and intersecting with the channel portion CH6 of the sixth transistor T6, and a first capacitor electrode CAE1 and a third capacitor electrode CAE3 separated from each other.

[0306] The gate electrode G5 of the fifth transistor T5 can be set as the part of the first emitter control line ECL1 that intersects with the channel CH5 of the fifth transistor T5.

[0307] The gate electrode G6 of the sixth transistor T6 can be set as the part of the second emitter control line ECL2 that intersects with the channel CH6 of the sixth transistor T6.

[0308] The first capacitor electrode CAE1 can be stacked with a portion of the electrode extension E16'.

[0309] The first capacitor electrode CAE1 can be electrically connected to the gate electrode G1 of the first transistor T1 through the first node connection electrode NCE1.

[0310] The third capacitor electrode CAE3 can be stacked with another part of the electrode extension E16'.

[0311] The third capacitor electrode CAE3 of the first light-emitting pixel driver EPD1 and the third capacitor electrode CAE3 of the second light-emitting pixel driver EPD2 can be connected to each other at the first boundary BDRY1.

[0312] The third capacitor electrode CAE3, which is disposed in the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 adjacent to each other along the first direction DR1, can be connected to each other at the first boundary BDRY1.

[0313] The second gate conductive layer GCDL2 may include a second capacitor electrode CAE2.

[0314] The second capacitor electrode CAE2 can be stacked with the first capacitor electrode CAE1 and the third capacitor electrode CAE3.

[0315] The second capacitor electrode CAE2 can be electrically connected to the second electrode E21 of the first transistor T1 through the second node connection electrode NCE2.

[0316] The second gate conductive layer GCDL2 may also include a first reference voltage connection electrode VRCE1.

[0317] The first reference voltage connection electrode VRCE1 can be parallel to the second boundary BDRY2 and can intersect with the extension of the third boundary BDRY3.

[0318] like Figure 14 As shown, the second semiconductor layer SEL2 may include the channel portion CH1, the first electrode E11 and the second electrode E21 of the first transistor T1, and the channel portion CH4, the first electrode E14 and the second electrode E24 of the fourth transistor T4.

[0319] The third gate conductive layer GCDL3 may include the gate electrode G1 of the first transistor T1, which is stacked with the channel portion CH1 of the first transistor T1, extends in the first direction DR1, and transmits the first power ( Figure 5 The first power main line VDMNL of the ELVDD) and the bias control signal extending on the first direction DR1 and transmitting the bias control signal ( Figure 5 The bias control line GBL in GB).

[0320] The first power main line VDMNL can be connected to the third capacitor electrode ( Figure 13 The CAE3 in the middle intersects with the third capacitor electrode CAE3 through the connecting hole.

[0321] In an embodiment, the bias control line GBL can be superimposed on the third boundary BDRY3.

[0322] Additionally, the bias control line GBL may include a protruding portion projecting from the opposite side in the second direction DR2. That is, the bias control line GBL may include a protruding portion superimposed on the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4, which are extensions of the contact third boundary BDRY3, and on the first direction DR1, a second light-emitting pixel driver EPD2, a third light-emitting pixel driver EPD3, a fifth light-emitting pixel driver EPD5, and a sixth light-emitting pixel driver EPD6, which are parallel to the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4.

[0323] Therefore, at least one second shared line CMML2 electrically connected to the first light-emitting pixel driver EPD1, the second light-emitting pixel driver EPD2, the third light-emitting pixel driver EPD3, the fourth light-emitting pixel driver EPD4, the fifth light-emitting pixel driver EPD5, and the sixth light-emitting pixel driver EPD6 may include a bias control line GBL.

[0324] The protruding portion of the bias control line GBL can be the gate electrode G4 of the fourth transistor T4, which is superimposed on the channel portion CH4 of the fourth transistor T4.

[0325] like Figure 15 As shown, the first source-drain conductive layer SDCDL1 may include a first power connection auxiliary electrode VDCE1, a second power connection auxiliary electrode VDCE2, a first anode connection electrode ANCE1, a second reference voltage connection electrode VRCE2, and an initialization voltage line VAIL.

[0326] The first power connection auxiliary electrode VDCE1 can be electrically connected to the third capacitor electrode. Figure 13 CAE3 in the middle) and the first power main line ( Figure 14 VDMNL in (the context of VDMNL).

[0327] As a result, the third capacitor electrode ( Figure 13 CAE3 in the first power connection can be electrically connected to the first power main line VDMNL via the first power connection auxiliary electrode VDCE1.

[0328] The first power connection auxiliary electrode VDCE1 of the second light-emitting pixel driver EPD2 and the first power connection auxiliary electrode VDCE1 of the third light-emitting pixel driver EPD3 can be connected to each other at the second boundary BDRY2.

[0329] The second power connection auxiliary electrode VDCE2 can be electrically connected to the first power main line VDMNL and the first electrode E15 of the fifth transistor T5.

[0330] As a result, the first electrode E15 of the fifth transistor T5 can be electrically connected to the first power main line VDMNL via the second power connection auxiliary electrode VDCE2.

[0331] The second power connection auxiliary electrode VDCE2 of the first light-emitting pixel driver EPD1 and the second power connection auxiliary electrode VDCE2 of the second light-emitting pixel driver EPD2 can be connected to each other at the first boundary BDRY1.

[0332] The first anode connection electrode ANCE1 can be electrically connected to the second electrode E24 of the fourth transistor T4 and the second electrode E26 of the sixth transistor T6.

[0333] The second reference voltage connection electrode VRCE2 can be stacked with the second boundary BDRY2 and can be electrically connected to the first reference voltage connection electrode VRCE1.

[0334] The initial voltage line VAIL can be superimposed on the third boundary BDRY3.

[0335] The initialization voltage line VAIL may include a protruding portion that extends on opposite sides of the second direction DR2 and is superimposed on the first electrode E14 of the fourth transistor T4. That is, the initialization voltage line VAIL may include a protruding portion superimposed on the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4, which are connected to the extension of the contact third boundary BDRY3, and on the first direction DR1, a second light-emitting pixel driver EPD2, a third light-emitting pixel driver EPD3, a fifth light-emitting pixel driver EPD5, and a sixth light-emitting pixel driver EPD6, which are parallel to the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4.

[0336] Therefore, at least one second shared line CMML2 electrically connected to the first light-emitting pixel driver EPD1, the second light-emitting pixel driver EPD2, the third light-emitting pixel driver EPD3, the fourth light-emitting pixel driver EPD4, the fifth light-emitting pixel driver EPD5, and the sixth light-emitting pixel driver EPD6 may include an initialization voltage line VAIL.

[0337] The initialization voltage line VAIL can be electrically connected to the first electrode E14 of the fourth transistor T4 through a connection hole superimposed on the protrusion.

[0338] like Figure 16 As shown, the second source-drain conductive layer SDCDL2 may include a data line DL, a second auxiliary line ASL2, a first power sub-line VDSBL, a reference voltage sub-line VRSBL, and a second anode connection electrode ANCE2.

[0339] Each of the data line DL, the second auxiliary line ASL2, the first power sub-line VDSBL, and the reference voltage sub-line VRSBL can extend in the second direction DR2.

[0340] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1.

[0341] The first power sub-line VDSBL can be electrically connected to the first power mainline via the first power connection auxiliary electrode VDCE1. Figure 14 VDMNL in (the context of VDMNL).

[0342] The first power sub-line VDSBL can be superimposed on the first boundary BDRY1 and can be adjacent to the second auxiliary line ASL2.

[0343] The first power sub-line VDSBL can be electrically connected to the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, which are in contact with the first boundary BDRY1, and the fourth light-emitting pixel driver EPD4 and the fifth light-emitting pixel driver EPD5, which are parallel to the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 in the second direction DR2.

[0344] In other words, the first shared line CMML1, which is electrically connected to the first light-emitting pixel driver EPD1, the second light-emitting pixel driver EPD2, the fourth light-emitting pixel driver EPD4, and the fifth light-emitting pixel driver EPD5, may include the first power sub-line VDSBL.

[0345] In this way, the first power ( Figure 5 ELVDD in the middle can not only transmit to the first power main ( Figure 14The first power line (VDMNL) can be transmitted to the light-emitting pixel driver (EPD), which is in the form of a grid including the first power main line (VDMNL) and the first power sub-line (VDSBL) in the display area (DA). Therefore, the delay or voltage drop of the first power line (ELVDD) due to line resistance can be reduced.

[0346] Additionally, in an embodiment, the first shared line CMML1, including the first power sub-line VDSBL, is electrically connected to two pixel columns that are adjacent to each other in the first direction DR1 among the pixel columns in the display area DA, each composed of light-emitting pixel drivers EPD arranged in parallel in the second direction DR2.

[0347] Therefore, the total number of first power sub-lines VDSBLs arranged in the display area DA can be reduced to half the number of pixel columns, thus reducing the width of the display area DA consumed by arranging the first power sub-lines VDSBLs. This can be advantageous in increasing the resolution of the display device 100.

[0348] The reference voltage sub-line VRSBL can be electrically connected to the second reference voltage connection electrode. Figure 15 VRCE2 in (the text is incomplete and cannot be translated).

[0349] The reference voltage sub-line VRSBL can be superimposed on the second boundary BDRY2 and can be adjacent to the data line DL.

[0350] In other words, the reference voltage sub-line VRSBL can be electrically connected to the second light-emitting pixel driver EPD2 and the third light-emitting pixel driver EPD3, which are in contact with the second boundary BDRY2, and the fifth light-emitting pixel driver EPD5 and the sixth light-emitting pixel driver EPD6, which are parallel to the second light-emitting pixel driver EPD2 and the third light-emitting pixel driver EPD3 in the second direction DR2.

[0351] In other words, the additional shared line ACMML electrically connected to the second light-emitting pixel driver EPD2, the third light-emitting pixel driver EPD3, the fifth light-emitting pixel driver EPD5, and the sixth light-emitting pixel driver EPD6 may include the reference voltage sub-line VRSBL.

[0352] In this way, the reference voltage ( Figure 5 The reference voltage sub-lines (VREF) in the display area DA can be transmitted to the light-emitting pixel driver EPD, which is in the form of a grid including reference voltage sub-lines (VRSBL) in the display area DA, and the total number of reference voltage sub-lines (VRSBL) in the display area DA can be reduced to half the number of pixel columns. Therefore, since the width of the display area DA consumed by arranging the reference voltage sub-lines (VRSBL) can be reduced, it can be advantageous in increasing the resolution of the display device 100.

[0353] As described above, since the circuit layer 120 of the display device 100 in the embodiment includes a first shared line CMML1 electrically connected to the light-emitting pixel drivers EPDs that are adjacent to each other in the first direction DR1 and at least one second shared line CMML2 electrically connected to the light-emitting pixel drivers EPDs that are adjacent to each other in the second direction DR2, it can be advantageous in increasing the resolution of the display device 100.

[0354] Figure 17 It is shown Figure 12 A plan view of an embodiment of the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer of part I.

[0355] Since, in addition to circuit layer 120, there is at least one third shared line CMML3 adjacent to the fourth boundary BDRY4, Figure 17 The display device 100 in the embodiment shown is Figures 1 to 16 The display device 100 in the embodiments shown is substantially the same, so repeated descriptions will be omitted below.

[0356] like Figure 17 As shown, in an embodiment, circuit layer 120 may further include at least one third shared line CMML3 that extends in the first direction DR1 and is adjacent to (adjacent to) the fourth boundary BDRY4.

[0357] At least one third shared line CMML3 can extend along the first direction DR1 and can be electrically connected to the fourth light-emitting pixel driver EPD4, the fifth light-emitting pixel driver EPD5, the seventh light-emitting pixel driver EPD7, and the eighth light-emitting pixel driver EPD8, which are in contact with the fourth boundary BDRY4 and its extension. The first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the seventh light-emitting pixel driver EPD7 can be symmetrical with respect to the extension of the first boundary BDRY1 of the eighth light-emitting pixel driver EPD8. The first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the seventh light-emitting pixel driver EPD7 can be symmetrical with respect to the fourth boundary BDRY4 between the fourth light-emitting pixel driver EPD4 and the seventh light-emitting pixel driver EPD7. The first semiconductor layer SEL1 and the second semiconductor layer SEL2 of the eighth light-emitting pixel driver EPD8 can be symmetrical with respect to the extension of the fourth boundary BDRY4 of the fifth light-emitting pixel driver EPD5.

[0358] In this way, the third shared line CMML3 can be electrically connected to two adjacent (adjacent) pixel rows in the display area DA, which are composed of light-emitting pixel drivers EPDs arranged parallel to each other in the first direction DR1. Therefore, since the number of any one third shared line CMML3 in the display area DA can be reduced to half the number of pixel rows in the display area DA, the width of the display area DA consumed by arranging the third shared line CMML3 can be reduced. As a result, this can be advantageous in increasing the resolution of the display device 100.

[0359] like Figure 17 As shown, the second gate conductive layer GCDL2 may extend in the first direction DR1 and transmit a reference voltage ( Figure 5 The reference voltage main line VRMNL of VREF).

[0360] The reference voltage main line VRMNL can be connected to the electrode via the first reference voltage. Figure 13 VRCE1) and the second reference voltage connection electrode ( Figure 15 VRCE2 is electrically connected to the reference voltage sub-line ( Figure 16 VRSBL in (the context of VRSBL).

[0361] In an embodiment, when the first reference voltage is connected to the electrode ( Figure 13 When VRCE1 protrudes from the reference voltage main line VRMNL, the reference voltage main line VRMNL can be connected to the electrode via the first reference voltage. Figure 13 VRCE1) and the second reference voltage connection electrode ( Figure 15 VRCE2 is electrically connected to the reference voltage sub-line ( Figure 16 VRSBL in (the context of VRSBL).

[0362] In an embodiment, the reference voltage main line VRMNL may include a protruding portion superimposed on the fourth light-emitting pixel driver EPD4, the fifth light-emitting pixel driver EPD5, the seventh light-emitting pixel driver EPD7, and the eighth light-emitting pixel driver EPD8.

[0363] The reference voltage main line VRMNL can be electrically connected to the first electrode E13 of the third transistor T3 of each of the fourth light-emitting pixel drivers EPD4, the fifth light-emitting pixel driver EPD5, the seventh light-emitting pixel driver EPD7, and the eighth light-emitting pixel driver EPD8 through a connection hole superimposed with the protrusion.

[0364] Therefore, at least one third shared line CMML3 electrically connected to the fourth light-emitting pixel driver EPD4, the fifth light-emitting pixel driver EPD5, the seventh light-emitting pixel driver EPD7, and the eighth light-emitting pixel driver EPD8 may include the reference voltage main line VRMNL.

[0365] The second semiconductor layer SEL2 may include the channel CH2 of the second transistor T2, the first electrode E12 and the second electrode E22, and the channel CH3 of the third transistor T3, the first electrode E13 and the second electrode E23.

[0366] The third gate conductive layer GCDL3 may include the gate electrode G2 of the second transistor T2, which is stacked with the channel portion CH2 of the second transistor T2, and the transmission reset control signal. Figure 5 The reset control line GRL in GR).

[0367] The reset control line GRL may include a reset control main line GRMNL extending in the first direction DR1 and superimposed with the fourth light-emitting pixel driver EPD4 and the fifth light-emitting pixel driver EPD5, a reset control protruding line GRPRL protruding from the reset control main line GRMNL and extending in the second direction DR2, and a reset control extension line GREXL connected to the reset control protruding line GRPRL, extending in the first direction DR1 and superimposed with the seventh light-emitting pixel driver EPD7 and the eighth light-emitting pixel driver EPD8.

[0368] In each of the fourth light-emitting pixel driver EPD4 and the fifth light-emitting pixel driver EPD5, the gate electrode G3 of the third transistor T3 can be configured as part of the reset control mainline GRMNL.

[0369] Additionally, in each of the seventh and eighth light-emitting pixel drivers EPD7 and EPD8, the gate electrode G3 of the third transistor T3 can be configured as part of the reset control extension line GREXL.

[0370] In other words, the reset control line GRL can be electrically connected to the third transistor T3 located in the fourth light-emitting pixel driver EPD4, the fifth light-emitting pixel driver EPD5, the seventh light-emitting pixel driver EPD7, and the eighth light-emitting pixel driver EPD8. The third transistor T3 can be turned on by the reset control signal GR of the reset control line GRL.

[0371] Therefore, at least one third shared line CMML3 electrically connected to the fourth light-emitting pixel driver EPD4, the fifth light-emitting pixel driver EPD5, the seventh light-emitting pixel driver EPD7, and the eighth light-emitting pixel driver EPD8 may include a reset control line GRL.

[0372] Therefore, since the number of reset control lines GRL can be reduced to half the number of pixel rows, it can be advantageous in increasing the resolution of the display device 100.

[0373] Figure 18 It is shown Figure 12 A plan view of part J, including the first semiconductor layer, the first gate conductive layer, and the second gate conductive layer.

[0374] Since, in addition to the second shared line CMML2 of circuit layer 120 including the second transmit control line ECL2, Figure 18 The display device 100 in the embodiment shown is Figures 1 to 16 The display device 100 in the embodiments shown is substantially the same, so repeated descriptions will be omitted below.

[0375] In an embodiment, circuit layer 120 may include at least one second shared line CMML2 that is adjacent to (adjacent to) the third boundary BDRY3 between the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4 and extends in the first direction DR1.

[0376] The second shared line CMML2 can be electrically connected to the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4, as well as the second light-emitting pixel driver EPD2 and the fifth light-emitting pixel driver EPD5, which are parallel to the first light-emitting pixel driver EPD1 and the fourth light-emitting pixel driver EPD4 in the first direction DR1.

[0377] like Figure 18 As shown in the embodiment, the first semiconductor layer SEL1 may include the channel portion CH5 of the fifth transistor T5, the first electrode E15 and the second electrode E25, and the channel portion CH6 of the sixth transistor T6, the first electrode E16 and the second electrode E26.

[0378] The first gate conductive layer GCDL1 may include a first capacitor electrode CAE1, a third capacitor electrode CAE3, a first emitter control line ECL1, and a second emitter control line ECL2.

[0379] The second gate conductive layer GCDL2 may include a second capacitor electrode CAE2 and a first reference voltage connection electrode VRCE1.

[0380] The first emitter control line ECL1 can extend in the first direction DR1 and intersect with the channel CH5 of the fifth transistor T5.

[0381] The first transmit control line, ECL1, can be set by pixel row.

[0382] In other words, a first emission control line ECL1 can be stacked with the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, and can be electrically connected to the fifth transistor T5 of each of the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0383] Another first transmit control line ECL1 can be stacked with the fourth light-emitting pixel driver EPD4 and the fifth light-emitting pixel driver EPD5, and can be electrically connected to the fifth transistor T5 of each of the fourth light-emitting pixel driver EPD4 and the fifth light-emitting pixel driver EPD5.

[0384] exist Figure 18 In an embodiment, the second emission control line ECL2 may include an emission control main line ECMNL extending in the first direction DR1 and superimposed with the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, an emission control protrusion line ECPRL protruding from the emission control main line ECMNL and extending in the second direction DR2, and an emission control extension line ECEXL connected to the emission control protrusion line ECPRL, extending in the first direction DR1 and superimposed with the fourth light-emitting pixel driver EPD4 and the fifth light-emitting pixel driver EPD5.

[0385] In each of the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, the gate electrode G6 of the sixth transistor T6 can be configured as part of the emission control mainline ECMNL.

[0386] Additionally, in each of the fourth light-emitting pixel driver EPD4 and the fifth light-emitting pixel driver EPD5, the gate electrode G6 of the sixth transistor T6 can be configured as part of the emission control extension line ECEXL.

[0387] In other words, the second transmit control line ECL2 can be electrically connected to the sixth transistor T6 disposed in the first light-emitting pixel driver EPD1, the second light-emitting pixel driver EPD2, the fourth light-emitting pixel driver EPD4, and the fifth light-emitting pixel driver EPD5. The sixth transistor T6 can be controlled by the second transmit control signal of the second transmit control line ECL2 (…). Figure 5 EC2 in the middle is turned on.

[0388] Therefore, at least one second shared line CMML2 electrically connected to the first light-emitting pixel driver EPD1, the second light-emitting pixel driver EPD2, the fourth light-emitting pixel driver EPD4, and the fifth light-emitting pixel driver EPD5 may include a second emission control line ECL2.

[0389] Therefore, since the number of second emission control lines ECL2 can be reduced to half the number of pixel rows, it can be advantageous in increasing the resolution of the display device 100.

[0390] Figure 19 This is a block diagram illustrating an embodiment of an electronic device. Figure 20 This shows what is implemented as a smartphone. Figure 19 A view of an embodiment of an electronic device.

[0391] Reference Figure 19 and Figure 20 In this embodiment, the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be connected to… Figure 1 The electronic device 1000 corresponds to the display device 100. The electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, etc. In one embodiment, the electronic device 1000 may be implemented as a television. In another embodiment, the electronic device 1000 may be implemented as a smartphone. However, the embodiments are not limited thereto; in another embodiment, the electronic device 1000 may be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted (e.g., mounted) display (“HMD”), etc.

[0392] Processor 1010 can perform various computing functions. In embodiments, processor 1010 may be a microprocessor, a central processing unit (“CPU”), an application processor (“AP”), etc. Processor 1010 may be integrated with other components via address buses, control buses, data buses, etc. In embodiments, processor 1010 may be integrated with an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0393] The memory device 1020 can store data for the operation of the electronic device 1000. In embodiments, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, etc.

[0394] In an embodiment, storage device 1030 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, or a CD-ROM device. In an embodiment, I / O device 1040 may include input devices such as a keyboard, keypad, mouse device, touchpad, touch screen, etc., and output devices such as a printer, speaker, etc.

[0395] Power supply 1050 can provide power for the operation of electronic device 1000. Power supply 1050 can also provide power to display device 1060. Display device 1060 can be connected to other components via a bus or other communication link. In an embodiment, display device 1060 may be included in I / O device 1040.

[0396] In one embodiment, the electronic device can be implemented as a smartphone. However, the embodiments of this disclosure are exemplary and may not be limited thereto. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smartpad, smartwatch, television, tablet PC, vehicle display, computer monitor, laptop computer, head-mounted display device, etc. Alternatively, the electronic device 1000 can be a television set, monitor, laptop computer, or tablet computer. Additionally, the electronic device 1000 can be a car.

[0397] However, the effects of the disclosure are not limited to those set forth herein. The above and other effects of the disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device comprising: a substrate including a display region and a non-display region provided around the display region, a light emitting region being arranged in the display region; a circuit layer provided on the substrate, the circuit layer including: light emitting pixel drivers arranged in a first direction and a second direction; a first shared line extending in the second direction, adjacent to a first boundary between first and second light emitting pixel drivers, which are adjacent to each other in the first direction, among the light emitting pixel drivers, and electrically connected to the first and second light emitting pixel drivers; a first semiconductor layer provided on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer provided on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer provided on the second gate insulating layer; a first intermediate insulating layer covering the second gate conductive layer; and a second semiconductor layer provided on the first intermediate insulating layer; and an element layer provided on the circuit layer, and including light emitting elements each provided in the light emitting region and electrically connected to the light emitting pixel drivers, wherein one of the light emitting pixel drivers includes a first transistor that generates a drive current for one of the light emitting elements, a channel portion, a first electrode, and a second electrode of the first transistor are provided in the second semiconductor layer, and the first and second semiconductor layers of the first light emitting pixel driver are symmetrical to the first and second semiconductor layers of the second light emitting pixel driver with respect to the first boundary.

2. The display device according to claim 1, wherein the light emitting pixel drivers further include: a third light emitting pixel driver adjacent to the second light emitting pixel driver in the first direction; a fourth light emitting pixel driver adjacent to the first light emitting pixel driver in the second direction; a fifth light emitting pixel driver adjacent to the second light emitting pixel driver in the second direction; and a sixth light emitting pixel driver adjacent to the third light emitting pixel driver in the second direction, the first and second semiconductor layers of the second light emitting pixel driver are symmetrical to the first and second semiconductor layers of the third light emitting pixel driver with respect to a second boundary between the second and third light emitting pixel drivers, the first and second semiconductor layers of the first light emitting pixel driver are symmetrical to the first and second semiconductor layers of the fourth light emitting pixel driver with respect to a third boundary between the first and fourth light emitting pixel drivers, the first and second semiconductor layers of the second light emitting pixel driver are symmetrical to the first and second semiconductor layers of the fifth light emitting pixel driver with respect to an extension line of the third boundary, and the first shared line is further electrically connected to the fourth and fifth light emitting pixel drivers.

3. The display device of claim 2, wherein, The circuit layer further includes: a data line that transmits a data signal to the light-emitting pixel driver; a reference voltage line that transmits a reference voltage to the light-emitting pixel driver; an initialization voltage line that transmits an initialization voltage to the light-emitting pixel driver; a first power line that transmits a first power to the light-emitting pixel driver; a scan write line that transmits a scan write signal to the light-emitting pixel driver; a reset control line that transmits a reset control signal to the light-emitting pixel driver; a bias control line that transmits a bias control signal to the light-emitting pixel driver; a first emission control line that transmits a first emission control signal to the light-emitting pixel driver; and a second emission control line that transmits a second emission control signal to the light-emitting pixel driver.

4. The display device according to claim 3, wherein The circuit layer further includes: a third gate insulating layer that covers the second semiconductor layer; a third gate conductive layer provided on the third gate insulating layer; a second intermediate insulating layer that covers the third gate conductive layer; a first source-drain conductive layer provided on the second intermediate insulating layer; a first planarization layer that covers the first source-drain conductive layer; a second source-drain conductive layer provided on the first planarization layer; and a second planarization layer that covers the second source-drain conductive layer, and the one of the light-emitting pixel drivers further includes a second transistor electrically connected between the gate electrode of the first transistor and the data line, a third transistor electrically connected between the gate electrode of the first transistor and the reference voltage line, a fourth transistor electrically connected between one of the light-emitting elements and the initialization voltage line, a fifth transistor electrically connected between the first electrode of the first transistor and the first power line, a sixth transistor electrically connected between the second electrode of the first transistor and the one of the light-emitting elements, a first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor, and a second capacitor electrically connected between the first power line and the second electrode of the first transistor.

5. The display device of claim 4, wherein, The first power line includes: a first power main line provided in the third gate conductive layer and extending in the first direction; and a first power sub-line provided in the second source-drain conductive layer and extending in the second direction, and the first shared line includes the first power sub-line.

6. The display device of claim 5, wherein, The circuit layer further includes: an electrode extension portion extending from a first electrode of the sixth transistor; a first capacitor electrode provided in the first gate conductive layer, superimposed with a portion of the electrode extension portion, and electrically connected to the gate electrode of the first transistor; a second capacitor electrode provided in the second gate conductive layer, superimposed with the first capacitor electrode, and electrically connected to the second electrode of the first transistor; a third capacitor electrode disposed in the first gate conductive layer, separated from the first capacitor electrode, stacked with another portion of the electrode extension and the second capacitor electrode, and electrically connected to the first power line; a first power connection auxiliary electrode disposed in the first source-drain conductive layer and electrically connected to the third capacitor electrode and the first power main line, and a second power connection auxiliary electrode disposed in the first source-drain conductive layer and electrically connected to the first electrode of the fifth transistor and the first power main line, the third capacitor electrode of the first light-emitting pixel driver and the third capacitor electrode of the second light-emitting pixel driver are connected to each other at the first boundary, the second power connection auxiliary electrode of the first light-emitting pixel driver and the second power connection auxiliary electrode of the second light-emitting pixel driver are connected to each other at the first boundary, the first capacitor is provided as a stacked region between the first capacitor electrode and each of the electrode extension and the second capacitor electrode, and the second capacitor is provided as a stacked region between the third capacitor electrode and each of the electrode extension and the second capacitor electrode.

7. The display device of claim 6, wherein, the first power connection auxiliary electrode of the second light-emitting pixel driver and the first power connection auxiliary electrode of the third light-emitting pixel driver are connected to each other at the second boundary and electrically connected to the first electrode of the fifth transistor of the first semiconductor layer.

8. The display device according to claim 4, wherein The circuit layer further includes at least one second shared line extending in the first direction, adjacent to the third boundary, and electrically connected to the first light-emitting pixel driver, the second light-emitting pixel driver, the fourth light-emitting pixel driver, and the fifth light-emitting pixel driver.

9. The display device of claim 8, wherein, The fourth transistor is turned on by the bias control signal of the bias control line, The bias control line is disposed in the third gate conductive layer, extends in the first direction, and is stacked with the third boundary, and The at least one second shared line includes the bias control line.

10. The display device of claim 8, wherein, The initialization voltage line is disposed in the first source-drain conductive layer, extends in the first direction, and is stacked with the third boundary, and The at least one second shared line includes the initialization voltage line.

11. The display device of claim 8, wherein, The fifth transistor is turned on by the first emission control signal of the first emission control line, The sixth transistor is turned on by the second emission control signal of the second emission control line, The second emission control line includes: an emission control main line disposed in the first gate conductive layer, extending in the first direction, and stacked with the fourth light-emitting pixel driver and the fifth light-emitting pixel driver; an emission control protruding line protruding from the emission control main line and extending in the second direction; and a reset control extension line connected to the emission control protruding line, extending in the first direction, and stacked with the fifth light-emitting pixel driver and the sixth light-emitting pixel driver, and The at least one second shared line includes the second emission control line.

12. The display device according to claim 4, wherein The light emitting pixel driver further includes: a seventh light emitting pixel driver adjacent to the fourth light emitting pixel driver in the second direction; and an eighth light emitting pixel driver adjacent to the fifth light emitting pixel driver in the second direction, the first semiconductor layer and the second semiconductor layer of the seventh light emitting pixel driver are symmetrical to the first semiconductor layer and the second semiconductor layer of the eighth light emitting pixel driver with respect to an extension line of the fourth boundary, the first semiconductor layer and the second semiconductor layer of the seventh light emitting pixel driver are symmetrical to the first semiconductor layer and the second semiconductor layer of the fourth light emitting pixel driver with respect to a fourth boundary between the fourth light emitting pixel driver and the seventh light emitting pixel driver, the first semiconductor layer and the second semiconductor layer of the eighth light emitting pixel driver are symmetrical to the first semiconductor layer and the second semiconductor layer of the fifth light emitting pixel driver with respect to the extension line of the fourth boundary, and the circuit layer further includes at least one third shared line extending in the first direction, adjacent to the fourth boundary, and electrically connected to the fourth light emitting pixel driver, the fifth light emitting pixel driver, the seventh light emitting pixel driver, and the eighth light emitting pixel driver.

13. The display device of claim 12, wherein, the third transistor is turned on by the reset control signal of the reset control line, the reset control line includes: a reset control main line provided in the third gate conductive layer, extending in the first direction, and superposed with the fourth light emitting pixel driver and the fifth light emitting pixel driver; a reset control protruding line protruding from the reset control main line and extending in the second direction; and a reset control extension line connected to the reset control protruding line, extending in the first direction, and superposed with the seventh light emitting pixel driver and the eighth light emitting pixel driver, and the at least one third shared line includes the reset control line.

14. The display device of claim 12, wherein, The reference voltage line includes: a reference voltage main line provided in the second gate conductive layer, extending in the first direction, and superposed with the fourth boundary; and a reference voltage sub-line provided in the second source / drain conductive layer, extending in the second direction, adjacent to the second boundary, and electrically connected to the reference voltage main line, and the at least one third shared line includes the reference voltage main line.

15. An electronic device, the electronic device including: a display device as a display screen, The display device includes: a substrate including a display area and a non-display area disposed around the display area, a light emitting area being arranged in the display area; a circuit layer disposed on the substrate, the circuit layer including: light emitting pixel drivers arranged in a first direction and a second direction; data lines extending in the second direction and transmitting data signals to the light emitting pixel drivers; a first bypass auxiliary line extending in the first direction and electrically connected to first data lines among the data lines adjacent to the non-display area in the first direction; a second bypass auxiliary line extending in the second direction, adjacent to second data lines among the data lines spaced farther apart from the non-display area than the first data lines in the first direction, and electrically connected to the first bypass auxiliary line; and a first shared line extending in the second direction, adjacent to a boundary between two light emitting pixel drivers among the light emitting pixel drivers adjacent to each other in the first direction, and electrically connected to the two light emitting pixel drivers; and an element layer disposed on the circuit layer and including light emitting elements each disposed in the light emitting area and electrically connected to the light emitting pixel drivers, The circuit layer includes a first semiconductor layer disposed on the substrate and a second semiconductor layer disposed on one or more insulating layers covering the first semiconductor layer, The two light emitting pixel drivers include the first semiconductor layer and the second semiconductor layer symmetrical with respect to the boundary between the two light emitting pixel drivers, and The other two light emitting pixel drivers among the light emitting pixel drivers adjacent to each other in the second direction include the first semiconductor layer and the second semiconductor layer symmetrical with respect to the boundary between the other two light emitting pixel drivers. 16.The electronic device of claim 15, wherein, The circuit layer further includes: the first semiconductor layer; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed on the second gate insulating layer; a first intermediate insulating layer covering the second gate conductive layer; the second semiconductor layer disposed on the first intermediate insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer disposed on the third gate insulating layer; a second intermediate insulating layer covering the third gate conductive layer; a first source-drain conductive layer disposed on the second intermediate insulating layer; a first planarization layer covering the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer, Each of the light emitting pixel drivers includes: a first transistor; a second transistor electrically connected between the data line that transmits the data signal and a gate electrode of the first transistor; a third transistor electrically connected between a reference voltage line that transmits a reference voltage and the gate electrode of the first transistor; a fourth transistor electrically connected between an initialization voltage line that transmits an initialization voltage and the light emitting element; a fifth transistor electrically connected between a first power line that transmits a first power and a first electrode of the first transistor; a sixth transistor electrically connected between a second electrode of the first transistor and the light emitting element; a first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; and a second capacitor electrically connected between the first power line and the second electrode of the first transistor, a channel portion, a first electrode, and a second electrode of each of the first transistor, the second transistor, the third transistor, and the fourth transistor are provided in the second semiconductor layer, a channel portion, a first electrode, and a second electrode of each of the fifth transistor and the sixth transistor are provided in the first semiconductor layer, the third transistor is turned on by a reset control signal of a reset control line, the fourth transistor is turned on by a bias control signal of a bias control line, the fifth transistor is turned on by a first emission control signal of a first emission control line, and the sixth transistor is turned on by a second emission control signal of a second emission control line. 17.The electronic device of claim 16, wherein, The light emitting pixel driver includes: a first light emitting pixel driver; a second light emitting pixel driver adjacent to the first light emitting pixel driver in the first direction; a third light emitting pixel driver adjacent to the second light emitting pixel driver in the first direction; a fourth light emitting pixel driver adjacent to the first light emitting pixel driver in the second direction; a fifth light emitting pixel driver adjacent to the second light emitting pixel driver in the second direction; a sixth light emitting pixel driver adjacent to the third light emitting pixel driver in the second direction; a seventh light emitting pixel driver adjacent to the fourth light emitting pixel driver in the second direction; and an eighth light emitting pixel driver adjacent to the fifth light emitting pixel driver in the second direction, the first power line includes: a first power main line provided in the third gate conductive layer and extending in the first direction; and a first power sub-line provided in the second source / drain conductive layer and extending in the second direction, and the first shared line is adjacent to a boundary between the first light emitting pixel driver and the second light emitting pixel driver, and includes the first power sub-line. 18.The electronic device of claim 17, wherein, Each of the light emitting pixel drivers further includes: an electrode extension portion extending from a first electrode of the sixth transistor; a first capacitor electrode provided in the first gate conductive layer, superposed with a portion of the electrode extension portion, and electrically connected to the gate electrode of the first transistor; a second capacitor electrode disposed in the second gate conductive layer, stacked with the first capacitor electrode, and electrically connected to the second electrode of the first transistor; and a third capacitor electrode disposed in the first gate conductive layer, separated from the first capacitor electrode, stacked with another portion of the electrode extension and the second capacitor electrode, and electrically connected to the first power line, the first capacitor is provided as a stacked region between the first capacitor electrode and each of the electrode extension and the second capacitor electrode, and the second capacitor is provided as a stacked region between the third capacitor electrode and each of the electrode extension and the second capacitor electrode. 19.The electronic device of claim 17, wherein, The circuit layer further includes: at least one second shared line extending in the first direction, adjacent to a boundary between the second light emitting pixel driver and the third light emitting pixel driver, and electrically connected to the second light emitting pixel driver, the third light emitting pixel driver, the fifth light emitting pixel driver, and the sixth light emitting pixel driver, the second emission control line includes: an emission control main line disposed in the first gate conductive layer, extending in the first direction, and stacked with the fourth light emitting pixel driver and the fifth light emitting pixel driver; an emission control protruding line protruding from the emission control main line and extending in the second direction; and a reset control extension line connected to the emission control protruding line, extending in the first direction, and stacked with the fifth light emitting pixel driver and the sixth light emitting pixel driver, and the at least one second shared line includes at least one of the bias control line, the initialization voltage line, and the second emission control line. 20.The electronic device of claim 17, wherein, The circuit layer further includes: at least one third shared line extending in the first direction, adjacent to a boundary between the fourth light emitting pixel driver and the seventh light emitting pixel driver, and electrically connected to the fourth light emitting pixel driver, the fifth light emitting pixel driver, the seventh light emitting pixel driver, and the eighth light emitting pixel driver, the reference voltage line includes: a reference voltage main line disposed in the second gate conductive layer and extending in the first direction; and a reference voltage sub-line disposed in the second source-drain conductive layer, extending in the second direction, and electrically connected to the reference voltage main line, the reset control line includes: a reset control main line extending in the first direction and stacked with the fourth light emitting pixel driver and the fifth light emitting pixel driver; a reset control protruding line protruding from the reset control main line and extending in the second direction; and a reset control extension line connected to the reset control protruding line, extending in the first direction, and stacked with the seventh light emitting pixel driver and the eighth light emitting pixel driver, and the at least one third shared line includes at least one of the reference voltage main line and the reset control line.

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