2.5 D substrate interconnection packaging structure and preparation method thereof

Abstract

The invention discloses a 2.5 D substrate interconnection packaging structure and a preparation method thereof, and relates to the technical field of chip packaging, the 2.5 D substrate interconnection packaging structure comprises a substrate wiring layer, a first stacking wiring layer, a second stacking wiring layer, a first chip, a first packaging layer, a second chip, a second packaging layer, a third chip and a third packaging layer, the first stacking wiring layer, the second stacking wiring layer and the first chip are sequentially arranged on the substrate wiring layer; the second chip and the third chip are respectively arranged on the second stacking wiring layer and the first stacking wiring layer; the first packaging layer, the second packaging layer and the third packaging layer respectively wrap the first chip, the second chip and the third chip; and the height of the first stacking wiring layer is greater than that of the second stacking wiring layer. Compared with the prior art, the number of layers and the thickness of wiring in different areas are different, product customization is achieved, the stacking degree is high, the integration degree is high, and the stress warping phenomenon can be relieved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a 2.5D substrate interconnect packaging structure and its fabrication method. Background Technology

[0002] Fan-out wafer-level package (FOWLP) structures are widely used in the semiconductor industry. RDL-first process is an important process in fan-out wafer-level package. It first coats a removable laser release material onto a glass carrier wafer, then builds an RDL substrate layer on this layer, and finally encapsulates the chip onto the RDL substrate using flip-chip bonding technology to form a 2.5D package.

[0003] In current chiplet design, various small chips with different process technologies (e.g., 45nm, 28nm, 7nm, or 5nm) need to be mounted. Since the I / O density varies across different process technologies, and wiring layers are required to bring out the I / O pins, chips with smaller process nodes (e.g., 7nm or 5nm) require denser and more wiring layers to ensure performance output. However, wiring layers are typically of uniform thickness. Using multi-layer wiring structures for smaller nodes leads to an increase in the thickness of wiring layers in areas of larger nodes (e.g., 45nm, 28nm). Furthermore, thicker wiring layers result in increased internal resistance (R) and capacitance (C), leading to longer signal transmission distances and potentially causing exponentially increasing RC delay.

[0004] Furthermore, with product design iterations, the wiring layer thickness in existing packaging technologies is a uniform structure, making product customization impossible. The low stacking density also results in low integration of the packaging structure. Additionally, the need for complete molding of the entire package makes it prone to stress imbalances, leading to warping and stress-induced fractures at the chip solder joints. Summary of the Invention

[0005] The purpose of this invention is to provide a 2.5D substrate interconnect packaging structure and its fabrication method, which enables different numbers and thicknesses of wiring layers in different regions, thereby achieving product customization and solving the problem of excessive wiring layer thickness for some chips. Simultaneously, it offers high stacking and integration, and by encapsulating the chip with different encapsulation layers, it can mitigate stress warping phenomena in the molding compound.

[0006] The embodiments of the present invention are implemented as follows: In a first aspect, embodiments of the present invention provide a 2.5D substrate interconnect package structure, comprising: Substrate wiring layer; A first stacked wiring layer is disposed in a first wiring region of the base wiring layer, and the first stacked wiring layer is electrically connected to the base wiring layer. A second stacked wiring layer is disposed in a second wiring region of the base wiring layer, wherein the second stacked wiring layer is disposed at least on one side of the first stacked wiring layer, and the second stacked wiring layer is electrically connected to the base wiring layer; A first chip is disposed in the third wiring region of the substrate wiring layer, and the first chip is electrically connected to the substrate wiring layer. A first encapsulation layer is disposed in the third wiring region of the substrate wiring layer, and the first encapsulation layer at least covers the first chip; A second chip is disposed on the second stacked wiring layer, and the second chip is electrically connected to the second stacked wiring layer; A second encapsulation layer is disposed on the second stacked wiring layer, the second encapsulation layer at least covering the second chip; A third chip is disposed on the first stacked wiring layer, and the third chip is electrically connected to the first stacked wiring layer; A third encapsulation layer is disposed at least on the first stacked wiring layer, and the third encapsulation layer at least covers the third chip; Wherein, the height of the first stacked wiring layer relative to the base wiring layer is greater than the height of the second stacked wiring layer relative to the base wiring layer.

[0007] In an optional embodiment, the third wiring region of the substrate wiring layer is further provided with a first solder interconnect layer, the first chip is flip-chip mounted on the first solder interconnect layer and electrically connected to the substrate wiring layer through the first solder interconnect layer; the second stacked wiring layer is further provided with a second solder interconnect layer, the second chip is flip-chip mounted on the second solder interconnect layer and electrically connected to the second stacked wiring layer through the second solder interconnect layer; the first stacked wiring layer is further provided with a third solder interconnect layer, the third chip is flip-chip mounted on the third solder interconnect layer and electrically connected to the first stacked wiring layer through the third solder interconnect layer.

[0008] In an optional implementation, the height of the first chip relative to the substrate wiring layer is lower than the height of the second stacked wiring layer relative to the substrate wiring layer, and the height of the second chip relative to the substrate wiring layer is lower than the height of the first stacked wiring layer relative to the substrate wiring layer.

[0009] In an optional embodiment, the first encapsulation layer is flush with the second stacked wiring layer, the second encapsulation layer is flush with the first stacked wiring layer, and the edge of the second encapsulation layer is aligned with the edge of the second stacked wiring layer.

[0010] In an optional embodiment, the first encapsulation layer covers the first chip and the second stacked wiring layer, the second encapsulation layer is disposed on the side of the first encapsulation layer away from the substrate wiring layer and covers the second chip and the first stacked wiring layer, and the third encapsulation layer is disposed on the side of the second encapsulation layer away from the substrate wiring layer.

[0011] In an optional embodiment, the third encapsulation layer is disposed on the first stacked wiring layer, the second encapsulation layer, and the first encapsulation layer, so that the third encapsulation layer simultaneously encapsulates the third chip, the second encapsulation layer, and the first encapsulation layer.

[0012] In an optional embodiment, a first encapsulation notch is formed on the side of the first encapsulation layer away from the first stacked wiring layer, and the first encapsulation notch is formed on the substrate wiring layer. A second encapsulation notch is also formed on the side of the second encapsulation layer away from the first stacked wiring layer, and the second encapsulation notch is formed on the second stacked wiring layer. The third encapsulation layer simultaneously encapsulates the third chip, the second encapsulation layer, and the first encapsulation layer, and fills the first encapsulation notch and the second encapsulation notch.

[0013] In an optional embodiment, a first antenna layer is disposed on the side of the first encapsulation layer away from the substrate wiring layer, the first antenna layer is spaced apart from the second encapsulation layer, and the third encapsulation layer covers the first antenna layer.

[0014] In an optional embodiment, a second antenna layer is further provided on the side of the second encapsulation layer away from the substrate wiring layer, the second antenna layer is spaced apart from the third chip, and the third encapsulation layer covers the second antenna layer.

[0015] In an optional embodiment, the second stacked wiring layer is disposed on both sides of the first stacked wiring layer, and the first chip is disposed on the side of the second stacked wiring layer away from the first stacked wiring layer.

[0016] In another aspect, embodiments of the present invention provide a method for fabricating a 2.5D substrate interconnect package structure, used to fabricate the aforementioned substrate interconnect package structure, the method comprising: Provide a vehicle; A substrate wiring layer is formed on the carrier; A photosensitive layer is formed on the substrate wiring layer; Partially remove the photosensitive layer to form a first opening, wherein the first opening exposes a first wiring region of the substrate wiring layer; A first stacked wiring layer is formed on the base wiring layer within the first opening, wherein the first stacked wiring layer is electrically connected to the base wiring layer; Partially remove the photosensitive layer around the first stacked wiring layer to form a second opening, wherein the second opening exposes a second wiring region of the substrate wiring layer; A second stacked wiring layer is formed on the base wiring layer within the second opening, wherein the second stacked wiring layer is electrically connected to the base wiring layer; Remove the remaining photosensitive layer to form a third opening, wherein the third opening exposes a third wiring region of the substrate wiring layer; A first chip is mounted on the substrate wiring layer within the third opening, and the first chip is electrically connected to the substrate wiring layer. A first encapsulation layer is formed on the substrate wiring layer within the third opening, and the first encapsulation layer at least covers the first chip; A second chip is mounted on the second stacked wiring layer, and the second chip is electrically connected to the second stacked wiring layer. A second encapsulation layer is formed on the second stacked wiring layer, and the second encapsulation layer at least covers the second chip; A third chip is mounted on the first stacked wiring layer, and the third chip is electrically connected to the first stacked wiring layer. A third encapsulation layer is formed on the first stacked wiring layer, and the third encapsulation layer at least covers the third chip; Wherein, the height of the first stacked wiring layer relative to the base wiring layer is greater than the height of the second stacked wiring layer relative to the base wiring layer.

[0017] In an optional implementation, the step of forming a third encapsulation layer on the first stacked wiring layer includes: A third encapsulation layer is formed on the first stacked wiring layer, the second encapsulation layer, and the first encapsulation layer, wherein the third encapsulation layer simultaneously encapsulates the third chip, the second encapsulation layer, and the first encapsulation layer.

[0018] In an optional implementation, prior to the step of forming a third encapsulation layer on the first stacked wiring layer, the method includes: A first antenna layer is formed on the side of the first encapsulation layer away from the substrate wiring layer; The third encapsulation layer covers the first antenna layer.

[0019] In an optional implementation, prior to the step of forming a third encapsulation layer on the first stacked wiring layer, the method includes: A second antenna layer is formed on the side of the second encapsulation layer away from the substrate wiring layer; The third encapsulation layer covers the second antenna layer.

[0020] The beneficial effects of the embodiments of the present invention include: The 2.5D substrate interconnect packaging structure provided in this invention comprises a first stacked wiring layer in a first wiring region of the substrate wiring layer, a second stacked wiring layer in a second wiring region, and a first chip in a third wiring region. The height of the first stacked wiring layer relative to the substrate wiring layer is greater than the height of the second stacked wiring layer relative to the substrate wiring layer, thus forming a stepped stacked wiring structure. This allows for different wiring layers and thicknesses in different wiring regions, solving the problem of excessive wiring layer thickness, thereby enabling product customization, and achieving high stacking degree and higher integration. Furthermore, a first encapsulation layer covers the first chip, a second encapsulation layer covers the second chip, and a third encapsulation layer covers the third chip. The first, second, and third encapsulation layers encapsulate the chip separately, avoiding stress warpage problems caused by overall encapsulation. Compared to existing technologies, the 2.5D substrate interconnect packaging structure provided in this invention can achieve different wiring layers in different regions, thereby enabling product customization, and achieving high stacking degree and high integration. Moreover, by encapsulating the chip separately with different encapsulations, stress warpage phenomena occurring in the molding compound can be mitigated. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of a first 2.5D substrate interconnect packaging structure provided in an embodiment of the present invention; Figure 2 A schematic diagram of a second 2.5D substrate interconnect packaging structure provided in an embodiment of the present invention; Figure 3a A schematic diagram of a third 2.5D substrate interconnect packaging structure provided in an embodiment of the present invention; Figure 3b A schematic diagram of a fourth 2.5D substrate interconnect packaging structure provided in an embodiment of the present invention; Figure 4A schematic diagram of the fifth 2.5D substrate interconnect packaging structure provided in the embodiments of the present invention; Figure 5 A top view of the sixth 2.5D substrate interconnect packaging structure provided in this embodiment of the invention; Figure 6 A schematic diagram of the seventh 2.5D substrate interconnect packaging structure provided in the embodiments of the present invention; Figure 7 A schematic diagram of the eighth 2.5D substrate interconnect packaging structure provided in the embodiments of the present invention; Figures 8 to 22 A process flow diagram of the fabrication method of the 2.5D substrate interconnect packaging structure provided in the embodiments of the present invention.

[0023] icon: 100 - 2.5D substrate interconnect package structure; 110 - substrate wiring layer; 111 - first solder interconnect layer; 120 - first stacked wiring layer; 121 - third solder interconnect layer; 130 - second stacked wiring layer; 131 - second solder interconnect layer; 140 - first chip; 141 - first encapsulation notch; 142 - second encapsulation notch; 150 - first encapsulation layer; 151 - first antenna layer; 160 - second chip; 170 - second encapsulation layer; 171 - second antenna layer; 180 - third chip; 190 - third encapsulation layer; 200 - carrier; 210 - photosensitive layer. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0026] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0027] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," not that the structure must be completely horizontal, but can be slightly tilted.

[0029] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] As disclosed in the background section, current fan-out wafer packaging structures feature a uniform wiring layer structure, meaning the wiring layers are formed in a single step with a consistent thickness. This makes product customization impossible, such as setting different wiring layer numbers for different chips. Furthermore, a uniform wiring layer number also leads to insufficient stacking, resulting in lower wiring integration and chip integration.

[0031] In current chiplet design, various small chips with different manufacturing processes (e.g., 45nm, 28nm, 7nm, or 5nm) need to be mounted. Since the I / O density varies across different process nodes, and wiring layers are required to bring the I / O pins out, smaller process nodes (e.g., 7nm or 5nm) require denser and more wiring layers to ensure performance output (i.e., relatively thicker wiring layers). However, wiring layers are typically of uniform thickness. Smaller node chips use multi-layer wiring structures, which leads to an increase in the thickness of wiring layers in areas of larger node chips (e.g., 45nm, 28nm). Thicker wiring layers result in increased internal resistance (R) and capacitance (C), leading to longer signal transmission distances and potentially causing exponentially increasing RC delay.

[0032] Furthermore, existing packaging structures typically require molding after chip mounting, using a monolithic molding process to fully cover the wiring layers and the chip. However, because the heat generated by the chips varies across different parts of the package, resulting in varying thermal stresses, stress imbalances can easily occur in the molding compound. This can lead to warping of the molding compound and stress fracture at the solder joints of the stacked chips.

[0033] To address the aforementioned issues, embodiments of the present invention provide a 2.5D substrate interconnect packaging structure and its fabrication method. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0034] The 2.5D substrate interconnect packaging structure provided by the embodiments of the present invention can realize different wiring layers and thicknesses in different regions, thereby realizing product customization. It also has a high degree of stacking and high integration. Furthermore, by encapsulating different chips with different encapsulation layers, stress warping of the molding compound can be mitigated.

[0035] See Figure 1The 2.5D substrate interconnect package structure 100 provided in this embodiment of the invention includes a substrate wiring layer 110, a first stacked wiring layer 120, a second stacked wiring layer 130, a first chip 140, a first encapsulation layer 150, a second chip 160, a second encapsulation layer 170, a third chip 180, and a third encapsulation layer 190. The substrate wiring layer 110 has a first wiring region, a second wiring region, and a third wiring region that are sequentially adjacent. The first stacked wiring layer 120 is disposed in the first wiring region of the substrate wiring layer 110 and is electrically connected to the substrate wiring layer 110. The second stacked wiring layer 130 is disposed in the second wiring region of the substrate wiring layer 110, wherein the second stacked wiring layer 130 is at least disposed on one side of the first stacked wiring layer 120 and is electrically connected to the substrate wiring layer 110. The first chip 140 is disposed in the third wiring region of the substrate wiring layer 110. In the third wiring region, a first chip 140 is electrically connected to a substrate wiring layer 110; a first encapsulation layer 150 is disposed in the third wiring region of the substrate wiring layer 110, and the first encapsulation layer 150 at least covers the first chip 140; a second chip 160 is disposed on a second stacked wiring layer 130, and the second chip 160 is electrically connected to the second stacked wiring layer 130; a second encapsulation layer 170 is disposed on the second stacked wiring layer 130, and the second encapsulation layer 170 at least covers the second chip 160; a third chip 180 is disposed on a first stacked wiring layer 120, and the third chip 180 is electrically connected to the first stacked wiring layer 120; a third encapsulation layer 190 is at least disposed on the first stacked wiring layer 120, and the third encapsulation layer 190 at least covers the third chip 180; wherein, the height of the first stacked wiring layer 120 relative to the substrate wiring layer 110 is greater than the height of the second stacked wiring layer 130 relative to the substrate wiring layer 110.

[0036] It should be noted that the wiring processes of the first stacked wiring layer 120 and the second stacked wiring layer 130 are consistent. The height of the first stacked wiring layer 120 relative to the base wiring layer 110 is greater than the height of the second stacked wiring layer 130 relative to the base wiring layer 110, indicating that the number of wiring layers in the first stacked wiring layer 120 is greater than the number of wiring layers in the second stacked wiring layer 130, and the thickness of the first stacked wiring layer 120 is greater than the thickness of the second stacked wiring layer 130. Therefore, the first stacked wiring layer 120, the second stacked wiring layer 130, and the base wiring layer 110 constitute a stepped stacked wiring structure, achieving different numbers and thicknesses of wiring layers in different wiring regions. Thus, the first chip 140, the second chip 160, and the third chip 180 can use chips of different types and processes, solving the problems of increased capacitance and resistance and increased signal transmission distance caused by medium-thickness wiring layers in traditional technology, thereby achieving product customization and a high degree of stacking. Simultaneously, the stacking of the first chip 140, the second chip 160, and the third chip 180 results in higher integration. Furthermore, the first encapsulation layer 150 covers the first chip 140, the second encapsulation layer 170 covers the second chip 160, and the third encapsulation layer 190 covers the third chip 180. The first encapsulation layer 150, the second encapsulation layer 170, and the third encapsulation layer 190 respectively achieve encapsulation. The encapsulation range of the first encapsulation layer 150, the second encapsulation layer 170, and the third encapsulation layer 190 is limited, which alleviates the phenomenon of uneven thermal stress at various points and avoids the stress warping problem caused by overall encapsulation.

[0037] Furthermore, a first bonding interconnect layer 111 is also provided in the third wiring region of the substrate wiring layer 110. The first chip 140 is flip-chip mounted on the first bonding interconnect layer 111 and electrically connected to the substrate wiring layer 110 through the first bonding interconnect layer 111. Specifically, the first bonding interconnect layer 111 includes a dielectric layer and metal pads disposed on the dielectric layer. In actual fabrication, a dielectric material can be first coated in the third wiring region to form a dielectric layer, and then exposed and electroplated to form metal pads. These metal pads are electrically connected to the substrate wiring layer 110. The first chip 140 is flip-chip mounted on the metal pads, realizing the electrical connection between the first chip 140 and the substrate wiring layer 110. The flip-chip structure used here can further improve the chip integration.

[0038] In some embodiments, a second bonding interconnect layer 131 is further disposed on the second stacked wiring layer 130. The second chip 160 is flip-chip mounted on the second bonding interconnect layer 131 and electrically connected to the second stacked wiring layer 130 through the second bonding interconnect layer 131. Specifically, the structure of the second bonding interconnect layer 131 can be the same as that of the first bonding interconnect layer 111, or it can be fabricated separately. The second bonding interconnect layer 131 also adopts a metal pad structure, using the metal pads to achieve the electrical connection between the second chip 160 and the second stacked wiring layer 130. The second chip 160 also adopts a flip-chip structure, which can further improve the chip integration.

[0039] In some embodiments, a third bonding interconnect layer 121 is further disposed on the first stacked wiring layer 120. The third chip 180 is flip-chip mounted on the third bonding interconnect layer 121 and electrically connected to the first stacked wiring layer 120 through the third bonding interconnect layer 121. Specifically, the structure of the third bonding interconnect layer 121 can be the same as that of the first bonding interconnect layer 111, or it can be fabricated separately. The third bonding interconnect layer 121 also adopts a metal pad structure, using the metal pads to achieve electrical connection between the third chip 180 and the third stacked wiring layer. The third chip 180 also adopts a flip-chip structure, which can further improve chip integration.

[0040] Furthermore, the height of the first chip 140 relative to the substrate wiring layer 110 is lower than the height of the second stacked wiring layer 130 relative to the substrate wiring layer 110, and the height of the second chip 160 relative to the substrate wiring layer 110 is lower than the height of the first stacked wiring layer 120 relative to the substrate wiring layer 110. By employing flip chips, the stacking height of the first chip 140 and the second chip 160 on the stepped structure can be effectively controlled, resulting in a relatively low height for the first chip 140 and the second chip 160, facilitating smooth encapsulation by the first encapsulation layer 150 and the second encapsulation layer 170.

[0041] In some embodiments, a first encapsulation layer 150 covers the first chip 140 and the second stacked wiring layer 130. A second encapsulation layer 170 is disposed on the side of the first encapsulation layer 150 away from the base wiring layer 110 and covers the second chip 160 and the first stacked wiring layer 120. A third encapsulation layer 190 is disposed on the side of the second encapsulation layer 170 away from the base wiring layer 110. Specifically, the first encapsulation layer 150, the second encapsulation layer 170, and the third encapsulation layer 190 can all be dielectric materials or molding compound materials. During molding, the first encapsulation layer 150 can cover the first chip 140 and simultaneously cover the surface of the second stacked wiring layer 130 away from the base wiring layer 110. This eliminates the need for additional dielectric layer fabrication when fabricating the second solder interconnect layer 131. Instead, grooves can be directly cut on the surface of the first encapsulation layer 150 corresponding to the second stacked wiring layer 130 and electroplated to form metal pads, reducing the number of steps. Similarly, the second encapsulation layer 170 can cover the second chip 160 during molding, and at the same time cover the side surface of the first stacked wiring layer 120 away from the base wiring layer 110. This eliminates the need for additional dielectric layer fabrication when fabricating the third solder interconnect layer 121. Instead, grooves can be directly cut on the surface of the second encapsulation layer 170 corresponding to the third stacked wiring layer and electroplated to form metal pads, reducing the number of steps.

[0042] Furthermore, the third encapsulation layer 190 is disposed on the first stacked wiring layer 120 and covers the third chip 180, and the edge of the third encapsulation layer 190 is flush with the edge of the first stacked wiring layer 120, so that the first encapsulation layer 150, the second encapsulation layer 170 and the third encapsulation layer 190 can also form a stepped structure, further mitigating the warping phenomenon.

[0043] See Figure 2 In some embodiments, the first encapsulation layer 150 is flush with the second stacked wiring layer 130, and the second encapsulation layer 170 is flush with the first stacked wiring layer 120, with the edge of the second encapsulation layer 170 aligned with the edge of the second stacked wiring layer 130. Specifically, in actual fabrication, the first encapsulation layer 150 only covers the first chip 140 and does not extend to the second stacked wiring layer 130, and the second encapsulation layer 170 only covers the second chip 160 and does not extend to the third stacked wiring layer. This design allows for a further reduction in the encapsulation range of the first encapsulation layer 150 and the second encapsulation layer 170, further mitigating warpage.

[0044] See Figure 3aIn some embodiments, a third encapsulation layer 190 is disposed on the first stacked wiring layer 120, the second encapsulation layer 170, and the first encapsulation layer 150, so that the third encapsulation layer 190 simultaneously covers the third chip 180, the second encapsulation layer 170, and the first encapsulation layer 150. Specifically, the edge of the third encapsulation layer 190 is flush with the edge of the substrate wiring layer 110. By expanding the coverage area of ​​the third encapsulation layer 190, the third encapsulation layer 190 can cover the stepped structure of the first encapsulation layer 150 and the second encapsulation layer 170, thereby improving the adhesion of the third encapsulation layer 190 and reducing the risk of the third encapsulation layer 190 peeling off.

[0045] See Figure 3b In some embodiments, a first encapsulation notch 141 is formed on the side of the first encapsulation layer 150 away from the first stacked wiring layer 120. The first encapsulation notch 141 is formed on the base wiring layer 110. A second encapsulation notch 142 is formed on the side of the second encapsulation layer 170 away from the first stacked wiring layer 120. The second encapsulation notch 142 is formed on the second stacked wiring layer 130. The third encapsulation layer 190 simultaneously encapsulates the third chip 180, the second encapsulation layer 170 and the first encapsulation layer 150, and fills the first encapsulation notch 141. Specifically, the edge of the third encapsulation layer 190 is flush with the edge of the base wiring layer 110, and the sidewall of the first encapsulation layer 150 is also covered within the third encapsulation layer 190. By expanding the coverage area of ​​the third encapsulation layer 190, the third encapsulation layer 190 can cover the entire stepped structure composed of the first encapsulation layer 150, the second encapsulation layer 170 and the base wiring layer 110, thereby improving the bonding strength of the third encapsulation layer 190 and reducing the risk of the third encapsulation layer 190 peeling off.

[0046] See Figure 4 and Figure 5 In some embodiments, a first antenna layer 151 is disposed on the side of the first encapsulation layer 150 away from the substrate wiring layer 110. The first antenna layer 151 is spaced apart from the second encapsulation layer 170, and a third encapsulation layer 190 covers the first antenna layer 151. Specifically, a layer of metal material can be deposited on the surface of the first encapsulation layer 150 to form the first antenna layer 151. The first antenna layer 151 can be an integrated structure of a metal layer and an inductor coil. Since the first antenna layer 151 is not disposed on the substrate wiring layer 110, parasitic capacitance and inductance can be reduced, and the capacitance effect can be optimized. Furthermore, the first antenna layer 151 can be covered by the third encapsulation layer 190, thereby providing protection while ensuring unobstructed transmission and better penetration.

[0047] See Figure 6Furthermore, a second antenna layer 171 is provided on the side of the second encapsulation layer 170 away from the substrate wiring layer 110. The second antenna layer 171 is spaced apart from the third chip 180, and the third encapsulation layer 190 covers the second antenna layer 171. Specifically, a metal material can be deposited on the surface of the second encapsulation layer 170 to form the second antenna layer 171. The second antenna layer 171 can be an integrated structure of a metal layer and an inductor coil. Since the second antenna layer 171 is not disposed on the substrate wiring layer 110 or the second stacked wiring layer 130, parasitic capacitance and inductance can be reduced, and the capacitance effect can be optimized. Furthermore, the second antenna layer 171 can be covered by the third encapsulation layer 190, thereby providing protection while ensuring that the emission is not blocked by the chip and has better penetration.

[0048] It is worth noting that the first antenna layer 151 and the second antenna layer 171 can be set separately or together; the specific configuration is not limited here. Furthermore, it should be noted that the first antenna layer 151 can be electrically connected to the second solder interconnect layer 131, and the second antenna layer 171 can be electrically connected to the third solder interconnect layer 121, thereby achieving electrical interconnection of the antenna layers.

[0049] See Figure 7 In some embodiments, the second stacked wiring layer 130 is disposed on both sides of the first stacked wiring layer 120, and the first chip 140 is disposed on the side of the second stacked wiring layer 130 away from the first stacked wiring layer 120. Specifically, the first stacked wiring layer 120 is located in the central region of the substrate wiring layer 110, the second stacked wiring layer 130 is located on both sides of the first stacked wiring layer 120, and the first chip 140 is disposed on the side of the second stacked wiring layer 130 away from the first stacked wiring layer 120, thereby forming a stepped structure on both sides, and the third encapsulation layer 190 can simultaneously encapsulate the first encapsulation layer 150 and the second encapsulation layer 170. On the one hand, it can improve the integration and stacking density of the chip and wiring structure; on the other hand, the third encapsulation layer 190 can simultaneously encapsulate the stepped structure on both sides, further improving the bonding strength of the third encapsulation layer 190.

[0050] This invention also provides a method for fabricating a 2.5D substrate interconnect package structure 100, which is used to fabricate the aforementioned substrate interconnect package structure. The method includes the following steps: S1: Provide one vehicle (200).

[0051] See Figure 8Specifically, a carrier 200 is provided, and a UV adhesive layer is coated on the surface of the carrier 200 to facilitate subsequent peeling. The carrier 200 can be a substrate or a base plate. A liquid adhesive layer is applied to the surface of the carrier 200 using a spin coater, and then the coating is set by a hot plate. The UV adhesive layer can be separated by irradiation with UV light. Materials include epoxy resin, polyimide, benzocyclobutene, and other polymer composite materials.

[0052] S2: A base wiring layer 110 is formed on the carrier 200.

[0053] See Figure 9 Specifically, the substrate circuit layer can be a combination of multiple wiring layers and multiple dielectric layers. In actual fabrication, a dielectric material can be coated first, followed by exposure and development to form patterned layer openings. Then, an electroplating process is used to form the wiring layer, and finally, a spin coating process is used to form the dielectric material again. After multiple coatings and electroplating, the substrate circuit layer is formed. It should be noted that the fabrication process of the substrate circuit layer here can refer to the fabrication process of redistribution layers in the prior art.

[0054] S3: A photosensitive layer 210 is formed on the substrate wiring layer 110.

[0055] See Figure 10 Specifically, a photosensitive layer 210, which is a photosensitive material, can be coated on the surface of the substrate circuit layer using a spin coating process.

[0056] S4: Partially remove the photosensitive layer 210 to form a first opening, wherein the first opening exposes a first wiring area of ​​the substrate wiring layer 110.

[0057] See Figure 11 Specifically, a portion of the photosensitive layer 210 can be removed through an exposure and development process to form a first opening, which exposes the substrate wiring layer 110. The area of ​​the substrate wiring layer 110 exposed by the first opening can be designated as the first wiring area.

[0058] S5: A first stacked wiring layer 120 is formed on the base wiring layer 110 within the first opening, wherein the first stacked wiring layer 120 is electrically connected to the base wiring layer 110.

[0059] See Figure 12Specifically, a first stacked wiring layer 120 can be formed in the first wiring region. In forming the first stacked wiring layer 120, a first dielectric layer can be formed using a spin-coating process, followed by an exposure and development process to form patterned openings on the first dielectric layer, then electroplating to form the first wiring layer. A second dielectric layer is then formed again using spin-coating, followed by an exposure and development process to form patterned openings on the second dielectric layer, and then electroplating to form the second wiring layer. This process can form multiple dielectric layers and multiple wiring layers, thus forming the first stacked wiring layer 120. The fabrication process of the first stacked wiring layer 120 can also refer to the fabrication process of multilayer redistribution layers in the prior art.

[0060] S6: Partially remove the photosensitive layer 210 around the first stacked wiring layer 120 to form a second opening, wherein the second opening exposes the second wiring area of ​​the base wiring layer 110.

[0061] See Figure 13 Specifically, a portion of the photosensitive layer 210 can be removed using an exposure and development process to form a second opening, which also exposes the substrate wiring layer 110. The area of ​​the substrate wiring layer 110 exposed by this second opening can be designated as a second wiring region. After the fabrication of the first stacked wiring layer 120 is completed, the photosensitive layer 210 can be coated using an exposure and development process, and the photosensitive layer 210 can be decomposed using ultraviolet light, thereby forming a second opening between the first stacked wiring layer and the remaining photosensitive layer 210. The second opening exposes the substrate wiring layer.

[0062] S7: A second stacked wiring layer 130 is formed on the base wiring layer 110 within the second opening, wherein the second stacked wiring layer 130 is electrically connected to the base wiring layer 110.

[0063] See Figure 14 Specifically, referring to the process of the first stacked wiring layer 120, a multi-layered second stacked wiring layer 130 is formed on the base wiring layer 110 inside the second opening, and the number of stacked layers of the second stacked wiring layer 130 is less than the number of layers of the first stacked wiring layer 120.

[0064] The height of the first stacked wiring layer 120 relative to the base wiring layer 110 is greater than the height of the second stacked wiring layer 130 relative to the base wiring layer 110.

[0065] S8: Remove the remaining photosensitive layer 210 to form a third opening, wherein the third opening exposes the third wiring area of ​​the substrate wiring layer 110.

[0066] See Figure 15Specifically, the photosensitive layer 210 can be applied using an exposure and development process, and the photosensitive layer 210 can be decomposed using ultraviolet light. Finally, the remaining photosensitive layer 210 can be cleaned using chemical agents, so that the remaining photosensitive layer 210 can be removed, and a third opening can be formed on the side of the second stacked wiring layer 130 away from the first stacked wiring layer 120.

[0067] S9: The first chip 140 is mounted on the substrate wiring layer 110 inside the third opening, and the first chip 140 is electrically connected to the substrate wiring layer 110.

[0068] See Figure 16 Specifically, a first solder interconnect layer 111 is first formed on the substrate wiring layer 110 within the third opening, and then a first chip 140 is mounted on the first solder interconnect layer 111. The first chip 140 is a flip-chip structure.

[0069] S10: A first encapsulation layer 150 is formed on the substrate wiring layer 110 within the third opening, and the first encapsulation layer 150 at least covers the first chip 140.

[0070] See Figure 17 Specifically, a first encapsulation layer 150 is formed by a molding process. The first encapsulation layer 150 may be a dielectric material, and the first encapsulation layer 150 may cover the first chip 140 and extend to cover the side of the second stacked wiring layer 130 away from the base wiring layer 110.

[0071] S11: The second chip 160 is mounted on the second stacked wiring layer 130 and is electrically connected to the second stacked wiring layer 130.

[0072] See Figure 18 Specifically, before mounting the second chip 160, the second solder interconnect layer 131 can be prepared first. After slotting on the first encapsulation layer 150 in the corresponding area of ​​the second stacked wiring layer 130, metal pads are formed by electroplating. Then the second chip 160 is mounted. The second chip 160 is a flip chip.

[0073] S12: A second encapsulation layer 170 is formed on the second stacked wiring layer 130, and the second encapsulation layer 170 at least covers the second chip 160.

[0074] See Figure 19 Specifically, using the same molding process, a second encapsulation layer 170 is formed on the second stacked wiring layer 130. The edge of the second encapsulation layer 170 away from the first stacked wiring layer 120 is flush with the edge of the second stacked wiring layer 130, while the other side of the second encapsulation layer 170 can extend to the surface of the first stacked wiring layer 120, thereby simultaneously covering the second chip 160 and the surface of the first stacked wiring layer 120 away from the base wiring layer 110.

[0075] S13: A third chip 180 is mounted on the first stacked wiring layer 120, and the third chip 180 is electrically connected to the first stacked wiring layer 120.

[0076] See Figure 20 Specifically, before mounting the third chip 180, the third solder interconnect layer 121 can be prepared and then mounted on the first stacked wiring layer 120 via a flip-chip process.

[0077] S14: A third encapsulation layer 190 is formed on the first stacked wiring layer 120, and the third encapsulation layer 190 at least covers the third chip 180.

[0078] See Figure 21 Specifically, a third encapsulation layer 190 can be formed through a molding process. The third encapsulation layer 190 can only cover the third chip 180, and the two side edges of the third encapsulation layer 190 are flush with the two side edges of the first stacked wiring layer 120, so that the first encapsulation layer 150, the second encapsulation layer 170 and the third encapsulation layer 190 also form a stepped structure.

[0079] See Figure 22 After the third encapsulation layer 190 is prepared, the carrier 200 can be removed, and the metal layer and solder balls can be prepared on the side of the substrate wiring layer 110 away from the third encapsulation layer 190. Finally, the product is cut to obtain a single unit.

[0080] In some other embodiments, the step of forming a third encapsulation layer 190 on the first stacked wiring layer 120 includes: forming a third encapsulation layer 190 on the first stacked wiring layer 120, the second encapsulation layer 170 and the first encapsulation layer 150, wherein the third encapsulation layer 190 simultaneously encapsulates the third chip 180, the second encapsulation layer 170 and the first encapsulation layer 150.

[0081] In some other embodiments, prior to the step of forming the third encapsulation layer 190 on the first stacked wiring layer 120, the method further includes: forming a first antenna layer 151 on the side of the first encapsulation layer 150 away from the substrate wiring layer 110; wherein the third encapsulation layer 190 covers the first antenna layer 151. A second antenna layer 171 is formed on the side of the second encapsulation layer 170 away from the substrate wiring layer 110; wherein the third encapsulation layer 190 covers the second antenna layer 171.

[0082] In summary, the 2.5D substrate interconnect package structure 100 and its fabrication method provided in this embodiment of the invention provide a first stacked wiring layer 120 in a first wiring region of the substrate wiring layer 110, a second stacked wiring layer 130 in a second wiring region, and a first chip 140 in a third wiring region. The height of the first stacked wiring layer 120 relative to the substrate wiring layer 110 is greater than the height of the second stacked wiring layer 130 relative to the substrate wiring layer 110, thus forming a stepped stacked wiring structure. This allows for different numbers of wiring layers in different wiring regions, enabling product customization, and achieving a high degree of stacking and integration. Furthermore, the first encapsulation layer 150 encapsulates the first chip 140, the second encapsulation layer 170 encapsulates the second chip 160, and the third encapsulation layer 190 encapsulates the third chip 180. The separate encapsulation by the first encapsulation layer 150, the second encapsulation layer 170, and the third encapsulation layer 190 avoids stress warping problems caused by overall encapsulation. Compared to existing technologies, the 2.5D substrate interconnect packaging structure 100 provided in this embodiment of the invention can achieve different wiring layers in different regions, thereby enabling product customization. It also has a high degree of stacking and integration. Furthermore, by encapsulating the chip with different encapsulations, the stress warping phenomenon of the molding compound can be mitigated.

[0083] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A 2.5D substrate interconnect package structure, characterized by, The application comprises: a base wiring layer; a first stacked wiring layer arranged at a first wiring area of the base wiring layer, the first stacked wiring layer being electrically connected with the base wiring layer; a second stacked wiring layer arranged at a second wiring area of the base wiring layer, wherein the second stacked wiring layer is arranged at least at one side of the first stacked wiring layer, the second stacked wiring layer being electrically connected with the base wiring layer; a first chip arranged at a third wiring area of the base wiring layer, the first chip being electrically connected with the base wiring layer; a first encapsulation layer arranged at the third wiring area of the base wiring layer, the first encapsulation layer at least covering the first chip; a second chip arranged on the second stacked wiring layer, the second chip being electrically connected with the second stacked wiring layer; a second encapsulation layer arranged on the second stacked wiring layer, the second encapsulation layer at least covering the second chip; a third chip arranged on the first stacked wiring layer, the third chip being electrically connected with the first stacked wiring layer; a third encapsulation layer arranged at least on the first stacked wiring layer, the third encapsulation layer at least covering the third chip; wherein a height of the first stacked wiring layer relative to the base wiring layer is greater than a height of the second stacked wiring layer relative to the base wiring layer.

2. The 2.5D substrate interconnect package structure of claim 1, wherein, The third wiring area of the base wiring layer is further provided with a first solder interconnection layer, the first chip is attached on the first solder interconnection layer and is electrically connected with the base wiring layer through the first solder interconnection layer; the second stacked wiring layer is further provided with a second solder interconnection layer, the second chip is attached on the second solder interconnection layer and is electrically connected with the second stacked wiring layer through the second solder interconnection layer; the first stacked wiring layer is further provided with a third solder interconnection layer, the third chip is attached on the third solder interconnection layer and is electrically connected with the first stacked wiring layer through the third solder interconnection layer.

3. The 2.5D substrate interconnect package structure of claim 1, wherein, The height of the first chip relative to the base wiring layer is lower than the height of the second stacked wiring layer relative to the base wiring layer, and the height of the second chip relative to the base wiring layer is lower than the height of the first stacked wiring layer relative to the base wiring layer.

4. The 2.5D substrate interconnect package structure of claim 3, wherein, The first encapsulation layer is flush with the second stacked wiring layer, the second encapsulation layer is flush with the first stacked wiring layer, and the edge of the second encapsulation layer is aligned with the edge of the second stacked wiring layer.

5. The 2.5D substrate interconnect package structure of claim 3, wherein, The first encapsulation layer covers the first chip and the second stacked wiring layer, the second encapsulation layer is arranged at a side of the first encapsulation layer away from the base wiring layer and covers the second chip and the first stacked wiring layer, and the third encapsulation layer is arranged at a side of the second encapsulation layer away from the base wiring layer.

6. The 2.5D substrate interconnect package structure of claim 3, wherein, The third encapsulation layer is arranged on the first stacked wiring layer, the second encapsulation layer and the first encapsulation layer, so that the third encapsulation layer covers the third chip, the second encapsulation layer and the first encapsulation layer at the same time.

7. The 2.5D substrate interconnect package structure of claim 1, wherein, The first encapsulation layer is further formed with a first encapsulation notch on a side away from the first stacked wiring layer, the second encapsulation layer is further formed with a second encapsulation notch on a side away from the first stacked wiring layer, and the third encapsulation layer is simultaneously encapsulated on the third chip, the second encapsulation layer and the first encapsulation layer, and fills the first encapsulation notch and the second encapsulation notch.

8. The 2.5D substrate interconnect package structure of claim 1, wherein, The first encapsulation layer is further formed with a first encapsulation notch on a side away from the first stacked wiring layer, the second encapsulation layer is further formed with a second encapsulation notch on a side away from the first stacked wiring layer, and the third encapsulation layer is simultaneously encapsulated on the third chip, the second encapsulation layer and the first encapsulation layer, and fills the first encapsulation notch and the second encapsulation notch.

9. The 2.5D substrate interconnect package structure of claim 1 or 8, wherein, The second encapsulation layer is further formed with a second antenna layer on a side away from the base wiring layer, the second antenna layer is spaced apart from the third chip, and the third encapsulation layer is encapsulated on the second antenna layer.

10. The 2.5D substrate interconnect package structure of claim 1, wherein, The second stacked wiring layer is arranged on both sides of the first stacked wiring layer, and the first chip is arranged on a side of the second stacked wiring layer away from the first stacked wiring layer.

11. A method of fabricating a 2.5D substrate interconnect package structure for fabricating the substrate interconnect package structure of claim 1, wherein, Comprising: providing a carrier; forming a base wiring layer on the carrier; forming a photosensitive layer on the base wiring layer; partially removing the photosensitive layer to form a first opening, wherein the first opening exposes a first wiring area of the base wiring layer; forming a first stacked wiring layer on the base wiring layer in the first opening, wherein the first stacked wiring layer is electrically connected to the base wiring layer; partially removing the photosensitive layer around the first stacked wiring layer to form a second opening, wherein the second opening exposes a second wiring area of the base wiring layer; forming a second stacked wiring layer on the base wiring layer in the second opening, wherein the second stacked wiring layer is electrically connected to the base wiring layer; removing the remaining photosensitive layer to form a third opening, wherein the third opening exposes a third wiring area of the base wiring layer; mounting a first chip on the base wiring layer in the third opening, the first chip being electrically connected to the base wiring layer; forming a first encapsulation layer on the base wiring layer in the third opening, the first encapsulation layer being encapsulated at least on the first chip; mounting a second chip on the second stacked wiring layer, the second chip being electrically connected to the second stacked wiring layer; forming a second encapsulation layer on the second stacked wiring layer, the second encapsulation layer being encapsulated at least on the second chip; mounting a third chip on the first stacked wiring layer, the third chip being electrically connected to the first stacked wiring layer; forming a third encapsulation layer on the first stacked wiring layer, the third encapsulation layer being encapsulated at least on the third chip; wherein the height of the first stacked wiring layer relative to the base wiring layer is greater than the height of the second stacked wiring layer relative to the base wiring layer.

12. The method of claim 11, wherein the 2.5D substrate interconnect package structure is prepared by: The step of forming a third encapsulation layer on the first stacked wiring layer comprises: forming a third encapsulation layer on the first stacked wiring layer, the second encapsulation layer, and the first encapsulation layer, wherein the third encapsulation layer simultaneously encapsulates the third chip, the second encapsulation layer, and the first encapsulation layer.

13. The method of claim 12, wherein the 2.5D substrate interconnect package structure is prepared by: Before the step of forming the third encapsulation layer on the first stacked wiring layer, the method comprises: forming a first antenna layer on a side of the first encapsulation layer away from the base wiring layer; wherein the third encapsulation layer encapsulates the first antenna layer.

14. The method of claim 11 or 13, wherein the 2.5D substrate interconnect package structure is prepared by the steps of: providing a substrate; forming a plurality of through-substrate vias in the substrate; forming a plurality of redistribution layers on the substrate; and forming a plurality of bumps on the redistribution layers. Before the step of forming the third encapsulation layer on the first stacked wiring layer, the method comprises: forming a second antenna layer on a side of the second encapsulation layer away from the base wiring layer; wherein the third encapsulation layer encapsulates the second antenna layer.

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