Floating-point number multiplication and accumulation processor based on spinning electron storage device

Abstract

The invention belongs to the field of integrated circuit design, and particularly relates to a floating-point number multiplication and accumulation processor based on a spinning electron storage device. A magnetic domain wall device (which is a nonvolatile memory device and has the advantages of non-volatility, high density, zero static power consumption, high durability and the like) driven by the spin Hall effect is utilized to efficiently realize in-situ write-in, read-out and shift operation of data, the magnetic domain wall device is combined to be used for multiplication and accumulation of floating-point numbers, MAC operation of the floating-point numbers is realized by using an analog circuit and a magnetic device, and the device is simple in structure and convenient to operate. And exponential part operation is carried out on a time domain, and a mantissa alignment function is realized by using a magnetic device, so that the total power consumption of the circuit is greatly reduced, and energy-saving optimization of the circuit is realized. According to the method, the inherent defects of high calculation power consumption of a traditional CMOS scheme and low volatility and density of an SRAM scheme are fundamentally avoided, and finally high-performance and high-energy-efficiency AI calculation far higher than the level of the prior art is achieved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a floating-point multiply-accumulate processor based on spintronic memory devices. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and high-performance computing, the demand for high-precision, high-energy-efficiency floating-point multiply-accumulate (MAC) operations is becoming increasingly urgent. However, traditional CMOS-based floating-point MAC processors face severe energy consumption challenges when performing these operations. On the one hand, floating-point operations themselves involve complex steps such as exponent alignment, mantissa multiplication and addition, normalization, and rounding, requiring large-scale digital logic circuits for implementation. This directly leads to huge dynamic switching power consumption and static leakage power consumption. On the other hand, these processors generally adopt the von Neumann architecture with in-memory separation. When processing massive amounts of data, frequent data transfer between the processor and memory leads to a severe "memory wall" bottleneck, further exacerbating overall latency and energy consumption.

[0003] To address the "memory wall" problem, in-memory computing technology based on static random access memory (SRAM) has been proposed as a solution. It reduces data movement by integrating computing and storage units. However, its inherent volatility, high static power consumption, and limited storage density restrict its application potential in building large-scale, energy-efficient computing arrays, and it does not fundamentally solve the power consumption problem. Summary of the Invention

[0004] To address the aforementioned problems or shortcomings and to solve the high power consumption issue of existing floating-point MAC processors, this invention provides a floating-point multiply-accumulate (MAC) processor based on spintronic memory devices. This processor achieves low power consumption while performing complex multiply-accumulate MAC operations.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A floating-point multiply-accumulate processor based on spintronic memory devices includes a multiplier, a time-domain adder, a maximum exponent search circuit, a mantissa alignment signal generation circuit, a mantissa alignment module based on a magnetic domain wall device, and an accumulator. The processor receives digital signals of n sets of input data and n sets of weight data, and outputs digital signals of the output sign bit, the output exponent, and the output mantissa.

[0007] The multiplier multiplies the mantissa digital signal of each of the n sets of input data with the mantissa digital signal of the corresponding weight data to obtain n sets of mantissa product digital signals, and outputs them; wherein, there are n sets of weight data, which correspond one-to-one with the n sets of input data; the input data includes the digital signal of the sign bit, the digital signal of the exponent, and the digital signal of the mantissa.

[0008] The time-domain adder converts the exponential digital signals of n sets of input data and the exponential digital signals of n sets of weight data into the delay time of the edge of a voltage pulse signal in the time domain. It then adds the edge delay time of the exponential part of each set of input data and the corresponding exponential part of weight data to obtain a total of n sets of voltage pulse signals with exponential summation after delay, which is used as the output of the time-domain adder.

[0009] The maximum exponent search circuit finds the voltage pulse signal with the largest exponent sum from the n outputs of the time-domain adder, and uses this signal as the output of the maximum exponent search circuit to the mantissa alignment signal generation circuit. Simultaneously, it converts the voltage pulse signal with the largest exponent sum into a digital signal with the largest exponent sum, which is directly used as the final output exponent of the MAC operation.

[0010] The mantissa alignment signal generation circuit subtracts the voltage pulse signal of the sum of n exponents generated by the time-domain adder from the voltage pulse signal of the sum of the maximum exponents generated by the maximum exponent search circuit, respectively, to obtain the voltage pulse signal of the difference of the sum of n exponents, and outputs it to the mantissa alignment module based on the magnetic domain wall memory.

[0011] The mantissa alignment module based on the domain wall memory includes a VI converter, a DI converter, a domain wall memory, and an ID converter. Based on the voltage pulse signal of the difference between the sums of n exponents output by the mantissa alignment signal generation circuit, the n mantissa product digital signals output by the multiplier are shifted and aligned through the domain wall memory to obtain n aligned mantissa product digital signals.

[0012] The VI converter converts the voltage pulse signal, which is the difference of the sum of n exponents output by the mantissa alignment signal generation circuit, into a current pulse signal, which is the difference of the sum of n exponents.

[0013] The DI converter converts the n sets of mantissa product digital signals output by the multiplier into n sets of mantissa product current pulse signals.

[0014] The domain wall memory consists of n domain wall devices driven by the spin Hall effect, where n is the number of input data sets for MAC operations. Each domain wall device includes a magnetic nanowire, a write magnetic tunnel junction, and a read magnetic tunnel junction. n sets of mantissa product current pulse signals and n sets of exponent sum difference current pulse signals are input into the domain wall memory to obtain n aligned mantissa product current pulse signals.

[0015] The ID converter converts the current pulse signal of the n-group aligned mantissa product output from the domain wall memory into a digital signal of the n-group aligned mantissa product, and outputs it to the accumulator.

[0016] The accumulator performs an accumulation operation on the digital signal of the product of n aligned mantissas according to the sign information of the sign bit of each group of input data, to obtain the final digital signal of the output mantissa part and the digital signal of the output sign bit of the MAC operation.

[0017] The final outputs of the floating-point multiply-accumulate processor based on spintronic memory devices are: the digital signal of the maximum exponent sum, the digital signal of the mantissa portion, and the digital signal of the sign bit.

[0018] Furthermore, for the domain wall device driven by the spin Hall effect, the specific workflow is as follows: first, the current pulse signal of the product of each set of mantissas is input to the write magnetic tunnel junction of the domain wall device; then, the current pulse signal of the difference of the sum of each set of exponents is input to the magnetic nanowire; finally, the aligned current pulse signal of the product of mantissas is obtained from the readout magnetic tunnel junction.

[0019] Furthermore, the time-domain adder is composed of several edge delay units cascaded together.

[0020] This invention provides a floating-point multiply-accumulate processor based on spintronic memory devices, in which the exponential part of the input data and the exponential part of the corresponding weighted data are delayed by the edge of an externally input pulse signal, and the delay time is added in the time domain to obtain a voltage pulse signal with a delayed exponential sum. Then, the voltage pulse signal with the largest exponential sum is found among n sets of exponential sum voltage pulse signals. The voltage pulse signal with the largest exponential sum is converted into a digital signal, which is used as the exponential part of the final MAC operation. On the other hand, the voltage pulse signal with the largest exponential sum is compared with each of the n sets of exponential sum voltage pulse signals and the difference is calculated to obtain a voltage pulse signal with the difference of the n sets of exponential sums.

[0021] For the mantissa portion of the input data, it is multiplied by the mantissa portion of the corresponding weighted data to obtain n sets of mantissa product digital signals, which are then converted into n sets of mantissa product current pulse signals. The voltage pulse signal representing the difference between the n exponential sums is then passed through a mantissa alignment module based on magnetic domain wall devices to control the mantissa products stored in magnetic nanowires for mantissa alignment, resulting in aligned mantissa product current pulse signals, which are then converted into digital signals. The n magnetic domain wall memories then output the n sets of aligned mantissa product digital signals.

[0022] Finally, the accumulator performs an accumulation operation on the n aligned mantissa product digital signals according to the sign information of the sign bit of each group of input data, to obtain the final output mantissa digital signal and the output sign bit digital signal of the MAC operation.

[0023] In summary, this invention utilizes spin Hall effect-driven magnetic domain wall devices (non-volatile memory devices with advantages such as non-volatility, high density, zero static power consumption, and high durability) to efficiently achieve in-situ data writing, reading, and shifting operations. These devices are then combined for floating-point multiplication and accumulation. Analog circuits and magnetic devices are used to implement floating-point MAC operations, performing exponentiation in the time domain. Magnetic devices are used to achieve mantissa alignment, significantly reducing the overall circuit power consumption and achieving energy-saving optimization. This invention fundamentally avoids the high power consumption of traditional CMOS solutions and the inherent defects of SRAM solutions, such as volatility and low density, ultimately achieving high-performance and energy-efficient AI computing far exceeding existing technologies. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of floating-point MAC operations;

[0025] Figure 2 This is an overall flowchart of the present invention;

[0026] Figure 3 The circuit diagram of the edge delay unit in the embodiment;

[0027] Figure 4 Here is the truth table for the edge delay unit in this embodiment;

[0028] Figure 5 This is a schematic diagram of the output pulse waveform of the mantissa alignment signal generation circuit in the embodiment;

[0029] Figure 6 This is a schematic diagram of the magnetic domain wall device used in the embodiment;

[0030] Figure 7 This is a schematic diagram of two different magnetoresistive states of the magnetic tunnel junction in the domain wall device of the embodiment;

[0031] Figure 8 This is a specific block diagram of the mantissa alignment module based on the domain wall memory in the embodiment;

[0032] Figure 9 The above is a simulation waveform diagram of the time-domain adder in the embodiment. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0034] This invention aims to implement floating-point multiplication and accumulation operations, as illustrated in the diagram below. Figure 1 As shown, each of the n sets of input data needs to be multiplied by its corresponding weight data first, and then the results of the n multiplications are accumulated to obtain the final result of the multiplication-accumulation operation. The floating-point type used in this embodiment is BF16.

[0035] In this embodiment, the overall flowchart of the operation is as follows: Figure 2 As shown: The digital signals of the exponent portion of n sets of input data are input to a time-domain adder, and added in the time domain to each of the digital signals of the exponent portion of n sets of weight data, resulting in a voltage pulse signal of n exponential sums. A maximum exponent search circuit searches for the voltage pulse signal of the maximum exponential sum among the voltage pulse signals of the n exponential sums. In the mantissa alignment signal generation circuit, the voltage pulse signal of the maximum exponential sum is compared with each of the voltage pulse signals of the n exponential sums and the difference is calculated, resulting in a voltage pulse signal of the difference between the n exponential sums. Each of the digital signals of the mantissa portion of the n sets of input data is multiplied by each of the digital signals of the mantissa portion of the n sets of weight data, resulting in a digital signal of n mantissa products. This digital signal, along with the voltage pulse signal of the difference between the n exponential sums, is input to a floating-point multiplier-accumulator based on a spintronic memory device, resulting in a digital signal of n aligned mantissa products. The digital signal of the product of n aligned mantissas and the sign bit of each input data group are input into an accumulator to obtain the final digital signal of the mantissa portion and the digital signal of the sign bit of the MAC operation. The voltage pulse signal of the maximum exponent sum is converted into a digital signal to obtain the digital signal of the exponent portion of the output. The output sign bit, the output exponent portion, and the output mantissa portion constitute the final output of the MAC operation.

[0036] The multiplier multiplies the mantissa of n sets of input data with the corresponding mantissa of n sets of weights that were multiplied with the input data. For BF16 floating-point data types, the number of bits in the resulting n mantissa products is the same as the number of bits in the mantissa of the input data; that is, the first eight bits are selected as the multiplier output. The output n mantissa products are in digital signal form.

[0037] A time-domain adder converts a digital signal bit-by-bit into a voltage pulse signal in the time domain by adjusting the edge delay time. In this embodiment, the time-domain adder is composed of 30n cascaded edge delay units. The internal circuitry of each edge delay unit is as follows: Figure 3 As shown, the truth table of the edge delay unit is as follows: Figure 4 As shown. The V value of the edge delay unit. IN The input terminal receives a pulse signal with a sufficiently long pulse width. If V R V F Both are high level, output terminal V OUT The resulting delay is negligible; if V R Low level, V F When the voltage is high, MN3 is off, and the bias voltage V is high. A This will cause a certain delay and inversion on the rising edge of the input signal, while the falling edge will be unaffected. V MID Terminal output V IN The inverted signal, V MID The falling edge compared to V IN The rising edge has a fixed delay of Δt, V MID The rising edge has almost no delay, while V MID To V OUT The delay between them is negligible compared to Δt, therefore V OUT Output and V IN In-phase pulse signals with a rising edge delay of Δt and no falling edge delay; if V R High level, V F V is low level. MID The signal is V IN The signal is inverted and has no delay, V OUT Output and V IN A pulse signal that is in phase, has no delay on the rising edge, and has a delay of Δt on the falling edge. The delay time is determined by the process angle, temperature, and bias voltage V. A It is determined by factors such as these.

[0038] The exponent portions of the input data are added in the time-domain adder. The floating-point type is BF16, and the exponent portion has 8 bits. Edge delay units are cascaded according to weighted relationships to obtain an adder for the exponent input data in the time domain. A pulse signal IN is input to the edge delay module, and the exponent portion E of the nth input data... INn The [7:4] bit and weighted data index part E Wn The [7:4] bits are sequentially accumulated into the delay of the rising edge of IN, E INn and E Wn Bits [3:0] are accumulated into the delay of the falling edge of IN, and the voltage pulse signal after the delay and exponential summation is DE. n .

[0039] n sets of delayed, exponentially summed voltage pulse signals DE0, DE1...DE n Input the value into the maximum exponent search circuit to find the maximum exponent sum DE. MAX At the same time, the voltage pulse signal DE MAX Converted to digital signal E OUT This serves as the final output exponent of the MAC operation. The maximum exponent is summed to form DE. MAX Sum of the nth exponent DE n By comparison, the voltage pulse signal V representing the difference of the nth group of exponential sums is obtained. SHIFTn ,like Figure 5 As shown.

[0040] A mantissa alignment module based on a domain wall memory is used to perform the mantissa product shifting, such as... Figure 6 As shown. The domain wall memory consists of n spin Hall effect driven domain wall devices. One spin Hall effect driven domain wall device comprises a magnetic nanowire, a write magnetic tunnel junction, and a read magnetic tunnel junction. The spin electrons in the magnetic tunnel junction have two different states, such as... Figure 7 As shown, the spin electron direction in the upper part is fixed and cannot be changed, while the spin electron direction in the lower part changes according to the magnitude of the input write current. If the two spin electron directions in the upper and lower parts of the magnetic tunnel junction are the same, the magnetoresistance of the magnetic tunnel junction is a low-resistance state; otherwise, it is a high-resistance state. Magnetic nanowires contain magnetic domains, with adjacent domains separated by domain walls. The spin electron direction in the domain is determined by the polarity of the write pulse current in the magnetic tunnel junction. When the current is positive, the magnetic tunnel junction is in a low-resistance state, and the spin electron directions in the upper and lower parts are the same; when the current is negative, the magnetic tunnel junction is in a high-resistance state, and the spin electron directions in the upper and lower parts are opposite.

[0041] In magnetic domain wall devices, a shift current is injected into magnetic nanowires to shift the written data. The direction of the shift current determines the direction of the shifted stored data. The shift current shifts the written data in either the forward or reverse direction, moving the magnetic domains with altered spin electron orientations within the magnetic nanowires, thus enabling the next write or read operation.

[0042] In domain wall devices, a pulse signal containing readout data can be obtained from the output of the readout magnetic tunnel junction. A readout voltage is applied across the upper and lower ends of the readout magnetic tunnel junction, while a shift current controls the movement of the magnetic domain containing the readout data within the magnetic nanowire. If the spin electrons in the upper and lower parts of the magnetic tunnel junction are in opposite directions, a high-resistivity state is observed, and the current output from the readout magnetic tunnel junction is small; if the spin electrons in the upper and lower parts of the magnetic tunnel junction are in the same direction, a low-resistivity state is observed, and the current output from the readout magnetic tunnel junction is large. Simultaneously, the shift current controls the movement of the spin electrons in the magnetic domain, and the readout magnetic tunnel junction continuously outputs a current pulse signal according to the spin electron direction.

[0043] like Figure 8 As shown, the digital signal M, which is the product of the nth group of mantissas output by the multiplier, is... Mn First, it is converted into a current pulse signal I, which is the product of the nth group of mantissas, by a DI converter. WRITEn The high level is converted to a negative current, and the low level is converted to a positive current, which is then input to the write magnetic tunnel junction of the nth domain wall device. Next, the voltage pulse signal V, representing the difference between the sums of the nth set of exponents output by the mantissa alignment signal generation circuit, is... SHIFTn The signal is converted into the difference current pulse signal I of the nth exponential sum through a VI converter. SHIFTn The signal is input to the magnetic nanowire to control the movement of spin electrons in the stored magnetic domains. Then, a current pulse signal I, the product of the first eight mantissas aligned to the readout magnetic tunnel junction, is selected. READn I READn The ID converter then converts the result into an aligned mantissa product digital signal M. An It has 8 digits.

[0044] n sets of input data sign bits of digital signal S IN0 S IN1 ...S INn The digital signal M, consisting of n aligned mantissa products output by the mantissa alignment module based on the domain wall memory. A0 M A1 ...M An As input, the digital signal M of the final output mantissa of the MAC operation is obtained. OUT and the digital signal S of the output sign bit OUT .

[0045] Figure 9 The simulation waveform diagram of the time-domain adder shows the first input pulse waveform IN and the output waveforms corresponding to the four different input codewords, where E... IN When =1111, the output pulse DE is... 1111 Minimum delay; E IN =1111 and E INThe rising edges of the pulses between =1110 differ by a Δt, E IN =1110 and E IN The rising edges of the pulses between 1100 and 2Δt differ by 2Δt, E IN =1100 and E IN The rising edges of pulses between 1000 and 1000 differ by 4Δt. This demonstrates the accuracy of the simulation of the circuit portion of this invention.

[0046] As can be seen from the above embodiments, this invention utilizes a spin Hall effect-driven magnetic domain wall device to efficiently achieve in-situ data writing, reading, and shifting operations. This is combined for floating-point multiplication and accumulation, with analog circuits and magnetic devices used to implement floating-point MAC operations. Exponent operations are performed in the time domain, and mantissa alignment is achieved using magnetic devices, significantly reducing the overall circuit power consumption and achieving energy-saving optimization. This invention fundamentally avoids the high power consumption of traditional CMOS solutions and the inherent defects of SRAM solutions, such as volatility and low density, ultimately achieving high-performance and high-energy-efficiency AI computing far exceeding existing technologies.

Claims

1. A floating-point multiply-accumulate processor based on spintronic memory devices, characterized in that: It includes a multiplier, a time-domain adder, a maximum exponent search circuit, a mantissa alignment signal generation circuit, a mantissa alignment module based on a magnetic domain wall device, and an accumulator; it inputs the digital signals of n sets of input data and n sets of weight data into the processor, and the output results include the digital signal of the output sign bit, the digital signal of the output exponent, and the digital signal of the output mantissa; The multiplier multiplies the mantissa digital signal of each of the n sets of input data with the mantissa digital signal of the corresponding weight data to obtain n sets of mantissa product digital signals, and outputs them; wherein, there are n sets of weight data, which correspond one-to-one with the n sets of input data. The time-domain adder converts the exponential digital signals of n sets of input data and the exponential digital signals of n sets of weight data into the delay time of the edge of the voltage pulse signal in the time domain, and adds the edge delay time of the exponential part of each set of input data and the corresponding exponential part of weight data to obtain a total of n sets of voltage pulse signals with exponential summation after delay, which is used as the output of the time-domain adder. The maximum exponent search circuit finds the voltage pulse signal with the largest exponent sum from the n outputs of the time-domain adder, and uses it as the output of the maximum exponent search circuit to the mantissa alignment signal generation circuit; at the same time, it converts the voltage pulse signal with the largest exponent sum into a digital signal with the largest exponent sum, and uses it directly as the final output exponent of the MAC operation. The mantissa alignment signal generation circuit subtracts the voltage pulse signal of the sum of n exponents generated by the time-domain adder from the voltage pulse signal of the sum of the maximum exponents generated by the maximum exponent search circuit, respectively, to obtain the voltage pulse signal of the difference of the n sums of exponents, and outputs it to the mantissa alignment module based on the magnetic domain wall memory. The mantissa alignment module based on the domain wall memory includes a VI converter, a DI converter, a domain wall memory, and an ID converter; based on the voltage pulse signal of the difference between the sums of n exponents output by the mantissa alignment signal generation circuit, the n mantissa product digital signals output by the multiplier are shifted and aligned through the domain wall memory to obtain n aligned mantissa product digital signals. The VI converter converts the voltage pulse signal, which is the difference of the sum of n exponents, output by the mantissa alignment signal generation circuit, into a current pulse signal, which is the difference of the sum of n exponents. The DI converter converts the n sets of mantissa product digital signals output by the multiplier into n sets of mantissa product current pulse signals. The domain wall memory consists of n domain wall devices driven by the spin Hall effect, where n is the number of input data sets for MAC operation; each domain wall device includes a magnetic nanowire, a write magnetic tunnel junction, and a read magnetic tunnel junction; n sets of mantissa product current pulse signals and n sets of exponent sum difference current pulse signals are input into the domain wall memory to obtain n sets of aligned mantissa product current pulse signals; The ID converter converts the n aligned mantissa product current pulse signals output from the domain wall memory into n aligned mantissa product digital signals and outputs them to the accumulator. The accumulator performs an accumulation operation on the digital signal of the product of n aligned mantissas according to the sign information of the sign bit of each group of input data, to obtain the final digital signal of the output mantissa part and the digital signal of the output sign bit of the MAC operation.

2. The floating-point multiply-accumulate processor based on spintronic memory devices as described in claim 1, characterized in that, The specific workflow is as follows: The magnetic domain wall device first inputs the current pulse signal of the product of each set of mantissas to the write magnetic tunnel junction of the magnetic domain wall device, then inputs the current pulse signal of the difference of the sum of each set of exponents to the magnetic nanowire, and finally obtains the aligned current pulse signal of the product of mantissas from the readout magnetic tunnel junction.

3. The floating-point multiply-accumulate processor based on spintronic memory devices as described in claim 1, characterized in that: The time-domain adder is composed of several cascaded edge delay units.

4. The floating-point multiply-accumulate processor based on spintronic memory devices as described in claim 3, characterized in that: The edge delay unit is a buffer structure consisting of six inverters with enable control.

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