Interrupt verification method and system for system-on-chip (SoC)

Abstract

The invention discloses an interrupt verification method and system for a system-on-chip (SoC), and the method comprises the steps: converting peripheral pulse interrupt into a stable level signal in a unified manner through multiplexing a pulse broadening module (w1cstrbreg) with cross-clock domain synchronization; and the verification platform directly triggers interruption by using a single-side force instruction, and all interruption sources can be efficiently covered without reproducing a real scene. According to the method, verification manpower is reduced to a single-person universal process from a mode of'specially-assigned person for each module ', simulation time is shortened by 30 times, manpower cost is reduced by 16 times, and 100% coverage of corner cases such as asynchronous interruption and interruption storm is supported. The method is suitable for interrupt link verification of complex SoC design.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit verification, in particular to an interrupt verification method and system for a system on chip (SoC). BACKGROUND

[0002] The interrupt scenarios of the soc system verification are numerous and complex, and a high-efficiency and safe interrupt verification technology is needed. The disadvantages of the prior art: the traditional interrupt verification method is to construct the interrupt triggering scene to verify whether the CPU can respond to the interrupt generated by the module. With the increasing complexity of large-scale SOC design, the number of interrupts is increasing, and the scene is increasing. According to the traditional scheme, verifying all interrupts will consume a lot of simulation time and manpower. The more complex the SOC design is, the lower the efficiency of the traditional verification method is.

[0003] In the SoC design of advanced process nodes (such as 7nm and below), the interrupt system presents the following characteristics: Scale explosion: modern SoC integrates hundreds of peripherals (such as PCIe, DDR controller, AI accelerator), and the number of interrupt sources can reach 1024+; Protocol complexity: interrupt signals may pass through multiple levels of synchronization (CDC), priority arbitration (Arbiter), interrupt aggregation (Aggregator), etc. logic; Verification inefficiency: the traditional method needs to construct an independent test scene for each interrupt source (such as simulating DMA transmission error to trigger DMA_IRQ

[127] ), resulting in: simulation cost: O(n) linear growth of test case development time (n = number of interrupts); manpower bottleneck: requires cooperation of peripheral experts and verification engineers (such as USB3.0 interrupt needs protocol experts to configure registers); Coverage blind area: asynchronous interrupts (such as wake-up interrupts after clock gating) are difficult to reproduce.

[0004] 2. Defects of existing technical solutions Solution one (directed testing): reproduce the real interrupt scene through UVM sequence, defect: need to maintain the UVM agent of each peripheral (such as SPI_UVC), the code amount is more than 100,000 lines; Solution two (formal verification): use Formal tools to prove interrupt assertions, defect: limited ability to verify the timing of "back-to-back interrupts"; Solution three (FPGA prototype): run real software to trigger interrupts on FPGA, defect: cannot inject corner cases (such as metastable state interrupts when the phase difference between PCLK and HCLK is 90°).

[0005] For verification, it is an urgent problem to efficiently and safely cover all interrupts. SUMMARY

[0006] The present application proposes a method and system for verifying interrupt of a system on chip (SoC) to solve the technical problems in the background art.

[0007] The present application adopts the technical solution of: A method for verifying interrupt of a system on chip (SoC) comprises: acquiring an interrupt signal of a module to be verified, the interrupt signal being a pulse signal; widening the pulse signal into a level signal by a pulse widening module w1c_strb_reg, wherein the pulse widening module is shared by a plurality of peripheral modules; in a verification case, simulating interrupt triggering by forcing the interrupt signal to be a valid level and releasing after maintaining for one clock cycle; judging whether a central processing unit (CPU) responds to the interrupt and executes an interrupt service function, and whether a write-1-clear operation is completed; based on the judging result, confirming correctness of the interrupt function of the module to be verified.

[0008] Preferably, the pulse widening module w1c_strb_reg is configured to: when a pulse rising edge of the interrupt signal is detected, widen it into a continuous level signal until the CPU completes the write-1-clear operation and then pulls it low.

[0009] Preferably, the forcing operation is triggered by a verification platform at an APB clock PCLK rising edge, and does not need to reproduce a real interrupt triggering scenario.

[0010] Preferably, the method is applicable to interrupt verification of a plurality of peripheral modules, and interrupt verification of all the modules is performed by the same verification personnel.

[0011] In a second aspect, the present application further provides a system for verifying interrupt of a system on chip (SoC), comprising: a pulse widening module w1c_strb_reg coupled to a plurality of peripheral modules, for widening a pulse interrupt signal output by the peripheral modules into a level signal; a verification platform configured to force the interrupt signal of any peripheral module to be a valid level and release after maintaining for one clock cycle; a central processing unit (CPU) configured to respond to the level signal and execute an interrupt service function, and complete a write-1-clear operation; wherein the verification platform verifies the interrupt function of the peripheral module based on a response result of the CPU.

[0012] Preferably, the pulse expansion module w1c_strb_reg is a hardware logic module, the input of which is the pulse interrupt signal of the peripheral module, and the output is the expanded level signal.

[0013] Preferably, the verification platform communicates with the peripheral module through the bus interface APB to perform the force operation.

[0014] Compared with the prior art, the present application has the following beneficial effects: 1. Improving the efficiency of interrupt verification: in all modules that need to generate interrupts, the w1c_strb_reg module is multiplexed to ensure the consistency of the processing of the pulse signal, i.e. the pulse signal is expanded into a level signal. On the basis of ensuring this, the scenario of interrupt generation can be simulated by simply forcing the interrupt signal of the module to be 1 for one pclk and then to 0 (lines 36-38 of the code), without reproducing the interrupt triggering scenario, which can save a lot of simulation time and improve the verification efficiency.

[0015] 2. Saving manpower of the verification personnel: the traditional verification method requires the verification personnel to reproduce the interrupt triggering scenario, which requires the verification personnel to be familiar with the module, and the interrupt verification of different modules can only be performed by the verification person in charge of the module. The technology provided by us only needs to force the interrupt signal of the module to be 1 for one pclk and then to 0, so the interrupt verification of all modules can be performed by one person. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 Method flow provided for the first embodiment of the present application Figure 1 ; Figure 2 Schematic diagram of pulse expansion provided for the first embodiment of the present application Figure 3 Test case provided for the first embodiment of the present application Figure 1 ; Figure 4 Method flow provided for the second embodiment of the present application Figure 2 ; DETAILED DESCRIPTION

[0017] In the following description, specific details are set forth such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, persons skilled in the art should understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary details.

[0018] This embodiment uses a module that multiplexes interrupt pulses, combined with a method of triggering interrupts using test cases, to quickly traverse all interrupts. Previously, the number of interrupt verification personnel was equal to the number of modules; each module required one verification personnel to verify its interrupts because the verification personnel needed to be very familiar with the interrupt triggering scenarios. With this technology, regardless of the number of modules, only one verification personnel is needed to cover all interrupts, and the verification time is significantly reduced.

[0019] In large-scale SOC verification, this technology can reduce manpower required to interrupt verification and improve verification efficiency while ensuring security.

[0020] Overall plan as follows Figure 1 As shown, The principle of pulse widening in `W1c_strb_reg` is shown in Figure 2, and the test case flow is shown in Figure 3. `PCLK` is the apb clock. An interrupt is generated at the rising edge of `PCLK`, lasting for one clock cycle. After passing through the `w1c_strb_reg` module, the pulse signal is widened into a level signal to ensure correct sampling by the CPU. The `w1c_strb_reg` module is multiplexed; all peripherals call this module to ensure consistent pulse signal processing. If interrupts are enabled, the CPU will immediately interrupt the current process and enter the interrupt service function after sampling the interrupt, then perform a write-to-clear operation. Afterward, `w1c_strb_reg` will pull the interrupt signal passed to the CPU low. It is only necessary to determine whether the CPU responded to the interrupt, whether it entered the interrupt service function, and whether it was able to perform a write-to-clear operation.

[0021] Example 2 Compared with Example 1, such as Figure 4 As shown, the w1c_strb_reg module has been removed, making the RTL design simpler, the logic clearer, and saving chip area.

[0022] By forcing the module's interrupt signal to 1 for one pclk and then forcing it to 0 in the test case, the CPU determines whether to jump to the interrupt service function based on whether the pulse signal is sampled.

[0023] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0024] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction, and do not limit the protection scope of the present application. The specific working process of the unit and module in the system can refer to the corresponding process in the foregoing method embodiment, which will not be described here.

[0025] The embodiment of the present application also provides a network device, comprising at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the foregoing method embodiments when executing the computer program.

[0026] The embodiment of the present application provides a computer program product, which, when running on a mobile terminal, enables the mobile terminal to implement the steps in any of the foregoing method embodiments.

[0027] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the embodiment of the present application can implement all or part of the processes in the foregoing method embodiments by a computer program to instruct related hardware to complete, and the computer program can be stored in a computer-readable storage medium. When the processor executes the computer program, the steps of the foregoing method embodiments can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer-readable medium at least includes any entity or device capable of carrying the computer program code to the photographing apparatus / terminal device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium. For example, U disk, mobile hard disk, magnetic disk or optical disk, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunication signal.

[0028] In the above embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0029] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0030] In the embodiments provided in the present application, it should be understood that the disclosed apparatus / network device and method can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0031] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or they can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0032] The above described embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. An interrupt verification method for a system-on-a-chip (SoC), characterized in that, include: Obtain the interrupt signal of the module to be verified, wherein the interrupt signal is a pulse signal; The pulse signal is widened into a level signal by a multiplexed pulse widening module w1c_strb_reg, wherein the pulse widening module is shared by multiple peripheral modules; In the verification test case, the interrupt signal was forced to a valid level and held for one clock cycle before being released to simulate interrupt triggering; Determine whether the central processing unit (CPU) responds to the interrupt and executes the interrupt service function, and whether the write-1 clear operation is completed; Based on the judgment result, the correctness of the interrupt function of the module to be verified is confirmed.

2. The interruption verification method according to claim 1, characterized in that, The pulse broadening module w1c_strb_reg is configured as follows: When the rising edge of the interrupt signal is detected, it is widened into a continuous level signal until the CPU completes the write-1 clear operation and then pulls it low.

3. The interruption verification method according to claim 1 or 2, characterized in that, The forced operation is triggered by the verification platform at the rising edge of the APB clock PCLK, and there is no need to reproduce the actual interrupt triggering scenario.

4. The interruption verification method according to any one of claims 1-3, characterized in that, The method is applicable to interrupt verification of multiple peripheral modules, and the interrupt verification of all modules is performed by the same verification personnel.

5. An interrupt verification system for a system-on-a-chip (SoC), characterized in that, include: The pulse widening module w1c_strb_reg is coupled to multiple peripheral modules and is used to widen the pulse interrupt signal output by the peripheral modules into a level signal. The verification platform is configured to force the interrupt signal of any peripheral module to be active and release it after one clock cycle. The central processing unit (CPU) is configured to respond to the level signal and execute an interrupt service function, as well as complete the write-1 clear operation; The verification platform verifies the interrupt function of the peripheral module based on the CPU's response results.

6. The interruption verification system according to claim 5, characterized in that, The pulse widening module w1c_strb_reg is a hardware logic module. Its input is the pulse interrupt signal of the peripheral module, and its output is the widened level signal.

7. The interruption verification system according to claim 5 or 6, characterized in that, The verification platform communicates with the peripheral module via the bus interface APB to execute the forced operation.

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