A method and apparatus for flipping coverage test, a storage medium and an electronic device

Abstract

This invention proposes a flip-flop coverage testing method, apparatus, storage medium, and electronic device. The method involves obtaining target port mapping relationships, where each port of a target IP module in a chip design file is mapped to a matching target physical node. The target IP module can be any IP module in the chip design. The target port mapping relationships are input into a flip-flop coverage testing tool. This tool performs flip-flop coverage testing on the target ports and generates a corresponding flip-flop coverage test report. The target ports include the ports of each target physical node matched by the target IP module. By directly performing flip-flop coverage testing on the ports of the target physical nodes, the method focuses on truly effective key coverage points and allows for reuse or reference across different iterations or milestones.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip testing, in particular to a toggle coverage test method and device, a storage medium and an electronic equipment. BACKGROUND

[0002] Chip verification testing is an important link in the chip development process and is a key factor to ensure the reliability of chip design and the success rate of tape-out.

[0003] Among them, toggle coverage is a key indicator in chip verification testing, which requires that the signals (including port signals and internal signals) of each module in the design under test (DUT) complete 0→1 and 1→0 state toggling. This toggle coverage indicator is used to evaluate the test sufficiency of RTL code in simulation or formal verification, and directly affects the reliability of chip design and the success rate of tape-out.

[0004] Due to the large scale of SoC chips, it is usually necessary to divide the logical view according to the back-end floorplan / tile view. However, such division will introduce an additional Tile hierarchy, and the Tile division scheme may differ between different projects or different stages. Although the current scheme generates toggle coverage data for Tile interfaces, these data make it difficult for engineers to focus on truly effective key coverage points. In addition, the covered objects also change with the adjustment of the Tile division scheme, resulting in that the results of coverage review cannot be reused or referenced between different delta projects or different milestones. SUMMARY

[0005] The purpose of the present application is to provide a toggle coverage test method, device, storage medium and electronic equipment to improve the above problems.

[0006] In order to achieve the above purpose, the technical scheme adopted by the embodiments of the present application is as follows:

[0007] In a first aspect, the embodiments of the present application provide a toggle coverage test method, which comprises:

[0008] Obtaining a target port mapping relationship, wherein the target port mapping relationship is the mapping relationship between each port of a target IP module in a chip design file and a matching target physical node, and the target IP module is any IP module in the chip design;

[0009] Input the target port mapping relationship into the flip-coverage test tool;

[0010] The flip coverage testing tool performs flip coverage testing on the target port and generates a corresponding flip coverage test report.

[0011] The target port includes the ports of each target physical node matched by the target IP module.

[0012] Secondly, embodiments of the present invention provide a flip-coverage testing device, the device comprising:

[0013] The first processing unit is used to obtain the target port mapping relationship, wherein the target port mapping relationship is the mapping relationship between each port of the target IP module in the chip design file and the matching target physical node, and the target IP module is any IP module in the chip design;

[0014] The first processing unit is also used to input the target port mapping relationship into the flip coverage test tool;

[0015] The second processing unit is used to perform a flip coverage test on the target port by the flip coverage test tool and generate a corresponding flip coverage test report.

[0016] The target port includes the ports of each target physical node matched by the target IP module.

[0017] Thirdly, embodiments of the present invention provide a storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0018] Fourthly, embodiments of the present invention provide an electronic device, the electronic device comprising: a processor and a memory, the memory being used to store one or more programs; when the one or more programs are executed by the processor, the above-described method is implemented.

[0019] Compared to existing technologies, the present invention provides a flip-flop coverage testing method, apparatus, storage medium, and electronic device. This method obtains target port mapping relationships, where each port of a target IP module in a chip design file is mapped to a matching target physical node. The target IP module can be any IP module in the chip design. The target port mapping relationships are input into a flip-flop coverage testing tool. The tool performs flip-flop coverage testing on the target ports and generates a corresponding flip-flop coverage test report. The target ports include the ports of each target physical node matched by the target IP module. By directly performing flip-flop coverage testing on the ports of the target physical nodes, the method focuses on truly effective key coverage points and allows for reuse or reference across different iterations or milestones.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0023] Figure 2 This is one of the flowcharts illustrating the flip coverage test method provided in an embodiment of the present invention.

[0024] Figure 3 This is the second flowchart illustrating the flipping coverage test method provided in this embodiment of the invention.

[0025] Figure 4 This is the third flowchart illustrating the flipping coverage test method provided in this embodiment of the invention.

[0026] Figure 5 This is a schematic diagram of a unit of the flipping coverage testing device provided in an embodiment of the present invention.

[0027] In the diagram: 10-Processor; 11-Memory; 12-Bus; 13-Communication interface; 501-First processing unit; 502-Second processing unit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0030] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0032] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0033] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0034] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0035] This invention provides an electronic device, which may be a server device, a computer device, or a mobile phone device. Please refer to... Figure 1 This is a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12. The processor 10 is used to execute executable modules, such as computer programs, stored in the memory 11.

[0036] Processor 10 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the flip-coverage test method can be completed through integrated logic circuits in the hardware of processor 10 or through software instructions. The processor 10 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0037] The memory 11 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage.

[0038] Bus 12 can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. Figure 1 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus 12 or one type of bus 12.

[0039] The memory 11 is used to store programs, such as programs corresponding to the flip-coverage testing device. The flip-coverage testing device includes at least one software functional module that can be stored in the memory 11 in the form of software or firmware or embedded in the operating system (OS) of the electronic device. After receiving an execution instruction, the processor 10 executes the program to implement the flip-coverage testing method.

[0040] The electronic device provided in this embodiment of the invention may further include a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0041] It should be understood that, Figure 1 The structure shown is only a partial schematic diagram of the electronic device; the electronic device may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0042] The flip coverage testing method provided in this embodiment of the invention can be applied to, but is not limited to, [various applications]. Figure 1 For the specific process of the electronic devices shown, please refer to [link / reference]. Figure 2 The flipping coverage test methods include S21, S22 and S24, which are described in detail below.

[0043] S21, obtain the target port mapping relationship.

[0044] The target port mapping relationship refers to the mapping relationship between each port of the target IP module in the chip design file and the matching target physical node. The target IP module can be any IP module in the chip design. IP (Intellectual Property) modules can be, but are not limited to, central processing unit (CPU) modules, graphics processing unit (GPU) modules, neural network processing unit (NPU) modules, and video processing unit (VPU) modules.

[0045] S22, input the target port mapping relationship into the flip coverage test tool.

[0046] Flip coverage testing tools can be, but are not limited to, Electronic Design Automation (EDA) tools.

[0047] S24, the flip coverage test tool performs a flip coverage test on the target port and generates a corresponding flip coverage test report.

[0048] The target ports include the ports of each target physical node matched by the target IP module.

[0049] Due to the large size of SoC chips, the logical view typically needs to be partitioned into tiles based on the backend floorplan / tile view. However, this partitioning introduces an additional tile hierarchy, and tile partitioning schemes may differ between different projects or stages. While the current approach generates toggle coverage data for tile interfaces, this data makes it difficult for engineers to focus on truly effective critical coverage points. Furthermore, covered objects change with adjustments to the tile partitioning scheme, making coverage review results unusable or unreferenceable across different iterations or milestones.

[0050] In the flip coverage testing method provided in this embodiment of the invention, the flip coverage test is performed directly on the port of the target physical node, focusing on the truly effective key coverage points, and can be reused or referenced between different iteration projects or different milestones.

[0051] As chip size continues to increase, the amount of coverage data generated by large-scale System-on-Chips (SoC) simulations can reach millions of records. This necessitates a significant investment of time for verification and design personnel in data analysis and inspection. Under current technological solutions, completing a full coverage analysis for a project typically takes several months.

[0052] To reduce the consumption of engineers' analytical resources and simplify coverage convergence, this embodiment of the invention also provides an optional implementation method, please refer to... Figure 3 Before the flip coverage testing tool performs flip coverage testing on the target port and generates the corresponding flip coverage test report in S24, the flip coverage testing method also includes S23, which is described in detail below.

[0053] S23, ignores rule file input and flips the coverage test tool.

[0054] The ignore rule file includes identifiers for the first category of ports to be ignored. These first category ports are all ports on the target physical nodes, and each port can be either an input or output port. It should be noted that ports on a target physical node that are both inputs and outputs cannot be ignored.

[0055] S24, the flip coverage test tool performs a flip coverage test on the target port and generates a corresponding flip coverage test report, including: S24A, as follows.

[0056] S24A removes ports to be ignored from the target ports, performs a flip-over coverage test on the remaining target ports, and generates a corresponding flip-over coverage test report.

[0057] Among them, the ports to be ignored include the first type of ports to be ignored and the second type of ports to be ignored as described below.

[0058] If toggle coverage data is collected simultaneously from all directional interfaces (input / output / inout), individual collection by interface direction is not supported. This implementation will cause the SoC's toggle coverage database to double in size, consuming more than 50% of engineers' analysis resources and significantly increasing the difficulty of coverage convergence.

[0059] After excluding the first type of ports to be ignored, unidirectional flip coverage testing can be performed according to the interface direction (input or output), reducing the consumption of engineers' analysis resources and lowering the difficulty of coverage convergence. The coverage convergence cycle of a typical SoC design is accelerated by 67% (months to days); the number of toggle objects to be analyzed is reduced by 68% (millions to hundreds of thousands); and coverage analysis results can be efficiently reused across different iterations or development stages (milestones), significantly reducing the workload of repetitive coverage analysis.

[0060] Building upon the preceding text, this invention also provides an optional implementation method to further reduce the number of ports requiring flip-over coverage testing, thereby reducing the analysis workload and accelerating convergence. Please refer to the following text for details.

[0061] The ignore rule file also includes the identifier of the second type of ports to be ignored. The second type of ports to be ignored are the remaining ports of the target physical node excluding the first type of ports. The target physical node to be ignored is the target physical node whose hierarchical attribute value is greater than the hierarchical threshold (which can be set by the user).

[0062] Assuming the first type of port is an input port, the level threshold is 5, and the target IP module is the CPU, then the ports that need to be ignored include all ports of physical nodes whose level attribute value corresponding to the CPU is greater than 5, as well as the input ports of physical nodes whose level attribute value corresponding to the CPU is less than or equal to 5. Only the output ports and input / output ports of physical nodes whose level attribute value corresponding to the CPU is less than or equal to 5 need to be analyzed.

[0063] Building upon the foregoing, this embodiment of the invention also provides an optional implementation method for generating the ignore rule file. Please refer to [link / reference needed]. Figure 4 The flipping coverage test method also includes: S11, S12, S13 and S14, which are described in detail below.

[0064] S11, parse the RTL file corresponding to the target IP module in the chip design to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of the target IP module.

[0065] S12, determine each type of first-class port to be ignored based on the port direction of the target physical node.

[0066] S13, determine the target physical nodes to be ignored based on the hierarchical threshold and the hierarchical attribute value of the target physical node, and then determine each second type of port to be ignored.

[0067] S14. Generate an ignore rule file based on the determined first type of ports to be ignored and the second type of ports to be ignored.

[0068] Based on the preceding text, regarding the content of S11, this embodiment of the invention also provides an optional implementation method, please refer to the following text. S11, parsing the RTL file corresponding to the target IP module in the chip design to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of the target IP module, including: S111 and S112, which are specifically described below.

[0069] S111 loads the list of RTL files corresponding to each IP module in the chip design into the hierarchical recognition engine.

[0070] The RTL file list contains the RTL design file identifiers for each IP module, and the hierarchy recognition engine can be, but is not limited to, the Novas NPI engine developed based on Python.

[0071] S112, the hierarchical recognition engine parses the list of RTL files it has obtained in parallel through multiple processes to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of each IP module.

[0072] Based on the preceding text, regarding the content of S112, this embodiment of the invention also provides an optional implementation method, please refer to the following text. S112, the hierarchical recognition engine parses the list of RTL files it has obtained in parallel through multiple processes to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of each IP module, including: S112A, S112B and S112C, which are described in detail below.

[0073] S112A, the hierarchical recognition engine creates N sub-processes, where N is the total number of IP modules in the chip design.

[0074] S112B assigns the list of the nth RTL files corresponding to the nth IP module to the nth subprocess, where 1≤n≤N, and N is the total number of IP modules in the chip design.

[0075] S112C, the nth child process parses the nth RTL file list to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of the nth IP module.

[0076] In one alternative implementation, the ignore rule file also includes bit width attribute information of the ports to be ignored (including the first type of ports to be ignored and the second type of ports to be ignored below) for use by EDA tools.

[0077] Please see Figure 5 , Figure 5The present invention provides a flip-over coverage testing device, which is optionally applied to the electronic device described above.

[0078] The flip-coverage testing device includes: a first processing unit 501 and a second processing unit 502.

[0079] The first processing unit 501 is used to obtain the target port mapping relationship, wherein the target port mapping relationship is the mapping relationship between each port of the target IP module and the matching target physical node in the chip design file, and the target IP module is any IP module in the chip design;

[0080] The first processing unit 501 is also used to input the target port mapping relationship into the flip coverage test tool;

[0081] The second processing unit 502 is used to perform a flip coverage test on the target port using the flip coverage test tool and generate a corresponding flip coverage test report.

[0082] The target ports include the ports of each target physical node matched by the target IP module.

[0083] Optionally, the second processing unit 502 may execute S24 as described above, and the first processing unit 501 may execute other steps in the above method embodiments.

[0084] It should be noted that the flipping coverage testing device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effect. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0085] This invention also provides a storage medium storing computer instructions and programs, which, when read and executed, perform the flip-flop coverage test method described above. The storage medium may include memory, flash memory, registers, or a combination thereof.

[0086] The following describes an electronic device, which can be a server device, a computer device, or a mobile phone device. This electronic device is as follows: Figure 1 As shown, the above-described flip-over coverage test method can be implemented. Specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 may be a CPU. The memory 11 is used to store one or more programs, which, when executed by the processor 10, perform the flip-over coverage test method of the above embodiment.

[0087] In summary, the present invention provides a flip-flop coverage testing method, apparatus, storage medium, and electronic device. This method obtains target port mapping relationships, where each port of a target IP module in a chip design file is mapped to a matching target physical node. The target IP module can be any IP module in the chip design. The target port mapping relationships are input into a flip-flop coverage testing tool. The tool performs flip-flop coverage testing on the target ports and generates a corresponding flip-flop coverage test report. The target ports include the ports of each target physical node matched by the target IP module. By directly performing flip-flop coverage testing on the ports of the target physical nodes, the method focuses on truly effective key coverage points and allows for reuse or reference across different iterations or milestones.

[0088] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0089] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for testing flipped coverage, characterized in that, The method includes: Obtain the target port mapping relationship, wherein the target port mapping relationship is the mapping relationship between each port of the target IP module in the chip design file and the matching target physical node, and the target IP module is any IP module in the chip design; Input the target port mapping relationship into the flip-coverage test tool; The flip coverage testing tool performs flip coverage testing on the target port and generates a corresponding flip coverage test report. The target port includes the ports of each target physical node matched by the target IP module; Before the flip coverage testing tool performs flip coverage testing on the target port and generates a corresponding flip coverage test report, the method further includes: Input the ignore rule file into the flip coverage test tool; The ignore rule file includes the identifier of the first type of ports to be ignored, which are the first type of ports of all target physical nodes, and the first type of ports are either input ports or output ports. The flip-coverage testing tool performs flip-coverage testing on the target port and generates a corresponding flip-coverage test report, including: Remove the ports to be ignored from the target ports, perform a flip coverage test on the remaining target ports, and generate a corresponding flip coverage test report; The ignore rule file also includes the identifier of the second type of ports to be ignored. The second type of ports to be ignored are the remaining ports of the target physical node excluding the first type of ports. The target physical node to be ignored is the target physical node whose hierarchical attribute value is greater than the hierarchical threshold. The flip coverage test method also includes: The RTL file corresponding to the target IP module in the chip design is parsed to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of the target IP module. Each first-type port to be ignored is determined based on the port direction of the target physical node; The target physical nodes that need to be ignored are determined based on the level threshold and the level attribute value of the target physical node, and then each second type of port to be ignored is determined. Based on the identified first and second categories of ports to be ignored, generate an ignore rule file.

2. The flipping coverage test method as described in claim 1, characterized in that, The step of parsing the RTL file corresponding to the target IP module in the chip design to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of the target IP module includes: Load the list of RTL files corresponding to each IP module in the chip design into the hierarchical recognition engine; The RTL file list includes the RTL design file identifiers for each IP module; The hierarchical recognition engine parses the obtained RTL file list in parallel through multiple processes to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of each IP module.

3. The flipping coverage test method as described in claim 2, characterized in that, The hierarchical recognition engine parses the acquired RTL file list in parallel through multiple processes to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of each IP module, including: The hierarchical recognition engine creates N sub-processes, where N is the total number of IP modules in the chip design; Assign the list of the nth RTL files corresponding to the nth IP module to the nth child process, where 1 ≤ n ≤ N; The nth subprocess parses the nth RTL file list to obtain the hierarchical attribute values ​​and port directions of the target physical nodes corresponding to each RTL design file of the nth IP module.

4. The flipping coverage test method as described in claim 1, characterized in that, The ignore rule file also includes bit width attribute information for the ports to be ignored.

5. A flipping coverage testing device, characterized in that, The device includes: The first processing unit is used to obtain the target port mapping relationship, wherein the target port mapping relationship is the mapping relationship between each port of the target IP module in the chip design file and the matching target physical node, and the target IP module is any IP module in the chip design; The first processing unit is also used to input the target port mapping relationship into the flip coverage test tool; The second processing unit is used to perform a flip coverage test on the target port by the flip coverage test tool and generate a corresponding flip coverage test report. The target port includes the ports of each target physical node matched by the target IP module; Before the flip coverage testing tool performs a flip coverage test on the target port and generates a corresponding flip coverage test report, the flip coverage testing device is further configured to: input an ignore rule file into the flip coverage testing tool; wherein, the ignore rule file includes an identifier of a first type of port to be ignored, the first type of port to be ignored being a first type of port of all target physical nodes, wherein the first type of port is an input port or an output port; The flip coverage testing tool performs flip coverage testing on the target port and generates a corresponding flip coverage test report, including: removing ports to be ignored from the target port, performing flip coverage testing on the remaining target ports, and generating a corresponding flip coverage test report. The ignore rule file also includes the identifier of the second type of ports to be ignored. The second type of ports to be ignored are the remaining ports of the target physical node excluding the first type of ports. The target physical node to be ignored is the target physical node whose hierarchical attribute value is greater than the hierarchical threshold. The flip-coverage testing device is further configured to: parse the RTL file corresponding to the target IP module in the chip design to obtain the hierarchical attribute value and port direction of the target physical node corresponding to each RTL design file of the target IP module; determine each first type of port to be ignored based on the port direction of the target physical node; determine the target physical node to be ignored based on the hierarchical threshold and the hierarchical attribute value of the target physical node, and then determine each second type of port to be ignored; and generate an ignore rule file based on the determined first type of port to be ignored and second type of port to be ignored.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method as described in any one of claims 1-4.

7. An electronic device, characterized in that, include: Processor and memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method as described in any one of claims 1-4 is implemented.

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