Memory system, voltage regulator circuit and operation method thereof

Abstract

The invention discloses a memory system, a voltage stabilizer circuit and an operation method thereof. The regulator circuit includes a global voltage generator circuit having a reference input to receive a reference voltage and an output to output a gate signal replicating the reference voltage. A plurality of driver circuits each have an input connected to an output of the global generator circuit. An output of each of the driver circuits is connected to a corresponding one or more of the plurality of memory giant sets. The driver circuits are each configured to output a control signal that copies a reference voltage to its corresponding memory macro.

Description

Technical Field

[0001] This disclosure relates to a memory system, a voltage regulator circuit, and its operation method. Background Technology

[0002] Reference voltage generators, such as low-dropout (LDO) regulators, are commonly used in semiconductor devices. For example, LDO regulators are typically used to provide accurate and stable direct-current (DC) voltages. Typically, LDO regulators are characterized by their low dropout voltage, which refers to the small difference between the corresponding input and output voltages. A typical application of LDO regulators is in semiconductor memory devices, where they can be used to provide bit-line or word-line voltages. Summary of the Invention

[0003] This disclosure includes a voltage regulator circuit, comprising: a global voltage generator circuit, including: a differentiating amplifier having a first input terminal, a second input terminal, and an output terminal for receiving a reference voltage signal; a feedback loop connected between the output terminal of an error amplifier and the second input terminal of the differentiating amplifier; and a driver circuit, each of the driver circuits including: a first driver stage including an input terminal connected to the output terminal of the differentiating amplifier; a second driver stage including an input terminal connected to the output terminal of the differentiating amplifier and an output node; and a buffer stage connected to the output node of the second amplifier stage and having an output terminal.

[0004] This disclosure includes a memory system comprising: a memory macro, each comprising an array of memory cells; a global voltage generator circuit having a reference input for receiving a reference voltage and an output for outputting a gate signal that replicates the reference voltage; and driver circuits, each of the driver circuits having an input connected to the output of the global generator circuit and an output connected to a corresponding one of the memory macros that outputs a control signal that replicates the reference voltage, wherein the driver circuits do not include compensation capacitors.

[0005] This disclosure includes a method of operating a voltage regulator circuit, comprising the following steps: receiving a reference voltage by a global voltage generator circuit; generating a gate control signal by the global voltage generator circuit, including comparing the gate control signal with the reference voltage using a differentiating amplifier, such that the gate control signal replicates the reference voltage; outputting the gate control signal from the global voltage generator circuit to each of the local driver circuits; receiving the gate control signal at the driver stage of each of the local driver circuits; and outputting a memory control signal replicating the reference voltage signal from the buffer stage of each of the local driver circuits. Attached Figure Description

[0006] The nature of this disclosure is best understood when read in conjunction with the accompanying drawings, based on the following detailed description. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In practice, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation. Furthermore, the drawings are illustrative examples of embodiments of the present disclosure and are not intended to be limiting.

[0007] Figure 1 A block diagram illustrating an example of a memory system according to some of the disclosed embodiments;

[0008] Figure 2 A schematic diagram illustrating an example of a voltage regulator circuit according to some of the disclosed embodiments;

[0009] Figure 3 A schematic diagram illustrating another example of a voltage regulator circuit according to some of the disclosed embodiments;

[0010] Figure 4 A schematic diagram illustrating an example of a local driver circuit according to some of the disclosed embodiments;

[0011] Figure 5 A schematic diagram illustrating another example of a local driver circuit according to some of the disclosed embodiments;

[0012] Figure 6 A schematic diagram illustrating yet another example of a voltage regulator circuit according to some of the disclosed embodiments;

[0013] Figure 7 A schematic diagram illustrating yet another example of a local driver circuit according to some of the disclosed embodiments;

[0014] Figure 8 A flowchart illustrating an example of a voltage regulator method according to some of the disclosed embodiments.

[0015] [Symbol Explanation]

[0016] 10: Memory System

[0017] 20: Memory Macros

[0018] 22: Wire

[0019] 24: Bandgap regulator circuit

[0020] 30, 30a: Voltage Regulator System

[0021] 100: Global Voltage Generator Circuit

[0022] 110, 41 Differential Amplifier

[0023] 112, 412: Feedback loop

[0024] 114, 414: MN1 NMOS transistor

[0025] 116, 416: MP1 PMOS transistor

[0026] 118, 218, 300, 301, 418, 518, 570, 572, 576: I1 current source

[0027] 120, 420: Compensation capacitors

[0028] 130, 230, 240, 430, 530, 540, 542, 544, 546: Nodes

[0029] 200: Distributed Local Area Driver Circuit

[0030] 201, 501a: First driver stage

[0031] 202, 502: Second source follower stage

[0032] 203, 203a, 203b: Level 3

[0033] 214, 242, 244, 246, 254, 272, 274, 278, 306, 308, 514, 556: NMOS transistors

[0034] 216, 245, 252, 256, 270, 276, 280, 302, 304, 516, 554, 580: PMOS transistors

[0035] 218, 227: Current source

[0036] 224, 524: MN2 NMOS transistors

[0037] 226, 526: MP2 PMOS transistors

[0038] 227, 228, 527, 528: I2 current sources

[0039] 260, 290, 310, 560: Output nodes

[0040] 501: First Source Follower Stage

[0041] 503, 503a: Push-pull amplifier stage

[0042] 502a: Second Driver Stage

[0043] 504: Third Driver Level

[0044] 574: I3 Current Source

[0045] 578: Common-gate stacked NMOS transistor

[0046] 600: Voltage Regulator Method

[0047] 610, 612, 614, 616, 618: Operation bnc, bpc, N1, N2: Bias voltage; GATE: Gate bias signal; NGATE: Bias signal

[0048] VBL: Bit line signal

[0049] VREF: Voltage Reference Signal Detailed Implementation

[0050] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0051] Additionally, for ease of description, spatial relative terms (such as “below,” “under,” “bottom,” “above,” “upper,” and the like) may be used herein to describe the relationship between one component or feature and another, as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatial relative descriptive terms used herein may be interpreted accordingly.

[0052] Low-dropout (LDO) regulators provide a specified and stable direct-current (DC) output voltage (e.g., a regulated output voltage) based on an input voltage with a low dropout voltage (e.g., an unregulated input voltage). As used herein, "dropout voltage" refers to the minimum voltage across the (LDO) regulator required to maintain the regulated output voltage. Even if the input voltage supplied by the power supply drops to a level very close to the output voltage and remains unregulated, the LDO regulator can still produce a regulated and stable output voltage. This stable characteristic enables LDO regulators to be used in a wide range of integrated circuit (IC) applications. For example, on-chip LDO regulators are used to provide regulated voltages to bit lines and / or word lines in large-scale memory arrays such as DRAM, MRAM, RRAM, and the like.

[0053] To save space, shared and centralized LDOs are sometimes used for sections with multiple memory macros or memory arrays. However, the wire resistance of the connectors increases with the number of connected macros, and the voltage drop worsens with the number of macros. Due to this IR drop, a strong power grid is used to distribute the LDO output voltage across all memory arrays, which uses additional metal rails and increases process costs. Furthermore, large dynamic load currents and macro capacitive loads can complicate LDO design due to the large compensation capacitors used to stabilize the LDO, which in turn reduces its speed. Some attempted solutions use several local LDO regulators to drive the respective macros or memory partitions, but this can increase area and power consumption, and also increase cost.

[0054] This disclosure relates to a voltage regulation system connected to a global voltage generator for each of a plurality of distributed local driver circuits. For example, each of the local driver circuits outputs a voltage signal to a corresponding memory macro of a memory system, wherein the output signal from the local driver circuit replicates a reference voltage received by the global voltage generator.

[0055] In all the disclosed examples, a feedback loop is provided only at the global voltage generator circuit. The local driver has neither a feedback loop nor a compensation capacitor, thus increasing area and improving power efficiency. The disclosed configuration further provides a smaller IR drop when outputting voltage signals to the memory macro because the local driver is located near the memory macro or partition.

[0056] Because the feedback is provided at the global voltage generator, rather than at the local driver, the global regulator can output an accurate voltage output. This is because a slower, larger feedback circuit can be used. Using a local power supply, a fast push-pull circuit, and eliminating the feedback loop reduces the size of the distributed local driver circuitry.

[0057] Figure 1 An example memory system 10 according to the disclosed embodiments is described. The described system 10 includes a plurality of memory macros 20, each memory macro 20 containing a plurality of memory cells. In various instances, the memory device 10 is a large-scale memory, for example, a gigabit or megabit array. The memory cells of the memory macros 20 may be DRAM, SRAM, MRAM, RRAM, OTP, and the like, but this disclosure is not limited to a particular memory type.

[0058] The memory system 10 further includes a voltage regulator system 30 for outputting voltage signals to the memory macro 20. In the illustrated example, the voltage regulator system 30 is used to output memory control signals to the memory macro 20, such as the bit line signal VBL, although in various configurations, the voltage regulator system 30 may output other memory control signals to the memory macro 20, such as word line signals, source line signals, enable signals, etc.

[0059] The voltage regulation system 30 is divided into multiple parts, including a global voltage generator circuit 100 and multiple distributed local driver circuits 200, each part being connected to one or more memory macros 20 via wires 22. In some embodiments, the global voltage generator circuit 100 is an LDO circuit that receives a voltage reference signal VREF. In some embodiments, the VREF signal is provided by a bandgap regulator circuit 24. Because the local driver circuits 200 are located closer to the memory macros 20, the wires 22 can be shorter, thereby reducing the resistance of the wires 22. In some instances, the global voltage generator 100 provides a gate bias signal GATE that replicates the reference voltage VREF received at its input, which is used to drive the various parts of the memory macros 20. The distributed local drivers 200 receive the gate bias voltage output from the global voltage generator 100 and output a desired output voltage to the memory macros 20.

[0060] Figure 2 Further details of an example of voltage regulator system 30 are provided. Figure 2The example illustrates an example of one of a global voltage generator circuit 100 and a distributed local driver circuit 200. The global voltage generator circuit 100 is used to output a bias voltage signal to control one or more transistors of the distributed local driver circuit 200, which output a bit line voltage signal VBL that replicates the reference voltage VREF input to the global voltage generator circuit 100.

[0061] In the illustrated example, the global voltage generator circuit 100 and the distributed local driver circuit 200 employ p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), referred to herein as PMOS and NMOS transistors, respectively. Other transistor technologies are also within the scope of this disclosure. Figure 2 An example is used to output an NGATE signal to bias the NMOS transistors of the distributed local driver circuit 200, thereby providing a bit line voltage signal VBL that replicates the reference voltage VREF. However, this disclosure is not limited to outputting the NGATE bias signal from the global voltage generator circuit 100 or the VBL signal from the distributed local driver circuit 200.

[0062] The global voltage generator circuit 100 includes a differentiating amplifier 110 having a first input, a second input, and an output. The first input is connected to a reference voltage signal VREF, for example, received by a self-bandgap circuit. In some embodiments, the reference voltage VREF is a voltage level (e.g., 1 volt) suitable for biasing the elements of the distributed local driver circuit 200 to output a voltage signal to the memory macro 20 to operate the memory array as needed. Therefore, the global voltage generator circuit 100 is used to output a bias signal NGATE that replicates (i.e., approaches) the VREF signal to bias the elements of the distributed local driver circuit 200 as needed to drive the memory array of the memory macro 20.

[0063] Feedback loop 112 is connected between the output of differentiating amplifier 110 and its second input, allowing differentiating amplifier 110 to compare the output signal NGATE with a reference signal VREF. Feedback loop 112 includes an amplifier circuit, such as a source follower amplifier, comprising an MN1 NMOS transistor 114 having a first source / drain (S / D) terminal connected to a first voltage rail and a second S / D terminal connected to node 130, which is connected to the second input of differentiating amplifier 110. In various embodiments disclosed herein, the first voltage rail is the Vdd voltage rail, but this disclosure is not limited thereto. As used herein, the source / drain (S / D) terminal may refer individually or jointly to a source or drain, depending on the context. The gate of MN1 transistor 114 is connected to the output of differentiating amplifier 110.

[0064] MP1 PMOS transistor 116 has one S / D terminal connected to node 130 and another S / D terminal connected to I1 current source 118. MP1 transistor 116 is a diode connected in a common-source configuration. I1 current source 118 is connected to a second voltage rail, and compensation capacitor 120 is connected between the output of differentiating amplifier 110 and the second voltage rail. In the various embodiments disclosed herein, the second voltage rail is ground or Vss voltage rail, but this disclosure is not limited thereto. Global voltage generator circuit 100 is thus used to establish a voltage level at node 130 that replicates or is very close to the reference voltage VREF.

[0065] The output of the global voltage generator circuit 100 is connected to the input of each of the distributed local driver circuits 200. Figure 2 In this example, each of the distributed local driver circuits 200 has a first driver stage 201. The first driver stage 201 is a source follower stage containing an input transistor. Figure 2 In this circuit, the input transistor is an NMOS transistor 214 having a first S / D terminal connected to the first voltage rail and a second S / D terminal connected to node 230. The gate of the NMOS transistor 214 is connected to the input of the distributed local driver circuit 200. In other words, the gate of the input NMOS transistor 214 receives the NGATE signal output by the global voltage generator circuit 100. The PMOS transistor 216 has one S / D terminal connected to node 230 and another S / D terminal connected to current source 218. Like the MP1 transistor 116, the PMOS transistor 218 is diode-connected. The current source 218 is connected to the second voltage rail.

[0066] The distributed local driver circuit 200 further includes a second driver state, which in the illustrated example is a second source follower stage 202. The second source follower stage 202 includes an MN2 NMOS transistor 224 having a gate terminal connected to the input of the distributed local driver circuit 200. In other words, the gate of the MN2 transistor 224 receives the NGATE signal output by the global voltage generator circuit 100. One S / D terminal of the MN2 transistor 224 is connected to an I2 current source 227, while the other S / D terminal is connected to node 240. The I2 current source 227 is further connected to a first voltage rail. Node 240 is connected to a first S / D terminal of an MP2 PMOS transistor 226, which has a second S / D terminal connected to an I2 current source 228. The current source 228 is further connected to a second or ground voltage rail. The gate of the MP2 transistor 226 is connected to the gate terminal of the PMOS transistor 216. Unless otherwise stated, in the examples discussed herein, the current I1 is the same as the current I2, or I1 = I2.

[0067] The distributed local driver circuit 200 also includes a third stage 203, which is a buffer stage with a push-pull configuration. The push-pull amplifier stage 203 includes a PMOS transistor 252 connected between a first voltage rail and an output node 260. An NMOS transistor 254 is connected between the output node 260 and a second voltage rail. The NMOS transistor 254 has a gate connected to the junction of current source 227 and MN2 transistor 224, and the PMOS transistor 256 has a gate connected to the junction of current source 228 and MP2 transistor 226.

[0068] As described above, the feedback loop 112 of the global voltage generator circuit 100 is located on the source side of the source follower configuration. Therefore, the voltage at node 130 is approximately the reference voltage VREF plus the gate-source voltage (VGS) of transistor MN1 114 (VREF + VGS of MN1). In the illustrated example, the first amplifier stage 201 of the distributed local driver circuit 200 is a source follower stage. The gate of NMOS transistor 214 receives an NGATE signal from the global voltage generator circuit 100, which is the same as or very close to the reference voltage VREF. The source follower configuration of the first amplifier stage 201 is also connected to the I1 current source 218. If NMOS transistor 214 and PMOS transistor 216 are manufactured similarly to MN1 transistor 114 and PMOS transistor 216, and the current through these transistors is the same, then the VGS of NMOS transistor 214 replicates the VGS of MN1 transistor 114 of the global voltage generator circuit 100 (i.e., is the same as or very close to it). Therefore, the voltage at node 230 will be the same as or close to the voltage at node 130. Furthermore, if the I2 current level is the same as the I1 current level, then the VGS of transistor MN2 224 will be replicated to be the same as or close to the VGS of NMOS transistor 214 and transistor MN1 114. Thus, the voltage at node 240 will replicate the voltage levels at nodes 130 and 230.

[0069] The third amplifier stage 203 is a buffer stage for outputting the VBL signal. For example, if the VBL output voltage at node 260 (and node 240) decreases, the VGS level of transistor MN2 224 increases. This causes an increase in the current of transistor 227, thereby reducing the bias voltage at the gate of NMOS transistor 254 and increasing the current flowing to NMOS transistor 254.

[0070] Therefore, instead of directly outputting the VBL signal from the global voltage generator circuit 100 to the memory macro 20, the global voltage generator circuit 100 includes a feedback loop 112 to output the bias signal NGATE to the distributed local driver circuit 200 that replicates the input signal VREF. The distributed local driver circuit 200 uses the bias signal NGATE to generate the VBL output signal that replicates the reference voltage VREF, without requiring a large feedback loop at the distributed local driver circuit 200.

[0071] Figure 3 illustrate Figure 2 The illustrated example implementations of the global voltage generator circuit 100 and the distributed local driver circuit 200 are shown. Figure 3In this configuration, I1 current sources 118 and 218 and I2 current sources 227 and 228 are replaced with specific components to achieve the desired current level. More specifically, NMOS transistor 242 is connected between the ground voltage rail and MP1 transistor 116. The gate of NMOS transistor 242 is connected to the NBIAS signal, which is used to bias NMOS transistor 242 to achieve the I1 current level. Similarly, NMOS transistor 244 is connected in a first stage 201 between the ground voltage rail and PMOS transistor 216. This transistor 244 has a gate connected to the NBIAS signal to bias NMOS transistor 244 in the same or similar manner as NMOS transistor 242 to achieve the I1 current level. PMOS transistor 245 and NMOS transistor 246 are included in a second stage 202. PMOS transistor 245 is connected between the Vdd voltage rail and MN2 transistor 224. MN2 transistor 245 has a gate connected to the PBIAS signal. NMOS transistor 246 is connected between the ground rail and MP2 transistor 226. NMOS transistor 246 has a gate connected to the NBIAS signal. PMOS transistor 245 and NMOS transistor 246 are thus biased to provide the desired I2 current, which is the same as or close to the I1 current.

[0072] Figure 4 This illustrates an example of an alternative distributed local driver circuit 200 that includes a current mirror push-pull stage. Figure 4 In one example, the distributed local driver circuit 200 includes essentially the same as Figure 2 and Figure 3 The examples shown are the same as the first two levels, 201 and 202. More specifically, Figure 4 The distributed local driver circuit 200 has a first source follower stage 201, wherein an NMOS transistor 214 has a first S / D terminal connected to a first voltage rail and a second S / D terminal connected to node 230. The gate terminal of the NMOS transistor 214 is connected to the input terminal of the distributed local driver circuit 200 to receive the NGATE signal output by the global voltage generator circuit 100. A PMOS transistor 216 has one S / D terminal connected to node 230 and another S / D terminal connected to an I1 current source 218. The I1 current source 218 is connected to a second (ground) voltage rail.

[0073] The second source follower stage 202 includes an MN2 NMOS transistor 224, which has a gate terminal connected to the input of the distributed local driver circuit 200 to receive the NGATE signal output by the global voltage generator circuit 100. One S / D terminal of the MN2 transistor 224 is connected to an I2 current source 227, while the other S / D terminal of the MN2 transistor 224 is connected to node 240. The I2 current source 227 is further connected to a first voltage rail. Node 240 is connected to a first S / D terminal of an MP2 PMOS transistor 226, which has a second S / D terminal connected to an I2 current source 228. The current source 228 is further connected to a second or ground voltage rail. The gate of the MP2 transistor 226 is connected to the gate terminal of the PMOS transistor 216.

[0074] The third stage 203a of the distributed local driver circuit 200 is a current mirror push-pull stage, which includes PMOS transistor 270 and NMOS transistor 272, respectively connected to PMOS transistor 245 and NMOS transistor 246 as current mirrors. Further, NMOS transistors 274 and 278 and PMOS transistors 276 and 280 are connected to form a push-pull current mirror configuration. The current mirror stage 203a has an output node 290 at the junction of NMOS transistor 278 and PMOS transistor 280, wherein the VBL output voltage is provided to the memory macro 20.

[0075] Figure 5 This describes another embodiment of the distributed local driver circuit 200, which uses a transconductance amplifier configuration that allows for a larger gate voltage swing. Like the previous examples of local driver circuits, the distributed local driver circuit 200 includes... Figures 2 to 4 The illustrated example uses similarly configured stages 201 and 202. The first source follower stage 201 includes an NMOS transistor 214, which has a first S / D terminal connected to a first voltage rail (e.g., Vdd) and a second S / D terminal connected to node 230. The gate of the NMOS transistor 214 is connected to the input of the distributed local driver circuit 200 to receive the NGATE signal output from the global voltage generator circuit 100. A PMOS transistor 216 has one S / D terminal connected to node 230 and another S / D terminal connected to an I1 current source 218. The I1 current source 218 is connected to a second (ground) voltage rail.

[0076] The second source follower stage 202 includes an MN2 NMOS transistor 224, which has a gate terminal connected to the input of the distributed local driver circuit 200 to receive the NGATE signal output by the global voltage generator circuit 100. One S / D terminal of the MN2 transistor 224 is connected to an I2 current source 227, while the other S / D terminal of the MN2 transistor 224 is connected to node 240. The I2 current source 227 is further connected to a first voltage rail. Node 240 is connected to a first S / D terminal of an MP2 PMOS transistor 226, which has a second S / D terminal connected to an I2 current source 228. The current source 228 is further connected to a second or ground voltage rail. The gate of the MP2 transistor 226 is connected to the gate terminal of the PMOS transistor 216.

[0077] The third stage 203b of the distributed local driver circuit 200 includes a PMOS transistor 302 connected between the second S / D terminal of the MN2 transistor 224 and the I1 current source 301. The PMOS transistor 302 is further connected to the gate of the NMOS transistor 306 in a common-gate stack configuration. The gate of the PMOS transistor 302 receives a bias voltage bpc. An NMOS transistor 308 is connected between the second S / D terminal of the MP2 transistor 226 and another I1 current source 300. The NMOS transistor 308 is further connected to the gate of the PMOS transistor 304 in a common-gate stack configuration. The gate of the NMOS transistor 308 receives a bias voltage bnc. The output node 310 is located at the junction of the PMOS transistor 304 and the NMOS transistor 306.

[0078] For example, if a strong current load (e.g., from the connected memory macro 20) is present at output node 310, the voltage level at output node 310 will drop. Therefore, the VBL output voltage will be lower than the steady-state output value, and the voltage at node 240 will also drop. The current through transistor MN2 224 will correspondingly increase from its quiescent current, and the current through the stacked PMOS transistor 302 will decrease (i.e., I2–MN2 current). The I1 current is now stronger or higher than the current through transistor 302, causing the N2 bias voltage level to decrease and reducing the bias voltage at the gate of NMOS transistor 306.

[0079] Furthermore, when the voltage at node 240 decreases, less current flows through MP2 transistor 226 (the gate bias voltage of MP2 transistor 226, set by the first stage 201, remains constant), resulting in more current flowing through the stacked NMOS transistor 308, which reduces the N1 bias voltage. The reduced N1 bias voltage causes more current to flow through PMOS transistor 304 to the output node 310, thereby restoring the VBL output voltage to the VREF level. If the output voltage at node 310 increases, the distributed local driver circuit 200 will operate in the opposite manner, increasing the N2 bias voltage to turn on NMOS transistor 306 to drain current from output node 310, and decreasing the N1 bias voltage to turn off PMOS transistor 304 to reduce the current flowing to output node 310, thereby reducing the voltage at node 310 to the desired VBL level (i.e., VREF). The common-gate stack configuration provides rail-to-rail voltage swing for bias voltages N1 and N2, thereby allowing for greater gate swing of transistors 304 and 306.

[0080] The examples discussed above are used to output NGATE signals to bias NMOS transistors in various local driver circuits. However, this disclosure is not limited to outputting NGATE bias signals for controlling NMOS devices. Figure 6 The illustrated example is a voltage regulator system 30a, in which a global voltage generator circuit 100 outputs a PGATE bias signal to bias the PMOS transistors of a distributed local driver circuit 200. The PGATE bias signal, and therefore the VBL output signal, replicates the VREF signal received by the global voltage generator circuit 100. It should be noted that this disclosure is not limited to the output bit line signal VBL.

[0081] Figure 6 The global voltage generator circuit 100 shown in the example includes a differentiating amplifier 410 having a first input, a second input, and an output. The first input is connected to a reference voltage signal VREF. As in previous embodiments, for example, the VREF signal can be received by a bandgap reference circuit. A feedback loop 412 is connected between the output of the differentiating amplifier 410 and the second input of the differentiating amplifier 410, allowing the differentiating amplifier 410 to compare the output signal PGATE with the reference signal VREF. An MN1 NMOS transistor 414 has one S / D terminal connected to an I1 current source 418 and another S / D terminal connected to node 430. The transistor 418 is a diode connected in a common-source configuration. The current source 418 is connected to a first voltage rail (Vdd), and a compensation capacitor 420 is connected between the output of the differentiating amplifier 410 and the first voltage rail. The global voltage generator circuit 100 is thus used to establish a voltage level at node 430 that replicates or is very close to the reference voltage VREF.

[0082] MP1 PMOS transistor 416 has a first S / D terminal connected to node 430 and a second S / D terminal connected to the second voltage rail. The gate terminal of transistor 416 is connected to the output of differentiating amplifier 410.

[0083] The output of the global voltage generator circuit 100 is connected to the input of each distributed local driver circuit 200. Figure 6 The distributed local driver circuit 200 has a first source follower stage 501 including an NMOS transistor 514, which has one S / D terminal connected to an I1 current source 518 and another S / D terminal connected to node 530. The PMOS transistor 518 is diode-connected. The I1 current source 518 is connected to a first voltage rail. The PMOS transistor 516 has a first S / D terminal connected to node 530 and a second S / D terminal connected to a second voltage rail. The gate of the PMOS transistor 516 receives the PGATE signal output by the global voltage generator circuit 100. As discussed above with the NMOS-based distributed local driver circuit 200, node 530 is used to replicate the voltage (i.e., VREF) at node 430 of the global voltage generator circuit 100.

[0084] The distributed local driver circuit 200 further includes a second source follower stage 502, wherein the MP2 PMOS transistor 526 has a gate terminal connected to the gate of the PMOS transistor 516, and thus also receives the PGATE signal output by the global voltage generator circuit 100. One S / D terminal of the MP2 PMOS transistor 526 is connected to an I2 current source 528, while the other S / D terminal of the MP2 transistor 526 is connected to node 540. The I2 current source 528 is further connected to a second voltage rail. An I2 current source 527 is connected to a first S / D terminal of the MN2 NMOS transistor 524, which has a second S / D terminal connected to node 540. The current source 527 is further connected to a first voltage rail. The gate of the MN2 transistor 524 is connected to the gate terminal of the transistor 514.

[0085] The distributed local driver circuit 200 includes a push-pull amplifier stage 503, which includes a PMOS transistor 554 connected between a first voltage rail and an output node 560. An NMOS transistor 556 is connected between the output node 560 and a second voltage rail. The PMOS transistor 554 has a gate connected to the junction of current source 527 and MN2 transistor 524, and the NMOS transistor 556 has a gate connected to the junction of current source 528 and MP2 transistor 526.

[0086] Figure 7An alternative embodiment of the PMOS-based local driver circuit 200 is described. The distributed local driver circuit 200 also receives a PGATE bias signal from the global voltage generator circuit 100 and uses it to output a VBL output signal that replicates the VREF signal. The first driver stage 501a includes an I1 current source 518 connected at node 530 to a PMOS transistor 516. The PMOS transistor 516 is connected between node 530 and a second voltage rail, and has a gate terminal connected to receive the PGATE signal output from the global voltage generator circuit 100.

[0087] The second driver stage 502a includes an I1 current source 570 connected at node 540 to an MP2 PMOS transistor 526. The MP2 PMOS transistor 526 is connected between node 540 and an I2 current source 528 connected to a second voltage rail. The gate of the MP2 PMOS transistor 526 is connected to receive the PGATE signal output from the global voltage generator circuit 100.

[0088] The third driver stage 504 includes an I1 current source 572 connected at node 542 to a PMOS transistor 580. The PMOS transistor 580 is connected between node 542 and an I3 current source 574, which is connected to a second voltage rail. Figure 7 In this example, I1 = I2 = I3. The gate of the PMOS transistor 580 is also connected to receive the PGATE signal output by the global voltage generator circuit 100.

[0089] Figure 7 The distributed local driver circuit 200 further includes a push-pull amplifier stage 503a, which includes a PMOS transistor 554 connected between a first voltage rail and an output node 560. The output node 560 is connected to nodes 540 and 542 of the corresponding second driver stage 502a and third driver stage 504. An NMOS transistor 556 is connected between the output node 560 and the second voltage rail. Transistor 554 has a gate at node 544 connected to the junction of an I1 current source 576 and a common-gate stacked NMOS transistor 578. Transistor 578 has a gate connected to a bias signal bnc. NMOS transistor 556 has a gate at node 546 connected to the junction of an I2 current source 528 and an MP2 PMOS transistor 526.

[0090] If the current load at output node 560 causes a drop in the VBL output voltage, the voltage at node 542 will also drop, and the current flowing through MP3 PMOS transistor 580 will decrease. Therefore, the current through stacked transistor 578 will increase. When the current flowing through stacked transistor 578 exceeds the I1 current level, the bias voltage at node 544 will decrease, thereby turning on PMOS transistor 554 to deliver additional current to output node 560 to increase the VBL voltage level. Since transistor 554 is directly connected to the first voltage rail, it can deliver the full Vdd voltage.

[0091] If the VBL voltage at output node 560 increases, the voltages at nodes 540 and 542 increase, and the currents through transistors 526 and 580 also increase accordingly. If the current through transistor 526 exceeds the I2 current level, the bias voltage at node 546 will increase, thereby turning on NMOS transistor 556 to draw current from output node 560 and reduce the VGL voltage level.

[0092] Figure 8 This describes a voltage regulator method 600 according to some embodiments. Referring to the discussion above... Figure 2 Method 600 includes receiving a reference voltage VREF by a global voltage generator circuit 100 at operation 610. At operation 612, the global voltage generator circuit 100 generates a gate control signal NGATE. In some instances, generating the gate control signal NGATE involves comparing the gate control signal with the reference voltage using a differentiating amplifier 110, such that the gate control signal NGATE replicates the reference voltage VREF. In other words, the voltage level of NGATE is the same as or very close to the voltage level of VREF. At operation 614, the global voltage generator circuit 100 outputs the gate control signal NGATE to each of the plurality of local driver circuits 200. At operation 616, the gate control signal NGATE is received by multiple driver stages 201, 202 of each of the plurality of local driver circuits 200. At operation 618, each of the plurality of local driver circuits 200 outputs a memory control signal VBL to the corresponding memory macro 20. Figure 1 (or a corresponding set of memory macros 20). The memory control signal VBL is output by the buffer stage 203 of each of the local driver circuits 200. Further, the memory control signal VBL replicates the reference voltage signal VREF.

[0093] Therefore, this disclosure provides a regulator system incorporating distributed local driver circuitry, wherein the plurality of distributed local driver circuits are compactly integrated with a push-pull driver stage. The local driver circuitry operates with low standby power and can drive large memory arrays without suffering from IR issues. Each distributed local driver circuit receives a bias voltage from a global regulator, which uses a feedback loop to replicate the received reference voltage, thereby generating an accurate output signal.

[0094] According to some embodiments, the voltage regulator circuit includes a global voltage generator circuit with a differentiating amplifier having a first input, a second input, and an output for receiving a reference voltage signal. A feedback loop is connected between the output of an error amplifier and the second input of the differentiating amplifier. Multiple driver circuits each include: a first driver stage having an input connected to the output of the differentiating amplifier; a second driver stage having an input connected to the output of the differentiating amplifier and an output node; and a buffer stage connected to the output node of the second amplifier stage and having an output.

[0095] In some embodiments, the feedback loop includes an amplifier circuit connected to the output of the differentiating amplifier. In some embodiments, the amplifier circuit of the feedback loop includes a source follower amplifier. In some embodiments, the voltage regulator circuit further includes a compensation capacitor connected to the output of the differentiating amplifier. In some embodiments, the first driver stage includes a first source follower stage connected to the output of the differentiating amplifier, and the second driver stage includes a second source follower stage connected to the output of the differentiating amplifier. In some embodiments, the buffer stage includes a push-pull amplifier connected to the output node of the second driver stage. In some embodiments, the push-pull amplifier includes a current mirror push-pull circuit. In some embodiments, the push-pull amplifier includes a transconductance amplifier circuit. In some embodiments, the buffer stage is used to provide an output signal that replicates a reference voltage signal. In some embodiments, the first driver stage includes a first NMOS transistor, and the input of the first driver stage includes the gate of the first NMOS transistor, and the second driver stage includes a second NMOS transistor, and the input of the second driver stage includes the gate of the second NMOS transistor. In some embodiments, the first driver stage includes a first PMOS transistor, and the input of the first driver stage includes the gate of the first PMOS transistor, and the second driver stage includes a second PMOS transistor, and the input of the second driver stage includes the gate of the second PMOS transistor. In some embodiments, the driver circuit does not include a feedback loop.

[0096] According to a further example embodiment, the memory system includes multiple memory macros, each memory macro having an array of memory cells. A global voltage generator circuit has a reference input for receiving a reference voltage and an output for outputting a gate signal that replicates the reference voltage. Multiple driver circuits each have an input connected to the output of the global voltage generator circuit and an output connected to a corresponding one of the multiple memory macros. Each driver circuit outputs a control signal that replicates the reference voltage, wherein the multiple driver circuits do not include compensation capacitors.

[0097] In some embodiments, the global voltage generator circuit includes: a differentiating amplifier having an input terminal and an output terminal of the global voltage generator circuit; a feedback loop including a common-source amplifier; and a compensation capacitor connected between the common-source amplifier and the output terminal. In some embodiments, the common-source amplifier includes: a first transistor having a gate terminal connected to the output terminal of the global voltage generator circuit, a first source / drain terminal connected to a first voltage rail, and a second source / drain terminal connected to a feedback node, wherein the feedback node is connected to a second input of the differentiating amplifier; a second transistor having a first source / drain terminal and a second source / drain terminal connected to the feedback node, and a gate terminal connected to the second source / drain terminal of the second transistor; a current source connected between the second voltage rail and the second source / drain terminal of the second transistor; and wherein the compensation capacitor is connected between the second voltage rail and the output terminal. In some embodiments, each of the driver circuits includes: a first driver stage including an input terminal connected to the output terminal of the differentiating amplifier; a second driver stage including an input terminal connected to the output terminal of the differentiating amplifier and an output node; and a buffer stage connected to the output node of the second amplifier stage and having an output terminal.

[0098] According to a further embodiment, the voltage regulator method includes receiving a reference voltage by a global voltage generator circuit and generating a gate control signal by the global voltage generator circuit. Generating the gate control signal includes comparing the gate control signal with the reference voltage using a differentiating amplifier, such that the gate control signal replicates the reference voltage. The gate control signal is output by the global voltage generator circuit to each of a plurality of local driver circuits. The gate control signal is received by multiple driver stages of each of the plurality of local driver circuits. A memory control signal replicating the reference voltage signal is output by a buffer stage of each of the plurality of local driver circuits.

[0099] In some embodiments, each of the local driver circuits outputs a memory control signal to a corresponding memory macro. In some embodiments, the step of receiving a gate control signal by the driver stage of each of the local driver circuits includes the step of amplifying the received gate control signal by a source follower amplifier stage. In some embodiments, the step of outputting a memory control signal that replicates a reference voltage signal by the buffer stage of each of the local driver circuits includes the step of processing the gate control signal by a push-pull buffer circuit.

[0100] This disclosure outlines various embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A voltage regulator circuit, characterized in that, include: A global voltage generator circuit includes: A differentiating amplifier has a first input terminal, a second input terminal, and an output terminal for receiving a reference voltage signal; A feedback loop is connected between the output terminal of the differentiating amplifier and the second input terminal of the differentiating amplifier; A plurality of driver circuits, each of the plurality of driver circuits comprising: A first driver stage includes an input terminal connected to the output terminal of the differentiating amplifier; A second driver stage includes an input terminal and an output node connected to the output terminal of the differentiating amplifier; A buffer stage is connected to the output node of the second amplifier stage and has an output terminal.

2. The voltage regulator circuit as described in claim 1, characterized in that, The feedback loop includes an amplifier circuit connected to the output of the differentiating amplifier.

3. The voltage regulator circuit as described in claim 2, characterized in that, The amplifier circuit of the feedback loop includes a source follower amplifier.

4. The voltage regulator circuit as described in claim 1, characterized in that, The first driver stage includes a first source follower stage connected to the output of the differentiating amplifier, and the second driver stage includes a second source follower stage connected to the output of the differentiating amplifier.

5. The voltage regulator circuit as described in claim 1, characterized in that, The first driver stage includes a first N-channel metal-oxide-semiconductor transistor, and the input terminal of the first driver stage includes the gate terminal of the first N-channel metal-oxide-semiconductor transistor. The second driver stage includes a second N-channel metal-oxide-semiconductor transistor, and the input terminal of the second driver stage includes a gate terminal of the second N-channel metal-oxide-semiconductor transistor.

6. The voltage regulator circuit as described in claim 1, characterized in that, The first driver stage includes a first P-channel metal-oxide-semiconductor transistor, and the input terminal of the first driver stage includes the gate terminal of the first P-channel metal-oxide-semiconductor transistor. The second driver stage includes a second P-channel metal-oxide-semiconductor transistor, and the input terminal of the second driver stage includes a gate terminal of the second P-channel metal-oxide-semiconductor transistor.

7. A memory system, characterized in that, include: Multiple memory macros, each containing an array of memory cells; A global voltage generator circuit has a reference input terminal for receiving a reference voltage and an output terminal for outputting a gate signal that replicates the reference voltage. and A plurality of driver circuits, each of the plurality of driver circuits having an input terminal connected to the output terminal of the global generator circuit and an output terminal connected to a corresponding one of the plurality of memory macros for outputting a control signal for replicating the reference voltage, wherein the plurality of driver circuits do not include a compensation capacitor.

8. The memory system as claimed in claim 7, characterized in that, The global voltage generator circuit includes: A differentiating amplifier having the input terminal and the output terminal of the global voltage generator circuit; A feedback loop, including a common-source amplifier; and A compensation capacitor is connected between the common-source amplifier and the output terminal.

9. The memory system as claimed in claim 7, characterized in that, This common-source amplifier includes: A first transistor has a gate terminal connected to the output terminal of the global voltage generator circuit, a first source / drain terminal connected to a first voltage rail, and a second source / drain terminal connected to a feedback node, wherein the feedback node is connected to the second input of the differentiating amplifier; A second transistor having a first source / drain terminal connected to the feedback node, a second source / drain terminal connected to the second source / drain terminal of the second transistor; A current source is connected between a second voltage rail and the second source / drain terminals of the second transistor; and The compensation capacitor is connected between the second voltage rail and the output terminal.

10. A method for operating a voltage regulator circuit, characterized in that, Includes the following steps: A reference voltage is received by a global voltage generator circuit; The global voltage generator circuit generates a gate control signal, which includes comparing the gate control signal with the reference voltage using a differentiating amplifier, so that the gate control signal replicates the reference voltage. The global voltage generator circuit outputs the gate control signal to each of the multiple local driver circuits. The gate control signal is received by multiple driver stages of each of the multiple local driver circuits; and A memory control signal that replicates the reference voltage signal is output by a buffer stage of each of the plurality of local driver circuits.

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