Semiconductor test structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor test structure and its manufacturing method, relating to the field of semiconductor technology. The semiconductor test structure includes: a test array region, comprising a first array of active test regions arranged in an array, the angle between the extension direction of the first active test regions and a first direction being a preset angle, wherein two adjacent second active test regions located in different columns are connected to each other at a first boundary of the test array region along a second direction; and a plurality of test conductive line groups arranged along the first direction, wherein each test conductive line group includes two adjacent test conductive lines, each test conductive line extending along the second direction through the test array region, and the test conductive lines in the plurality of test conductive line groups are correspondingly coupled to the first active test regions, wherein the first ends of the two adjacent test conductive lines in each test conductive line group are electrically connected through interconnected second active test regions. This disclosure can improve the reliability and stability of test bit lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor test structure and its manufacturing method. Background Technology

[0002] In semiconductor devices, bit lines serve as crucial interconnect structures in devices such as Dynamic Random Access Memory (DRAM), their core function being the selection of target cells after voltage is applied. The electrical performance parameters of these conductive lines directly determine whether the device functions correctly. With the miniaturization of manufacturing processes, bit lines are prone to breakage or short circuits. However, existing testing methods have significant drawbacks: firstly, single bit line testing structures cannot efficiently detect the resistance values ​​of a large number of bit lines, failing to reflect the overall failure situation; secondly, in improved solutions, when adjacent bit line groups are connected in series via peripheral electrical connection structures, the height difference between the peripheral region and the array region can easily lead to breakage of the connection structure, making it difficult to accurately reflect the true failure modes of the bit lines within the array region.

[0003] However, the shortcomings of existing test structures in terms of reliability and stability have become a major bottleneck in evaluating bit line electrical performance and thus improving device performance. Therefore, there is an urgent need for a semiconductor testing solution that improves test reliability and simplifies interconnection structures.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a semiconductor test structure and its manufacturing method, which improves the reliability and stability of the bit line test process.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a semiconductor test structure is provided, comprising: a test array region including a first test active region arranged in an array, wherein the angle between the extension direction of the first test active region and a first direction is a preset angle, wherein two second test active regions located in different columns and adjacent to each other are connected to each other at a first boundary of the test array region along a second direction; a plurality of test conductive line groups arranged along the first direction, wherein each test conductive line group includes two adjacent test conductive lines, each test conductive line extending through the test array region along the second direction, wherein the test conductive lines in the plurality of test conductive line groups are correspondingly coupled to the first test active region, wherein the first ends of the two adjacent test conductive lines in each test conductive line group are electrically connected through the interconnected second test active regions.

[0008] In some embodiments, the system further includes: at least one electrical connection structure and two external structures located at the second end of the test conductive line in the plurality of test conductive line groups, wherein the first end and the second end of the test conductive line are opposite to each other, the at least one electrical connection structure is electrically connected to the adjacent test conductive lines in adjacent test conductive line groups in the plurality of test conductive line groups, and the two external structures are respectively electrically connected to the two outermost test conductive lines among all the test conductive lines in the plurality of test conductive line groups.

[0009] In some embodiments, the number of electrical connection structures is multiple, including multiple first electrical connection structures and multiple second electrical connection structures. The first electrical connection structures and the second electrical connection structures are alternately arranged in a direction perpendicular to the extension of the test conductive line and are offset in a direction parallel to the extension of the test conductive line.

[0010] In some embodiments, the method further includes: two third active test regions located in different columns and adjacent to each other at the second boundary of the test array region along the second direction, such that the second ends of adjacent test conductive lines in adjacent test conductive lines of the plurality of test conductive lines are electrically connected through the interconnected third active test regions, wherein the first boundary and the second boundary of the test array region are opposite to each other; and two external structures, the two external structures being electrically connected to the two outermost test conductive lines of all test conductive lines in the plurality of test conductive lines respectively.

[0011] In some embodiments, the semiconductor test structure further includes a pad structure located at the end of the external structure away from the test conductive line group and connected to the external structure.

[0012] In some embodiments, the connection between two second test active regions located in different columns and adjacent to each other is achieved by modifying the boundary position of the active region trimming mask so that no shallow trench isolation is formed at the boundary of the active region trimming mask.

[0013] In some embodiments, the two second test active regions located in different columns and adjacent to each other are connected by shrinking the boundary of the active region trimming mask by a predetermined spacing.

[0014] In some embodiments, the preset spacing is a character line spacing.

[0015] In some embodiments, two second active test regions connected to each other at a first boundary of the test array region along a second direction and two third active test regions connected to each other at a second boundary of the test array region along a second direction are staggered in a first direction.

[0016] In some embodiments, the test conductive line is a test bit line.

[0017] According to another aspect of this disclosure, a method for manufacturing a semiconductor test structure is provided for manufacturing the semiconductor test structure described in any one of the preceding claims. The method includes: providing a semiconductor substrate, the semiconductor substrate including a device structure region and a dicing region; forming an array of active regions in the device structure region, and simultaneously forming an array of first test active regions in the dicing region, wherein forming the first test active region includes trimming the active region using an active region trimming mask, the first boundary of the active region trimming mask shrinking by a first preset spacing, such that at the first boundary of the test array region, active regions located in different columns... Furthermore, two adjacent second test active regions are connected to each other; multiple ring-shaped conductive lines and multiple ring-shaped conductive test lines are formed along the first direction, each of the ring-shaped conductive lines passing through the array of active regions; both ends of each of the multiple ring-shaped conductive lines are removed to form multiple conductive lines, and the same end of each of the multiple ring-shaped conductive test lines is removed to form multiple test conductive line groups; wherein, the first ends of two adjacent test conductive lines are aligned with the connected second test active regions at the first boundary of the test array area.

[0018] In some embodiments, the test conductive line includes a first end and a second end that are opposite to each other, two adjacent test conductive lines constitute the test conductive line group, and the first ends of two test conductive lines in the same test conductive line group are connected through the second test active region that is connected to each other.

[0019] In some embodiments, after forming the plurality of test conductive line groups, the method further includes: forming at least one electrical connection structure and two external structures, the electrical connection structure electrically connecting adjacent test conductive lines in adjacent test conductive line groups of the plurality of test conductive line groups; the two external structures being electrically connected to the two outermost test conductive lines among all the test conductive lines of the plurality of test conductive line groups, respectively.

[0020] In some embodiments, forming the first test active region further includes active region trimming using an active region trimming mask, wherein the second boundary of the active region trimming mask shrinks by a second preset spacing such that two third test active regions are connected to each other at the second boundary of the test array region.

[0021] In some embodiments, both the first preset spacing and the second preset spacing are one character line spacing.

[0022] In some embodiments, the test conductive line is a test bit line.

[0023] This disclosure provides a semiconductor test structure and its manufacturing method. The semiconductor test structure includes: a test array region, comprising a first array of active test regions arranged in an array, the angle between the extension direction of the first active test region and the first direction being a preset angle; wherein, at the first boundary of the test array region along the second direction, two adjacent second active test regions located in different columns are connected to each other; and a plurality of test conductive line groups arranged along the first direction, wherein each test conductive line group includes two adjacent test conductive lines, each test conductive line extending along the second direction through the test array region, and the test conductive lines in the plurality of test conductive line groups are coupled to the first active test regions accordingly; wherein, the first ends of the two adjacent test conductive lines in each test conductive line group are electrically connected through the interconnected second active test regions. In this disclosure, the interconnected second active test regions at the boundary of the test array region enable the plurality of test conductive lines contained in adjacent test conductive line groups to form a series structure. This connection structure of the test conductive lines is implemented within the test array region, thereby simplifying the wiring and connection process of the test conductive lines and reducing the risk caused by damage to the series connection structure. This allows for more stable monitoring of bit lines, which is beneficial for timely detection and accurate location of bit line faults, thereby improving the reliability and stability of the testing process.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 This diagram illustrates one of the semiconductor testing structures in the prior art.

[0027] Figure 2 This is a second schematic diagram of a semiconductor testing structure in the prior art;

[0028] Figure 3 This is the third schematic diagram of a semiconductor testing structure in the prior art;

[0029] Figure 4 This diagram illustrates a semiconductor testing structure according to an embodiment of the present disclosure.

[0030] Figure 5 This diagram shows a partial enlarged view of a semiconductor test structure according to an embodiment of the present disclosure;

[0031] Figure 6 This diagram illustrates a structural schematic of another semiconductor testing structure according to an embodiment of the present disclosure;

[0032] Figure 7 This diagram shows a partial enlarged view of another semiconductor test structure in an embodiment of this disclosure;

[0033] Figure 8 This illustration shows one of the structural schematic diagrams of yet another semiconductor test structure according to an embodiment of the present disclosure;

[0034] Figure 9 This is a second schematic diagram of another semiconductor testing structure in an embodiment of the present disclosure;

[0035] Figure 10 This is one of the schematic diagrams of an active region provided in the embodiments of this disclosure;

[0036] Figure 11 This is a second schematic diagram of an active region provided in an embodiment of the present disclosure;

[0037] Figure 12 This is the third schematic diagram of an active region provided in an embodiment of the present disclosure;

[0038] Figure 13 This is the fourth schematic diagram of an active region provided in an embodiment of the present disclosure;

[0039] Figure 14This is a comparative schematic diagram of shallow trench isolation provided in an embodiment of the present disclosure;

[0040] Figure 15a This is a schematic diagram of a conventional shallow trench isolation technique in the prior art;

[0041] Figure 15b This is a schematic diagram of a conventional shallow trench isolation structure in the prior art along the BB' section;

[0042] Figure 16 This is the fifth of a schematic diagram of an active region provided in an embodiment of the present disclosure;

[0043] Figure 17 A schematic diagram of shallow trench isolation along the AA' section provided in this embodiment of the present disclosure;

[0044] Figure 18 This diagram illustrates a method for manufacturing a semiconductor test structure according to an embodiment of the present disclosure.

[0045] Figure 19 This illustration shows one of the structural schematic diagrams of a semiconductor test structure during the fabrication process according to an embodiment of the present disclosure;

[0046] Figure 20 This is a second schematic diagram showing the fabrication process of a semiconductor testing structure according to an embodiment of the present disclosure;

[0047] Figure 21 This is shown as a third schematic diagram of the semiconductor test structure during the fabrication process in an embodiment of this disclosure;

[0048] Figure 22 This is shown as a fourth schematic diagram of the fabrication process of a semiconductor testing structure according to an embodiment of the present disclosure;

[0049] Figure 23 This is shown as the fifth schematic diagram of the semiconductor test structure during the fabrication process in an embodiment of this disclosure;

[0050] The reference numerals in the attached figures are explained as follows:

[0051] M, Electrical connection structure; 101, Device structure region; 102, Cut-out region; 10, Semiconductor substrate; A0, Original array; A1, Test array region; A2, First peripheral region; A3, Second peripheral region; A4, Array region; AA1, First test active area; AA2, Second test active area; AA3, Third test active area; AA4, Active area; AA5, Shallow trench isolation; AA5-1, Formed shallow trench isolation; AA5-2, Unformed shallow trench isolation; AA6, Non-conductive area; B1, First boundary; B2, Second boundary; D, Preset spacing; D1, First end of test conductive line L1; D2, Second end of test conductive line L1; L1a, Test conductive line group; L1a', Circular conductive test line; L1, Test conductive line; L1-1, First test conductive line; L1-2, Second test conductive line; L2a', Circular conductive line; L2, Conductive line; L3 (WL), Word line; M1-1. First active area trimming mask; M1-2, second active area trimming mask; M1-3, third active area trimming mask; M1-4, fourth active area trimming mask; PC, contact plug structure; P1, center of second test active area AA2; P2, center of third test active area AA3; P3, distance between the center of second test active area AA2 and the center of third test active area AA3; S, electrical connection structure; 11, first electrical connection structure; 111, first contact structure; 112, second contact structure; 113, first solder pad; 12, second electrical connection structure; 121, third contact structure; 122, fourth contact structure; 123, second solder pad; 13, external structure; 14, solder pad structure. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0053] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0054] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] Conductive lines are common components in semiconductor devices. They enable the selection of target cells by applying a suitable voltage. During the use of semiconductor devices, the electrical properties of the conductive lines play a crucial role in the device's functionality. For example, short circuits or high resistance in the conductive lines can easily cause overheating, leading to malfunctions or significant power loss at the location of the conductive lines, thus affecting the device's lifespan and performance.

[0059] As manufacturing processes shrink, bit lines (BLs) are prone to breakage or short circuits. In traditional technologies, see... Figure 1 As shown, bit line resistance monitoring in DRAM typically employs the following method: a polysilicon connection is made across the two ends of the same bit line, and a metal lead is used to connect it to the test pad. However, since the current test structure only contains a single bit line, it is difficult to efficiently detect the resistance of a large number of bit lines, and therefore cannot effectively reflect failures related to bit line breaks or short circuits. Figure 2 As shown, in the improved related technology, adjacent test conductive line groups are interconnected through an electrical connection structure M, thereby forming a series connection structure among the multiple test conductive lines contained in each group. However, research has found that, referring to... Figure 3 As shown, due to the height difference between the peripheral area where the electrical connection structure is located and the array area, the series connection structure connecting adjacent test conductive lines is at risk of breakage in the transition area formed between the peripheral area and the array area. Therefore, it is difficult to accurately reflect failure modes such as breakage or short circuit of the center line in the array area.

[0060] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0061] The semiconductor test structure provided in this disclosure includes:

[0062] The test array area includes a first test active area arranged in an array. The angle between the extension direction of the first test active area and the first direction is a preset angle. At the first boundary of the test array area along the second direction, two second test active areas located in different columns and adjacent in position are connected to each other.

[0063] Multiple test conductive line groups are arranged along a first direction, wherein each test conductive line group includes two adjacent test conductive lines, each test conductive line extends along a second direction through a test array area, and the test conductive lines in the multiple test conductive line groups are coupled to a first test active area, wherein the first ends of the two adjacent test conductive lines in each test conductive line group are electrically connected through a second test active area that is connected to each other.

[0064] In this embodiment, a second active test region interconnected at the boundary of the test array area enables multiple test conductive lines in adjacent test conductive line groups to form a series structure. This connection structure is implemented within the test array area, simplifying the wiring and connection process and reducing the risk of damage to the series connection structure. Consequently, bit lines can be monitored more stably, facilitating timely detection and accurate location of bit line faults, and improving the reliability and stability of the testing process.

[0065] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0066] Figure 4 This is a schematic diagram of a semiconductor testing structure provided in an embodiment of the present disclosure; Figure 5 This is a partial enlarged view of a semiconductor test structure provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of another semiconductor testing structure provided in an embodiment of the present disclosure; Figure 7 This is a partial structural diagram of a semiconductor test structure provided in an embodiment of this disclosure.

[0067] The semiconductor test structure provided in the embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings.

[0068] like Figures 4-6 As shown, the semiconductor test structure includes:

[0069] The test array area A1 includes a first test active area AA1 arranged in an array. The angle between the extension direction of the test active area and the first direction is a preset angle. At the first boundary B1 of the test array area A1 along the second direction, two second test active areas AA2 located in different columns and adjacent in position are connected to each other.

[0070] Multiple test conductive line groups L1a are arranged along a first direction, wherein each test conductive line group L1a includes two adjacent test conductive lines L1, each test conductive line L1 extends along a second direction through a test array region A1, and the test conductive lines L1 in the multiple test conductive line groups L1a are correspondingly coupled to a first test active region AA1, wherein the first ends D1 of the two adjacent test conductive lines L1 in each test conductive line group are electrically connected through a second test active region AA2 that is connected to each other.

[0071] The angle between the extension direction of the first test active region AA1 and the first direction is a preset angle, which must be adapted to the photolithographic pattern of the active region of the actual device. (Refer to...) Figure 10 As shown, in DRAM devices, since the initial active region definition mask is usually defined only on the diagonal of the array, the preset angle is preferably 20-80°, so that the first test active region AA1 extends diagonally, forming the shape of the active region in the actual device, and the same doping as the actual device is used to ensure that the carrier mobility and contact characteristics are matched.

[0072] Along the first boundary of the test array region A1 in the second direction, denoted as B1, and near the edge of the first peripheral region A2, two adjacent second test active regions located in different columns are denoted as AA2. For example, columns 2 and 3, 4 and 5, ..., columns 2n and 2n+1 are connected to each other. The connected second test active regions AA2 form a structure that smoothly transitions with the two adjacent second test active regions AA2, without steps or edge defects, ensuring a uniform current path and avoiding an increase in local parasitic resistance.

[0073] The test conductive line L1 is coupled to the first test active region AA1 and the second test active region AA2 through heavily doped contact regions. At the intersection of each test conductive line L1 and the first test active region AA1, a contact region is formed on the surface of the first test active region AA1. The heavily doped region is in direct contact with the test conductive line L1 to form an ohmic contact. This coupling method is consistent with the connection method of the active region of the bit line in the actual device, ensuring that the electrical characteristics of the test conductive line can directly reflect the actual bit line.

[0074] See details Figure 5 In each test conductive line group L1a, the first ends D1 (the ends closest to the first boundary B1) of the two test conductive lines L1 are electrically connected through the second test active regions AA2. Specifically, the first end of the first test conductive line L1-1 in the group is coupled to the heavily doped region of the second test active region AA2 in the nth column, and the first end of the second test conductive line L1-2 is coupled to the heavily doped region of the second test active region AA2 in the (n+1)th column. The second test active regions AA2 in the nth and (n+1)th columns are directly connected, thus forming a series path of "L1-1→AA2(nth column)→AA2(n+1th column)→L1-2", achieving series connection of the two test conductive lines within the group. This connection requires no additional metal or polysilicon, relying solely on the conductivity of the active regions themselves, reducing test errors introduced by parasitic structures.

[0075] In some embodiments, the semiconductor test structure includes a semiconductor substrate 10.

[0076] Here, the material of the semiconductor substrate 10 specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In one specific embodiment, the semiconductor substrate 10 is a silicon substrate.

[0077] Continue to refer to Figure 4 and Figure 6 As shown, in some embodiments, the semiconductor substrate 10 includes a device structure region 101 and a dicing region 102.

[0078] In some embodiments, the device structure region 101 includes an array region A4, which includes multiple active regions AA4 and multiple conductive lines L2 (bit lines BL2) passing through the active regions AA4. The dicing region 102 is used to separate multiple chip structures located on the wafer after performing relevant bonding operations on the wafer obtained by forming various structures on the semiconductor substrate 10.

[0079] In practice, the various structures located on the cutting channel area 102 are often used for testing purposes. This helps to avoid setting up connection structures for testing on the various structures located on the device structure area 101 when the test operation is performed. This does not change the original structural settings on the device structure area 101, thus helping to maintain the function of the original structure and avoiding additional costs and losses due to the execution of the test operation.

[0080] In actual operation, the active area AA4 can be set in the middle area of ​​the conductive line L2 in the extension direction, while in the cutting channel area 102, the positional relationship between the first test active area AA1 and the test conductive line L1 can be flexibly set according to the test requirements, without specific limitations.

[0081] In this embodiment, isolation between active regions is achieved through shallow trench isolation (STI) technology. In device structure region 101, STI completely covers the gaps between active regions, ensuring electrical isolation between device cells. However, in test array region A1 of cut-out region 102, STI only covers areas without active region connections. Since no trenches are formed between active regions at the first boundary B1, no STI insulating material is filled, and adjacent test active regions are directly connected. This avoids situations such as... Figure 3As shown, due to the height difference between the peripheral area where the electrical connection structure is located and the array area, the conductive connection structure connecting adjacent test conductive lines is at risk of damage, making it difficult to accurately reflect failure modes such as breakage or short circuit of the center line in the array area.

[0082] The layout, size, and materials of the test array area and test conductive line group in this embodiment are consistent with the actual device, requiring no additional process steps and can be directly integrated into the existing mass production process; and the test bit lines are connected in series through direct connection of the active area, avoiding the parasitic resistance introduced by the additional conductive structure, and the test results can directly reflect the actual bit line resistance value; in addition, the test structure is located in the dicing area, which does not occupy the area of ​​the device structure area and does not require sacrificing the effective functional area of ​​the chip.

[0083] In some embodiments, the material of the test bit line BL1 may comprise a conductive material. The conductive material may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanide).

[0084] It should be noted that, in the appendix Figure 4 and attached Figure 6 Although the diagram shows that the test bit lines BL1 are arranged side by side along the first direction and extend along the second direction, this is only to illustrate the arrangement and extension of the test conductive lines L1 in the semiconductor test structure, and is not intended to limit the actual arrangement and extension direction of the test bit lines BL1.

[0085] In some embodiments, refer to Figure 4 As shown, the semiconductor structure includes at least one electrical connection structure S and two external structures 13, located on the second end D2 of the test conductive line L1 in multiple test conductive line groups L1a. The first end D1 and the second end D2 of the test conductive line L1 are opposite to each other. The at least one electrical connection structure S is electrically connected to adjacent test conductive lines L1 in adjacent test conductive line groups L1a. The two external structures 13 are respectively electrically connected to the two outermost test conductive lines L1 in all test conductive lines L1a. In this embodiment, the electrical connection structure S and the external structures 13 achieve the overall series connection of multiple test conductive line groups, forming a test path that can be directly interfaced with external test equipment.

[0086] See Figure 4 , 5 and Figure 8 As shown, the electrical connection structure S is located at the second end D2 of the test conductive line L1 in multiple test conductive line groups L1a. Its function is to connect adjacent test conductive lines in adjacent test conductive line groups, connecting the test conductive line groups L1a in series to form a complete resistance path. See also... Figure 8 The second end of the second test conductive line L1-2 of group ① L1a is connected to the second end of the first test conductive line L1-1 of group ② L1a via an electrical connection structure, and so on, ultimately forming a series loop of "Group 1 L1-1 → Group 1 L1-2 → Group 2 L1-1 → Group 2 L1-2 → ... → Group N L1-2". The number of electrical connection structures can be N-1 groups of test conductive lines, with one connection structure for each gap, ensuring that all test conductive lines are included in the series loop without omissions or redundancy.

[0087] External structures 13 are located at the second end of the test conductive lines. There are two of them, which are electrically connected to the two outermost test conductive lines of all test conductive lines in the N groups of test conductive lines L1a, namely the first test conductive line L1-1 of group ① (the starting point of the series loop) and the second test conductive line L1-2 of group N (the ending point of the series loop). The core function of the external structures is to serve as test interfaces, connecting the series loop to external test equipment to realize the input and output of test current.

[0088] In this embodiment, the test lines are connected in series into a single path through an electrical connection structure. The resistance of all test lines can be monitored through only two external structures, without the need to test each line individually.

[0089] In some embodiments, the number of electrical connection structures S is multiple, and the multiple electrical connection structures S include multiple first electrical connection structures 11 and multiple second electrical connection structures 12. The first electrical connection structures 11 and the second electrical connection structures 12 are arranged alternately in a direction perpendicular to the extension of the test conductive line L1, and are offset in a direction parallel to the extension of the test conductive line L1.

[0090] It is understandable that the spacing of the test conductive line group L1a is limited. If all electrical connection structures adopt the same layout, it is easy to cause the metal pads of adjacent electrical connection structures to overlap. Alternating arrangement can avoid layout conflicts by staggering the positions, and at the same time reserve a larger operating window for photolithography and etching processes.

[0091] The first electrical connection structure 11 and the second electrical connection structure 12 are offset in a direction parallel to the extension of the test conductive line, with the offset direction being away from the test array area A1. It is understandable that, since the test conductive line L1 extends along the second direction, if the electrical connection structure is not offset, the current paths of adjacent electrical connection structures are prone to local overlap, resulting in uneven current distribution; while the preset distance offset in the second direction ensures that the current path of each test conductive line L1 is straight, without bends or intersections, thus improving the repeatability of the test results.

[0092] In some embodiments, the first electrical connection structure 11 includes at least a first contact structure 111 and a second contact structure 112, and the second electrical connection structure 12 includes at least a third contact structure 121 and a fourth contact structure 122, wherein: the first contact structure 111 and the second contact structure 112 are alternately arranged in a direction perpendicular to the extension of the test conductive line L1, and are offset in a direction parallel to the extension of the test conductive line L1; the third contact structure 121 and the fourth contact structure 122 are alternately arranged in a direction perpendicular to the extension of the test conductive line L1, and are offset in a direction parallel to the extension of the test conductive line L1.

[0093] In some embodiments, the first contact structure 111, the second contact structure 112, the third contact structure 121, and the fourth contact structure 122 can all be contact plug structures.

[0094] In some embodiments, the first electrical connection structure 11 further includes a first solder pad 113, which connects the first contact structure 111 and the second contact structure 112. The second electrical connection structure 12 further includes a second solder pad 123, which connects the third contact structure 121 and the fourth contact structure 122. Thus, the connection of adjacent test conductive lines L1 in adjacent test conductive line groups L1a can be achieved through the first solder pad 113 and the second solder pad 123.

[0095] In some embodiments, compared to the case where the first contact structure 111, the second contact structure 112, the third contact structure 121, and the fourth contact structure 122 are arranged side-by-side in the direction perpendicular to the extension of the test conductive line L1 and there is no offset in the direction parallel to the extension of the test conductive line L1, the arrangement of the first contact structure 111 and the second contact structure 112 alternating in the direction perpendicular to the extension of the test conductive line L1 and offset in the direction parallel to the extension of the test conductive line L1, and the arrangement of the third contact structure 121 and the fourth contact structure 122 alternating in the direction perpendicular to the extension of the test conductive line L1 and offset in the direction parallel to the extension of the test conductive line L1, helps to provide a larger process operation window for multiple contact structures during the process formation. This effectively prevents connection misalignment caused by a high density of multiple contact structures, which could lead to incorrect test results due to incorrect connection relationships. Simultaneously, it also effectively prevents mutual interference between multiple contact structures during operation, thus increasing the reliability of the test results.

[0096] Reference Figure 6 , 7 As shown in Figure 9, at the second boundary B2 along the second direction in the test array area A1, two third active test areas AA3 located in different columns and adjacent in position are physically connected to each other, such that the second ends D2 of adjacent test conductive lines L1 in multiple test conductive line groups L1a are electrically connected through the interconnected third active test areas AA3, wherein the first boundary B1 and the second boundary B2 of the test conductive lines L1 are opposite to each other; the two external structures 13 are respectively electrically connected to the two outermost test conductive lines L1 of all test conductive lines L1 in multiple test conductive line groups L1a.

[0097] This embodiment connects the active region at the second boundary and achieves a metal-free series connection at the second end of the test conductive line through double boundary connection, further simplifying the structure and reducing parasitic resistance.

[0098] See details Figure 6 The second boundary of the test array area A1 along the second direction is denoted as B2. Opposite to the first boundary B1, near the edge of the second peripheral area A3, are two adjacent third active test areas located in different columns, denoted as AA3. At the second boundary B2, two adjacent third active test areas AA3 located in different columns of adjacent conductor groups ① and ② are physically connected. For example, the third active test areas AA3 corresponding to the second column of group ① and the first column of group ② are physically connected to each other. The connection pattern is consistent with the second active test area AA2 at the first boundary B1, and the formation principle is similar.

[0099] It should be noted that the two second active test areas AA2 connected to each other at the first boundary B1 along the second direction of the test array area A1 and the two third active test areas AA3 connected to each other at the second boundary B2 along the second direction of the test array area A1 are staggered in the first direction.

[0100] Specifically, the second test active area AA2 (columns 1-2, 3-4, ..., n-(n+1)) connecting the first boundary B1 and the third test active area AA3 (columns 2-3, 4-5, ..., (n-1)-n) connecting the second boundary B2 are staggered in the first direction, with the stagger distance being the column spacing of the test active areas. For example, see... Figure 9 The center of the second test active region AA2 is located at P1, the center of the third test active region AA3 is located at P2, and the distance between the center of the second test active region AA2 and the center of the third test active region AA3 is P3.

[0101] In adjacent test conductive line groups L1a, the second ends D2 of adjacent test conductive lines L1 are electrically connected through the third test active region AA3 connected at the second boundary B2. Specifically, the second end of the second test conductive line L1-2 in the k-th group L1a is coupled to the heavily doped region of the third test active region AA3 in the k-th column; the second end of the first test conductive line L1-1 in the (k+1)-th group L1a is coupled to the heavily doped region of the third test active region AA3 in the (k+1)-th column; and the third test active regions AA3 in the k-th and (k+1)-th columns are directly connected, thus forming a series path of "k-th group L1-2 → AA3 (k-th column) → AA3 (k+1-th column) → k+1-th group L1-1", achieving series connection between adjacent test conductive line groups.

[0102] In this embodiment, since the test conductive wires have been connected in series through the active region at the second boundary B2, there is no need to set up an electrical connection structure. Only two external structures need to be retained, which are electrically connected to L1-1 (series start point) of the first group L1a and L1-2 (series end point) of the Nth group L1a, respectively. The construction of the external structure 13 is the same as in the above embodiment.

[0103] This embodiment replaces the metal electrical connection structure with an active region connection, reducing the fabrication steps of the electrical connection structure and lowering the process complexity. Furthermore, the resistance of the active region connection is much smaller than that of the metal electrical connection structure, thereby reducing parasitic resistance and further improving the accuracy of the test results. In addition, the metal electrical connection structure is susceptible to electromigration, while the active region connection is made of monocrystalline silicon, which has better resistance to electromigration.

[0104] In some embodiments, such as Figure 4 , 5As shown in Figure 8, the resistance of the test conductor L1 can be determined as follows: First, the structure of multiple test conductor groups L1a is considered as a simple repetition of a single test conductor group L1a. After obtaining the total resistance of the multiple test conductor groups L1a, the resistance is then determined based on the total resistance R. total = n × R0, where n represents the number of repetitions (i.e., the number of test conductive wire groups L1a), and R0 represents the resistance value of a single repetition unit; then, according to R0 = 2 × R L1 +R S Among them, R L1 R is the resistance of a single test conductor L1 among two test conductors L1 contained in a test conductor group L1a. S R represents the resistance of the electrical connection structure. S Specifically, it may include the contact structure that constitutes the electrical connection structure S and the resistance of the solder pads.

[0105] Understandably, since the two test conductive lines L1 are connected through an active region, the resistance can be ignored. Simultaneously, the resistance of the electrical connection structure S is ignored, meaning the wiring resistance between the test conductive line L1 and the contact plug and solder pad is also ignored. Therefore, R is obtained. S ≈0; thus, the actual resistance R of the test resistor can be obtained. total ≈2×n×R L1 Therefore, the final measured resistance per unit length of the test conductor L1 is R. L1 =R total / (n×2L), where 2L represents the length of the part of a single test conductive wire group L1a that participates in the resistance test. In other embodiments, when the length value of this part changes, the corresponding parameter variables can be adjusted to obtain the corresponding resistance value per unit length.

[0106] Similarly, such as Figure 6 , 7 As shown in Figure 9, since both ends of the two test conductive lines L1 are connected through the active region, the resistance can be ignored; thus, the actual test resistance R can be obtained. total ≈2×n×R L1 Therefore, the final measured resistance per unit length of the test conductor L1 is R. L1 =R total / (n×2L), where 2L represents the length of the part of a single test conductive wire group L1a that participates in the resistance test. In other embodiments, when the length value of this part changes, the corresponding parameter variables can be adjusted to obtain the corresponding resistance value per unit length.

[0107] In some embodiments, the test structure further includes a pad structure 14, which is located at the end of the external structure 13 on the side away from the test conductive line group L1a and connected to the external structure 13. In this embodiment, the pad structure 14 is used to contact the test structure, such as a probe, during the electrical performance testing operation of the test conductive line L1, thereby establishing an electrical connection between the test conductive line L1 and the external test equipment, improving the convenience and reliability of the test operation.

[0108] Specifically, the pad structure 14 is located at the end of the external structure 13 away from the test conductive line group L1a, and is electrically connected to the external structure 13. Each external structure corresponds to one pad structure. The core function of the pad structure is to serve as a direct contact carrier for the test probe. It can be understood that the metal wire of the external structure 13 is narrow, while the diameter of the test probe is usually 1μm. Direct contact is prone to misalignment. The pad structure adopts a large-size design, which can accommodate the positional deviation of the probe, while protecting the external structure from being scratched by the probe.

[0109] The metal wires of the pad structure 14 and the external structure 13 can be made of the same Al-1Cu alloy layer, with a rectangular shape and an area much larger than the contact area of ​​the probe. Effective contact can still be achieved even if the probe position deviation is within ±0.5μm. The surface of the pad structure is treated with chemical mechanical polishing, and the surface roughness is controlled within 5nm to ensure that the contact between the probe and the pad is a surface contact.

[0110] In some embodiments, the external structure 13 can achieve electrical connection with the outermost test conductor L1 among all the test conductors L1 of the plurality of test conductor groups L1a through the contact plug structure PC.

[0111] Figure 10 This is one of the schematic diagrams of an active region provided in the embodiments of this disclosure; Figure 11 This is a second schematic diagram of an active region provided in an embodiment of the present disclosure; Figure 12 This is the third schematic diagram of an active region provided in an embodiment of the present disclosure; Figure 13 This is the fourth schematic diagram of an active region provided in this embodiment of the present disclosure. Figure 14 This is a comparative schematic diagram of shallow trench isolation provided in an embodiment of the present disclosure; Figure 15a This is a schematic diagram of shallow trench isolation in the prior art provided by an embodiment of this disclosure. Figure 15b This is a schematic diagram of a shallow trench isolation along the BB' section in the prior art, provided as an embodiment of the present disclosure; Figure 16 This is the fifth of a schematic diagram of an active region provided in an embodiment of the present disclosure; Figure 17 This is a schematic diagram of a shallow trench isolation along the AA' section provided in an embodiment of the present disclosure.

[0112] See Figure 10-13 As shown, in some embodiments, two second test active regions AA2 located in different columns and adjacent in position are connected to each other by modifying the boundary position of the active region trimming mask so that shallow trench isolation AA5 is not formed at the boundary of the active region trimming mask. The active region trimming mask may include multiple masks. For example, in the four-step photomask formation of the active region, the active region trimming mask may include a first active region trimming mask M1-1, a second active region trimming mask M1-2, a third active region trimming mask M1-3, and a fourth active region trimming mask M1-4. It should be noted that AA5-1 represents the formed shallow trench isolation, and AA5-2 represents the failed shallow trench isolation.

[0113] The first active region trimming mask M1-1 is a key mask defining the final shape of the active region. Its function is to trim the initial active region pattern defined by the trimming mask, removing redundant active region portions and retaining areas that match the device function. In conventional processes, the boundary of the first active region trimming mask M1-1 is aligned with the array boundary trimming mask (such as the array boundary trimming mask, denoted as the BLZ mask, which defines the boundary of the bit line array, not shown in the figure) to ensure that a complete shallow trench isolation is formed between the active regions. It should be noted that the initial active region pattern formed by the first active region trimming mask M1-1 determines the range of the angle between the extension direction of all subsequent test active regions and the first direction. Specifically, this pattern provides a common extension direction reference for the first test active region AA1, the second test active region AA2, and the third test active region AA3, so their extension directions all have the same preset angle with the first direction.

[0114] In this embodiment, see Figures 14-17 As shown, the boundary of the fourth active region trimming mask M1-4 is moved inwards from the array, so that the two adjacent second test active regions AA2 that should have been isolated by STI are still within the coverage of the fourth active region trimming mask M1-4. The active region reserved area covered by the fourth active region trimming mask M1-4 includes the area corresponding to the shallow trench isolation AA5-2 that was not formed. Therefore, it will not be etched in the subsequent shallow trench isolation etching process, and the area corresponding to the shallow trench isolation AA5-2 that was not formed will not form shallow trench isolation. The two adjacent second test active regions AA2 can be integrally formed to form interconnected second test active regions AA2.

[0115] Taking the second test active region AA2 at the first boundary B1 as an example, see... Figure 14 In the original array A0, the boundary of the conventional fourth active region trimming mask is aligned with the boundary of the BLZ mask. The area between adjacent active regions is not covered by the fourth active region trimming mask and will be etched to form shallow trench isolation AA5 (see...). Figure 15a and Figure 15bThe modified fourth active region trimming mask boundary moves inward, so that the area where shallow trench isolation is formed at the edges of adjacent active regions is covered by the fourth active region trimming mask. This area is not etched during STI etching (see...). Figure 16 ), ultimately forming the connecting part (see Figure 17 This enables the active regions of adjacent columns to conduct. It should be noted that... Figure 15a and Figure 16 Both show L3 (WL), the word line, perpendicular to the first test conductive line L1-1 (bit line BL) and the second test conductive line L1-2 (bit line BL). Furthermore, Figure 15b and Figure 17 The cross-sectional schematic diagram further reveals the non-conductive region AA6 and its adjacent L3 (WL) structure.

[0116] This embodiment only modifies the layout data of the active region trimming mask, without redesigning the mask layer, and the mask manufacturing cost is not increased. It is 100% compatible with traditional processes. The second test active region connection is a monolithic silicon structure with no interface, so interface failure will not occur during long-term use. By adjusting the boundary movement of the active region trimming mask, the size of the connection part can be precisely controlled to meet the needs of different test scenarios.

[0117] In some embodiments, two second test active regions located in different columns and adjacent to each other are formed by shrinking the boundary of the active region trimming mask by a predetermined spacing.

[0118] The array boundary trimming mask (BLZ mask, Bit Line Zone mask) is a mask that defines the boundary of the bit line array. Its boundary position determines the range of the bit line array. In the device structure region, the boundary of the BLZ mask corresponds to the outermost edge of the bit line. In the test array region A1 of the cut channel region, the boundary of the BLZ mask (denoted as "first array boundary" and "second array boundary") corresponds to the outer edge of the test bit line array, and is consistent with the BLZ boundary process parameters of the device structure region.

[0119] The preset spacing, denoted as D, refers to the distance by which the boundary of the active area trimming mask contracts inwards from the array. This spacing design must meet two conditions: first, it must ensure that the shallow trench isolation area between two adjacent and collinear active areas in different columns within the array boundary region can be completely covered by the fourth active area trimming mask M1-4, allowing the two collinear active areas to form a connection through the mask's shielding effect; second, it must avoid excessive contraction leading to residual active areas (affecting other structures). In other words, in some implementations, it ensures that the shallow trench isolation area between two adjacent active areas in different columns within the array boundary region, located on the same straight line, can be covered by the fourth active area trimming mask M1-4, thus forming a connection between the two active areas. Specifically, it ensures that the shallow trench isolation area between two adjacent collinear active areas in different columns within the array boundary region is covered by the active area trimming mask, thereby forming a connection between the two active areas.

[0120] The first boundary of the active region trimming mask shrinks by a preset distance D relative to the first boundary of the original active region trimming mask; if there are two third test active regions AA3 connected at the second boundary B2, the second boundary of the active region trimming mask also shrinks by a preset distance D relative to the second boundary of the original active region trimming mask.

[0121] It should be noted that, in order to offset the two second active test regions AA2 connected to each other at the first boundary B1 along the second direction of the test array region A1 and the two third active test regions AA3 connected to each other at the second boundary B2 along the second direction of the test array region A1 in the first direction, the shrinkage of the second boundary of the active region trimming mask relative to the second boundary of the original active region trimming mask can be achieved by shrinking the boundary of other active region trimming masks. For example, the modified boundary of the third active region trimming mask M1-3 can be moved inward so that the edges of adjacent active regions are covered by the third active region trimming mask M1-3, avoiding etching during STI etching, and finally forming a connection part, so that the adjacent active regions are connected.

[0122] It should be noted that the formation principle of the two third test active regions AA3 connected to each other at the second boundary B2 is the same as that of the two second test active regions AA2 connected to each other at the first boundary B1. This embodiment will not elaborate on this principle.

[0123] In some embodiments, the preset spacing is word line spacing. In this embodiment, a word line spacing (WL pitch) is used to associate the design of the active area connection with the core linewidth parameters of the device, thereby improving process compatibility.

[0124] Word line pitch (WL pitch) is the distance between two adjacent bit lines in a memory device. It is determined by the process node (e.g., WL pitch = 30nm for a 30nm process node and WL pitch = 20nm for a 20nm process node) and is one of the core baseline parameters for device layout design (the dimensions of all structures are proportional to WL pitch).

[0125] This embodiment uses WL pitch as the preset spacing, which associates the design of the active area connection with the core parameters of the device without the need to define a new size reference, simplifying the layout design process; moreover, the process deviation of WL pitch is small, which reduces the batch-to-batch deviation of the active area connection resistor from ±10% to ±5%, making the test results more comparable; when the process node size changes, there is no need to change the connection principle, resulting in low migration cost.

[0126] In some embodiments, the test conductive line is a test bit line.

[0127] The semiconductor test structure provided in this disclosure can be applied to dynamic random access memory (DRAM).

[0128] This disclosure also provides a method for manufacturing a semiconductor test structure, such as... Figure 18 As shown, the manufacturing method includes the following steps:

[0129] S182, providing a semiconductor substrate, the semiconductor substrate including a device structure region and a dicing region.

[0130] S184, forming an array of active regions in the device structure region, and simultaneously forming an array of first test active regions in the cut-out region, wherein forming the first test active region includes using an active region trimming mask to trim the active region, the first boundary of the active region trimming mask shrinks by a first preset spacing, such that at the first boundary of the test array region, two second test active regions located in different columns and adjacent in position are connected to each other.

[0131] Specifically, refer to Figures 10-13 As shown, the test active region forming the array arrangement specifically includes:

[0132] See Figure 10 First active region trimming mask M1-1 photolithography and etching: Photoresist is applied, and exposure is performed using the first active region trimming mask M1-1 (initial active region definition mask); after development, a photoresist pattern is formed, retaining only the diagonal active region pattern of the test array area A1 in the cut channel region; dry etching (using S... / A mixed gas was used to form the initial test active region pattern (etched to a depth of 0.5 μm).

[0133] See Figure 11 Second active area trimming mask M1-2 photolithography and trimming: Apply new photoresist, expose using the second active area trimming mask M1-2 (unit array opening mask), and retain the range of test array area A1 after development; dry etching to remove the initial active area outside test array area A1 and define the array range of test active area.

[0134] See Figure 12 Photolithography and trimming of the third active region trimming mask M1-3: Coating photoresist, exposing with the third active region trimming mask M1-3 (array activation trimming mask), and after development, retaining the main body of the first test active region AA1 (removing redundant edge areas); dry etching to adjust the morphology of the first test active region AA1.

[0135] See Figure 13 The fourth active region trimming mask M1-4 is photolithographically modified and its boundaries are modified. Photoresist is applied, and the modified fourth active region trimming mask M1-4 is exposed. The first boundary of the fourth active region trimming mask M1-4 is reduced by a first preset spacing relative to the original fourth active region trimming mask M1-4. After development, the adjacent active region edge areas at the first boundary B1 of the test array area A1 are covered by photoresist. Dry etching is performed to remove only the active region portions not covered by photoresist, while retaining the adjacent active region connection portions at the first boundary B1, forming the interconnected second test active region AA2.

[0136] Shallow trench isolation (STI) formation: Si is deposited on the etched substrate surface. The trenches between the active regions are filled; CMP flattening is performed to form an STI structure. Since the adjacent active regions at the first boundary B1 are covered by the fourth active region trimming mask M1-4, there are no trenches in this area, so no STI is formed, and the adjacent active regions are directly connected.

[0137] S186, forming multiple ring-shaped conductive lines arranged along the first direction and multiple ring-shaped conductive test lines arranged along the first direction, each ring-shaped conductive line passing through the active region arranged in the array.

[0138] See Figure 19 As shown, forming a ring-shaped conductive line and a ring-shaped conductive test line may include the following steps: depositing conductive material: depositing a bottom layer of polycrystalline silicon; depositing a top layer of WS To form polycrystalline silicon-WS Composite conductive layer. Photoresist is coated, exposed using a bit line mask, and after development, multiple ring-shaped conductive lines (bit lines for the device structure region, denoted as L2a') arranged along the first direction are formed. Simultaneously, a test bit line mask is exposed, and after development, multiple ring-shaped conductive test lines (test bit lines for the cut channel region, denoted as L1a') arranged along the first direction are formed. Dry etching is used to remove the conductive layer not covered by photoresist, forming ring-shaped conductive lines L2a' and ring-shaped conductive test lines L1a'. Each ring-shaped conductive line L2a' passes through the active region AA4 of the device structure region, and each ring-shaped conductive test line L1a' passes through the first test active region AA1 of the test array region A1.

[0139] S188, remove both ends of each of the multiple loop conductive lines to form multiple conductive lines, and at the same time remove the same end of each of the multiple loop conductive test lines to form multiple test conductive line groups; wherein, the first ends of two adjacent test conductive lines are aligned with the second test active area connected to each other at the first boundary of the test array area.

[0140] In this embodiment, refer to Figure 20 As shown, the specific process may include: coating photoresist, exposing using a bit line cutting mask, developing and then covering the middle region of the ring-shaped conductive line L2a', exposing both ends; dry etching to remove both ends of the ring-shaped conductive line L2a', forming multiple independent conductive lines L2 in the device structure region. Coating photoresist, exposing using a test line cutting mask, developing and then covering the second end region of the ring-shaped conductive test line L1a', exposing the first end; dry etching to remove the first end of the ring-shaped conductive test line L1a', forming multiple test conductive line groups L1a in the cut channel region; aligning the first ends of two adjacent ring-shaped conductive test lines L1a' with two connected second test active regions AA2 at the first boundary B1 of the test active region, ensuring effective coupling between the first end of the test conductive line L1 and the second test active region AA2.

[0141] In some embodiments, such as Figure 20 As shown, the test conductive line L1 includes a first end D1 and a second end D2 that are opposite to each other. Two adjacent test conductive lines L1 constitute a test conductive line group L1a, and the first ends D1 of the two test conductive lines in the same test conductive line group L1a are connected through the two second test active regions AA2 that are connected to each other.

[0142] See Figure 21 After forming multiple test conductive wire groups L1a, the manufacturing method further includes:

[0143] At least one electrical connection structure S and two external structures 13 are formed. The electrical connection structure S is electrically connected to adjacent test conductive lines L1 in adjacent test conductive line groups L1a. The two external structures 13 are respectively electrically connected to the two outermost test conductive lines L1 of all test conductive lines L1 in the multiple test conductive line groups L1a.

[0144] In some embodiments, the number of electrical connection structures S is multiple, forming at least one electrical connection structure S, including:

[0145] Multiple electrical connection structures S are formed, including multiple first electrical connection structures 11 and multiple second electrical connection structures 12. The first electrical connection structures 11 and the second electrical connection structures 12 are arranged alternately in a direction perpendicular to the extension of the test conductive line L1, and are offset in a direction parallel to the extension of the test conductive line L1.

[0146] In some embodiments, the first electrical connection structure 11 includes at least a first contact structure 111 and a second contact structure 112, and the second electrical connection structure 12 includes at least a third contact structure 121 and a fourth contact structure 122, wherein: the first contact structure 111 and the second contact structure 112 are alternately arranged in a direction perpendicular to the extension of the test conductive line L1, and are offset in a direction parallel to the extension of the test conductive line L1; the third contact structure 121 and the fourth contact structure 122 are alternately arranged in a direction perpendicular to the extension of the test conductive line L1, and are offset in a direction parallel to the extension of the test conductive line L1.

[0147] In some embodiments, the first contact structure 111, the second contact structure 112, the third contact structure 121, and the fourth contact structure 122 can all be contact plug structures.

[0148] In some embodiments, such as Figure 22 The formation of the test active region also includes active region trimming using an active region trimming mask. The second boundary B2 of the active region trimming mask shrinks the second preset spacing so that at the second boundary B2 of the test array region, two third test active regions AA3 are connected to each other.

[0149] In some embodiments, such as Figure 23 As shown, two external structures 13 are formed, and the two external structures 13 are electrically connected to the two outermost test conductive lines of all test conductive lines of multiple test conductive line groups, respectively.

[0150] In some embodiments, the first preset spacing and the second preset spacing are a character line spacing.

[0151] In some embodiments, the test conductive line is a test bit line.

[0152] In summary, the embodiments of this application, through the design of active region connection and mask boundary optimization, achieve direct and accurate monitoring of bit line resistance without increasing process costs, while possessing high process compatibility and mass production feasibility, providing key support for bit line process optimization of semiconductor memory devices.

[0153] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor testing structure, characterized in that, include: The test array area includes a first test active area arranged in an array. The angle between the extension direction of the first test active area and the first direction is a preset angle. At the first boundary of the test array area along the second direction, two second test active areas located in different columns and adjacent in position are connected to each other. The connection between the two second test active areas located in different columns and adjacent in position is achieved by modifying the boundary position of the active area trimming mask so that no shallow trench isolation is formed at the boundary of the active area trimming mask. A plurality of test conductive line groups are arranged along a first direction, wherein each test conductive line group includes two adjacent test conductive lines, each test conductive line extends along a second direction through the test array region, and the test conductive lines in the plurality of test conductive line groups are coupled to the first test active region, wherein the first ends of the two adjacent test conductive lines in each test conductive line group are electrically connected through the second test active region that is connected to each other.

2. The semiconductor test structure according to claim 1, characterized in that, Also includes: At least one electrical connection structure and two external structures are located at the second end of the test conductive line in the plurality of test conductive line groups, wherein the first end and the second end of the test conductive line are opposite to each other, the at least one electrical connection structure is electrically connected to the adjacent test conductive lines in the plurality of test conductive line groups, and the two external structures are respectively electrically connected to the two outermost test conductive lines among all the test conductive lines in the plurality of test conductive line groups.

3. The semiconductor test structure according to claim 2, characterized in that, The number of electrical connection structures is multiple, including multiple first electrical connection structures and multiple second electrical connection structures. The first electrical connection structures and the second electrical connection structures are arranged alternately in the direction perpendicular to the extension of the test conductive line, and are offset in the direction parallel to the extension of the test conductive line.

4. The semiconductor test structure according to claim 1, characterized in that, Also includes: At the second boundary of the test array area along the second direction, two third active test areas located in different columns and adjacent in position are physically connected to each other, such that the second ends of adjacent test conductive lines in adjacent test conductive lines in the plurality of test conductive lines are electrically connected through the third active test areas connected to each other, wherein the first boundary and the second boundary of the test array area are opposite to each other. Two external structures are respectively electrically connected to the two outermost test conductive lines of all test conductive lines in the plurality of test conductive line groups.

5. The semiconductor test structure according to claim 2, characterized in that, The semiconductor test structure also includes a pad structure, which is located at the end of the external structure away from the test conductive line group and is connected to the external structure.

6. The semiconductor test structure according to claim 1, characterized in that, The two second test active regions located in different columns and adjacent to each other are connected by shrinking the boundary of the active region trimming mask by a preset spacing.

7. The semiconductor test structure according to claim 6, characterized in that, The preset spacing is one character line spacing.

8. The semiconductor test structure according to claim 4, characterized in that, The two second active test regions connected to each other at the first boundary of the test array region along the second direction and the two third active test regions connected to each other at the second boundary of the test array region along the second direction are staggered in the first direction.

9. The semiconductor test structure according to claim 1, characterized in that, The test conductive line is a test bit line.

10. A method for manufacturing a semiconductor test structure, characterized in that, The method for manufacturing the semiconductor test structure according to any one of claims 1-9 includes: A semiconductor substrate is provided, the semiconductor substrate including a device structure region and a dicing region; An array of active regions is formed in the device structure region, and an array of first test active regions is formed in the cut-out region. The formation of the first test active region includes active region trimming using an active region trimming mask. The first boundary of the active region trimming mask shrinks by a first preset spacing, such that two second test active regions located in different columns and adjacent to each other are connected at the first boundary of the test array region. Multiple ring-shaped conductive lines and multiple ring-shaped conductive test lines are formed along the first direction, each of the ring-shaped conductive lines passing through the arrayed active region; Remove both ends of each of the multiple ring-shaped conductive lines to form multiple conductive lines, and simultaneously remove the same end of each of the multiple ring-shaped conductive test lines to form multiple test conductive line groups. In this configuration, the first ends of two adjacent test conductive lines are aligned with the second test active region connected to each other at the first boundary of the test array region.

11. The method for manufacturing a semiconductor test structure according to claim 10, characterized in that, The test conductive line includes a first end and a second end that are opposite to each other. Two adjacent test conductive lines constitute the test conductive line group, and the first ends of two test conductive lines in the same test conductive line group are connected through the second test active region that is connected to each other.

12. The method for manufacturing a semiconductor test structure according to claim 10, characterized in that, After forming the plurality of test conductive line groups, the method further includes: At least one electrical connection structure and two external structures are formed. The electrical connection structure is electrically connected to the adjacent test conductive lines in the plurality of test conductive line groups. The two external structures are respectively electrically connected to the two outermost test conductive lines of all test conductive lines in the plurality of test conductive line groups.

13. The method for manufacturing a semiconductor test structure according to claim 10, characterized in that, The formation of the first test active region further includes active region trimming using an active region trimming mask, wherein the second boundary of the active region trimming mask shrinks by a second preset spacing, such that at the second boundary of the test array region, two third test active regions are connected to each other.

14. The method for manufacturing a semiconductor test structure according to claim 13, characterized in that, Both the first preset spacing and the second preset spacing are one character line spacing.

15. The method for manufacturing a semiconductor test structure according to claim 10, characterized in that, The test conductive line is a test bit line.

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