A digital-to-analog conversion circuit and chip

Abstract

The application discloses a digital-to-analog conversion circuit and chip, and the circuit comprises: a current source array for proportionally mirroring a reference current to N first current branches controlled by digital codes to turn on and off states and N second current branches controlled by corresponding inverse codes to turn on and off states; a reference current source module for generating the reference current; a common mode level adjusting module for adjusting a common mode level of a feedback end according to an adjusting signal; wherein the feedback end of the common mode level adjusting module is connected with a common mode end of a positive output module and a common mode end of a negative output module; the positive output module is used for voltage conversion of total output currents of the N first current branches and outputs a positive voltage signal in combination with the common mode level; and the negative output module is used for voltage conversion of total output currents of the N second current branches and outputs a negative voltage signal in combination with the common mode level. The application can flexibly adapt to interface voltage requirements of different subsequent circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital-to-analog conversion circuit and integrated circuit, and particularly relates to a digital-to-analog conversion circuit and a chip. BACKGROUND

[0002] A digital-to-analog converter (DAC) is a key bridge connecting the digital world and the analog reality. The core idea of its work is "adding by weight": for the input binary digital signal, each bit corresponds to a unique weight coefficient (for example, the weight of the most significant bit in an 8-bit DAC is 128 times that of the least significant bit). The DAC maps the "0 / 1" state of the digital bit to a current or voltage component proportional to the corresponding weight through the internal circuit, and finally outputs an analog signal proportional to the input digital value through component summation.

[0003] However, the voltage range of the output interface of the existing DAC circuit is fixed at the circuit design stage, and it cannot drive subsequent circuits with different voltage requirements, so the adaptability and flexibility of the output interface are low. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a digital-to-analog conversion circuit and a chip, which dynamically adjusts the common-mode level through a common-mode level adjusting module and an adjusting signal, and synchronously feeds back the adjusted common-mode level to the common-mode end of the positive output module and the negative output module, so as to flexibly adapt to subsequent circuits with different voltage requirements.

[0005] The first aspect of the present application provides a digital-to-analog conversion circuit, comprising: a current source array, a reference current source module, a common-mode level adjusting module, a positive output module, and a negative output module; wherein the feedback end of the common-mode level adjusting module is connected with the common-mode end of the positive output module and the common-mode end of the negative output module;

[0006] The current source array is configured to mirror the reference current to N paths of first current branches controlled by digital codes to turn on and off and N paths of second current branches controlled by corresponding inverted codes to turn on and off; N is greater than or equal to 1.

[0007] The reference current source module is configured to generate the reference current.

[0008] The common-mode level adjusting module is configured to adjust the common-mode level of the feedback end according to an adjusting signal.

[0009] The positive output module is configured to convert the output total current of the N paths of the first current branches into a voltage, and output a positive voltage signal in combination with the common-mode level; wherein the output ends of the N paths of the first current branches are all connected with the input end of the positive output module.

[0010] The negative electrode output module is configured to perform voltage conversion on the output total current of the N second current branches and output a negative electrode voltage signal in combination with the common-mode level; wherein the output ends of the N second current branches are connected with the input end of the negative electrode output module.

[0011] Optionally, under the control of any one of the digital code and the corresponding inverted code, the output total current of the current source array remains unchanged.

[0012] Optionally, the adjustment signal comprises a first control signal and a second control signal.

[0013] The common-mode level adjustment module comprises an adjustable MOS unit and a first adjustable resistance unit.

[0014] The first control signal is configured to adjust the equivalent impedance of the adjustable MOS unit.

[0015] The second control signal is configured to adjust the resistance value of the first adjustable resistance unit; wherein the total impedance of the common-mode level adjustment module is the sum of the equivalent impedance and the resistance value of the first adjustable resistance unit.

[0016] Optionally, the adjustable MOS unit comprises an adjustable voltage division branch and a first MOS tube.

[0017] The adjustable voltage division branch is configured to adjust the intermediate node voltage of the adjustable voltage division branch according to the first control signal; wherein the intermediate node voltage is within the voltage range in which the first MOS tube operates in a linear region.

[0018] The control end of the first MOS tube is connected with the intermediate node of the adjustable voltage division branch, the input end of the first MOS tube is connected with the first end of the first adjustable resistance unit, and the output end of the first MOS tube is grounded.

[0019] Optionally, the second end of the first adjustable resistance unit is the feedback end, and the control end of the first adjustable resistance unit is configured to access the second control signal.

[0020] Optionally, the jth first current branch comprises a first switch tube and a second MOS tube; wherein 1≤j≤N.

[0021] The first switch tube is configured to control the on-off state of the jth first current branch according to the corresponding binary bit in the digital code.

[0022] The second MOS tube is configured to mirror the reference current in proportion to generate a corresponding output current when the jth first current branch is turned on.

[0023] Optionally, the reference current source module comprises an enabling switch and a reference current branch.

[0024] The enabling switch is configured to control the working state of the reference current branch according to an enabling signal.

[0025] The reference current branch is configured to generate the reference current when the enabling switch is turned on.

[0026] Optionally, the positive output module comprises a positive output end, a first resistor and a second resistor.

[0027] The first end of the first resistor is the input end of the positive output module, and the second end of the first resistor is connected with the positive output end.

[0028] The first end of the second resistor is connected with the positive output end, and the second end of the second resistor is the common-mode end of the positive output module.

[0029] Optionally, the first adjustable resistance unit comprises M second switch tubes and M third resistors connected in series; each of the third resistors is configured with a corresponding second switch tube; and M is greater than or equal to 1.

[0030] The second switch tube is configured to switch the corresponding third resistor to an access state or a short-circuit state according to a corresponding binary bit in the second control signal.

[0031] Optionally, the adjustable voltage division branch comprises a fixed resistor and a second adjustable resistance subunit.

[0032] The resistors in the first adjustable resistance unit and the second adjustable resistance subunit are configured as virtual resistors on a layout to reduce the area of the layout.

[0033] The second aspect embodiment of the present application provides a chip comprising the digital-to-analog conversion circuit of any one of the first aspect embodiments.

[0034] Compared with the prior art, the present application provides a digital-to-analog conversion circuit and a chip, which dynamically adjusts the common-mode level through the common-mode level adjustment module and the adjustment signal, and synchronously feeds back the adjusted common-mode level to the common-mode ends of the positive output module and the negative output module, thereby flexibly changing the voltage range of the positive voltage signal and the negative voltage signal to flexibly adapt to subsequent circuits with different voltage requirements. In addition, the current source array realizes the current distribution logic of “this increases and that decreases” through the cooperative control of the digital code and the inverse code, the total output current of the current source array remains unchanged, so that the adjusted common-mode level also remains stable, thereby avoiding the problem that the stability and accuracy of the positive voltage signal and the negative voltage signal are affected due to the common-mode level drift. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a structural schematic diagram of one embodiment of the digital-to-analog conversion circuit provided by the present application;

[0036] Figure 2 is a structural schematic diagram of another embodiment of the digital-to-analog conversion circuit provided by the present application;

[0037] Figure 3 is a structural schematic diagram of still another embodiment of the digital-to-analog conversion circuit provided by the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0039] Reference is made to Figure 1 is a structural schematic diagram of one embodiment of the digital-to-analog conversion circuit provided by the present application.

[0040] The embodiment of the present application provides a digital-to-analog conversion circuit, comprising: a current source array 100, a reference current source module 200, a common-mode level adjusting module 300, a positive electrode output module 400, and a negative electrode output module 500; wherein a feedback end of the common-mode level adjusting module 300 is connected with a common-mode end of the positive electrode output module 400 and a common-mode end of the negative electrode output module 500.

[0041] The current source array 100 is configured to mirror a reference current to N paths of first current branches controlled by digital codes to turn on and off and N paths of second current branches controlled by corresponding inverted codes to turn on and off; N≥1.

[0042] The reference current source module 200 is configured to generate the reference current.

[0043] The common-mode level adjusting module 300 is configured to adjust a common-mode level of the feedback end according to an adjusting signal.

[0044] The positive electrode output module 400 is configured to perform voltage conversion on an output total current of the N paths of the first current branches and output a positive electrode voltage signal in combination with the common-mode level; wherein output ends of the N paths of the first current branches are all connected with input ends of the positive electrode output module 400.

[0045] The negative electrode output module 500 is configured to perform voltage conversion on the output total current of the N second current branches and output a negative electrode voltage signal in combination with the common-mode level; wherein the output ends of the N second current branches are connected with the input end of the negative electrode output module 500.

[0046] It should be noted that the current source array 100 includes N first current branches (providing current input for the positive electrode output module 400) and N second current branches (providing current input for the negative electrode output module 500); wherein the value of N can be flexibly set according to the accuracy requirement of the DAC in actual application.

[0047] Taking N=4 as an example, the on-off state of the 4 first current branches is controlled by a group of 4-digit codes (such as P_SOURCE<3:0>), and the digital code P_SOURCE<3:0> includes four independent control levels of P_SOURCE<3>, P_SOURCE<2>, P_SOURCE<1> and P_SOURCE<0>. The current mirror size of the 4 first current branches is proportionally designed in the order from the most significant bit (MSB) to the least significant bit (LSB) of the digital code (for example, the current mirror size of the MSB branch is 8 times that of the LSB branch, the next high bit is 4 times, and so on), so as to ensure that the output current of each first current branch is proportional to the weight of the corresponding binary bit.

[0048] The on-off state of the 4 second current branches is controlled by a group of inverse codes corresponding to P_SOURCE<3:0> (such as N_SOURCE<3:0>), and the inverse code N_SOURCE<3:0> also includes four independent control levels of N_SOURCE<3>, N_SOURCE<2>, N_SOURCE<1> and N_SOURCE<0>, and N_SOURCE <k>level state of the corresponding P_SOURCE <k>On the contrary (0≤k≤3), the second current branch of each path is opposite to the on-off state of the corresponding first current branch. At the same time, the current mirror size of each second current branch is consistent with the corresponding first current branch.

[0049] When the current source array 100 is working (activated), the total output current of the current source array 100 remains unchanged under the control of any digital code and the corresponding inverse code. Specifically, when the jth first current branch is controlled to be turned on by the corresponding binary bit in the digital code (such as P_SOURCE <j-1>When the jth bit of the inverted code is low, the jth current branch is controlled to be open by the corresponding binary bit in the inverted code (e.g., N_SOURCE <j-1>If the digital code is high, the corresponding inverted code is low, and vice versa. Through this "trade-off" control logic, the output total current of the current source array 100 is always equal to a fixed multiple of the reference current during the operation process, regardless of the changes of the digital code and the corresponding inverted code, so that the voltage common mode (VCM) will remain unchanged once the adjustment is completed until the adjustment signal changes, which can improve the stability and accuracy of the positive voltage signal and the negative voltage signal.

[0050] The feedback end of the common mode level adjustment module 300 is connected with the common mode end of the positive output module 400 and the common mode end of the negative output module 500, so as to realize the synchronous adjustment of the common mode level. When the external input adjustment signal is input, the common mode level adjustment module 300 will adjust the working state of the internal circuit components (such as resistors and linear region NMOS tubes) according to the adjustment signal, so as to accurately control the VCM value of the feedback end.

[0051] In the signal conversion link, the input end of the positive output module 400 is connected with the output ends of all the first current branches, which is used to collect the total current (denoted as I1) of all the first current branches in the on state, and take VCM as the bias voltage, and convert I1 into the positive voltage signal (output by the positive output end OUTP) through the internal load resistor. Correspondingly, the input end of the negative output module 500 is connected with the output ends of all the second current branches, which is used to collect the total current (denoted as I2) of all the second current branches in the on state, and also take VCM as the bias voltage, and convert I2 into the negative voltage signal (output by the negative output end OUTN) through the internal load resistor. Since the sum of I1 and I2 (I3=I1+I2) is constant, the voltage difference between OUTP and OUTN is linearly adjusted only with the change of the digital code, and the common mode level of the two output signals always remains stable.

[0052] Compared with the prior art, the digital-to-analog conversion circuit provided by the embodiment of the present application has higher flexibility and adaptability. For example, in the application scenario of "eliminating comparator offset voltage", the comparator has inherent offset voltage in its internal due to the influence of manufacturing process, environmental factors, etc. Even if the two input terminals of the comparator are connected to voltages that are theoretically completely equal, the output terminal of the comparator may still appear an unexpected high level or low level. Therefore, the industry usually adds an offset elimination branch to the input terminal of the comparator, and the DAC generates a voltage equal in size and opposite in polarity to the offset. In actual application, the output voltage range of the existing DAC circuit is fixed at the circuit design stage, and cannot be flexibly adjusted according to the offset elimination requirements of different comparators, resulting in poor interface versatility of the existing DAC circuit. However, the digital-to-analog conversion circuit provided by the embodiment of the present application dynamically adjusts the common-mode level through the common-mode level adjustment module 300 and the adjustment signal, and synchronously feeds back the adjusted common-mode level to the common-mode terminals of the positive output module 400 and the negative output module 500, thereby flexibly changing the output voltage range of OUTP and OUTN, and flexibly adapting to subsequent circuits with different voltage requirements (such as different comparators).

[0053] In addition, the control logic of the current source array 100 ensures that the total output current of the current source array 100 remains unchanged, so that the adjusted common-mode level also remains stable, thereby avoiding the problem that the stability and accuracy of the positive and negative voltage signals are affected due to the drift of the common-mode level.

[0054] Referring to Figure 2 is a structural schematic diagram of another embodiment of the digital-to-analog conversion circuit provided by the present application.

[0055] In an optional embodiment, the adjustment signal includes a first control signal and a second control signal.

[0056] The common-mode level adjustment module 300 includes an adjustable MOS unit 302 and a first adjustable resistance unit 301.

[0057] The first control signal is used to adjust the equivalent impedance of the adjustable MOS unit 302.

[0058] The second control signal is used to adjust the resistance value of the first adjustable resistance unit 301; wherein the total impedance of the common-mode level adjustment module 300 is the sum of the equivalent impedance and the resistance value of the first adjustable resistance unit 301.

[0059] It should be noted that the first control signal can be a multi-bit digital signal (such as a 4-bit binary code FINE_TUNE<3:0>), which is used to adjust the equivalent impedance (denoted as RFINE_TUNE) of the adjustable MOS unit 302. mos_eq The second control signal can also be a multi-bit digital signal (such as a 2-bit binary code COARSE_TUNE<1:0>), used to control the real-time resistance value R1 of the first adjustable resistor unit 301. Figure 2 As shown, I3 equals the total output current of the current source array (i.e., I3 = I1 + I2), and the common-mode level VCM = I3 × (R1 + R2). mos_eq Obviously, the embodiments of the present invention can achieve a wider VCM adjustment range and higher adjustment accuracy through the combination of "FINE_TUNE<3:0>" and "COARSE_TUNE<1:0>", so as to more flexibly and accurately adapt to the interface voltage requirements of different subsequent circuits.

[0060] In an optional embodiment, the adjustable MOS unit 302 includes: an adjustable voltage divider branch and a first MOS transistor;

[0061] The adjustable voltage divider branch is used to adjust the intermediate node voltage of the adjustable voltage divider branch according to the first control signal; wherein the value range of the intermediate node voltage is the voltage range of the first MOS transistor operating in the linear region;

[0062] The control terminal of the first MOS transistor is connected to the intermediate node of the adjustable voltage divider branch, the input terminal of the first MOS transistor is connected to the first terminal of the first adjustable resistor unit 301, and the output terminal of the first MOS transistor is grounded.

[0063] Furthermore, the second end of the first adjustable resistor unit 301 is the feedback end, and the control end of the first adjustable resistor unit 301 is used to connect to the second control signal.

[0064] It should be noted that the adjustable MOS unit 302 in this embodiment of the invention achieves fine equivalent impedance adjustment through a structure of "adjustable voltage divider branch + first MOS transistor operating in the linear region". The adjustable voltage divider branch is used to dynamically adjust its intermediate node voltage (denoted as VBIAS) according to a first control signal (such as FINE_TUNE<3:0>), and it must be ensured that the value range of VBIAS matches the voltage condition of "first MOS transistor operating in the linear region (ohmic region)". In this way, the adjustable voltage divider branch can indirectly realize the continuous adjustment of the equivalent impedance of the first MOS transistor and improve the linearity of impedance adjustment. Since R mos_eq The first control signal regulates the voltage, while the second control signal regulates the resistance R1. The synergistic effect of the two signals enables high-precision adjustment of the VCM. Finally, the VCM is synchronously applied to the common-mode terminals of the positive output module 400 and the negative output module 500 through the feedback terminal of the common-mode level adjustment module 300.

[0065] It is worth noting that if the common-mode level adjustment module 300 uses a series resistor voltage divider to achieve VCM adjustment, it often requires large-value resistors to cover a wide voltage range, which occupies a large chip layout area. In contrast, the embodiment of the present invention, through the structure of "adjustable voltage divider branch + first MOSFET operating in the linear region", can significantly reduce the chip layout area. This is because the adjustable voltage divider branch only needs to provide a suitable control terminal voltage VBIAS for the first MOSFET and does not need to carry a large current. Therefore, the resistance value used inside it can be designed to be very small, and the corresponding layout size can be greatly reduced. At the same time, the first MOSFET, as an active device, has a layout area much smaller than that of a passive resistor string. Based on this, the embodiment of the present invention can significantly reduce the chip layout area, thereby improving the chip integration effect.

[0066] See Figure 3 This is a schematic diagram of another embodiment of the digital-to-analog converter circuit provided by the present invention.

[0067] In an optional embodiment, the first adjustable resistor unit includes: M second switching transistors and M third resistors connected in series; wherein each of the third resistors is configured with a corresponding second switching transistor; M ≥ 1;

[0068] The second switching transistor is used to switch the corresponding third resistor to an on state or a short-circuit state according to the corresponding binary bit in the second control signal.

[0069] Furthermore, the adjustable voltage divider branch includes: a fixed resistor and a second adjustable resistor subunit;

[0070] The resistors in the first adjustable resistor unit 301 and the second adjustable resistor subunit are configured as virtual resistors on the layout to reduce the area of ​​the layout.

[0071] It should be noted that the first adjustable resistor unit 301 is a series-gated resistor array. When M is 2, the corresponding... Figure 3 The second control signal COARSE_TUNE<1:0> is used, and a "series resistor + parallel switch" structure is adopted. The source and drain of each second switch are connected to the two ends of the corresponding third resistor, and the gate of the second switch is connected to the corresponding binary bit in the second control signal, so as to realize the adjustment of the resistance value R1 in the first adjustable resistor unit 301: when a certain binary bit in the second control signal turns on the corresponding second switch, its corresponding third resistor is short-circuited (this third resistor does not participate in the calculation of the resistance value R1); when a certain binary bit in the second control signal turns off the corresponding second switch, its corresponding third resistor is connected to the series path (this third resistor participates in the calculation of the resistance value R1).

[0072] The second adjustable resistor subunit is also a series-gated resistor array, configured with 4 resistors and 4 switching transistors, corresponding to... Figure 3 The "first control signal FINE_TUNE<3:0>" in the code, similar in structure to the first adjustable resistor unit 301, is used to adjust the resistance value R2 of the second adjustable resistor subunit. The adjustable voltage divider branch is a series combination of a "fixed resistor + second adjustable resistor subunit." By changing the voltage division ratio between the fixed resistor and the second adjustable resistor subunit, an adjustable intermediate node voltage VBIAS is generated and applied to the first MOS transistor M1 (in...). Figure 3 The gate of the NMOS transistor is used to ultimately adjust the equivalent impedance of the first MOS transistor.

[0073] It is worth noting that in this embodiment of the invention, the resistors of the first adjustable resistor unit 301 and the second adjustable resistor subunit are not independently laid out. Instead, the resistors in the first adjustable resistor unit 301 (the two resistors corresponding to COARSE_TUNE<1:0>) and the resistors in the second adjustable resistor subunit (the four resistors corresponding to FINE_TUNE<3:0>) are combined with the dummy resistors of OUTP and OUTN. The dummy resistors are used to ensure layout symmetry and reduce the impact of process deviations on circuit performance. In this embodiment of the invention, the resistors of the first adjustable resistor unit 301 and the second adjustable resistor subunit directly reuse the dummy resistors, without needing to occupy additional independent layout area. This design further reduces the layout area of ​​the entire DAC circuit.

[0074] In an optional embodiment, the j-th current branch includes: a first switching transistor and a second MOSFET; wherein, 1≤j≤N;

[0075] The first switching transistor is used to control the on / off state of the j-th first current branch according to the corresponding binary bit in the digital code.

[0076] The second MOSFET is used to mirror the reference current proportionally to generate the corresponding output current when the first current branch of the j-th path is turned on.

[0077] It should be noted that, in Figure 3 In the specific embodiment, the second MOS tubes (i.e. M4~M7) of all the first current branches, the second MOS tubes (M12~M15) of all the second current branches and the output MOS tube (M3) of the reference current source are of the same type, such as all being PMOS; wherein the sources of M4~M7 and M12~M15 are all connected to the power supply voltage (VDD) of the DAC circuit, the drains are connected to the input ends of the first switch tubes in the corresponding current branches, and the gates are all connected to the gate of M3. M4~M7 and M12~M15 are all used for proportional mirroring of the reference current, and the proportion of the output current of the corresponding current branch to the reference current is determined by the "width-length ratio" of itself.

[0078] In the specific embodiment, Figure 3 In the specific embodiment, the first switch tubes (i.e. M8~M11) of all the first current branches and the first switch tubes (M16~M19) of all the second current branches are PMOS; wherein the sources of M8~M11 are connected to the drains of the MOS tubes in the corresponding first current branches, the gates are connected to the corresponding binary bits in the digital code (such as the P_SOURCE <j-1>), the drain of M16~M19 is connected to the input terminal of the negative output module 500. M8~M11 controls the on-off state of the corresponding first current branch according to the binary bit of the digital code, so that the output current of all the first current branches in the on state is combined to the input terminal of the positive output module 400 to form the current I1; and the positive output module 400 converts I1 into the positive voltage signal corresponding to the digital code through the internal load resistor. The working principle and function of "M16~M19" are similar to those of "M8~M11", and will not be described here.

[0079] In an optional embodiment, the reference current source module 200 comprises an enabling switch and a reference current branch.

[0080] The enabling switch is configured to control the working state of the reference current branch according to an enabling signal.

[0081] The reference current branch is configured to generate the reference current when the enabling switch is turned on.

[0082] It should be noted that, in the above description, Figure 3 the reference current branch is composed of a current source and a MOS tube (M3). When the enabling signal (EN) is valid, the enabling switch (M2) is turned on, at which time the reference current branch starts to work and generates the reference current; and when the enabling signal (EN) is invalid, the enabling switch (M2) is turned off, at which time M3 has no driving current provided by the current source, resulting in that the reference current branch as a whole enters the off or dormant state, at which time there is no reference current output.

[0083] It can be understood that the enabling switch, as well as the first switch tube and the second switch tube described above, can be a commonly used triode, MOS tube, or other types of switching devices, and the embodiments of the present application are not specifically limited, which are determined when the embodiments of the present application are applied to specific products or technologies.

[0084] In an optional embodiment, the positive output module 400 comprises a positive output terminal OUTP, a first resistor and a second resistor.

[0085] The first end of the first resistor is the input terminal of the positive output module 400, and the second end of the first resistor is connected with the positive output terminal OUTP.

[0086] The first end of the second resistor is connected with the positive output terminal OUTP, and the second end of the second resistor is the common mode terminal of the positive output module 400.

[0087] It should be noted that, in the above description, Figure 3 In the embodiment, the first resistor R6 is used for adjusting the output impedance and isolating the load, reducing the influence of the load on the first current branch, so as to ensure that the output current of the first current branch is only controlled by the digital code; the second resistor R4 is a load resistor, used for converting the current I1 into a voltage, so that the positive voltage signal Voutp output by the positive output end OUTP is VCM+I1xR4. The working principle and the functional role of the negative output end OUTN, R5 and R7 in the negative output module 500 are similar to those of the positive output end OUTP, R4 and R6 in the positive output module 400, and will not be repeated here.

[0088] In summary, the digital-to-analog conversion circuit provided by the embodiment has the following beneficial effects:

[0089] (1) Through the synergistic effect of the first control signal and the second control signal, the common-mode level can be dynamically and accurately regulated, and the output range of the positive voltage signal and the negative voltage signal can be flexibly adjusted, so that the subsequent circuit with different voltage requirements can be adapted;

[0090] (2) The current source array 100 is controlled by the digital code and the inverted code, realizes the current distribution logic of "one up and one down", ensures that the total output current of the current source array 100 remains unchanged, avoids the common-mode level from drifting due to current fluctuation, and improves the stability and accuracy of the positive voltage signal and the negative voltage signal; at the same time, the common-mode level adjusting module 300 adjusts the VCM through the adjustable resistor and the MOS tube in the linear region, so that the adjustment linearity of the common-mode level, the positive voltage signal and the negative voltage signal is extremely high;

[0091] (3) Through the structure of "adjustable voltage dividing branch + first MOS tube working in linear region", the chip layout area can be greatly reduced; in addition, the resistances of the first adjustable resistance unit 301 and the second adjustable resistance unit are merged with the Dummy resistance, without the need to open up an independent layout space, further improving the integration of the chip.

[0092] The second aspect embodiment of the application further provides a chip comprising the digital-to-analog conversion circuit of any one of the first aspect embodiments.

[0093] It should be noted that the chip in the embodiment of the application can be any one of a CPU (Central Processing Unit, central processor), a GPU (Graphics Processing Unit, graphics processor), a TPU (Tensor Processing Unit, tensor processor), an NPU (Neural network Processing Unit, neural network processor), a DPU (Deeplearning Processing Unit, deep learning processor), an APU (Accelerated Processing Unit, accelerated processor), and a GPGPU (General-Purpose computing on Graphics Processing Unit, general-purpose graphics processor).

[0094] The above merely describes the preferred embodiments of the present application, and it should be noted that those of ordinary skill in the art can make several improvements and modifications without departing from the technical principles of the present application, and these improvements and modifications should also be considered within the protection scope of the present application. < / k> < / k>

Claims

1. A digital-to-analog conversion circuit, characterized by comprising: The current source array, the reference current source module, the common-mode level adjusting module, the positive electrode output module, and the negative electrode output module are connected; the feedback end of the common-mode level adjusting module is connected with the common-mode end of the positive electrode output module and the common-mode end of the negative electrode output module; The current source array is configured to mirror the reference current to N first current branches controlled by digital codes and N second current branches controlled by corresponding inverted codes; N is greater than or equal to 1; The reference current source module is configured to generate the reference current; The common-mode level adjusting module is configured to adjust the common-mode level of the feedback end according to an adjusting signal; The positive electrode output module is configured to convert the total output current of the N first current branches into a voltage and output a positive electrode voltage signal in combination with the common-mode level; the output ends of the N first current branches are connected with the input end of the positive electrode output module; The negative electrode output module is configured to convert the total output current of the N second current branches into a voltage and output a negative electrode voltage signal in combination with the common-mode level; the output ends of the N second current branches are connected with the input end of the negative electrode output module. Under the control of any of the digital codes and the corresponding inverted codes, the total output current of the current source array remains unchanged.

2. The digital-to-analog conversion circuit of claim 1, wherein, The adjusting signal includes a first control signal and a second control signal; 3. The digital-to-analog conversion circuit of claim 1, wherein, The common-mode level adjusting module includes an adjustable MOS unit and a first adjustable resistance unit; The first control signal is used to adjust the equivalent impedance of the adjustable MOS unit; The second control signal is used to adjust the resistance value of the first adjustable resistance unit; the total impedance of the common-mode level adjusting module is the sum of the equivalent impedance and the resistance value of the first adjustable resistance unit. The adjustable MOS unit includes an adjustable voltage division branch and a first MOS tube; 4. The digital-to-analog conversion circuit of claim 3, wherein, The adjustable voltage division branch is configured to adjust the intermediate node voltage of the adjustable voltage division branch according to the first control signal; the value range of the intermediate node voltage is the voltage range in which the first MOS tube works in a linear region; The control end of the first MOS tube is connected with the intermediate node of the adjustable voltage division branch, the input end of the first MOS tube is connected with the first end of the first adjustable resistance unit, and the output end of the first MOS tube is grounded. The second end of the first adjustable resistance unit is the feedback end, and the control end of the first adjustable resistance unit is configured to input the second control signal.

5. The digital-to-analog conversion circuit of claim 4, wherein, The jth first current branch includes a first switch tube and a second MOS tube; 1≤j≤N; 6. The digital-to-analog conversion circuit of claim 1, wherein, The first switch tube is configured to control the on-off state of the jth first current branch according to the corresponding binary bit in the digital code; The second MOS tube is configured to mirror the reference current to generate a corresponding output current when the jth first current branch is turned on. The reference current source module includes an enable switch and a reference current branch; 7. The digital-to-analog conversion circuit of claim 1, wherein, The enable switch is configured to control the working state of the reference current branch according to an enable signal. ​ The reference current branch is configured to generate the reference current when the enable switch is turned on.

8. The digital-to-analog conversion circuit of claim 1, wherein, The positive output module comprises a positive output end, a first resistor and a second resistor. A first end of the first resistor is an input end of the positive output module, and a second end of the first resistor is connected with the positive output end. A first end of the second resistor is connected with the positive output end, and a second end of the second resistor is a common mode end of the positive output module.

9. The digital-to-analog conversion circuit of claim 3, wherein, The first adjustable resistor unit comprises M second switch tubes and M third resistors connected in series; each of the third resistors is configured with a corresponding second switch tube; and M≥1. The second switch tube is configured to switch the corresponding third resistor to an access state or a short-circuit state according to a corresponding binary bit in the second control signal.

10. The digital-to-analog conversion circuit of claim 4, wherein, The adjustable voltage dividing branch comprises a fixed resistor and a second adjustable resistor subunit. The resistors in the first adjustable resistor unit and the second adjustable resistor subunit are configured as virtual resistors on a layout to reduce the area of the layout.

11. A chip, characterized by The digital-to-analog conversion circuit comprises any one of claims 1-10.

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