Semiconductor device and method of manufacturing semiconductor device

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate, a source electrode, a drain electrode and a gate electrode; the semiconductor substrate is provided with a source region corresponding to the source electrode and a drain region corresponding to the drain electrode, and a channel region is arranged between the source region and the drain region; the gate electrode is arranged above the channel region; a stepped work function layer is arranged in a connection position of the channel region and the gate electrode, and the stepped work function layer comprises a first work function layer, a second work function layer and a third work function layer, wherein the second work function layer is connected with the end of the first work function layer and the start of the third work function layer respectively, and the work function of the second work function layer is different from those of the first work function layer and the third work function layer; the surface height of the first work function layer is higher than that of the source region, and the surface height of the third work function layer is higher than that of the drain region. By using the technical scheme, the control ability of the gate electrode on the channel region can be improved, and the electrical performance of the semiconductor device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] With advancements in manufacturing processes, semiconductor devices have reached process nodes of 2nm or even 0.3nm, all aimed at increasing the number of transistors to improve chip operating speed. However, once transistor growth reaches a certain point, a bottleneck is reached; without structural changes, it's impossible to further increase the number of transistors. But structural changes may introduce new problems, such as limited gate control over the channel region, making it difficult to improve the electrical performance of semiconductor devices.

[0003] In view of this, there is an urgent need to provide a semiconductor device that can improve the gate's control over the channel region and enhance the electrical performance of the semiconductor device. Summary of the Invention

[0004] To address at least one or more of the technical problems mentioned above, this application proposes a semiconductor device and a method for manufacturing the semiconductor device in several aspects. This semiconductor device can improve the gate's control over the channel region and enhance the electrical performance of the semiconductor device.

[0005] In a first aspect, this application provides a semiconductor device, comprising: a semiconductor substrate 1, a source 2, a drain 3, and a gate 4; the semiconductor substrate 1 has a source region 5 corresponding to the source 2 and a drain region 6 corresponding to the drain 3, and a channel region 7 is provided between the source region 5 and the drain region 6; the gate 4 is disposed on the channel region 7; a stepped work function layer is provided at the connection position between the channel region 7 and the gate 4, the stepped work function layer comprising a first work function layer 81, a second work function layer 82, and a third work function layer 83, wherein the second work function layer 82 is connected to the end of the first work function layer 81 and the beginning of the third work function layer 83, and the work function magnitude of the second work function layer 82 is different from that of the first work function layer 81 and the third work function layer 83; and the metal gate material of the second work function layer 82 is adapted to the doping type of the source 2 and the drain 3; the surface height of the first work function layer 81 is higher than the surface height of the source region 5, and the surface height of the third work function layer 83 is higher than the surface height of the drain region 6.

[0006] In some embodiments, the second work function layer 82 is perpendicular to the first work function layer 81 and the third work function layer 83, respectively.

[0007] In some embodiments, the channel region 7 includes an interconnected first region 71 and a second region 72, the first region 71 being disposed between the source region 5 and the extension line of the second work function layer 82, and the second region 72 being disposed between the drain region and the extension line of the second work function layer 82.

[0008] In some embodiments, the side surface of the gate 4 is provided with an oxide protection layer 9, and the top of the gate is provided with a buffer protection layer 10.

[0009] In some embodiments, a stepped high dielectric layer 11 is further provided in the channel region 7; a stepped work function layer is arranged between the gate 4 and the stepped high dielectric layer 11, and the stepped high dielectric layer 11 and the stepped work function layer are arranged in parallel.

[0010] In some embodiments, in the vertical direction, the two side surfaces of the buffer protection layer 10, the oxide protection layer 9, the stepped work function layer and the stepped high dielectric layer 11 are all provided with a first protection layer 12.

[0011] In some embodiments, in the vertical direction, the second protection layer 13 is arranged on the first protection layer 12 on both sides.

[0012] In some embodiments, a first lightly doped region 14 is arranged at the outer periphery of the source region 5, and a second lightly doped region 15 is arranged at the outer periphery of the drain region 6; when the carrier of the semiconductor device is a hole, the first lightly doped region 14 and the second lightly doped region 15 are P-type lightly doped regions; when the carrier of the semiconductor device is an electron, the first lightly doped region 14 and the second lightly doped region 15 are N-type lightly doped regions.

[0013] In some embodiments, a well layer 16 is further arranged in the semiconductor substrate 1, and the well layer 16 is arranged below the first lightly doped region 14, the channel region 7 and the second lightly doped region 15.

[0014] In some embodiments, a deep well layer 17 is further arranged in the semiconductor substrate 1, and the deep well layer 17 is arranged below the well layer 16.

[0015] In the second aspect, the application provides a manufacturing method of a semiconductor device, comprising: forming a source region corresponding to a source and a drain region corresponding to a drain in a semiconductor substrate, a channel region being formed between the source region and the drain region; forming a stepped work function layer in the connection position of the channel region and a gate, wherein the stepped work function layer comprises a first work function layer, a second work function layer and a third work function layer, the second work function layer is connected with the end of the first work function layer and the beginning of the third work function layer respectively, and the work function size of the second work function layer is inconsistent with the work function size of the first work function layer and the third work function layer; and the metal gate material of the second work function layer is adapted to the doping type of the source and the drain; forming the gate on the channel region; forming the source on the source region and forming the drain on the drain region, wherein the surface height of the first work function layer is higher than the surface height of the source region, and the surface height of the third work function layer is higher than the surface height of the drain region.

[0016] The technical scheme provided by the application can include the following beneficial effects:

[0017] The semiconductor device provided by the application comprises a semiconductor substrate, a source electrode, a drain electrode and a gate electrode, wherein the semiconductor substrate is provided with a source region corresponding to the source electrode and a drain region corresponding to the drain electrode, a channel region is arranged between the source region and the drain region, and the gate electrode is arranged on the channel region. Further, a stepped work function layer is arranged at the connection position of the channel region and the gate electrode, the stepped work function layer comprises a first work function layer, a second work function layer and a third work function layer, the surface of the source region is in the same plane as the first work function layer, and the surface of the drain region is in the same plane as the third work function layer. The second work function layer is connected with the end of the first work function layer and the start of the third work function layer respectively, the work function of the second work function layer is different from that of the first work function layer and the third work function layer, and the metal gate material of the second work function layer is adapted to the doping type of the source electrode and the drain electrode, so that the work function layer of PNP can be formed at the same gate electrode in the NMOS region, and / or the work function layer of NPN can be formed at the same gate electrode in the PMOS region, which is beneficial to better adjusting the threshold voltage Vt. At the same time, the work function layers with different values are formed at the same gate electrode, which can improve the control ability of the gate electrode on the channel region, thereby improving the electrical performance of the semiconductor device, improving the driving current of the device and reducing the leakage problem of the source-drain through, and improving the hot carrier problem.

[0018] In general, the semiconductor device of the application can improve the control ability of the gate electrode on the channel region, thereby improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the exemplary embodiments of the present application will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 FIG. 1 shows a structural schematic diagram of a semiconductor device according to some embodiments of the application;

[0021] Figure 2 FIG. 2 shows a flowchart of a semiconductor device manufacturing method according to some embodiments of the application;

[0022] Figure 3 FIG. 3 shows a device structure schematic diagram of a semiconductor device manufacturing method according to some embodiments of the application;

[0023] Figure 4 FIG. 4 shows another device structure schematic diagram of a semiconductor device manufacturing method according to some embodiments of the application;

[0024] Figure 5 FIG. 5 shows a third device structure schematic diagram of a semiconductor device manufacturing method according to some embodiments of the application.

[0025] Figure 6 Figure 4 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0026] Figure 7 Figure 5 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0027] Figure 8 Figure 6 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0028] Figure 9 Figure 7 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0029] Figure 10 Figure 8 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0030] Figure 11 Figure 9 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0031] Figure 12 Figure 10 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0032] Figure 13 Figure 11 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0033] Figure 14 Figure 12 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0034] Figure 15 Figure 13 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0035] Figure 16 Figure 14 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0036] Figure 17 Figure 15 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0037] Figure 18 Figure 16 shows a device structure schematic of a semiconductor device manufacturing method according to some embodiments of the present application;

[0038] Figure 19Figure 17 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0039] Figure 20 Figure 18 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0040] Figure 21 Figure 19 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0041] Figure 22 Figure 20 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0042] Figure 23 Figure 21 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0043] Figure 24 Figure 22 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0044] Figure 25 Figure 23 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0045] Figure 26 Figure 24 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0046] Figure 27 Figure 25 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0047] Figure 28 Figure 26 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0048] Figure 29 Figure 27 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0049] Figure 30 Figure 28 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0050] Figure 31 Figure 29 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0051] Figure 32 Figure 30 shows a device structure diagram in a semiconductor device manufacturing method of some embodiments of the present application;

[0052] Figure 33 Figure 31 shows a device structure diagram in a semiconductor device manufacturing method according to some embodiments of the present application;

[0053] Figure 34 Figure 32 shows a device structure diagram in a semiconductor device manufacturing method according to some embodiments of the present application. DETAILED DESCRIPTION

[0054] In order to make the concept and ideas of the present application more clear to those skilled in the art, the present application is described in detail below in conjunction with specific embodiments. It should be understood that the embodiments given herein are only a part of all the embodiments that the present application can have. Those skilled in the art can make modifications, alternations, or replacements to some or all of the embodiments described below after reading the description of the present application, and these modifications, alternations, or replacements are also included in the scope of protection of the present application.

[0055] In the present document, the terms "one", "a", and other similar words are not intended to denote the existence of only one thing, but are intended to denote that the relevant description is only directed to one of the things, which can have one or more. In the present document, the terms "comprise", "include", and other similar words are intended to denote logical relationships, and cannot be regarded as indicating spatial structural relationships. For example, "A includes B" is intended to mean that B logically belongs to A, and does not mean that B is located inside A in space. In addition, the meaning of the terms "comprise", "include", and other similar words should be regarded as open, rather than closed. For example, "A includes B" is intended to mean that B belongs to A, but B does not necessarily constitute all of A, and A can also include C, D, E, and other elements.

[0056] In the present document, the terms "first", "second", and other similar words are not intended to imply any order, number, and importance, but are only used to distinguish different elements. In the present document, the terms "embodiment", "the embodiment", "an embodiment", "one embodiment" do not mean that the relevant description is only applicable to one specific embodiment, but means that the description can also be applicable to another one or more embodiments. Those skilled in the art should understand that any description made herein for a certain embodiment can be replaced, combined, or otherwise combined with the relevant description in another one or more embodiments, and the new embodiments resulting from the replacement, combination, or other combination are easy to be thought of by those skilled in the art, and belong to the scope of protection of the present application.

[0057] In the embodiments of the present application, the semiconductor device can refer to an electronic device made of semiconductor materials (such as silicon, germanium, gallium arsenide, etc.), the core function of which is to realize accurate regulation of current by controlling the conductivity of the material, so as to complete the tasks of signal processing, energy conversion, data storage, etc. Such devices are usually composed of basic structures such as PN junction, transistor, diode, field effect transistor, etc., which are constructed on a semiconductor substrate through processes such as photolithography, doping, thin film deposition, etc. Its unique electrical characteristics are derived from the characteristics of the semiconductor material whose conductivity is between that of a conductor and an insulator. The concentration and movement of carriers (electrons and holes) can be changed by external voltage, light or doping, so as to realize the functions of switching, amplifying, rectifying, etc. of the circuit.

[0058] Since the birth of Moore's Law, the number of transistors has doubled every year. As time goes on, the process node has reached 2nm or even 0.3nm, the purpose of which is to increase the number of transistors and improve the running speed of the chip. When it grows to a certain extent, the number of transistors cannot be increased without structural changes, but structural changes will make the process very complex, such as Fin FET (Fin Field-Effect Transistor, Fin Field-Effect Transistor) and GAA (Gate-All-Around, Gate-All-Around) etc. However, structural changes may introduce new problems, such as limited control ability of the gate to the channel region, and the electrical performance of the semiconductor device is difficult to improve.

[0059] Therefore, the embodiments of the present application provide a semiconductor device to improve the control ability of the gate to the channel region and improve the electrical performance of the semiconductor device.

[0060] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0061] Figure 1 The structure of the semiconductor device of some embodiments of the present application is shown in the structural schematic diagram of the semiconductor device, please refer to Figure 1 The semiconductor device shown in the embodiments of the present application can include:

[0062] The semiconductor substrate 1, the source 2, the drain 3 and the gate 4, wherein the semiconductor substrate 1 is provided with a source region 5 corresponding to the source 2 and a drain region 6 corresponding to the drain 3, a channel region 7 is provided between the source region 5 and the drain region 6, and the gate 4 is provided above the channel region 7.

[0063] Further, a stepped work function layer is arranged in the connection position of the channel region 7 and the gate 4, the stepped work function layer comprising a first work function layer 81, a second work function layer 82 and a third work function layer 83, the surface height of the first work function layer 81 is higher than the surface height of the source region 5, and the surface height of the third work function layer 83 is higher than the surface height of the drain region 6. The second work function layer 82 is connected to the end of the first work function layer 81 and the start of the third work function layer 83 respectively, and the work function of the second work function layer 82 is different from the work function of the first work function layer 81 and the third work function layer 83, and the metal gate material of the second work function layer 82 is adapted to the doping type of the source 2 and the drain 3. For example, assuming that the doping atoms of the source 2 and the drain 3 are group V atoms (such as phosphorus and arsenic), forming an N-type semiconductor, then the metal gate material of the second work function layer 82 can be a low work function (typical value 4.0 ~ 4.3 eV) "N-side" metal, for example TIALN, and the work function range can be 4.2 ~ 4.4 eV. Correspondingly, the metal gate material of the first work function layer 81 and the third work function layer 83 can be a high work function (typical value 4.9 ~ 5.2 eV) "P-side" metal, for example TIN, and the work function range can be 4.7 ~ 4.9 eV. At this time, the work function layer of PNP can be formed at the same gate in the N-type semiconductor (NMOS) region. In addition, assuming that the doping atoms of the source 2 and the drain 3 are group III elements (such as boron), forming a P-type semiconductor, then the metal gate material of the second work function layer 82 can be a high work function (typical value 4.9 ~ 5.2 eV) "P-side" metal, for example TIN, and the work function range can be 4.7 ~ 4.9 eV. Correspondingly, the metal gate material of the first work function layer 81 and the third work function layer 83 can be a low work function (typical value 4.0 ~ 4.3 eV) "N-side" metal, for example TIALN, and the work function range can be 4.2 ~ 4.4 eV. At this time, the work function layer of NPN can be formed at the same gate in the P-type semiconductor (PMOS) region. Thus, it is beneficial to better adjust the threshold voltage Vt.

[0064] In the embodiments of the present application, the work function Φ can refer to the minimum energy required for an electron on the surface of a material to escape into a vacuum, usually measured in electron volts (eV). It reflects the difficulty of an electron to break away from the atomic nucleus from the inside of the material, and the smaller the work function, the easier the electron escapes. In semiconductor technology, the work function is a key parameter for designing devices such as transistors. For example, the work function of the gate material directly affects the threshold voltage of the field effect transistor, and determines the on and off states of the device. By selecting materials with different work functions (such as metals or semiconductors), the electrical properties of the device can be adjusted. High work function materials are often used in enhancement mode devices to increase the threshold voltage, and low work function materials are used in depletion mode devices or to optimize current conduction. In addition, the difference in work function can precisely adjust the interface potential in a heterojunction or double-material gate structure, improve electrostatic control, suppress leakage current, and thus improve the energy efficiency and reliability of the device.

[0065] The semiconductor device of the embodiments of the present application comprises a semiconductor substrate, a source, a drain and a gate, wherein the semiconductor substrate is provided with a source region corresponding to the source and a drain region corresponding to the drain, a channel region is provided between the source region and the drain region, and the gate is arranged on the channel region. Further, a stepped work function layer is provided in the connection position of the channel region and the gate, the stepped work function layer comprises a first work function layer, a second work function layer and a third work function layer, the surface of the source region is in the same plane as the first work function layer, and the surface of the drain region is in the same plane as the third work function layer. The second work function layer is connected to the end of the first work function layer and the beginning of the third work function layer, respectively, and the work function of the second work function layer is different from that of the first work function layer and the third work function layer, and the metal gate material of the second work function layer is adapted to the doping type of the source and the drain, so that a PNP work function layer can be formed at the same gate in the NMOS region, and / or an NPN work function layer can be formed at the same gate in the PMOS region, which is beneficial to better adjusting the threshold voltage Vt. At the same time, the work function layers with different values are formed at the same gate, which can improve the control ability of the gate on the channel region, thereby improving the electrical properties of the semiconductor device, improving the driving current of the device and reducing the leakage problem of the source-drain through, and improving the hot carrier problem.

[0066] In summary, the semiconductor device of the present application can improve the control ability of the gate on the channel region, and improve the electrical properties of the semiconductor device.

[0067] In some embodiments, as Figure 1As shown, the surface of the drain 3 is higher than the surface of the source 2, causing the channel region 7 to also form a stepped shape. The channel region 7 includes an interconnected first region 71 and a second region 72. The first region 71 is located between the extension line of the source region 5 and the second work function layer 82, and the second region 72 is located between the drain region and the extension line of the second work function layer 82. The stepped channel region 7 extends not only horizontally but also vertically. This shape lengthens the channel region within the same horizontal area, suppressing the short-channel effect. Furthermore, since a longer channel region can be generated within the same area, the area of ​​silicon wafer occupied by semiconductor devices with the same channel region length can be reduced, thus improving silicon wafer utilization. The second work function layer 82 is perpendicular to the first work function layer 81 and the third work function layer 83, and also forms a stepped work function layer along the channel region 7, which facilitates the subsequent formation of different work function layers at the same gate.

[0068] In some embodiments, an oxide protective layer 9 is provided on the side of the gate 4, and a buffer protective layer 10 is provided on the top of the gate. A stepped high-dielectric layer 11 is also provided in the channel region 7, and a stepped work function layer is disposed between the gate 4 and the stepped high-dielectric layer 11, and the stepped high-dielectric layer 11 and the stepped work function layer are arranged in parallel. Further, in the vertical direction, a first protective layer 12 is provided on both sides of the buffer protective layer 10, the oxide protective layer 9, the stepped work function layer, and the stepped high-dielectric layer 11. In the vertical direction, a second protective layer 13 is provided on both sides of the first protective layer 12. In the embodiments of this application, the buffer protective layer 10 can be Ti or TiN, and the oxide protective layer 9 can be The first protective layer 12 can be an OX oxide layer (such as...). The second protective layer 13 can be made of SiN. By setting the aforementioned protective layer, the electric field concentration at the slot corner can be effectively alleviated. High electric fields can easily lead to gate breakdown, while the protective layer reduces the damage to the gate by adjusting the electric field distribution, thereby improving the device's withstand voltage and long-term reliability. The protective layer can serve as a physical support structure, maintaining the geometry of the gate and its surrounding structure in complex processes and preventing structural deformation or collapse. Furthermore, because the protective layer effectively protects the gate, it can improve the device's withstand voltage characteristics and protect the physical structure of the gate. Protective layers made of the above materials have proven to be particularly effective in realizing their technical benefits, allowing them to demonstrate their application value to the fullest extent.

[0069] Additionally, the stepped high-dielectric layer 11 (for example, can be made of...) The isolation layer can isolate the gate 4 and the channel region 7, avoiding direct contact between the two, which can cause short circuit. As a dielectric of the gate electric field, the dielectric constant and thickness of the isolation layer directly affect the strength and distribution of the electric field. By applying a gate voltage, the isolation layer transmits the electric field to the channel region, inducing or depleting the carriers in the channel, thereby controlling the conduction or cutoff of the device. The isolation layer can block the diffusion of impurities (such as metal ions) in the gate material to the channel region, preventing the channel doping concentration from being destroyed, thereby ensuring the stability of the threshold voltage and conductivity of the device.

[0070] In some embodiments, the outer periphery of the source region 5 is provided with a first lightly doped region 14, and the outer periphery of the drain region 6 is provided with a second lightly doped region 15. When the carriers of the semiconductor device are holes, the first and second lightly doped regions 14 and 15 are P-type lightly doped regions, and when the carriers of the semiconductor device are electrons, the first and second lightly doped regions 14 and 15 are N-type lightly doped regions. By inserting a lightly doped region between the source and drain and the channel, the electric field can be dispersed, reducing the electric field peak near the source and drain. This reduces the acceleration of carriers, thereby suppressing the generation of hot carriers, significantly improving the reliability and life of the device. The lightly doped region can adjust the electric field distribution between the source and drain and the channel, making the electric field more gentle, thereby alleviating the short channel effect, such as by reducing the influence of the source and drain on the channel barrier, helping to maintain a stable threshold voltage and improve the performance consistency of the device at small sizes.

[0071] In some embodiments, the semiconductor substrate 1 also has a well layer 16 disposed below the first lightly doped region 14, the channel region 7, and the second lightly doped region 15. The well layer is a heavily doped region formed on the substrate by doping. Its core function is to provide an independent container for MOS transistors, allowing PMOS and NMOS to be electrically isolated. This structure allows NMOS and PMOS to coexist on the same chip, avoiding mutual interference, thereby enabling the integration of complementary logic circuits. In addition, by adjusting the bias voltage of the well layer, the threshold voltage of the MOS transistor can be adjusted, thereby optimizing the power consumption and speed of the circuit.

[0072] In some embodiments, the semiconductor substrate 1 also has a deep well layer 17 disposed below the well layer 16. The deep well layer is a further deepened doped region below the well layer, which mainly serves to provide higher levels of isolation for devices sensitive to noise. The deep well layer can accommodate devices of different potentials, providing support for multi-voltage domain design of complex circuits. In high-density integration or high-noise requirement scenarios, the deep well layer reduces the impact of substrate noise on critical circuits through physical and electrical isolation, ensuring the stability and reliability of the circuit.

[0073] Corresponding to the foregoing embodiments of the semiconductor device, the application also provides a manufacturing method of the semiconductor device and corresponding embodiments. Please refer to Figures 2 to 33 The manufacturing method of the semiconductor device shown in the embodiments of the application can include:

[0074] In step S201, a source region corresponding to a source and a drain region corresponding to a drain are formed in a semiconductor substrate, and a channel region is formed between the source region and the drain region. Specifically, please refer to Figures 3 to 14 In the embodiments of the application, as shown in Figure 3 , a semiconductor substrate can be provided first, a pad oxide layer of a certain thickness is grown by a furnace tube, the main purpose of which is to prevent damage to the silicon surface in the subsequent ion implantation process, and then a deep N-well (DNW) is formed. Further as shown in Figure 4 , a certain thickness of silicon nitride (SiN) is deposited first, which serves as a hard mask, then photoresist (PR) is coated and developed, here mainly to form the isolation region STI (Shallow Trench Isolation) of NMOS (N-type MOS tube) and PMOS (P-type MOS tube). Further as shown in Figure 5 , the STI is etched. Further as shown in Figure 6 , a thin layer of liner oxide (Liner OX) is grown in the STI by a furnace tube, which is mainly used to repair the damage to the surface of the active area (AA) by etch plasma. Further as shown in Figure 7 , TEOS (Tetraethyl Orthosilicate) is deposited in the STI as an isolation part of the device by high aspect ratio process deposition (HARP depo), and annealing is performed at a certain temperature after HARP depo to make the deposited TEOS more dense. Then the TEOS is polished flat by CMP (Chemical Mechanical Polishing), and stopped on the silicon nitride (SiN) by using the way of grabbing EPD (Endpoint Detection). Further as shown in Figure 8 , phosphoric acid and DHF (Dilute Hydrofluoric Acid) are used to remove the silicon nitride (SiN) and oxide (Oxide, OX). Further as shown in Figure 9As shown, N-well (N-well) ion implantation is performed on the STI side. Specifically, photoresist (PR) is first coated, the N-well region is exposed and developed, and then ion implantation is performed. Phosphorus (P) and arsenic (As) ions are typically used. Ion implantation is performed in three steps, implanting to different depths each time. Furthermore, as... Figure 10 As shown, ion implantation of the P-well (P-well) is performed on the other side of the STI. Specifically, the photoresist (PR) left over from the previous process is first removed, then PR is applied, the P-well area is exposed and developed, and then ion implantation is performed. Boron (B) ions and boron difluoride (BF2) ions are generally used. Because B ions are lighter, they need to be implanted in four steps, each to a different depth. Furthermore, as... Figure 11 As shown, the preform ray (PR) residue from the previous process is first removed, and then a certain thickness of silicon nitride (SiN) is deposited to act as a hard mask. Next, PR is coated, exposed, and then developed. This mainly forms the drain and gate regions of the NMOS and PMOS transistors. Furthermore, as... Figure 12 As shown, etching of the hard mask and active region is performed. Then, as... Figure 13 As shown, an asher process is used to remove residual PR, and a wet clean area is used to etch away residual polymer and particles. Furthermore, as... Figure 14 As shown, SiN and OX are removed using phosphoric acid and DHF.

[0075] In step S202, a stepped work function layer is formed at the connection location between the channel region and the gate. In this embodiment, the stepped work function layer includes a first work function layer, a second work function layer, and a third work function layer. The second work function layer is connected to the end of the first work function layer and the beginning of the third work function layer, respectively. The work function magnitude of the second work function layer is different from that of the first and third work function layers. Furthermore, the metal gate material of the second work function layer is compatible with the doping type of the source and drain.

[0076] Specifically, please refer to Figures 15 to 19 In the embodiments of this application, such as Figure 15As shown, a certain thickness of input / output oxide (IO OX) can be generated on the surface of the AA region (active region, the surface containing the source, drain and channel region) by using the ISSG (In-Situ Steam Generation) process in the RTP (Rapid Thermal Processing) process, and the height thereof is about 23 Å (Angstroms, 1 Angstrom is equal to 0.1 nanometer), and then a certain thickness of High-K hafnium dioxide (HfO2) and titanium nitride (TiN) can be deposited by using the atomic layer deposition in sequence, and the height of the High-K hafnium dioxide can be about 16 Å, and the height of the titanium nitride can be about 20 Å. The purpose is to protect the HK (high-K material) and form the function layer, and then annealing at 680 degrees Celsius for 30 seconds, and the temperature is raised to 910 degrees Celsius in the last three seconds and then the temperature is lowered, and the purpose is to make the HK more dense. Further as shown, Figure 16 As shown, the PMOS region is opened as a whole by using the mask for making the PMOS function, and specifically, PR can be coated on the PW region, the NW region is exposed and developed, and then the horizontal titanium nitride (TiN) is removed by using the dry etching. Further as shown, Figure 17 As shown, the photoresist (PR) left by the previous process is removed, and then a certain thickness of TiAlN is deposited by using the atomic layer deposition technology, and the height thereof can be set to 20 Å, and here the PVD (Physical Vapor Deposition) process is adjusted to be deposited only on the horizontal surface. Further as shown, Figure 18 As shown, the NMOS region is opened as a whole by using the mask for making the NMOS function, and specifically, PR can be coated on the NW region, the PW region is exposed and developed, and then a certain dose of Al ions is injected into the vertical titanium nitride (TiN) by using the inclined ion implantation, so that the titanium nitride becomes TiAlN, thereby becoming the N-type function layer. Further as shown, Figure 19 As shown, the horizontal TiAlN in the NMOS region is removed by using the dry etching process, and then the PR is removed, thereby forming the stepped function layer in the connection position between the channel region and the gate. From the current structure, the function layer (TiAlN-TiN-TiAlN) of NPN is formed in the PMOS region (the region where the NW is located), and the function layer (TiN-TiAlN-TiN) of PNP is formed in the NMOS region (the region where the PW is located). Thus, different function layers can be formed in the same MOS without increasing any mask, so that we can better adjust the threshold voltage Vt of the semiconductor device.

[0077] In step S203, a gate is formed on the channel region. Specifically, please refer toFigures 20 to 25 In the embodiments of the present application, as shown in Figure 20 , a certain thickness of metal aluminum can be first formed on the surface of a wafer by using a CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition) process. Here, the surface of the polysilicon needs to be thoroughly cleaned before the deposition of Al, so as to remove the oxides, contaminants and other impurities on the surface. A surface treatment process, such as ion bombardment, plasma treatment or wet chemical treatment, can also be introduced to change the roughness and hydrophilicity of the surface, so as to facilitate the adhesion of the metal aluminum. After a certain thickness of Al is deposited by using PVD or CVD, an alloying treatment is performed, which needs to be performed under the atmosphere of an inert gas and by heat annealing, so as to promote the reaction between the metal aluminum and the polysilicon and form an alloying interface. This alloying layer can reduce the contact resistance and improve the stability of the interface. Then, a CMP (Chemical Mechanical Polishing) planarization treatment is performed. The thickness of the metal aluminum can be about 1600 Å, and then a certain thickness of TI / TIN is formed on the surface of the metal aluminum. Further, as shown in Figure 21 , a certain thickness of silicon nitride (SiN), a certain thickness of oxide (OX), a certain thickness of A-C (Amorphous Carbon), a certain thickness of ARC (Anti-Reflection Coating) and a certain thickness of BARC (Bottom Anti-Reflective Coating) are sequentially deposited, wherein the ARC includes SiON (silicon oxynitride) and OX (oxide). Then, PR is coated, and the exposure and development process of the mask of the gate is performed. Further, as shown in Figure 22 , a multi-step etching is performed by using a dry etching process. Further, as shown in Figure 23 , a R-oxide aluminum (recessed-oxide aluminum) process is performed, so that a certain thickness of oxide aluminum is generated on the sidewall of the metal aluminum layer. Further, as shown in Figure 24 , the SiN is removed by using phosphoric acid. Further, as shown in Figure 25 , a spacer one (first thin gate spacer) process is entered, a certain thickness of oxide (OX) and silicon nitride (SiN) is deposited, and then the horizontal OX and SiN are removed by using a self-aligned etching process. A certain thickness of OX is retained on the AA (active area).

[0078] In step S204, a source electrode is formed on the source region, and a drain electrode is formed on the drain region. In the embodiment of the present application, the surface height of the first work function layer is higher than the surface height of the source region, and the surface height of the third work function layer is higher than the surface height of the drain region.

[0079] Specifically, referring to Figures 26 to 34 In the embodiment of the present application, as shown in Figure 26 , a LDD (Lightly Doped Drain) process can be first entered, PR (photoresist) of the NLDD (N-type LDD) is coated, ion implantation is performed after exposure and development, and the ion implantation is set at a certain angle. Generally, Ge, C, B (pocket), N, P and As are sequentially implanted to a certain depth to form the NLDD region. Further, as shown in Figure 27 , the PR left by the previous process is removed, PR of the PLDD (P-type LDD) is coated, ion implantation is performed after exposure and development, and the ion implantation is set at a certain angle. Generally, Ge, C, As (pocket) and BF2 (boron difluoride) are sequentially implanted to a certain depth to form the PLDD region. Further, as shown in Figure 28 , the PR left by the previous process is removed, and N+ (N ion) and P+ (P ion) are formed on the source region and the drain region of the NMOS and the PMOS, respectively. Specifically, two photo processes can be performed here. First, the N+ region is mainly implanted with P, Ge, P, As and F to a certain depth, and then annealing is performed at a certain temperature (for example, 1050°C) by using a spike process, mainly to fix the implanted ions in a certain region. Further, as shown in Figure 29 , the PR left by the previous layer is removed, and then the P+ ion implantation is performed. The P+ region is mainly implanted with Ge, B and BF2 to a certain depth, and then annealing is performed at a certain temperature by using a spike process, for example, at 1050°C, mainly to fix the implanted ions in a certain region. Further, as shown in Figure 30As shown, the PR left by the previous layer is removed first, then the SAB (Self-Aligned Barrier) process and the process of forming NiSi (Nickel Silicide) are performed, and NiSi is formed in the area where CT (contact) is needed to reduce the resistance. OX (oxide) and SiN (silicon nitride) are deposited first to cover the area where metal silicide is not needed. Then the formation of metal silicide begins. SiCoNi pre-clean is performed first, with a thickness of about 60 A, so as to remove native impurities. Then NiPt alloy is deposited, with a deposition thickness of about 120 A. Then TiN capping layer is deposited, with a deposition thickness of 50 A. Then the first RTP1 (rapid thermal processing 1) is performed, with a process condition of 290 degrees Celsius and 30 seconds, to form high-resistance metal silicide Ni2PtSi (two nickel platinum silicon alloy), and then the second RTP2 (rapid thermal processing 2) is performed to form low-resistance NiPtSi2 (nickel platinum two silicon alloy), and after completion, the Ni (nickel) in the area where NiPtSi2 is not formed is removed. Further as shown Figure 31 As shown, the CT loop (contact loop) process is entered, and a CESL (Contact Etch Stop Layer) of 300 A of SiN is deposited first. Then a certain thickness of TEOS (tetraethyl orthosilicate) is deposited by using a high aspect ratio process (harp deposition), with a thickness of 1100 A. Then a certain thickness of PE-TEOS (Plasma Enhanced Chemical Vapor Deposition TEOS) is deposited by using CD (Critical Dimension) CVD, with a thickness of 3600 A. Then the ILD (Interlayer Dielectric) is ground flat by CMP, and then TEOS is re-deposited (recap), with a thickness of 600 A. This obtains the structure as shown. Further as shown Figure 32 As shown, a-C (Amorphous Carbon) with a thickness of 1900 A, ARC (composed of SiON with a thickness of 320 A and OX with a thickness of 50 A) with a certain thickness, and BARC with a thickness of 200 A are sequentially deposited. Then PR with a thickness of 1000 A is coated. Finally, the contact (Contact) is exposed and developed. Further as shown Figure 33 As shown, a multi-step dry etching process is performed. Further as shown Figure 34As shown, some material left over from etching the CT hole is cleaned using a WET (wet) process, then Ti of 100 A thickness and TiN of 50 A thickness are deposited in sequence, then W is deposited, and finally W is polished using CMP, and then the subsequent metal process is entered. The reason for depositing both Ti and TiN is as follows. If only Ti is deposited, W deposition will use WF6 (tungsten hexafluoride) which is very oxidizing and will react with Ti to form defects, which will cause the entire contact hole to peel off the substrate, so a layer of TiN is needed to prevent the diffusion and contact of WF6 and Ti. If only TiN is deposited, it has a large stress and is easily peeled off the substrate, so Ti is needed as a buffer layer to improve the bonding force.

[0080] While several embodiments of the application have been shown and described herein, it is to be understood that all the forms of this application need not have all of the described advantages. It is therefore contemplated that there will be many modifications in the designs, arrangements, details and steps which have been described and fall within the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate (1), source (2), drain (3) and gate (4); The semiconductor substrate (1) has a source region (5) corresponding to the source electrode (2) and a drain region (6) corresponding to the drain electrode (3), and a channel region (7) is provided between the source region (5) and the drain region (6); the gate (4) is disposed on the channel region (7); A stepped work function layer is provided at the connection position between the channel region (7) and the gate (4). The stepped work function layer includes a first work function layer (81), a second work function layer (82), and a third work function layer (83). The second work function layer (82) is connected to the end of the first work function layer (81) and the beginning of the third work function layer (83), respectively. The work function of the second work function layer (82) is inconsistent with that of the first work function layer (81) and the third work function layer (83). The metal gate material of the second work function layer (82) is adapted to the doping type of the source (2) and the drain (3) to form a PNP work function layer at the same gate in the N-type semiconductor region and / or an NPN work function layer at the same gate in the P-type semiconductor region. The second work function layer (82) is perpendicular to the first work function layer (81) and the third work function layer (83), respectively. The surface height of the first work function layer (81) is higher than the surface height of the source region (5), and the surface height of the third work function layer (83) is higher than the surface height of the drain region (6).

2. The semiconductor device according to claim 1, characterized in that, The channel region (7) includes an interconnected first region (71) and a second region (72). The first region (71) is located between the source region (5) and the extension line of the second work function layer (82), and the second region (72) is located between the drain region and the extension line of the second work function layer (82).

3. The semiconductor device according to claim 1, characterized in that, The gate (4) has an oxide protective layer (9) on its side and a buffer protective layer (10) on its top.

4. The semiconductor device according to claim 3, characterized in that, The trench region (7) is also provided with a stepped high dielectric layer (11); The stepped work function layer is disposed between the gate (4) and the stepped high dielectric layer (11), and the stepped high dielectric layer (11) and the stepped work function layer are matched and parallel.

5. The semiconductor device according to claim 4, characterized in that, In the vertical direction, the buffer protective layer (10), the oxide protective layer (9), the stepped work function layer and the stepped high dielectric layer (11) are provided with a first protective layer (12) on both sides.

6. The semiconductor device according to claim 5, characterized in that, In the vertical direction, a second protective layer (13) is provided on the first protective layer (12) on both sides.

7. The semiconductor device according to claim 1, characterized in that, A first lightly doped region (14) is provided on the outer periphery of the source region (5), and a second lightly doped region (15) is provided on the outer periphery of the drain region (6). Wherein, when the charge carrier of the semiconductor device is a hole, the first lightly doped region (14) and the second lightly doped region (15) are P-type lightly doped regions; when the charge carrier of the semiconductor device is an electron, the first lightly doped region (14) and the second lightly doped region (15) are N-type lightly doped regions.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor substrate (1) is further provided with a well layer (16), which is disposed below the first lightly doped region (14), the channel region (7) and the second lightly doped region (15).

9. The semiconductor device according to claim 8, characterized in that, The semiconductor substrate (1) is further provided with a deep well layer (17), which is disposed below the well layer (16).

10. A method for manufacturing a semiconductor device, characterized in that, include: A source region corresponding to the source and a drain region corresponding to the drain are formed in a semiconductor substrate, and a channel region is formed between the source region and the drain region; A stepped work function layer is formed at the connection location between the channel region and the gate. The stepped work function layer comprises a first work function layer, a second work function layer, and a third work function layer. The second work function layer is connected to the end of the first work function layer and the beginning of the third work function layer, respectively. The work function magnitude of the second work function layer is different from that of the first and third work function layers. Furthermore, the metal gate material of the second work function layer is adapted to the doping type of the source and drain electrodes to form a PNP work function layer at the same gate in the N-type semiconductor region, and / or an NPN work function layer at the same gate in the P-type semiconductor region. The second work function layer is perpendicular to both the first and third work function layers. A gate is formed on the channel region; A source electrode is formed on the source region, and a drain electrode is formed on the drain region, wherein the surface height of the first work function layer is higher than the surface height of the source region, and the surface height of the third work function layer is higher than the surface height of the drain region.

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