Semiconductor structure, semiconductor structure forming method, memory and electronic device
By designing a semiconductor structure with interlocking concave and convex structures between the floating gate and the control gate, the problems of dielectric layer aging and high power consumption in embedded flash memory are solved, improving the write and erase efficiency of the memory and enhancing its reliability.
Patent Information
- Application Number
- CN202410896130.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-04
- Publication Date
- 2026-01-09
AI Technical Summary
In existing embedded flash memory, applying high voltage to the control gate leads to aging of the dielectric layer and high power consumption, affecting chip reliability.
The design incorporates interlocking floating gate and control gate structures in a semiconductor structure, increasing the contact area between the floating gate and control gate, reducing the applied voltage, and delaying dielectric layer aging.
It improves the write and erase efficiency of flash memory, reduces power consumption, and enhances chip reliability.
Smart Images
Figure CN121310604A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor structure, a forming method of the semiconductor structure, a memory and an electronic device. BACKGROUND
[0002] Memory can be roughly divided into two categories: volatile memory and non-volatile memory. Volatile memory loses the information stored therein immediately when the system is turned off, so it needs a continuous power supply to maintain data, and most random access memories (RAMs) belong to this category. Non-volatile memory can maintain data information when the system is turned off or there is no power supply.
[0003] Embedded flash memory is a kind of non-volatile memory that can maintain data stability in the case of power failure. It usually uses a flash memory chip as a storage medium, and the flash memory chip is internally composed of a series of storage units, each of which can store one or more bits of data. The read and write operations of embedded flash memory are realized by applying voltage in the storage unit.
[0004] In the related art, a high voltage is applied to the control gate (CG) in the embedded flash memory, and the coupling voltage generated by the capacitor on the medium layer between the control gate CG and the floating gate (FG) is used for writing electrons, however, the higher voltage applied to the control gate can cause the medium layer to age, and at the same time consume a large amount of power, affecting the reliability of the chip. SUMMARY
[0005] To solve the above technical problems, the present application provides a semiconductor structure, a forming method of the semiconductor structure, a memory and an electronic device.
[0006] In one aspect, the embodiments of the present application disclose a semiconductor structure, comprising:
[0007] a substrate;
[0008] a tunneling oxide layer located on the substrate;
[0009] a first structure located on the tunneling oxide layer; the first structure comprises a floating gate located on the tunneling oxide layer, a medium layer located on the floating gate, and a control gate located on the medium layer;
[0010] The side of the floating gate facing the medium layer comprises a first concave-convex structure, and the side of the control gate facing the medium layer comprises a second concave-convex structure; the first concave-convex structure and the second concave-convex structure are embedded in each other.
[0011] In some possible embodiments, the first concave-convex structure comprises at least one first convex structure; the second concave-convex structure comprises at least one first concave structure;
[0012] The number of the first convex structure and the first concave structure are the same.
[0013] In some possible embodiments, the top surface of the first convex structure is higher than the bottom surface of the control gate.
[0014] In some possible embodiments, the first concave-convex structure includes at least one second concave structure; the second concave-convex structure includes at least one second convex structure.
[0015] The number of the second concave structure and the second convex structure are the same.
[0016] In some possible embodiments, the bottom surface of the second convex structure is higher than the top surface of the floating gate.
[0017] In some possible embodiments, the shape of the first or second concave-convex structure includes one or more of the following: rectangle, triangle, trapezoid.
[0018] In some possible embodiments, the dielectric layer includes an ONO dielectric layer.
[0019] In some possible embodiments, the first structure includes two first structures distributed along a first direction;
[0020] The semiconductor structure also includes an erase gate located between the two first structures.
[0021] In some possible embodiments,
[0022] The first structure includes multiple floating gate structures, multiple isolation structures, a dielectric layer, and a control gate;
[0023] Multiple floating gate structures are located on the tunneling oxide layer; the lower portions of multiple isolation structures are located in the substrate; the multiple floating gate structures and multiple isolation structures are spaced apart in the second direction.
[0024] The dielectric layer is located on the floating gate structure and the isolation structure; the control gate is located on the dielectric layer.
[0025] On the other hand, embodiments of this application disclose a method for forming a semiconductor structure, the method comprising:
[0026] Provide substrate;
[0027] A tunneling oxide layer is formed on the substrate;
[0028] Floating gates are formed on the tunneling oxide layer;
[0029] A dielectric layer is formed on the floating gate;
[0030] A control gate is formed on the dielectric layer; wherein the side of the floating gate facing the dielectric layer includes a first concave-convex structure, and the side of the control gate facing the dielectric layer includes a second concave-convex structure; the first concave-convex structure and the second concave-convex structure are interlocked with each other.
[0031] In some possible embodiments, forming a floating gate on the tunneling oxide layer includes:
[0032] A floating gate layer is formed on the tunneling oxide layer;
[0033] Multiple cavities are obtained by etching the floating gate layer, tunneling oxide layer, and substrate.
[0034] Multiple cavities were deposited to obtain multiple isolation structures;
[0035] The floating gate layer between the two isolation structures is etched to obtain a floating gate containing the first concave-convex structure.
[0036] In some possible embodiments, the floating gate layer includes a first region and a second region side by side; etching the floating gate layer to obtain a floating gate containing a first uneven structure includes:
[0037] The first region is etched to obtain the floating gate; the second region is a convex structure on the side of the floating gate facing the dielectric layer.
[0038] In some possible embodiments, the floating gate layer includes a first region and a second region side by side; etching the floating gate layer to obtain a floating gate containing a first uneven structure includes:
[0039] The second region is etched to obtain a floating gate; the cavity corresponding to the second region and the first region form a concave structure on the side of the floating gate facing the dielectric layer.
[0040] On the other hand, embodiments of this application disclose a flash memory, which includes the semiconductor structure described above.
[0041] On the other hand, embodiments of this application disclose an electronic device, which includes a flash memory as described above.
[0042] The technical solution provided in this application has the following technical effects:
[0043] The system includes a substrate, a tunneling oxide layer on the substrate, and a first structure on the tunneling oxide layer. The first structure includes a floating gate on the tunneling oxide layer, a dielectric layer on the floating gate, and a control gate on the dielectric layer. The floating gate has a first bump structure on the side facing the dielectric layer, and the control gate has a second bump structure on the side facing the dielectric layer. The first and second bump structures are interlocked. In this embodiment, the interlocking of the first bump structure in the floating gate and the second bump structure in the control gate increases the contact area between the floating gate and the control gate, thereby improving the coupling ratio from the control gate to the floating gate and enhancing the write and erase efficiency of the resulting flash memory. Simultaneously, the increased contact area between the floating gate and the control gate reduces the voltage applied to the control gate during writing, delaying the aging of the dielectric layer between the control gate and the floating gate, reducing power consumption, and improving the reliability of the flash memory. Attached Figure Description
[0044] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a semiconductor structure provided in an embodiment of this application;
[0046] Figure 2 This is a second semiconductor structure provided in the embodiments of this application;
[0047] Figure 3 This is a semiconductor structure three provided in the embodiments of this application;
[0048] Figure 4 This is a semiconductor structure four provided in the embodiments of this application;
[0049] Figure 5 This is a semiconductor structure five provided in the embodiments of this application;
[0050] Figure 6 This application provides a semiconductor structure six;
[0051] Figure 7 This is a semiconductor structure seven provided in the embodiments of this application;
[0052] Figure 8 This is a schematic diagram of a method for forming a semiconductor structure provided in an embodiment of this application;
[0053] Figures 9(a)-9(j)This is a schematic diagram of a method for forming a semiconductor structure provided in an embodiment of this application;
[0054] 10-Substrate; 20-Tunneling oxide layer; 30-Floating gate; 40-Dielectric layer; 50-Control gate; 300-First concave-convex structure; 500-Second concave-convex structure; 3001-First convex structure; 5001-First concave structure; 3002-Second concave structure; 5002-Second convex structure; 3003-Third convex structure; 5003-Third concave structure; 120-Erase gate; 130-Word line gate; 301-Floating gate structure; 200-Isolation structure; 60-Floating gate layer; 80-Control gate layer; 90-Control gate hard mask layer; 100-Control gate sidewall; 110-Sidewall dielectric layer. Detailed Implementation
[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0056] It should be noted that the term "an embodiment" or "embodiment" in the specification of the embodiments of this application refers to a specific feature, structure, or characteristic that can be included in at least one implementation of this application. It should be understood that in the specification, claims, and accompanying drawings of the embodiments of this application, the terms "upper," "lower," "top," "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, in the description of this embodiment, unless otherwise stated, "a plurality of" means two or more. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, or product that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0057] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.
[0058] To make the objectives, technical solutions, and advantages disclosed in the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.
[0059] In flash memory, the coupling ratio from the control gate (CG) to the floating gate (FG) directly affects the write and erase efficiency. Improving this coupling ratio is crucial for flash memory efficiency. In related technologies, after the floating gate is formed, an ONO (silicon dioxide-silicon nitride-silicon oxide, SiO2-SIN-SiO2) layer can be deposited, and then the control gate is deposited on the ONO layer. The ONO layer acts as a dielectric to form a capacitor, which the control gate (CG) uses to control the floating gate (FG) during application. However, based on current process flows, increasing the coupling ratio from the control gate to the floating gate necessitates thinning the ONO layer. However, thinning the ONO layer reduces charge storage time, making this approach unacceptable.
[0060] In view of this, embodiments of this application provide a semiconductor structure for increasing the coupling ratio from the control gate to the floating gate. Please refer to... Figure 1 , Figure 1 This is a semiconductor structure provided in an embodiment of this application. Figure 1 For example, a cross-sectional view of a semiconductor structure in the first direction, such as... Figure 1 As shown, the structure includes a substrate 10, a tunneling oxide layer 20 on the substrate 10, and a first structure on the tunneling oxide layer 20. The first structure includes a floating gate 30 on the tunneling oxide layer 20, a dielectric layer 40 on the floating gate 30, and a control gate 50 on the dielectric layer 40.
[0061] In this embodiment, the floating gate 30 includes a first concave-convex structure 300 on the side facing the dielectric layer 40, and the control gate 50 includes a second concave-convex structure 500 on the side facing the dielectric layer 40. The first concave-convex structure 300 and the second concave-convex structure 500 are interlocked.
[0062] Optionally, the dielectric layer 40 may also vary according to the structure of the floating gate 30 and the control gate 50.
[0063] In this embodiment, the first uneven structure 300 included in the floating gate 30 and the second uneven structure 500 included in the control gate 50 are interlocked, increasing the contact area between the floating gate 30 and the control gate 50. This improves the coupling ratio between the control gate 50 and the floating gate 30, thereby enhancing the write and erase efficiency of the final flash memory. Simultaneously, the increased contact area between the floating gate 30 and the control gate 50 reduces the voltage applied to the control gate 50 during writing, delaying the aging of the dielectric layer 40 between the control gate 50 and the floating gate 30, reducing power consumption, and improving the reliability of the flash memory.
[0064] In this embodiment, the substrate 10 may be made of silicon (Si), germanium (Ge), silicon-germanium-SiGe, or silicon carbide, or silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials. Optionally, the substrate 10 may include isolation channels, such as shallow trench isolation (STI), and may also include active regions.
[0065] In this embodiment, the tunneling oxide layer 20 can be formed on the substrate 10 to prevent ions from potentially passing through the floating gate 30 and entering the substrate 10 during ion implantation, thereby affecting the voltage state of the substrate 10 and adversely impacting the formation of the flash memory. The tunneling oxide layer 20 can be formed using a hot-tube furnace process or a rapid thermal oxidation process. In this embodiment, the material of the tunneling oxide layer 20 can be silicon oxide or nitrogen-doped silicon oxide.
[0066] In this embodiment, the floating gate 30 can be formed on the tunneling oxide layer 20, and the floating gate 30 can be polysilicon. Optionally, the floating gate 30 can be formed by deposition.
[0067] In this embodiment, the dielectric layer 40 is used to isolate the floating gate 30 and the control gate 50. The dielectric layer 40 can be an ONO dielectric layer. The ONO dielectric layer can be a silicon oxide-silicon nitride-silicon oxide, or a SiO2-SiO2 stack. The ONO dielectric layer can be formed, for example, by first forming a silicon oxide layer using thermal oxidation, then forming a silicon nitride layer on the silicon oxide layer using chemical vapor deposition, and finally oxidizing part of the silicon nitride layer with wet hydrogen and oxygen to form another silicon oxide layer. The material of the dielectric layer 40 in this embodiment is not limited to this; for example, in some embodiments, the dielectric layer 40 may also include a high dielectric constant material.
[0068] In this embodiment, the control gate 50 comprises the same material as the floating gate 30, such as polysilicon.
[0069] In this application embodiment, the first concave-convex structure 300 included on the side of the floating gate 30 facing the dielectric layer 40 and the second concave-convex structure 500 included on the side of the control gate 50 facing the dielectric layer 40 are interlocked and can be presented in various embodiments.
[0070] In one alternative embodiment, the first concave-convex structure includes at least one first convex structure, the second concave-convex structure includes at least one first concave structure, and the number of first convex structures and first concave structures are the same.
[0071] Optionally, the floating gate includes one first convex structure, and the control gate includes one first concave structure. See also... Figure 2 , Figure 2 This is a second semiconductor structure provided in the embodiments of this application. Figure 2 For example, a cross-sectional view of a semiconductor structure in the first direction, such as... Figure 2 As shown, the structure includes a substrate 10, a tunneling oxide layer 20 on the substrate 10, and a first structure on the tunneling oxide layer 20. The first structure includes a floating gate 30 on the tunneling oxide layer 20, a dielectric layer 40 on the floating gate 30, and a control gate 50 on the dielectric layer 40.
[0072] The first convex-concave structure 300 included on the side of the floating gate 30 facing the dielectric layer 40 is a first convex structure 3001 (circled in dashed lines), and the number of first convex structures 3001 is one. The second convex-concave structure 500 included on the side of the control gate 50 facing the dielectric layer 40 is a first concave structure 5001 (circled in dashed lines), and the number of first concave structures 5001 is one.
[0073] like Figure 2 As shown, the first convex structure 3001 and the first concave structure 5001 are interlocked. The dielectric layer 40 also exhibits an upwardly convex structure as the structure of the floating gate 30 and the control gate 50 adapts to the changes.
[0074] In this embodiment of the application, in order to increase the contact area between the floating gate 30 and the control gate 50, Figure 2 The top surface of the first convex structure 3001 shown can be higher than the bottom surface of the control gate. That is, the first convex structure 3001 of the floating gate 30 can penetrate into the first concave structure 5001 of the control gate 50, and based on the trade-off between the floating gate etching window and the coupling ratio, the ratio of the height of the first convex structure of the floating gate 30 to the height of the remaining structure of the floating gate 30 can be 2:1.
[0075] Alternatively, the top surface of the first convex structure 3001 can be equal to the bottom surface of the control gate.
[0076] Optionally, the floating gate may include multiple first convex structures, and the control gate may also include multiple first concave structures. See [link to relevant documentation]. Figure 3, Figure 3 This is a semiconductor structure three provided in the embodiments of this application. Figure 3 For example, a cross-sectional view of a semiconductor structure in the first direction, such as... Figure 3 As shown, the structure includes a substrate 10, a tunneling oxide layer 20 on the substrate 10, and a first structure on the tunneling oxide layer 20. The first structure includes a floating gate 30 on the tunneling oxide layer 20, a dielectric layer 40 on the floating gate 30, and a control gate 50 on the dielectric layer 40.
[0077] The first convex structure 300 included on the side of the floating gate 30 facing the dielectric layer 40 is a first convex structure 3001 (circled in dashed lines), and there are multiple first convex structures 3001. Figure 3 Two first convex structures 3001 are shown. The second concave-convex structure 500 included on the side of the control gate 50 facing the dielectric layer 40 is a first concave structure 5001 (circled in dashed lines), and there are multiple first concave structures 5001. Figure 3 Two first concave structures 5001 are shown.
[0078] like Figure 3 As shown, the first convex structure 3001 on the left and the first concave structure 5001 on the left are interlocked, and the first convex structure 3001 on the right and the first concave structure 5001 on the right are interlocked. The dielectric layer 40 also exhibits two upwardly convex structures as the structure of the floating gate 30 and the control gate 50 adapts.
[0079] In this embodiment of the application, in order to increase the contact area between the floating gate 30 and the control gate 50, Figure 2 The top surface of the first convex structure 3001 shown can be higher than the bottom surface of the control gate. That is, the first convex structure 3001 of the floating gate 30 can penetrate into the first concave structure 5001 of the control gate 50, and based on the trade-off between the floating gate etching window and the coupling ratio, the ratio of the height of the first convex structure of the floating gate 30 to the height of the remaining structure of the floating gate 30 can be 2:1.
[0080] Alternatively, the top surface of the first convex structure 3001 can be equal to the bottom surface of the control gate.
[0081] In another alternative embodiment, the first concave-convex structure includes at least one second concave structure, the second concave-convex structure includes at least one second convex structure, and the number of second concave structures and second convex structures are the same.
[0082] Optionally, the floating gate includes one second concave structure, and the control gate includes one second convex structure. For example... Figure 1As shown, the first concave-convex structure on the side of the floating gate 30 facing the dielectric layer 40 is a second concave structure 300 (circled in dashed lines), and the number of second concave structures 300 is one. The second concave-convex structure on the side of the control gate 50 facing the dielectric layer 40 is a second convex structure 500 (circled in dashed lines), and the number of second convex structures 500 is one.
[0083] like Figure 1 As shown, the second concave structure and the second convex structure are interlocked. The dielectric layer 40 also exhibits a downward convex structure, adapting to the structural changes of the floating gate 30 and the control gate 50.
[0084] In this embodiment of the application, in order to increase the contact area between the floating gate 30 and the control gate 50, Figure 1 The bottom surface of the second convex structure 500 shown is higher than the top surface of the floating gate. That is, the second convex structure 500 of the control gate 50 can penetrate deep into the second concave structure 300 of the floating gate 30, and based on the trade-off between the floating gate etching window and the coupling ratio, the ratio of the depth of the second concave structure of the floating gate 30 to the height of the non-concave structure in the floating gate 30 can be 2:1.
[0085] Alternatively, the bottom surface of the second convex structure 500 can be equal to the top surface of the floating gate.
[0086] Optionally, the floating gate may include multiple second concave structures, and the control gate may also include multiple second convex structures. See also... Figure 4 , Figure 4 This application provides a semiconductor structure four. Figure 4 For example, a cross-sectional view of a semiconductor structure in the first direction, such as... Figure 4 As shown, the structure includes a substrate 10, a tunneling oxide layer 20 on the substrate 10, and a first structure on the tunneling oxide layer 20. The first structure includes a floating gate 30 on the tunneling oxide layer 20, a dielectric layer 40 on the floating gate 30, and a control gate 50 on the dielectric layer 40.
[0087] The first concave-convex structure 300 on the side of the floating gate 30 facing the dielectric layer 40 is a second concave structure 3002 (circled in dashed lines), and there are multiple second concave structures 3002. Figure 4 Two second concave structures 3002 are shown. The second concave-convex structure 500 included on the side of the control gate 50 facing the dielectric layer 40 is a second convex structure 5002 (circled in dashed lines), and there are multiple second convex structures 500. Figure 4 Two second convex structures 5002 are shown.
[0088] like Figure 4As shown, the second concave structure 3002 on the left and the second convex structure 5002 on the left are interlocked, and the second concave structure 3002 on the right and the second convex structure 5002 on the right are interlocked. The dielectric layer 40 also exhibits two downwardly convex structures as the structure of the floating gate 30 and the control gate 50 adapts.
[0089] In this embodiment of the application, in order to increase the contact area between the floating gate 30 and the control gate 50, Figure 4 The bottom surface of the second convex structure 5002 shown is higher than the top surface of the floating gate. That is, the second convex structure 500 of the control gate 50 can penetrate deep into the second concave structure 300 of the floating gate 30, and based on the trade-off between the floating gate etching window and the coupling ratio, the ratio of the depth of the second concave structure of the floating gate 30 to the height of the non-concave structure in the floating gate 30 can be 2:1.
[0090] Alternatively, the bottom surface of the second convex structure 500 can be equal to the top surface of the floating gate.
[0091] In the implementation of this application, the shape of the first concave-convex structure or the second concave-convex structure includes one or more of the following: rectangle, triangle, trapezoid.
[0092] Optional, such as Figures 1-4 As shown, the shape of the first or second concave-convex structure can be rectangular, and the number of rectangles can be one or more.
[0093] Please see Figure 5 , Figure 5 This is a semiconductor structure five provided in the embodiments of this application. Figure 5 For example, a cross-sectional view of a semiconductor structure in the first direction, such as... Figure 5 As shown, the structure includes a substrate 10, a tunneling oxide layer 20 on the substrate 10, and a first structure on the tunneling oxide layer 20. The first structure includes a floating gate 30 on the tunneling oxide layer 20, a dielectric layer 40 on the floating gate 30, and a control gate 50 on the dielectric layer 40.
[0094] The first convex-concave structure 300 on the side of the floating gate 30 facing the dielectric layer 40 is a third convex structure 3003 (circled in dashed). The second convex-concave structure 500 on the side of the control gate 50 facing the dielectric layer 40 is a third concave structure 5003 (circled in dashed). The cross-sectional shape of the third convex structure 3003 and the third concave structure 5003 is triangular.
[0095] Optionally, the first concave-convex structure may include one triangular third convex structure 3003, and correspondingly, the second concave-convex structure may include one triangular third concave structure 5003. Optionally, the first concave-convex structure may include multiple triangular third convex structures 3003, and correspondingly, the second concave-convex structure may include multiple triangular third concave structures 5003.
[0096] Optionally, the first concave-convex structure may include one triangular second concave structure, and correspondingly, the second concave-convex structure may include one triangular second convex structure. Optionally, the first concave-convex structure may include multiple triangular second concave structures, and correspondingly, the second concave-convex structure may include multiple triangular second convex structures.
[0097] Optionally, the first concave-convex structure may include a triangular first convex structure and a trapezoidal first convex structure, and correspondingly, the second concave-convex structure includes a triangular first concave structure and a trapezoidal first concave structure.
[0098] In this embodiment, the tunneling oxide layer 20 may include a plurality of first structures. Optionally, the plurality of first structures may be two or more first structures.
[0099] Please see Figure 8 , Figure 8 This application provides a semiconductor structure six. Figure 8 For example, a cross-sectional view of a semiconductor structure in the first direction, such as... Figure 8 As shown, the tunneling oxide layer 20 may include two first structures, wherein the two first structures are distributed on the tunneling oxide layer 20 along a first direction.
[0100] Optionally, an erase gate (EG) 120 may be included between the two first structures, and a word line gate 130 may be formed on the opposite side of the two first structures.
[0101] Please see Figure 7 , Figure 7 This is a semiconductor structure seven provided in the embodiments of this application. Figure 7 For example, a cross-sectional view of a semiconductor structure in the second direction. Figure 7As shown, the structure includes a substrate 10, a tunneling oxide layer 20 on the substrate 10, and a first structure on the tunneling oxide layer 20. Optionally, from a cross-sectional view corresponding to the second direction, the first structure may include multiple floating gate structures 301, multiple isolation structures 200, a dielectric layer 40, and a control gate 50. The multiple floating gate structures 301 are located on the tunneling oxide layer 20, the lower portions of the multiple isolation structures 200 are located in the substrate 10, the multiple floating gate structures 301 and the multiple isolation structures 200 are spaced apart in the second direction, the dielectric layer 40 is located on the floating gate structures 301 and the isolation structures 200, and the control gate 50 is located on the dielectric layer 40.
[0102] Figure 8 This is a schematic diagram illustrating a method for forming a semiconductor structure according to an exemplary embodiment. It should be noted that this specification provides the operational steps of the methods described in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operational steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual systems or products, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment). Specifically, as shown in the figures... Figure 8 As shown, this flowchart includes at least the following steps S801-S809, which will be discussed below. Figures 9(a)-9(j) To elaborate in detail:
[0103] In step S801, a substrate is provided.
[0104] Figure 9(a) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure One As shown in Figure 9(a), the substrate 10 is included. In the embodiments of this application, the material of the substrate 10 may be silicon (Si), germanium (Ge), silicon-germanium-SiGe, or silicon carbide, or silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials.
[0105] In an optional embodiment, the substrate provided in step S801 may have already formed isolation channels, such as a shallow trench isolation structure (STI), and has undergone trap implantation, other ion implantation, and annealing. Those skilled in the art should understand that, in order to clearly express the core ideas of this application, the accompanying drawings only schematically illustrate the substrate and surrounding devices and structures, but this does not mean that the fabrication process of the flash memory involved in this invention only includes these devices and structures. For the flash memory involved in this invention, well-known flash memory structures and process steps may also be included.
[0106] In step S803, a tunneling oxide layer is formed on the substrate.
[0107] Figure 9(b) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure Two As shown in Figure 9(b), a tunneling oxide layer 20 can be formed on the surface of the substrate 10 to prevent ions from potentially passing through the floating gate into the substrate during ion implantation, thereby affecting the voltage state of the substrate and adversely impacting the formation of the flash memory. The tunneling oxide layer can be formed using a hot-furnace tube process or a rapid thermal oxidation process. In this embodiment, the material of the tunneling oxide layer can be silicon oxide or nitrogen-doped silicon oxide.
[0108] In step S805, a floating gate is formed on the tunneling oxide layer.
[0109] In this embodiment, the floating gate 30 can be formed on the tunneling oxide layer 20, and the floating gate 30 can be polysilicon. Optionally, the floating gate 30 can be formed by deposition.
[0110] Figure 9(c) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure Three Figure 9(c) shows the semiconductor structure, with cross-sectional views corresponding to the first direction and the second direction. As shown in Figure 9(c), a floating gate layer 60 can be formed on the tunneling oxide layer 20.
[0111] As can be seen from the cross-sectional view corresponding to the second direction in Figure 9(c), in an optional embodiment, after forming the floating gate layer 60 on the tunneling oxide layer 20, the floating gate layer 60, the tunneling oxide layer 20, and the substrate 10 can be etched to obtain multiple cavities. Then, the multiple cavities can be deposited to obtain multiple isolation structures 200, such as shallow trench isolation structures (STI).
[0112] In another alternative embodiment, after forming the floating gate layer 60 on the tunneling oxide layer 20, an oxide layer can be formed on the floating gate layer 60, and the oxide layer, floating gate layer 60, tunneling oxide layer 20 and substrate 10 can be etched to obtain multiple cavities. Then, the multiple cavities can be deposited to obtain multiple isolation structures 200, such as shallow trench isolation structures (STI).
[0113] Figure 9(d) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure FourFigure 9(d) shows the semiconductor structure, including cross-sectional views in the first and second directions. As shown in Figure 9(d), from the cross-sectional view in the first direction, the floating gate layer 60 is etched to obtain a floating gate containing the first uneven structure. From the cross-sectional view in the second direction, the floating gate layer 60 between the various isolation structures can be etched to obtain a floating gate containing the first uneven structure.
[0114] In one alternative embodiment, the floating gate layer may include a first region and a second region side by side, such as Figure 2 As shown, the first region (both sides of the convex structure) can be etched to obtain the floating gate, wherein the second region is the convex structure on the side of the floating gate facing the dielectric layer.
[0115] In another alternative embodiment, the floating gate layer may include a first region and a second region side by side, such as Figure 1 As shown, the second region can be etched to obtain a floating gate, wherein the cavity corresponding to the second region and the first region (both sides of the concave structure) form a concave structure on the side of the floating gate facing the dielectric layer.
[0116] In step S807, a dielectric layer is formed on the floating gate.
[0117] In this embodiment, the dielectric layer 40 is used to isolate the floating gate 30 and the control gate 50. The dielectric layer 40 can be an ONO dielectric layer. The ONO dielectric layer can be a silicon oxide-silicon nitride-silicon oxide, or a SiO2-SiO2 stack. The ONO dielectric layer can be formed, for example, by first forming a silicon oxide layer using thermal oxidation, then forming a silicon nitride layer on the silicon oxide layer using chemical vapor deposition, and finally oxidizing part of the silicon nitride layer with wet hydrogen and oxygen to form another silicon oxide layer. The material of the dielectric layer 40 in this embodiment is not limited to this; for example, in some embodiments, the dielectric layer 40 may also include a high dielectric constant material.
[0118] Figure 9(e) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure Five Figure 9(e) shows the semiconductor structure, a cross-sectional view corresponding to the first direction and a cross-sectional view corresponding to the second direction. As shown in Figure 9(e), a dielectric layer 40 is deposited on the floating gate and isolation structure 200 and the dielectric layer 40 is etched.
[0119] In step S809, a control gate is formed on the dielectric layer; wherein the side of the floating gate facing the dielectric layer includes a first concave-convex structure, and the side of the control gate facing the dielectric layer includes a second concave-convex structure; the first concave-convex structure and the second concave-convex structure are interlocked with each other.
[0120] Figure 9(f) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment.Figure Six Figure 9(f) shows the semiconductor structure, with cross-sectional views corresponding to the first direction and the second direction. As shown in Figure 9(f), a control gate layer 80 is deposited on the dielectric layer 40, and a control gate hard mask layer 90 is formed on the control gate layer 80.
[0121] Figure 9(g) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure Seven Figure 9(g) is a cross-sectional view of the semiconductor structure in the first direction. As shown in Figure 9(g), the control gate hard mask layer 90, the control gate layer 80 and the dielectric layer 40 can be processed by photolithography or etching processes.
[0122] Figure 9(h) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure Eight Figure 9(h) is a cross-sectional view of the semiconductor structure in the first direction. As shown in Figure 9(h), control gate sidewalls 100 can be formed on both sides of each control gate 30. The control gate sidewalls 100 can cover the control gate and the sidewalls of the control gate hard mask layer.
[0123] Optionally, the control gate sidewall 100 may include silicon dioxide.
[0124] Figure 9(i) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure 9(i) is a cross-sectional view of the semiconductor structure in the first direction. As shown in Figure 9(i), the floating gate layer 60 can be photolithographically or etched to obtain the floating gate 30. Optionally, the control gate sidewall 100 can be used as an etch barrier layer for etching the floating gate layer. The floating gate layer can be etched using a dry etching process.
[0125] Figure 9(j) is a schematic diagram of a semiconductor structure formation method according to an exemplary embodiment. Figure 9(j) is a cross-sectional view of the semiconductor structure in the first direction. As shown in Figure 9(j), the control gate sidewall 100 between the two control gates 50 can be removed, and a sidewall dielectric layer 110 is formed in the area where the control gate sidewall 100 is removed. The sidewall dielectric layer 110 can be formed using a chemical vapor deposition process, and the sidewall dielectric layer 110 can include an insulating material such as silicon oxide. Optionally, the thickness of the sidewall dielectric layer 110 is less than the thickness of the control gate sidewall 100.
[0126] In this embodiment of the application, after the sidewall dielectric layer 110 is formed, an erase gate 120 (EG) can be formed on the tunnel oxide layer 20 between the two control gates 50, the two dielectric layers 40, and the two floating gates 30.
[0127] In an alternative embodiment, an erase gate oxide layer may be formed first on the sidewall dielectric layer 110, and then an erase gate 120 covering the erase gate oxide layer may be formed.
[0128] Optionally, the material of the erase gate 120 may include polysilicon or polysilicon doped with ions. Specifically, a thicker erase gate layer may be formed on the surface of the erase gate oxide layer. The erase gate layer may be formed using a chemical vapor deposition process. For example, a thicker polysilicon layer may be deposited first, covering the erase gate oxide layer and exceeding the control gate hard mask layer 90, so that the polysilicon material covers the control gate hard mask layer 90. Then, planarization is performed, for example, by performing a chemical mechanical polishing (CMP) process to expose the upper surface of the control gate hard mask layer 90. Finally, the planarized polysilicon is dry etched to form the erase gate 120.
[0129] In this embodiment, word line gate layers can be formed on the tunneling oxide layer 20 on both sides of the two control gates facing away from each other, that is, on the left side of the first control gate and on the right side of the second control gate, and the word line gate layers are photolithographically and etched to form word line gate 130.
[0130] By using the method including the above steps, one or more memory cells of floating gate flash memory can be formed on substrate 10, thereby obtaining floating gate flash memory.
[0131] This application also provides a flash memory, which includes the semiconductor structure formed in the above embodiments. It should be noted that the method and the structural embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the structural embodiments, which will not be repeated here.
[0132] Accordingly, embodiments of this application also provide an electronic device, which includes the aforementioned flash memory.
[0133] The electronic device described in the embodiments of this application can be any electronic product or device such as a smartphone, desktop computer, tablet computer, laptop computer, digital assistant, augmented reality (AR) / virtual reality (VR) device, smart voice interaction device, smart home appliance, smart wearable device, vehicle terminal device, etc., or any intermediate product including the above-mentioned storage device.
[0134] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0135] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0136] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.
[0137] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A tunneling oxide layer located on the substrate; A first structure located on the tunneling oxide layer; the first structure includes a floating gate located on the tunneling oxide layer; The dielectric layer located on the floating grid; The control gate is located on the dielectric layer; The floating gate includes a first concave-convex structure on the side facing the dielectric layer, and the control gate includes a second concave-convex structure on the side facing the dielectric layer; the first concave-convex structure and the second concave-convex structure are interlocked.
2. The semiconductor structure according to claim 1, characterized in that, The first concave-convex structure includes at least one first convex structure; the second concave-convex structure includes at least one first concave structure. The number of the first convex structure and the number of the first concave structure are the same.
3. The semiconductor structure according to claim 2, characterized in that, The top surface of the first convex structure is higher than the bottom surface of the control gate.
4. The semiconductor structure according to claim 1, characterized in that, The first concave-convex structure includes at least one second concave structure; the second concave-convex structure includes at least one second convex structure. The number of the second concave structure and the second convex structure are the same.
5. The semiconductor structure according to claim 4, characterized in that, The bottom surface of the second convex structure is higher than the top surface of the floating gate.
6. The semiconductor structure according to any one of claims 2-5, characterized in that, The shape of the first concave-convex structure or the second concave-convex structure includes one or more of the following: rectangle, triangle, trapezoid.
7. The semiconductor structure according to any one of claims 1-5, characterized in that, The dielectric layer includes an ONO dielectric layer.
8. The semiconductor structure according to claim 1, characterized in that, The first structure includes two first structures distributed along a first direction; The semiconductor structure also includes an erase gate located between the two first structures.
9. The semiconductor structure according to claim 8, characterized in that, The first structure includes multiple floating gate structures, multiple isolation structures, the dielectric layer, and the control gate; The plurality of floating gate structures are located on the tunneling oxide layer; the lower ends of the plurality of isolation structures are located in the substrate; the plurality of floating gate structures and the plurality of isolation structures are spaced apart in a second direction; The dielectric layer is located on the floating gate structure and the isolation structure; the control gate is located on the dielectric layer.
10. A method for forming a semiconductor structure, characterized in that, The method includes: Provide substrate; A tunneling oxide layer is formed on the substrate; A floating gate is formed on the tunneling oxide layer; A dielectric layer is formed on the floating grid; A control gate is formed on the dielectric layer; wherein the side of the floating gate facing the dielectric layer includes a first concave-convex structure, and the side of the control gate facing the dielectric layer includes a second concave-convex structure; the first concave-convex structure and the second concave-convex structure are interlocked with each other.
11. The method for forming a conductor structure according to claim 10, characterized in that, The process of forming a floating gate on the tunneling oxide layer includes: A floating gate layer is formed on the tunneling oxide layer; The floating gate layer, the tunneling oxide layer, and the substrate are etched to obtain multiple cavities; Multiple isolation structures are obtained by depositing material into the multiple cavities; The floating gate layer between the two isolation structures is etched to obtain a floating gate containing the first concave-convex structure.
12. The method for forming a conductor structure according to claim 11, characterized in that, The floating gate layer includes a first region and a second region side by side; the etching of the floating gate layer to obtain a floating gate containing the first uneven structure includes: The first region is etched to obtain the floating gate; the second region is a convex structure on the side of the floating gate facing the dielectric layer.
13. The method for forming a conductor structure according to claim 11, characterized in that, The floating gate layer includes a first region and a second region side by side; the etching of the floating gate layer to obtain a floating gate containing the first uneven structure includes: The second region is etched to obtain the floating gate; the cavity corresponding to the second region and the first region form a concave structure on the side of the floating gate facing the dielectric layer.
14. A flash memory, characterized in that, The flash memory includes the semiconductor structure as described in any one of claims 1-9.
15. An electronic device, characterized in that, The electronic device includes the flash memory as described in claim 14.