Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention provides a semiconductor structure, a preparation method thereof and electronic equipment, relates to the technical field of semiconductors, and aims to improve the electrical performance and the structural stability of the semiconductor structure. The semiconductor structure comprises a substrate and a first groove penetrating through the surface of the substrate; the metal layer is arranged below the first groove; the conductive structure penetrates through the bottom of the first groove and is connected with the metal layer; the conductive structure includes a pad and a barrier layer covering at least sidewalls and a bottom of the pad. The semiconductor structure is applied to electrical connection.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for fabricating the same, and an electronic device. Background Technology

[0002] In semiconductor integrated circuit structures, spacers serve as channels connecting the semiconductor wafer and external circuitry. Defects in the spacers can lead to unstable electrical connections between the semiconductor wafer and external circuitry. Therefore, only by fabricating qualified spacers can the quality and reliability of the connection between the semiconductor wafer and external circuitry be guaranteed. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and an electronic device thereof, aimed at improving the electrical performance and structural stability of the semiconductor structure.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor structure is provided, comprising: a substrate, a first trench, a metal layer, and a conductive structure. The first trench extends through the surface of the substrate; the metal layer is disposed below the first trench; the conductive structure extends through the bottom of the first trench and is connected to the metal layer; the conductive structure includes a pad and a barrier layer, the barrier layer at least covering the sidewalls and bottom of the pad.

[0006] In the aforementioned semiconductor structure, a first trench penetrates the substrate surface; a metal layer is disposed below the first trench; a conductive structure penetrates the bottom of the first trench and is connected to the metal layer; the conductive structure includes a pad and a barrier layer, the barrier layer at least covering the sidewalls and bottom of the pad, thus the barrier layer can not only effectively prevent the metal in the pad from diffusing from the sidewalls of the pad to the film layer outside the sidewalls, but also prevent the metal in the pad 300 from diffusing into the metal layer. Compared to techniques where the barrier layer is only located between the pad and the metal layer and can only prevent the metal in the pad from diffusing into the metal layer, the above-provided technical solution can significantly improve the blocking effect of the barrier layer, thereby resulting in high electrical performance and structural stability of the semiconductor structure.

[0007] In some embodiments, the size of the pad gradually decreases in a first direction, which is the direction from the top of the first trench to the bottom of the first trench and perpendicular to the thickness of the substrate.

[0008] In some embodiments, the semiconductor structure further includes a passivation layer that fills the space between the sidewall of the conductive structure and the sidewall of the first trench, and covers the top surface of the conductive structure.

[0009] In some embodiments, the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer is located between the sidewall of the conductive structure and the sidewall of the first trench, and the second passivation layer covers the top surface of the conductive structure.

[0010] In some embodiments, the first passivation layer gradually decreases in size in the first direction.

[0011] In some embodiments, the conductive structure includes a main body portion and a connecting portion, the main body portion is located in the first trench, the connecting portion penetrates through the substrate between the bottom of the first trench and the metal layer, and the main body portion is connected to the metal layer through the connecting portion.

[0012] In another aspect, a method for manufacturing a semiconductor structure is provided, including: providing a substrate, a metal layer is formed in the substrate; forming a first trench penetrating through the surface of the substrate, the metal layer is located below the first trench; forming a first passivation layer on the sidewall of the first trench, the inner wall of the first passivation layer forms a second trench with the bottom of the first trench; and forming a conductive structure in the second trench.

[0013] The method for manufacturing a semiconductor structure provided above, compared with the technology of first forming a liner in the first trench, and then forming a passivation layer to fill the first trench, first, since the first trench has a large aspect ratio when the first passivation layer is formed, the first passivation layer can be fully filled between the first trench and the conductive structure, and the formation of a gap can be avoided. Secondly, residues will not be formed on the sidewall of the liner during the formation of the conductive structure, and the liner will not be corroded by the residues. Thirdly, when the liner is formed in the second trench, the liner is formed by lateral etching, so the roughness of the sidewall of the liner will not be increased. In summary, the semiconductor structure formed by the method for manufacturing a semiconductor structure provided above has high electrical performance and structural stability.

[0014] In some embodiments, the forming of the conductive structure in the second trench includes: forming a contact hole, the contact hole exposes the metal layer and penetrates through the second trench; forming an initial barrier layer, the initial barrier layer conformally covers the surface of the second trench and the surface of the contact hole; forming an initial liner layer, the initial liner layer conformally covers the surface of the initial barrier layer; removing part of the initial liner layer and the initial barrier layer along the second trench opening, and the remaining initial liner layer and the remaining initial barrier layer jointly form the conductive structure.

[0015] In some embodiments, after forming the conductive structure, further comprising: forming a second passivation layer, the second passivation layer filling the second trench.

[0016] In another aspect, an electronic device is provided, comprising: the semiconductor structure as described in the above embodiments; and a first conductive connection connecting the pad through the passivation layer in the semiconductor structure.

[0017] The electronic device has the same structure and beneficial technical effects as the semiconductor structure provided in some of the above embodiments, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some of the drawings of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0019] Figure 1 A flowchart of a method for manufacturing a semiconductor structure according to some embodiments;

[0020] Figures 2 to 6 Structure diagrams corresponding to each step in a method for manufacturing a semiconductor structure according to some embodiments;

[0021] Figure 7 A top view of a semiconductor structure in a manufacturing process according to some embodiments;

[0022] Figure 8 A local electron microscope diagram of a semiconductor structure according to some embodiments;

[0023] Figure 9 A local electron microscope diagram of a semiconductor structure according to some embodiments;

[0024] Figure 10 A structure diagram of a semiconductor structure according to some embodiments;

[0025] Figure 11 A flowchart of a method for manufacturing a semiconductor structure according to some embodiments;

[0026] Figures 12 to 19 Structure diagrams corresponding to each step in a method for manufacturing a semiconductor structure according to some embodiments;

[0027] Figure 20This is a structural diagram of an electronic device according to some embodiments;

[0028] Figure 21 for Figure 20 A cross-sectional view of the electronic equipment along the AA direction. Detailed Implementation

[0029] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0030] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0031] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0032] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0033] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0034] The use of “adapted to” or “configured to” herein means open and inclusive language that does not exclude additional devices or steps not explicitly described.

[0035] Additionally, the use of “based on” means open and inclusive, as the process, step, calculation, or other action based on one or more recited conditions or values can in practice be based on additional conditions or values beyond those recited.

[0036] As used herein, “about,” “approximately,” or “around” includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0037] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0038] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, referring to Figure 1 , comprising:

[0039] Step S1 : referring to Figure 2 , providing a substrate 100, a metal layer H is formed in the substrate 100.

[0040] Step S2: continuing to refer to Figure 2 , forming a first trench C1 penetrating the surface of the substrate 100, the metal layer H is located below the first trench C1.

[0041] Here, the process of forming the first trench C1 includes a photolithography process, wherein the photolithography process includes a dry etching process.

[0042] Step S3: continuing to refer to Figure 2 , forming a contact hole K penetrating the first trench C1 at the bottom of the first trench C1, the contact hole K exposes part of the metal layer H.

[0043] Here, the process of forming the contact hole K includes a photolithography process, wherein the photolithography process includes a dry etching process.

[0044] Step S4: referring to Figure 3 , Figure 4 and Figure 5 , forming the barrier layer 200 and the liner 300 in the contact hole K and the first trench C1, the orthographic projection of the contact hole K on the first surface M of the substrate 100 is within the orthographic projection of the liner 300 on the first surface M; the first surface M is the surface of the substrate 100 perpendicular to the thickness direction Y.

[0045] In some embodiments, the barrier layer 200 includes a tantalum nitride barrier layer or a titanium nitride barrier layer. The barrier layer 200 is used to isolate the liner 300 and the metal layer H, so as to prevent the metal in the liner 300 from diffusing.

[0046] In some embodiments, the liner 300 includes an aluminum liner.

[0047] In some embodiments, the step S4 includes: a step S41 of referring to Figure 3 , sequentially forming the barrier film 20 and the liner film 30 in the contact hole K and the first trench C1; a step S42 of referring to Figure 4 and Figure 5 , forming a photoresist pattern T on the liner film 30 in the first trench C1, and etching the barrier film 20 and the liner film 30 on the sidewall of the first trench C1 to form the barrier layer 200 and the liner 300 by taking the photoresist pattern T as a mask; and a step S43 of referring to Figure 5 , removing the photoresist pattern T.

[0048] Here, the process of forming the barrier film 20 and the liner film 30 includes a physical vapor deposition process.

[0049] Step S5: performing a cleaning process on the surface of the liner 300 and the sidewall of the first trench C1.

[0050] Here, the cleaning process includes a wet chemical cleaning. The gas used in the wet chemical cleaning includes chlorine and boron chloride.

[0051] Step S6: referring to Figure 6 , forming a passivation layer 400, the passivation layer 400 is filled between the sidewall of the liner 300 and the sidewall of the first trench C1, and covers the surface of the liner 300 away from the metal layer H.

[0052] Here, the passivation layer 400 is used to protect the liner 300, so as to prevent the liner 300 from being oxidized and corroded.

[0053] Here, the process of forming the passivation layer 400 includes a chemical vapor deposition process.

[0054] Based on the semiconductor structure fabrication method provided in the above embodiments, the inventors discovered that, in the step of forming a photoresist pattern T on the pad film 30 in the first trench C1, a photoresist layer (not shown) needs to be formed on the pad film 30 in the first trench C1. Then, the photoresist layer is sequentially exposed and developed to form the photoresist pattern T. However, because the distance between the photoresist layer above the pad film 20 and the sidewall of the first trench C1 is small, during exposure, light is reflected from the sidewall of the first trench C1 onto the sidewall of the photoresist layer above the pad film 30. This results in increased roughness of the sidewall of the formed photoresist pattern T after development. Figure 7 As shown, when etching the pad film 30 using the photoresist pattern T as a mask, the roughness of the sidewall of the photoresist pattern T will be transferred to the sidewall of the pad 300, resulting in a large roughness of the formed pad 300.

[0055] Secondly, during the etching of the pad film 30, methane or similar gases are used as passivating gases. These gases react with the photoresist pattern T to form a polymer, which adheres to the sidewalls of the pad 300, forming a passivation layer that prevents etching. Furthermore, during the etching process, the photoresist pattern T is consumed, and some of it falls onto the sidewalls of the pad 300. Simultaneously, the passivating gas directly acts on the sidewalls of the pad 300, forming a polymer that adheres to them, effectively protecting the sidewalls of the pad 300 from being "side-cut."

[0056] Secondly, when etching the barrier film 20 and the liner film 30 located on the sidewall of the first trench C1, the etching gas used is generally chlorine and boron chloride. Chlorine-containing byproducts generated during the etching process also adhere to the sidewall of the liner 300. Since the depth of the first trench C1 is 2.6 μm to 3.0 μm, for example, 2.8 μm, and after the liner 300 is formed, the distance L between the sidewall of the liner 300 and the sidewall of the first trench C1 is 1.6 μm to 1.8 μm, for example, 1.7 μm, the aspect ratio of the first trench C1 after the liner 300 is formed is approximately 1.64. That is, after the liner 300 is formed, the aspect ratio of the first trench C1 is relatively large. Therefore, wet chemical cleaning cannot completely remove the chlorine-containing byproducts remaining on the sidewall of the liner 300. Furthermore, since the chlorine-containing byproducts have a certain corrosive effect on the liner 300, they can easily damage the structure of the liner 300 (e.g., Figure 8 (As shown in the dashed box Q in the figure), this will cause irreversible damage to the pad 300, which in turn will lead to the inability to guarantee the reliability of the semiconductor structure.

[0057] Again, when depositing the passivation layer 400, due to the small distance L between the sidewall of the first trench C1 and the sidewall of the liner 300 and the large depth D of the first trench C1 to be filled, the large aspect ratio will cause the passivation layer 400 film to be unable to be uniformly deposited in the first trench C1, forming a seam defect (as shown in the dashed box S in FIG. 4B), which will extend to the surface of the semiconductor structure, making it difficult to meet the pre-shipment appearance inspection requirements of the product, and bringing potential risks of forming "hidden dirt" and existing non-removable residues for subsequent processes. Figure 9

[0058] To solve the above technical problems, embodiments of the present disclosure provide a semiconductor structure 1, referring to Figure 10 , comprising: a substrate 100, a first trench C1, a metal layer H, and a conductive structure G. The first trench C1 penetrates the surface of the substrate 100; the metal layer H is arranged below the first trench C1; the conductive structure G penetrates the bottom of the first trench C1 and is connected with the metal layer H; the conductive structure G comprises a liner 300 and a barrier layer 200, and the barrier layer 200 covers at least the sidewall and the bottom of the liner 300.

[0059] The semiconductor structure 1 provided by the embodiments, the barrier layer 200 covers at least the sidewall and the bottom of the liner 300, so that the barrier layer 200 can not only effectively prevent the metal in the liner 300 from diffusing from the sidewall of the liner 300 to the film layer outside the sidewall, but also can prevent the metal in the liner 300 from diffusing to the metal layer H. Compared with the technology that the barrier layer 200 is only located between the liner 300 and the metal layer H and can only block the diffusion of the metal in the liner 300 to the metal layer H, the above-mentioned technical solution can obviously improve the blocking effect of the barrier layer 200, thereby improving the electrical performance and structural stability of the semiconductor structure.

[0060] In some embodiments, continuing to refer to Figure 10 , the size of the liner 300 in the first direction X gradually decreases from one end of the liner 300 away from the metal layer H to the other end of the liner 300 close to the metal layer H, and the first direction X is a direction Y pointing from the top of the first trench C1 to the bottom of the first trench C1 and perpendicular to the thickness of the substrate 100.

[0061] In some embodiments, continuing to refer to Figure 10 , the semiconductor structure 1 further comprises a passivation layer 400, which is filled between the sidewall of the conductive structure G and the sidewall of the first trench C1 and covers the top surface of the conductive structure G. Since the passivation layer 400 is filled between the sidewall of the conductive structure G and the sidewall of the first trench C1, the stability of the semiconductor structure 1 is improved. The passivation layer 400 covers the top surface of the conductive structure G, which is beneficial to prevent the liner 300 from being oxidized and plays a certain protective role for the liner 300.

[0062] ​In some embodiments, the passivation layer 400 includes a first passivation layer 401 and a second passivation layer 402, the first passivation layer 401 is located between the sidewall of the conductive structure G and the sidewall of the first trench C1, and the second passivation layer 402 covers the top surface of the conductive structure G.

[0063] In some embodiments, the first passivation layer 401 and the second passivation layer 402 are made of the same material, and both include a silicate passivation layer. In other embodiments, the first passivation layer 401 and the second passivation layer 402 can also be made of different materials.

[0064] In some embodiments, the first passivation layer 401 gradually decreases in size in the first direction X.

[0065] In some embodiments, the passivation layer 400 is filled between the sidewall of the conductive structure G and the sidewall of the first trench C1, that is, the barrier layer 200 is located between the sidewall of the liner 300 and the passivation layer 400, so that the barrier layer 200 can avoid the risk of mutual diffusion between the metal (such as aluminum) in the liner and the silicon in the passivation layer 400.

[0066] In some embodiments, continuing to refer to Figure 10 , the conductive structure G includes a main body portion G1 and a connecting portion G2, the main body portion G1 is located in the first trench C1, the connecting portion G2 penetrates between the substrate 100 and the metal layer H through the bottom of the first trench C1, and the main body portion G1 is connected to the metal layer H through the connecting portion G2.

[0067] In some embodiments, the barrier layer 200 is also located between the connecting portion G2 and the metal layer H, and between the connecting portion G2 and the substrate 100. Wherein, the barrier layer 200 located between the connecting portion G2 and the metal layer H can avoid diffusion between the metal in the connecting portion G2 and the metal in the metal layer H; the barrier layer 200 located between the connecting portion G2 and the substrate 100 can avoid diffusion between the metal in the connecting portion G2 and the silicon in the substrate 100, which is beneficial to improve the electrical performance and stability of the structure of the semiconductor structure 1.

[0068] Embodiments of the present disclosure also provide a preparation method of a semiconductor structure, referring to Figure 11 , comprising:

[0069] Step S1: referring to Figure 12 , providing a substrate 100, and a metal layer H is formed in the substrate 100.

[0070] Step S2: forming a first trench C1 penetrating the surface of the substrate 100, and the metal layer H is located below the first trench C1.

[0071] Here, the size of the first trench C1 in the first direction X gradually decreases from the opening end of the first trench C1 to the bottom of the first trench C1, the first direction X being a direction in which the top of the first trench C1 points to the bottom of the first trench C1 and is perpendicular to the thickness direction Y of the substrate 100. In this way, the side wall of the first trench C1 has an inclination angle, which is beneficial to the subsequent formation of the first passivation layer film 4010 to fully fill the first trench C1, so as to avoid the formation of a gap between the first passivation layer film 4010 formed in the first trench C1 and the side wall of the first trench C1, and improve the stability of the finally formed semiconductor structure 1.

[0072] In some embodiments, the process of forming the first trench C1 includes a photolithography process. The photolithography process includes dry etching.

[0073] For example, the dry etching process uses chlorine, carbon tetrafluoride or hydrogen bromide.

[0074] In some embodiments, the width W of the first trench C1 is 36 μm to 42 μm, and the depth D of the first trench C1 is 2.6 μm to 3 μm. That is, the aspect ratio of the first trench is 0.04 to 0.07, so that the aspect ratio of the first trench is much smaller than the critical value 0.5 of the gap filling capability of the chemical vapor deposition process, which is beneficial to the subsequent formation of the first passivation layer film without seam defects.

[0075] For example, the width W of the first trench is 40 μm, and the depth D of the first trench is 2.8 μm, so that the aspect ratio of the first trench C1 is 0.06, and the first passivation layer film 4010 without seam defects can be formed.

[0076] Step S3: in combination with reference Figure 13 and Figure 14 The first passivation layer 401 is formed on the side wall of the first trench C1, and the inner wall of the first passivation layer 401 forms a second trench C2 with the bottom of the first trench C1.

[0077] The step S3 includes:

[0078] Step S31: in combination with reference Figure 13 The first passivation layer film 4010 filling the first trench C1 is formed.

[0079] Here, the process of forming the first passivation layer film 4010 includes a plasma enhanced chemical vapor deposition process. In this process, ethyl silicate is used to react with oxygen to form an ethyl silicate passivation layer, and the deposition thickness of the first passivation layer film 4010 can be 2.6 μm to 3 μm, for example, 2.8 μm.

[0080] It can be understood that the deposition thickness of the first passivation layer film 4010 is parallel to the direction of the depth D of the first trench C1. It can be understood that the deposition thickness of the first passivation layer film 4010 is parallel to the direction of the depth D of the first trench C1.

[0081] Step S32: performing a planarization process on the first passivation layer film 4010.

[0082] The planarization process includes a chemical mechanical polishing process.

[0083] The purpose of the planarization process is to remove the excess first passivation layer film 4010 on the surface of the substrate 100, so as to make the surface of the substrate 100 more planar, which is conducive to forming a mask pattern used for etching the first passivation layer film 4010 later.

[0084] Step S33: referring to Figure 14 , etching the first passivation layer film 4010 to form a first passivation layer 401.

[0085] In this step, a mask pattern can be formed on the surface of the first passivation layer film 4010, and then the first passivation layer film 4010 is etched to form the first passivation layer 401 using the mask pattern as a mask. The inner wall of the first passivation layer 401 forms a second trench C2 with the bottom of the first trench C1. The opening end of the second trench C2 to the bottom of the second trench C2, the size of the second trench C2 in the first direction X gradually decreases, the first direction X is the direction of the top of the first trench C1 to the bottom of the first trench C1 and perpendicular to the thickness direction Y of the substrate 100, that is, the side wall of the second trench C2 has an inclination angle.

[0086] In some embodiments, the process of etching the first passivation layer film 4010 includes a photolithography process.

[0087] The photolithography process includes dry etching. The gas used in the dry etching includes fluorocarbon or hydrogen-containing fluorocarbon.

[0088] Referring to Figure 14 , the thickness h of the first passivation layer 401 can be 1.6 μm to 3 μm, for example, 1.7 μm. In combination with the reference Figure 12 , the thickness h of the first passivation layer 401 is parallel to the direction of the width W of the first trench C1.

[0089] In the case where the width W of the first trench is 40 μm, the width of the bottom of the second trench C2 formed can be 36 μm.

[0090] Step S4: forming a conductive structure G in the second trench C2.

[0091] The step S4 includes:

[0092] Step S41: referring to Figure 15 , forming a contact hole K, the contact hole K exposes the metal layer H and penetrates the second trench C2.

[0093] Here, the process of forming the contact hole K includes a photolithography process.

[0094] The photolithography process includes dry etching. The gas used in the dry etching includes fluorocarbon.

[0095] Step S42: Referring to Figure 16 , an initial barrier layer 201 is formed, which conformally covers the surface of the second trench C2 and the contact hole K.

[0096] Here, the process of forming the initial barrier layer 201 includes a physical vapor deposition process. In some embodiments, the barrier layer 200 includes a titanium nitride barrier layer. The benefit of using a titanium nitride barrier layer is that the etching process of the titanium nitride barrier layer is relatively more mature, and it is also convenient to control the etching morphology subsequently.

[0097] Step S43: Referring to Figure 16 , an initial liner layer 301 is formed, which conformally covers the surface of the initial barrier layer 201.

[0098] Here, the process of forming the initial liner layer 301 includes a physical vapor deposition process.

[0099] Step S44: Referring to Figure 17 and Figure 18 , part of the initial liner layer 301 and the initial barrier layer 201 are removed along the second trench C2 opening, and the remaining initial liner layer and the remaining initial barrier layer together form a conductive structure G.

[0100] Here, the step of removing part of the initial liner layer 301 and the initial barrier layer 201 along the second trench opening C2 includes, referring to Figure 17 , a photoresist pattern T is formed around the second trench C2 opening, and part of the initial liner layer 301 and the initial barrier layer 201 are etched as a mask of the photoresist pattern T.

[0101] In some embodiments, the depth of removing part of the initial liner layer 301 along the second trench C2 opening can be 1.6 μm, and the depth of the liner 300 formed by the remaining initial liner layer 301 is 1.2 μm.

[0102] In some embodiments, the process of removing part of the initial liner layer 301 along the second trench C2 opening includes a photolithography process. The photolithography process includes dry etching. The gas used in the dry etching includes boron chloride, chlorine gas and argon gas.

[0103] In one aspect, since the removing part of the initial pad layer 301 along the opening of the second trench C2 is a lateral etching, compared with the technology of etching the pad film 30 with the photoresist pattern T as a mask, the embodiment can avoid increasing the roughness of the sidewall of the pad 300. In addition, during the etching process, part of the passivation layer located at the side of the initial pad layer 301 can also be etched, so that the chlorine-containing by-products formed on the sidewall of the pad 300 can be reduced, thereby avoiding the corrosion of the pad 300 by the chlorine-containing by-products, and further avoiding the structure of the pad 300 from being damaged.

[0104] On the other hand, since the volatility of aluminum chloride generated by the reaction of chlorine and aluminum in the etching gas is better than that of titanium chloride generated by the reaction of chlorine and titanium nitride, the etching rate of the blocking layer by chlorine is slightly smaller than that of the pad by chlorine, but the boron chloride and argon can be ionized to generate ions to provide physical bombardment during the etching process, thereby enhancing the etching rate of titanium nitride. Therefore, the etching rate of titanium nitride can be increased by adjusting the ratio of chlorine and boron chloride and increasing the bias power. Since the sidewall of the second trench C2 has an inclination, the etching reaction surface of titanium nitride from top to bottom is increased, thereby increasing the etching rate of titanium nitride, so that the height of the remaining titanium nitride is the same as that of the pad. After the etching of the initial pad layer 301 is completed, if the chloride remains for too long, it will react with water in the air and seriously erode the pad 300. Since chlorine and chlorine-containing by-products are mainly adsorbed in the photoresist pattern T, the photoresist pattern T needs to be removed immediately after the pad 300 is formed.

[0105] Here, before removing part of the initial pad layer 301 and the initial blocking layer 201 along the opening of the second trench C2, the initial pad layer 301 is further subjected to a planarization treatment.

[0106] The planarization treatment process includes a chemical mechanical polishing process.

[0107] The purpose of the planarization treatment is to remove the excess initial pad layer 301 on the surface of the substrate 100, so that the surface of the substrate 100 is more planar, which is beneficial to the formation of the subsequent mask pattern T used to remove part of the initial pad layer 301 close to the opening end of the second trench C2.

[0108] In one embodiment, the process of removing part of the initial pad layer 301 and the initial blocking layer 201 along the opening of the second trench C2 includes a photolithography process, wherein the photolithography process includes a dry etching process.

[0109] Step S5: Referring to Figure 19 , a second passivation layer 402 is formed, and the second passivation layer 402 fills the second trench C2; the first passivation layer 401 and the second passivation layer 402 form a passivation layer 400.

[0110] The process of forming the second passivation layer 402 includes a chemical vapor deposition process. After removing part of the initial liner layer 301 and the initial barrier layer 201 along the opening of the second trench C2, the aspect ratio of the second trench C2 can be in the range of 0.03-0.05. For example, the depth D of the second trench C2 can be 1.6 μm, and the minimum width W of the second trench C2 is greater than the maximum width 36 μm of the liner 300. In this case, the aspect ratio of the second trench C2 is 0.04, which is much less than the critical value 0.5 of the gap filling capability of the chemical vapor deposition method. Therefore, the second passivation layer 402 can sufficiently fill the second trench C2, and thus the second passivation layer 402 without seam defects can be formed.

[0111] In one embodiment, before forming the second passivation layer 402, the process further includes: performing a cleaning process on the surface of the second trench C2 and the liner 300.

[0112] Here, the time interval between removing part of the initial liner layer 301 and the initial barrier layer 201 along the opening of the second trench C2 and performing the cleaning process on the surface of the second trench C2 and the liner 300 is less than 2 hours, so that the residues can not further react with the liner 300 to erode the liner 300.

[0113] In one embodiment, the cleaning process includes a wet chemical cleaning.

[0114] The solution used in the cleaning process includes a dilute sulfuric peroxide mixture solution (DSP solution for short).

[0115] The purpose of the cleaning process is to remove the residues on the surface of the second trench C2 and the liner 300. Since the residues are mainly aluminum oxide and polymers (including chlorine and chlorine-containing by-products, etc.) gathered together, the hydrogen peroxide in the DSP solution can react with a small amount of aluminum on the surface of the liner to form aluminum oxide, and the aluminum oxide can react with sulfuric acid in the DSP solution to form aluminum sulfate and dissolve in water. Therefore, the residues gathered together will not adhere to the surface of the second trench C2 and the liner, and then water washing can remove the residues. Moreover, since the depth of the second trench at this time is 1.6 μm, and the width of the second trench C2 is greater than 27 μm, that is, the aspect ratio of the second trench C2 is small, the residues in the second trench C2 will fully react with the DSP solution and there will be no residues.

[0116] The preparation method of the semiconductor structure provided in the embodiment is compared with the technology of first forming the liner 300 in the first trench C1 and then forming the passivation layer 400 filling the first trench C1. In the preparation method of the semiconductor structure provided in the embodiment, firstly, when the first passivation layer 401 is formed, the first trench C1 has a large aspect ratio, so that the first passivation layer 401 formed can be fully filled between the first trench C1 and the liner 300, and the formation of a gap can be avoided. Secondly, no residue is formed on the sidewall of the liner 300 in the process of forming the liner 300, and the liner 300 is prevented from being corroded by the residue. Thirdly, when the liner 300 is formed in the second trench C2, the liner 300 is formed by using a horizontal etching method, so that the roughness of the sidewall of the liner 300 is not increased. In summary, the semiconductor structure formed by the preparation method of the semiconductor structure provided in the embodiment has high electrical performance and structural stability.

[0117] The embodiment of the present disclosure further provides an electronic device W, which is combined with reference Figure 20 and Figure 21 , and includes the semiconductor structure Q and the first conductive connecting piece J1.

[0118] The semiconductor structure Q includes the semiconductor structure provided in the above-mentioned embodiments.

[0119] With reference to Figure 21 , the first conductive connecting piece J1 is connected with the liner 300 through the passivation layer 400 in the semiconductor structure Q. An external electrical signal can be transmitted to the semiconductor structure Q through the first conductive connecting piece J1.

[0120] In some embodiments, the first conductive connecting piece J1 includes a gold wire.

[0121] With reference to Figure 20 , the electronic device W further includes a packaging layer R, which covers the semiconductor structure Q and protects the semiconductor structure Q.

[0122] In some embodiments, with reference to Figure 20 , the electronic device W further includes a second conductive connecting piece J2, which is connected with the first conductive connecting piece J1 and extends to the outside of the packaging layer R.

[0123] In some embodiments, the second conductive connecting piece J2 includes a pin.

[0124] The electronic device W provided by the above embodiment can be applied in a complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS for short) structure, and the reliability of the CIS structure can be improved.

[0125] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, and a first trench penetrating the surface of the substrate; A metal layer is disposed below the first trench; A conductive structure extends through the bottom of the first trench and is connected to the metal layer; The conductive structure includes a pad and a barrier layer, the barrier layer covering at least the sidewalls and bottom of the pad.

2. The semiconductor structure according to claim 1, characterized in that, The size of the pad gradually decreases in a first direction, which is the direction from the top of the first trench to the bottom of the first trench and perpendicular to the thickness of the substrate.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes a passivation layer, which fills the space between the sidewall of the conductive structure and the sidewall of the first trench, and covers the top surface of the conductive structure.

4. The semiconductor structure according to claim 3, characterized in that, The passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer is located between the sidewall of the conductive structure and the sidewall of the first trench, and the second passivation layer covers the top surface of the conductive structure.

5. The semiconductor structure according to claim 4, characterized in that, The size of the first passivation layer gradually decreases in the first direction.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The conductive structure includes a main body and a connecting part. The main body is located in the first trench, and the connecting part penetrates the bottom of the first trench and the substrate between the metal layer. The main body is connected to the metal layer through the connecting part.

7. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a metal layer is formed therein; A first trench is formed that penetrates the surface of the substrate, and the metal layer is located below the first trench; A first passivation layer is formed on the sidewall of the first trench, and the inner wall of the first passivation layer and the bottom of the first trench form a second trench. A conductive structure is formed in the second trench.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The formation of a conductive structure in the second trench includes: A contact hole is formed, which exposes the metal layer and communicates with the second trench; An initial barrier layer is formed, which conformally covers the surfaces of the second trench and the contact hole; An initial pad layer is formed, which conformally covers the surface of the initial barrier layer; a portion of the initial pad layer and the initial barrier layer are removed along the opening of the second trench, and the remaining initial pad layer and the remaining initial barrier layer together form the conductive structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After forming the conductive structure, the method further includes: forming a second passivation layer, wherein the second passivation layer fills the second trench.

10. An electronic device, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 6; A first conductive connector is connected to the pad through the passivation layer in the semiconductor structure.

Images