Deposition mask, method for manufacturing the same, and electronic device

Abstract

A deposition mask, a method for manufacturing the same, and an electronic device are provided. The deposition mask includes: a mask substrate including a semiconductor wafer; a first coating film on the mask substrate; and a second coating film on the first coating film and including a hole pattern and a mask pattern alternately arranged, in which an upper width of the hole pattern is smaller than a lower width of the hole pattern.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0091240, filed on July 10, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a deposition mask and a method for manufacturing the deposition mask. Background Technology

[0003] With the advancement of the information society, increasingly higher demands are being placed on display devices used to display images in various ways. Display devices can be liquid crystal displays, field emission displays, and / or light-emitting displays. Light-emitting displays can include organic light-emitting display devices or inorganic light-emitting display devices. Organic light-emitting display devices include organic light-emitting diodes (OLEDs) as light-emitting elements, while inorganic light-emitting display devices include inorganic light-emitting diodes as light-emitting elements.

[0004] Recently, there has been an increasing demand for display devices that provide high-resolution images, such as images with a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, organic light-emitting diodes on silicon (OLEDoS) are used, which can be applied to small organic light-emitting display devices with high resolution. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are disposed on a semiconductor wafer substrate including complementary metal-oxide-semiconductor (CMOS).

[0005] To fabricate self-emissive displays such as organic light-emitting displays, deposition methods are primarily used as techniques for depositing organic material for each pixel. In these techniques, a thin-film mask is firmly attached to a substrate to deposit the organic material at the desired location. When depositing organic material in large-area organic light-emitting displays, fine metal masks (FMMs) are widely used as thin-film metal masks. However, such metal masks are not suitable for high-resolution patterning.

[0006] In this regard, fine silicon masks (FSMs) made using semiconductor substrates such as wafers are gaining attention in order to manufacture high-resolution precision thin-film masks. Summary of the Invention

[0007] Aspects and features of embodiments of this disclosure provide a deposition mask for manufacturing a high-resolution display device and a method for manufacturing the deposition mask.

[0008] The embodiments and features of this disclosure also provide a deposition mask capable of improving the efficiency of a deposition process and a method for manufacturing the deposition mask.

[0009] Aspects and features of embodiments of this disclosure also provide a deposition mask capable of reducing or minimizing defective deposition areas and a method for manufacturing the deposition mask.

[0010] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0011] According to one or more embodiments of the present disclosure, a deposition mask is provided, the deposition mask comprising: a mask substrate including a semiconductor wafer; a first coating film on the mask substrate; and a second coating film on the first coating film, and including alternately arranged hole patterns and mask patterns, wherein the upper width of the hole pattern is smaller than the lower width of the hole pattern.

[0012] In one or more embodiments, the first coating film comprises silicon oxide.

[0013] In one or more embodiments, the second coating film comprises silicon nitride.

[0014] In one or more embodiments, the second coating film comprises a low-stress nitride.

[0015] In one or more embodiments, the deposition mask may further include a mask opening penetrating at least a portion of the mask substrate and at least a portion of the first coating film, wherein the mask opening is in communication with the aperture pattern.

[0016] In one or more embodiments, the mask substrate includes a first surface and a second surface positioned opposite to the first surface, the first coating film includes a first upper coating film on the first surface and a first lower coating film on the second surface, the second coating film includes a second upper coating film on the first surface and a second lower coating film on the second surface, and the mask opening penetrates the second lower coating film, the first lower coating film, the mask substrate, and the first upper coating film.

[0017] In one or more embodiments, the mask pattern includes a first portion and a second portion on the first portion, and the upper width of the first portion is greater than the lower width of the first portion.

[0018] In one or more embodiments, the first angle between the bottom surface and the side surface of the first portion is different from the second angle between the bottom surface and the side surface of the second portion.

[0019] In one or more embodiments, the first angle is greater than the second angle.

[0020] In one or more embodiments, the angle between the bottom surface and the side surface of the first portion is an obtuse angle.

[0021] In one or more embodiments, the side surface of the first portion is an inclined surface that slopes inward in the first portion as it extends from the top surface to the bottom surface of the first portion.

[0022] In one or more embodiments, the upper width of the second portion is greater than or equal to the lower width of the second portion.

[0023] In one or more embodiments, the angle between the bottom surface and the side surface of the second part is a right angle or an obtuse angle.

[0024] In one or more embodiments, the side surface of the second portion is an inclined surface that slopes inward in a direction from the top surface to the bottom surface of the second portion.

[0025] In one or more embodiments, the first portion includes a first sub-portion and a second sub-portion on the first sub-portion, and a third angle between the bottom surface and the side surface of the first sub-portion is different from a fourth angle between the bottom surface and the side surface of the second sub-portion.

[0026] In one or more embodiments, the deposition mask may further include alignment marks on the mask substrate, wherein the alignment marks are between the mask substrate and the first coating film or between the first coating film and the second coating film.

[0027] In one or more embodiments, the deposition mask may further include a third coating film on the second coating film, wherein the third coating film comprises silicon oxide.

[0028] According to one or more embodiments of the present disclosure, a method for manufacturing a deposition mask is provided, the method comprising the steps of: forming a first coating film on a mask substrate made of a semiconductor wafer; forming a second coating film on the first coating film; forming a mask pattern and a hole pattern in the second coating film; and forming a mask opening penetrating the mask substrate and the first coating film, wherein the step of forming the mask pattern and the hole pattern in the second coating film comprises: partially etching the second coating film to form a first trench; forming a passivation film on a side surface of the first trench; and primarily etching the remaining second coating film below the first trench to form the hole pattern and the mask pattern.

[0029] In one or more embodiments, the second coating film comprises a low-stress nitride, and the second coating film is formed by a low-pressure chemical vapor deposition (LPCVD) process.

[0030] In one or more embodiments, the passivation film comprises a fluorocarbon polymer.

[0031] In this embodiment, both the local etching and the main etching of the second coating film are performed by dry etching, and plasma is generated using an inductively coupled plasma method.

[0032] In one or more embodiments, the pressure inside the cavity during local etching is lower than the pressure inside the cavity during main etching.

[0033] In one or more embodiments, the source power in the local etch is lower than the source power in the main etch.

[0034] In one or more embodiments, the bias power in the local etch is greater than the bias power in the main etch.

[0035] According to one or more embodiments of the present disclosure, an electronic device is provided, the electronic device comprising: a processor for providing input image data; and a display device for displaying an image based on the input image data, wherein the display device is manufactured using the deposition mask described above.

[0036] According to one or more embodiments of the present disclosure, a deposition mask and a method for manufacturing the deposition mask can be used to manufacture a high-resolution display device.

[0037] The deposition mask and the method for manufacturing the deposition mask according to one or more embodiments of the present disclosure can improve the efficiency of the deposition process.

[0038] According to one or more embodiments of the present disclosure, the deposition mask and the method for manufacturing the deposition mask can reduce or minimize defective deposition areas.

[0039] However, the effects of the embodiments according to this disclosure are not limited to those illustrated above, and various other effects are incorporated herein. Attached Figure Description

[0040] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments; Figure 2 This is a block diagram illustrating a display device according to one or more embodiments; Figure 3 It is an equivalent circuit diagram of the first sub-pixel according to one or more embodiments; Figure 4 This is a plan view showing an example of a display panel according to one or more embodiments; Figure 5 and Figure 6 It is shown Figure 4 A plan view of an embodiment of the display area; Figure 7 It shows along Figure 5A cross-sectional view of an example display panel, taken by line X1-X1'; Figure 8 This is a cross-sectional view illustrating another example of a display panel included in a display device according to one or more embodiments; Figure 9 This is an exploded perspective view showing a head-mounted display according to one or more embodiments; Figure 10 This is a perspective view illustrating an augmented reality content providing device according to one or more embodiments; Figure 11 yes Figure 10 The augmented reality content provides an exploded perspective view of the back of the device; Figure 12 yes Figure 10 An exploded perspective view of the front of the augmented reality content delivery device; Figure 13 This is a plan view showing a parent semiconductor substrate including a display unit according to one or more embodiments; Figure 14 This is a plan view showing a deposition mask according to one or more embodiments; Figure 15 It is along Figure 14 A sectional view taken by line X2-X2'; Figure 16 yes Figure 15 A magnified view of region A; Figure 17 This is a cross-sectional view illustrating a process for manufacturing a display device using a deposition mask according to one or more embodiments; Figure 18 This is a schematic diagram showing the emission area and shadow area formed when manufacturing a display device using a deposition mask according to a comparative example; Figure 19 This is a schematic diagram illustrating the emission region formed when a display device is manufactured using a deposition mask according to one or more embodiments; Figure 20 This is a plan view showing a deposition mask according to one or more embodiments; Figure 21 This is a cross-sectional view showing a deposition mask according to one or more embodiments; Figure 22 This is a flowchart illustrating a method for manufacturing a deposition mask according to one or more embodiments; Figure 23 It is shown Figure 22 A sectional view of step S100; Figure 24 It is shown Figure 22 A sectional view of step S200; Figure 25 It is shown Figure 22 A sectional view of step S300; Figure 26 It is shown Figure 22 A sectional view of step S400; Figure 27 It is shown Figure 22 A sectional view of step S500; Figure 28 It is shown Figure 22 A sectional view of step S600; Figure 29 It is shown Figure 22 A flowchart detailing the sub-steps of step S500; Figure 30 It is shown Figure 29 A sectional view of step S510; Figure 31 It is shown Figure 29 A sectional view of step S520; and Figure 32 and Figure 33 It is shown Figure 29 The sectional view of step S530. Detailed Implementation

[0041] This disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. However, this disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0042] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on said other layer or substrate, or an intervening layer may also be present. Throughout the specification, the same reference numerals indicate the same components.

[0043] Furthermore, the phrase "in a plan view" refers to the view of an object portion from above, and the phrase "in a schematic sectional view" refers to the view of a schematic section taken by vertically cutting through an object portion from the side. The term "overlay" or variations thereof means that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlay" can include stacking, overlapping, facing or oriented, extending over, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlay" can include meanings such as "spaced apart from," "beside," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is placed between the first and second objects, the first and second objects, although still facing each other, can be understood as being indirectly opposite each other.

[0044] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” or “upper” may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are intended to cover different orientations of the device during use or operation. For example, in the case where the device shown in the drawings is flipped, the device located “below” or “under” another device may be placed “above” said other device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore spatial relative terms can be interpreted differently depending on the orientation.

[0045] When an element is referred to as being "connected" or "joined" to another element, the element may be "directly connected" or "directly joined" to said other element, or "electrically connected" or "electrically joined" to said other element, with one or more intermediary elements disposed therebetween. It will also be understood that when the terms "comprising," "having," "including," and / or variations thereof are used, they may specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0046] It will be understood that although the terms “first,” “second,” or “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or for convenience in describing and explaining it. For example, when a “first element” is discussed in the specification, it may be referred to as a “second element” or a “third element,” and “second element” and “third element” may be named in a similar manner without departing from the teaching herein.

[0047] As used herein, the terms “about” or “approximately” include the stated value and refer to an acceptable deviation of a particular value as determined by a person of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0048] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunction or disjunctive sense and can be understood to be equivalent to "and / or". In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one of the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0049] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless clearly defined in the specification, terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an ideal or overly formal sense.

[0050] It will be understood by those skilled in the art that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0051] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Figure 1This is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments.

[0053] Reference Figure 1 and Figure 2 The display device 10 according to one or more embodiments can be a device for displaying moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices, such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs). For example, the display device 10 according to one or more embodiments can be applied as a display unit in a television, laptop computer, monitor, billboard, and / or Internet of Things (IoT) terminal. Optionally, the display device 10 according to one or more embodiments can be applied to smartwatches, smartwatch phones, and / or head-mounted displays (HMDs) for realizing virtual reality and augmented reality.

[0054] The display device 10 according to one or more embodiments may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (e.g., a timing controller) 400, and a power supply circuit (e.g., a power supply unit) 500.

[0055] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side with a first direction DR1 and a long side with a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side on the first direction DR1 and the long side on the second direction DR2 intersect may be a right angle or rounded with a suitable curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, but may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0056] In the figures shown, the first direction DR1 and the second direction DR2 intersect each other as horizontal directions. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. Additionally, the third direction DR3 intersects the first direction DR1 and the second direction DR2, and may be, for example, a vertical direction orthogonal to the first direction DR1 and the second direction DR2. Unless otherwise defined, in this specification, the direction indicated by the arrows of the first direction DR1, the second direction DR2, and the third direction DR3 may be referred to as one side, and the opposite direction may be referred to as the other side. Furthermore, as used herein, the terms "above," "upper side," "upper part," "top," and "top surface" refer to the direction indicated by the arrow in the third direction DR3 in the figures, based on the accompanying drawings, and the terms "below," "lower side," "lower part," "bottom," and "bottom surface" refer to the direction opposite to the direction indicated by the arrow in the third direction DR3, based on the accompanying drawings.

[0057] like Figure 2 As shown, the display panel 100 may include a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0058] The display area (DAA) can include multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0059] Multiple pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, multiple pixels PX can be arranged along rows and columns of a matrix along the first direction DR1 and the second direction DR2. Multiple scan lines SL and multiple emission control lines EL can extend along the first direction DR1 and be arranged along the second direction DR2. Multiple data lines DL can extend along the second direction DR2 and be arranged along the first direction DR1.

[0060] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL can include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0061] Multiple pixels PX may include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 may include, as described later... Figure 3 The multiple pixel transistors shown can be formed and disposed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 7 For example, multiple pixel transistors can be formed using complementary metal-oxide-semiconductor (CMOS).

[0062] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to one of the multiple write scan lines GWL, one of the multiple control scan lines GCL, one of the multiple bias scan lines GBL, one of the multiple first emission control lines EL1, one of the multiple second emission control lines EL2, and one of the multiple data lines DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0063] The non-display area NDA may include a scan driver 610, a transmit driver 620, and a data driver 700.

[0064] The scan driver 610 may include multiple scan transistors, and the emitter driver 620 may include multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed using semiconductor processes and are disposed on a semiconductor substrate SSUB (see [link to semiconductor data]). Figure 7 On ), for example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS. Although in Figure 2 The diagram shows a scan driver 610 positioned on the left side of the display area DAA and a transmit driver 620 positioned on the right side of the display area DAA, but this disclosure is not limited thereto. For example, the scan driver 610 and the transmit driver 620 may be positioned on both the left and right sides of the display area DAA.

[0065] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0066] The transmit driver 620 may include a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 may receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 may generate a first transmit control signal based on the transmit timing control signal ECS and output them sequentially to a first transmit control line EL1. The second transmit control driver 622 may generate a second transmit control signal based on the transmit timing control signal ECS and output them sequentially to a second transmit control line EL2.

[0067] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed by semiconductor processes and disposed on a semiconductor substrate SSUB (see Figure 7 For example, multiple data transistors can be formed using CMOS.

[0068] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 can convert the digital video data DATA into an analog data voltage according to the data timing control signal DCS and output the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0069] The heat dissipation layer 200 can be stacked on the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 can be used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite with high thermal conductivity and metal layers such as silver (Ag), copper (Cu) and / or aluminum (Al).

[0070] Circuit board 300 can be electrically connected to the first pad (or "soldering pad") portion of display panel 100 PDA1 (see [link to circuit board 300]) using a conductive adhesive component such as an anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board (FPCB) with flexible material or flexible film. Although circuit board 300 is in Figure 1The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 can be a first pad portion PDA1 of the circuit board 300 connected to the display panel 100 using conductive adhesive members (see...). Figure 4 Multiple first pads PD1 (see) Figure 4 The opposite end of the other end of the ).

[0071] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0072] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0073] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0074] Optionally, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed by semiconductor processes and are disposed on a semiconductor substrate SSUB (see...). Figure 7 On the data driver 700. For example, multiple timing transistors and multiple power transistors can be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be arranged in the data driver 700 and the first pad PDA1 (see...). Figure 4 )between.

[0075] Figure 3 It is an equivalent circuit diagram of the first sub-pixel according to one or more embodiments.

[0076] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first driving voltage line VSL with a first driving voltage VSS corresponding to a low potential voltage, a second driving voltage line VDL with a second driving voltage VDD corresponding to a high potential voltage, and a third driving voltage line VIL with a third driving voltage VINT corresponding to an initialization voltage. That is, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In this case, the first driving voltage VSS can be lower than the third driving voltage VINT, and the second driving voltage VDD can be higher than the third driving voltage VINT.

[0077] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0078] The light-emitting element LE can emit light in response to a drive current (source-drain current) flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, and the light-emitting element LE can be, for example, a micro light-emitting diode.

[0079] The first transistor T1 may be a drive transistor that controls the drive current flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 may include a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0080] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0081] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 can be turned on by a control scan signal controlling the scan line GCL to connect the first node N1 to the second node N2. For this purpose, because the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 can be diode-connected). The third transistor T3 may include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0082] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 can be turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0083] A fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 can be turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0084] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 can be turned on by a second emitter control signal on the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0085] A first capacitor CP1 may be disposed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0086] The second capacitor CP2 can be disposed between the gate electrode (or the first node N1) of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 may include one electrode connected to the gate electrode (or the first node N1) of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0087] The first node N1 can be the connection point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 can be the connection point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 can be the connection point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0088] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. Optionally, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0089] Despite Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2, but the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 can be changed in various ways.

[0090] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be repeated in this disclosure.

[0091] Figure 4 This is a plan view showing an example of a display panel according to one or more embodiments.

[0092] Reference Figure 4 The display area DAA of the display panel 100 according to one or more embodiments may include a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments may include a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad PDA1, and a second pad PDA2.

[0093] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on the other side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on one side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be disposed on the left side of the display area DAA, and the transmit driver 620 can be disposed on the right side of the display area DAA. However, this disclosure is not limited thereto, and the scan driver 610 and the transmit driver 620 can be disposed on both the first and second sides of the display area DAA.

[0094] The first pad portion PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 by a conductive adhesive member. The first pad portion PDA1 may be disposed on the third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on the other side of the display area DAA in the second direction DR2. That is, the first pad portion PDA1 may be disposed on the underside of the display area DAA.

[0095] The first pad PDA1 can be disposed on the outside of the data driver 700 on the second direction DR2. That is, the first pad PDA1 can be disposed closer to the edge of the display panel 100 than the data driver 700.

[0096] The second pad PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. During the inspection process, the multiple second pads PD2 may be connected to a fixture or probe pins, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board (PCB) made of a rigid material or a flexible printed circuit board (FPCB) made of a flexible material.

[0097] The first distribution circuit 710 can distribute the data voltage applied through the first pad PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad PDA1 to P (P is a positive integer of 2 or greater) data lines DL, thus reducing the number of first pads PD1. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on the other side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0098] The second distribution circuit 720 can distribute the signal applied through the second pad PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on one side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0099] Figure 5 and Figure 6 It is shown Figure 4 A plan view of an embodiment of the display area.

[0100] Reference Figure 5 and Figure 6 Each of the pixels PX may include a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0101] In one or more embodiments, such as Figure 5 and Figure 6As shown, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a hexagonal shape formed by six straight lines in the plan view, but this disclosure is not limited thereto. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal shapes, circular shapes, elliptical shapes, or atypical shapes other than hexagons in the plan view.

[0102] In one or more embodiments, such as Figure 5 As shown, the maximum length of the third transmission region EA3 in the first direction DR1 can be less than the maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1. The maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1 can be substantially the same.

[0103] In one or more embodiments, such as Figure 5 As shown, the maximum length of the third transmission region EA3 in the second direction DR2 can be greater than the maximum length of the first transmission region EA1 in the second direction DR2 and the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2.

[0104] In one or more embodiments, such as Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the second direction DR2. The first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1. The second emission region EA2 and the third emission region EA3 can be adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be different.

[0105] In one or more embodiments, such as Figure 6 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1, but the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first diagonal direction DD1, and the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the second diagonal direction DD2.

[0106] In the accompanying drawings, the first oblique direction DD1 intersects each of the first direction DR1 and the second direction DR2, which are horizontal directions. For example, the first oblique direction DD1 may be a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, but this disclosure is not limited thereto. The second oblique direction DD2 intersects each of the first direction DR1 and the second direction DR2, which are horizontal directions. For example, the second oblique direction DD2 may be a direction inclined at 45 degrees relative to the opposite direction of the first direction DR1 and the second direction DR2, but this disclosure is not limited thereto. The second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0107] The first emission region EA1 can emit light of the first color, the second emission region EA2 can emit light of the second color, and the third emission region EA3 can emit light of the third color. Here, the first color of light can be light in the red band, the second color of light can be light in the green band, and the third color of light can be light in the blue band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370 nm to 460 nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to 560 nm, and the red band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to 750 nm.

[0108] exist Figure 5 and Figure 6 The illustration shows that each of a plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but this disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four or more emission regions.

[0109] Furthermore, the shape and arrangement of the emission regions of multiple pixel PXs are not limited to Figure 5 and Figure 6 The shapes and arrangements shown are illustrated. For example, the emission regions of multiple pixels PX can be configured as a strip structure in which the emission regions are arranged along a first direction DR1, or as a pentile in which the emission regions are arranged in a diamond shape. ® Structure. Pentile ® The pixel arrangement structure can be called an RGBG matrix structure (e.g., PENTILE). ® Matrix structure or RGBG structure (e.g., Pentium) ® Structure). PENTILE ® It is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0110] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line X1-X1'.

[0111] Reference Figure 7 The display panel 100 may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), an encapsulation layer (TFE), an organic film (APL), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0112] A semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may be referenced... Figure 3 The first transistor T1 to the sixth transistor T6 described (see Figure 3 ).

[0113] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Optionally, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0114] Each of the multiple well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0115] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0116] Each of the source region SA and drain region DA can be a region doped with type I impurities. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third-direction DR3. The channel region CH can be stacked with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0117] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTR is increased, thereby preventing breakdown and hot carrier phenomena that may be caused by short channels.

[0118] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB and the pixel transistor PTR. The first semiconductor insulating film SINS1 can be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0119] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0120] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to the gate electrode (GE), source region (SA), or drain region (DA) of each of the pixel transistors (PTRs) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of them.

[0121] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs) on the second semiconductor insulating film (SINS2). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0122] The semiconductor substrate SSUB can be replaced by a glass substrate and / or a polymer resin substrate such as polyimide. In this case, the pixel transistor PTR can be disposed on the glass substrate and / or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent and / or flexed.

[0123] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9.

[0124] The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The pixel circuit of the first sub-pixel SP1 shown is illustrated. For example, the first transistor T1 to the sixth transistor T6 are only disposed in the semiconductor backplane SBP, and the connection lines between the first transistor T1 to the sixth transistor T6, the first capacitor CP1, and the second capacitor CP2 can be disposed in the first conductive layers ML1 to the eighth conductive layers ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE can also be disposed in the first conductive layers ML1 to the eighth conductive layers ML8.

[0125] A first insulating film INS1 may be disposed on a semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 and may be connected to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating film INS1 and may be connected to the first via VA1.

[0126] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and can be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be disposed on the second insulating film INS2 and can be connected to the second via VA2.

[0127] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can penetrate the third insulating film INS3 and can be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be disposed on the third insulating film INS3 and can be connected to the third via VA3.

[0128] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 and can be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 and can be connected to the fourth via VA4.

[0129] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 and can be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 and can be connected to the fifth via VA5.

[0130] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 and can be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 and can be connected to the sixth via VA6.

[0131] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 and can be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 and can be connected to the seventh via VA7.

[0132] The eighth insulating film INS8 can be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can penetrate the eighth insulating film INS8 and can be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 can be disposed on the eighth insulating film INS8 and can be connected to the eighth via VA8.

[0133] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of these. The first insulating films INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0134] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 is approximately 1360 Å. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 is approximately 1440 Å. The thickness of each of the first via VA1, second via VA2, third via VA3, fourth via VA4, fifth via VA5, and sixth via VA6 is approximately 1150 Å. However, the thickness of the first conductive layer ML1, second conductive layer ML2, third conductive layer ML3, fourth conductive layer ML4, fifth conductive layer ML5, and sixth conductive layer ML6, as well as the first via VA1, second via VA2, third via VA3, fourth via VA4, fifth via VA5, and sixth via VA6, is not limited to this.

[0135] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 is approximately 9000 Å, and the thickness of each of the seventh via VA7 and the eighth via VA8 is approximately 6000 Å. However, the thicknesses of the seventh conductive layer ML7, the eighth conductive layer ML8, the seventh via VA7, and the eighth via VA8 are not limited to this.

[0136] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). xInorganic membranes can be formed, but this disclosure is not limited thereto.

[0137] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and can be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of them.

[0138] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include: light-emitting elements (LE), each including a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT); a reflective electrode layer (RL); a tenth insulating film (INS10) and an eleventh insulating film (INS11); a tenth via (VA10); a pixel defining film (PDL); and multiple grooves (TRC).

[0139] A reflective electrode layer RL can be disposed on the ninth insulating film INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include, for instance... Figure 7 The first reflective electrode, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 shown are examples, but not limited to these.

[0140] Each of the first reflective electrodes RL1 may be disposed on the ninth insulating film INS9 and may be connected to the ninth via VA9. The first reflective electrodes RL1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys or compounds including one or more of them. For example, the first reflective electrode RL1 may contain titanium nitride (TiN).

[0141] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of them. For example, the second reflective electrode RL2 may include aluminum (Al).

[0142] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or an alloy or compound comprising one or more of these. For example, the third reflective electrode RL3 may contain titanium nitride (TiN).

[0143] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of them. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0144] Because, in one or more embodiments, the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 is approximately 100 Å, and the thickness of the second reflective electrode RL2 is approximately 850 Å. However, the thicknesses of the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 are not limited thereto. For example, as... Figure 7 As shown, since the fourth reflective electrode RL4 is an electrode that essentially reflects light from the light-emitting element LE, the thickness of the fourth reflective electrode RL4 can be greater than the thickness of each of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3.

[0145] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9. The tenth insulating film INS10 can be disposed between adjacent reflective electrode layers RL along the horizontal direction. The tenth insulating film INS10 can be made of silicon oxide (SiO2). x The formation of an inorganic film is described, but this disclosure is not limited thereto. In one or more embodiments, the tenth insulating film INS10 may be disposed not only between the reflective electrode layers RL, but also on the reflective electrode layers RL.

[0146] The eleventh insulating film INS11 can be disposed on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be made of silicon oxide (SiO2). x( ) Inorganic film formation, but this disclosure is not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 can be optical auxiliary layers through which light reflected from the light emitted from the light-emitting element LE by the reflective electrode layer RL passes.

[0147] In one or more embodiments, in order to adjust the resonant distance of light emitted from the light-emitting element LE, in at least one sub-pixel selected from the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the total thickness of the insulating film disposed between the first electrode AND and the reflective electrode layer RL may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0148] In one or more embodiments, as shown in the accompanying drawings, when the tenth insulating film INS10 is not disposed between the first electrode AND and the reflective electrode layer RL, but the eleventh insulating film INS11 is disposed between the first electrode AND and the reflective electrode layer RL, the thickness of the eleventh insulating film INS11 disposed in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be different. For example, the thickness of the eleventh insulating film INS11 disposed in the first sub-pixel SP1 may be less than the thickness of the eleventh insulating film INS11 disposed in the second sub-pixel SP2, and the thickness of the eleventh insulating film INS11 disposed in the second sub-pixel SP2 may be less than the thickness of the eleventh insulating film INS11 disposed in the third sub-pixel SP3.

[0149] In one or more embodiments, in the first sub-pixel SP1, the tenth insulating film INS10 and the eleventh insulating film INS11 may not be disposed between the first electrode AND and the reflective electrode layer RL; in the sub-pixel SP2, the tenth insulating film INS10 and / or the eleventh insulating film INS11 may be disposed between the first electrode AND and the reflective electrode layer RL; and in the third sub-pixel SP3, both the tenth insulating film INS10 and the eleventh insulating film INS11 may be disposed between the first electrode AND and the reflective electrode layer RL.

[0150] In one or more embodiments, a twelfth insulating film may also be disposed between the first electrode AND and the reflective electrode layer RL. In this case, in the first sub-pixel SP1, the tenth insulating film INS10, the eleventh insulating film INS11, and / or the twelfth insulating film may be disposed between the first electrode AND and the reflective electrode layer RL; in the second sub-pixel SP2, two of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be disposed between the first electrode AND and the reflective electrode layer RL; and in the third sub-pixel SP3, all of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be disposed between the first electrode AND and the reflective electrode layer RL.

[0151] In summary, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main peak wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence / absence or thickness of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0152] Although the accompanying drawings show that the total thickness of the insulating film disposed between the first electrode AND and the reflective electrode layer RL increases in the order of first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3, this disclosure is not limited thereto. That is, it is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, this disclosure is not limited thereto. The dimensional relationship of the total thickness of the insulating film disposed between the first electrode AND and the reflective electrode layer RL in each of the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 can vary depending on the resonant distance.

[0153] Each of the tenth vias VA10 can be connected to the reflective electrode layer RL exposed through the tenth insulating film INS10 and / or the eleventh insulating film INS11. The tenth via VA10 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of these. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3, and the thickness of the tenth via VA10 in the first sub-pixel SP1 can be less than the thickness of the tenth via VA10 in the second sub-pixel SP2, but this disclosure is not limited thereto.

[0154] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) or alloys or compounds including one or more of them. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0155] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can be used to separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0156] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0157] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x The formation of inorganic films is described, but this disclosure is not limited thereto. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may each have a thickness of approximately 500 Å.

[0158] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 form a single pixel defining film, the height of this single pixel defining film increases, making the first encapsulating inorganic film TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the greater the likelihood that the film will be cut at the inclined portion.

[0159] Therefore, to reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can have a cross-sectional structure with stepped portions. For example, the width of the first pixel-defining film PDL1 can be greater than the width of the second pixel-defining film PDL2 and the width of the third pixel-defining film PDL3, and the width of the second pixel-defining film PDL2 can be greater than the width of the third pixel-defining film PDL3. The width of the first pixel-defining film PDL1, the width of the second pixel-defining film PDL2, and the width of the third pixel-defining film PDL3 refer to the length in the horizontal direction perpendicular to the third third direction DR3.

[0160] Each of the plurality of grooves TRC can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Furthermore, each of the plurality of grooves TRC can penetrate the eleventh insulating film INS11. The eleventh insulating film INS11 can be at least partially recessed at each of the plurality of grooves TRC.

[0161] At least one notch TRC can be set between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 Two recessed TRCs are shown positioned between adjacent sub-pixels SP1, SP2, and SP3, but this disclosure is not limited thereto.

[0162] The light-emitting stack (IL) can include multiple intermediate layers. Figure 7 The illustration shows a light-emitting stack IL having a triple-tandem structure comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. For example, the light-emitting stack IL may have a double-tandem structure comprising two intermediate layers.

[0163] In a three-stage cascade structure, the light-emitting stack IL can have a cascade structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a second color, and a third stacked layer IL3 that emits light of a third color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0164] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0165] A first charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first stacked layer IL1 and a P-type charge generation layer that supplies holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0166] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type charge generation layer that supplies holes to the third stacked layer IL3.

[0167] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and can be disposed on the bottom surface of each recessed TRC. Due to the recessed TRC, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the recessed TRC, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space can be disposed between the first stacked layer IL1 and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the recessed TRC and can be configured to cover the second stacked layer IL2 in each of the recessed TRCs. That is, in the three-in-series structure, each of the plurality of recessed TRCs can be a structure for cutting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In addition, in the two-series structure, each of the grooves in the TRC can be a structure for cutting off the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer, as well as the lower intermediate layer.

[0168] To stably cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of recessed TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of recessed TRCs refers to the length of each of the plurality of recessed TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. To cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, another structure can exist to replace the recessed TRCs. For example, instead of recessed TRCs, an inverted conical partition wall can be provided on the pixel defining film PDL.

[0169] The number of stacked layers IL1, IL2, and IL3 that emit different light is not limited to Figure 7 The quantities shown are as described. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stack layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be disposed between the two intermediate layers.

[0170] in addition, Figure 7The diagram shows that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, but this disclosure is not limited thereto. For example, the first stacked layer IL1 may be disposed in the first emission region EA1 and may be omitted from the second emission region EA2 and the third emission region EA3. Furthermore, the second stacked layer IL2 may be disposed in the second emission region EA2 and may be omitted from the first emission region EA1 and the third emission region EA3. Similarly, the third stacked layer IL3 may be disposed in the third emission region EA3 and may be omitted from the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0171] The second electrode CAT can be disposed on the third stacked layer IL3. The second electrode CAT can be disposed on the third stacked layer IL3 in each of the multiple recessed TRCs. The second electrode CAT can be formed of a transparent conductive oxide (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency can be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to the microcavity effect.

[0172] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE2 to reduce or prevent oxygen and / or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0173] The first encapsulating inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is selected. x ), silicon oxynitride (SiON) and silicon oxide (SiO) x A multilayer of one or more inorganic films alternately stacked. The first encapsulating inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0174] The second encapsulating inorganic film TFE2 can be disposed on the first encapsulating inorganic film TFE1. The second encapsulating inorganic film TFE2 can be made of titanium oxide (TiO2). x ) and / or aluminum oxide (AlO) xThe second encapsulation inorganic film TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0175] The display panel 100 may also include an organic film APL. The organic film APL may be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0176] The optical layer OPL may include multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the organic film APL.

[0177] The first color filter CF1 can be superimposed on the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of the first color, that is, light in the red band. The red band can be approximately 600nm to 750nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0178] The second color filter CF2 can be superimposed on the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, namely, light in the green band. The green band can be approximately 480nm to 560nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0179] The third color filter CF3 can be superimposed on the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color, namely, light in the blue band. The blue band can be approximately 370nm to 460nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0180] Multiple lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed to the front of the display device 10. Each of the multiple lenses LNS can have a profile shape that convexes in the upward direction. In one or more embodiments, the multiple lenses LNS can be a microlens array (MLA).

[0181] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a suitable refractive index (e.g., a predetermined refractive index) such that light travels in the third-direction DR3 at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0182] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate and / or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL is used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FIL.

[0183] The polarizer POL can be disposed on one surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. However, the polarizer POL can be omitted when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0184] Figure 8 This is a cross-sectional view showing another example of a display panel included in a display device according to one or more embodiments.

[0185] Apart from Figure 7 In addition, refer to Figure 8 In one or more embodiments, the display device 10 may include, according to Figure 8 The display panel 100 of the embodiment, rather than referring to Figure 7 The described display panel 100.

[0186] according to Figure 8 The display panel 100 of the embodiment may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), and a packaging layer (TFE). However, this disclosure is not limited thereto, and is consistent with the referenced... Figure 7 The described display panel 100 is the same, according to Figure 8 The display panel 100 in the embodiment may also include an optical layer OPL, a cover layer CVL, and a polarizing plate POL on the encapsulation layer TFE.

[0187] Because the semiconductor backplane SBP and the light-emitting element backplane EBP are similar to the reference... Figure 7The semiconductor backplane SBP and the light-emitting element backplane EBP of the described display panel 100 are the same, so the description of the semiconductor backplane SBP and the light-emitting element backplane EBP is omitted here.

[0188] The display element layer (EML) can be disposed on the light-emitting element backplane (EBP). The display element layer (EML) may include light-emitting elements 170 and diaphragms 190. Each of the light-emitting elements 170 may include a first light-emitting electrode 171, a light-emitting layer 172, and a second light-emitting electrode 173.

[0189] The first light-emitting electrode 171 may be disposed on the backplane EBP of the light-emitting element. For example, in one or more embodiments, the first light-emitting electrode 171 may be connected to the eighth conductive layer ML8 via a ninth via VA9 that penetrates the ninth insulating film INS9 and exposes the eighth conductive layer ML8.

[0190] In the top emitting structure that emits light toward the second light-emitting electrode 173 when viewed relative to the light-emitting layer 172, the first light-emitting electrode 171 may be formed of a metallic material with high reflectivity, having a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0191] The dam 190 may be configured to separate the first light-emitting electrode 171 to define emission regions EA1, EA2, and EA3. The dam 190 may be configured to cover a portion of the edge of the first light-emitting electrode 171. The dam 190 may be formed of an organic film such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0192] Spacer 191 may be disposed on dam 190. Spacer 191 may be used to support deposition mask 800 during the process of fabricating light-emitting layer 172 (see [link to documentation]). Figure 14 The spacer 191 may be formed of an organic film such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0193] Each of the emission regions EA1, EA2 and EA3 represents a region in which the first light-emitting electrode 171, the light-emitting layer 172 and the second light-emitting electrode 173 are stacked sequentially, and holes from the first light-emitting electrode 171 and electrons from the second light-emitting electrode 173 recombine with each other in the light-emitting layer 172 to emit light.

[0194] In one or more embodiments, the light-emitting layer 172 may be disposed on the first light-emitting electrode 171. However, in one or more other embodiments, the light-emitting layer 172 may be disposed on both the first light-emitting electrode 171 and the dam 190. The light-emitting layer 172 may include organic materials to emit light of a suitable color (e.g., a predetermined color). For example, the light-emitting layer 172 may include a hole transport layer, an organic material layer, and / or an electron transport layer.

[0195] The second light-emitting electrode 173 can be disposed on the light-emitting layer 172, the dam 190, and the spacer 191. The second light-emitting electrode 173 can be formed to cover the light-emitting layer 172. The second light-emitting electrode 173 can be a common layer shared by all emitting regions EA1, EA2, and EA3. In one or more embodiments, a capping layer can be formed on the second light-emitting electrode 173.

[0196] In the top-emitting structure, the second light-emitting electrode 173 can be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO) that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second light-emitting electrode 173 is formed of a semi-transmissive conductive material, the light emission efficiency can be improved due to the microcavity effect.

[0197] An encapsulation layer TFE can be disposed on the second light-emitting electrode 173. The encapsulation layer TFE may include at least one inorganic film to prevent oxygen and / or moisture from penetrating into the light-emitting element layer. In addition, the encapsulation layer TFE may include at least one organic layer to protect the light-emitting element layer from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation film TFE1, a second encapsulation film TFE2, and a third encapsulation film TFE3.

[0198] A first encapsulation film TFE1 (e.g., a first encapsulation inorganic film) may be disposed on the second light-emitting electrode 173. The first encapsulation film TFE1 may be a single layer or a multilayer inorganic film. The first encapsulation film TFE1 may be formed as a single layer or a multilayer in which one or more inorganic films, such as silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer and aluminum oxide layer, are alternately stacked.

[0199] A second encapsulating film TFE2 (e.g., a first organic encapsulating film) may be disposed on the first encapsulating film TFE1. The second encapsulating film TFE2 may be a single layer or multiple layers of organic layers. The second encapsulating film TFE2 may include polymeric materials. Polymeric materials may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane and / or acrylic resins (e.g., polymethyl methacrylate or polyacrylic acid, etc.) or any combination thereof.

[0200] A third encapsulation film TFE3 (e.g., a second encapsulation inorganic film) may be disposed on the second encapsulation film TFE2. The third encapsulation film TFE3 may be a single layer or a multilayer inorganic film. The third encapsulation film TFE3 may comprise the same material as the first encapsulation film TFE1. For example, the third encapsulation film TFE3 may be formed as a single layer or as a multilayer in which one or more inorganic films, such as silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers, are alternately stacked.

[0201] Figure 9 This is an exploded perspective view showing a head-mounted display according to one or more embodiments.

[0202] Reference Figure 9 The head-mounted display 1000 is formed in the form of glasses or a head-mounted device to provide images to the user using the display device 10_1.

[0203] The head-mounted display 1000 may include a see-through type that provides augmented reality based on actual external objects and a see-closed type that provides virtual reality to the user on a screen independent of external objects.

[0204] The head-mounted display 1000 may include a main frame MF mounted on the user's body, a display device 10_1 mounted on the main frame MF to display images, and a cover frame CF covering the display device 10_1.

[0205] The display device 10_1 can be integrally formed with the head-mounted display 1000, or it can be formed as an assembly to the head-mounted display 1000, which can be carried by a user and easily attached to or detached from the face or head. The display device 10_1 can be combined with... Figure 1 The display device 10 described above is essentially the same.

[0206] The display device 10_1 may include a display panel DP for displaying an image, a first lens frame OS1 and a second lens frame OS2 for refracting image display light, and a first multi-channel lens LS1 and a second multi-channel lens LS2 for forming an optical path so that the image display light of the display panel DP is visible to the user.

[0207] The main frame MF can be worn on the user's face and head. The main frame MF can be shaped to correspond to the user's head and facial structure.

[0208] The main frame MF can be integrally formed with the display device 10_1 (i.e., the display panel DP, the first lens frame OS1 and the second lens frame OS2, and the first multi-channel lens LS1 and the second multi-channel lens LS2). Optionally, the display panel DP, the first lens frame OS1 and the second lens frame OS2, and the first multi-channel lens LS1 and the second multi-channel lens LS2 can be assembled and mounted to the main frame MF. For this purpose, the main frame MF can have a space or structure for accommodating the display panel DP, the first lens frame OS1 and the second lens frame OS2, and the first multi-channel lens LS1 and the second multi-channel lens LS2. The main frame MF can also include structures such as strips or bands to facilitate mounting, and the controller, image processing unit, and lens accommodating unit can also be included in the main frame MF.

[0209] The display panel DP can be divided into a front surface DP_FS for displaying images and a rear surface DP_RS located on the opposite side of the front surface DP_FS. Image display light can be emitted from the front surface DP_FS of the display panel DP. As described later, a first lens frame OS1 and a second lens frame OS2 can be disposed on the front surface DP_FS of the display panel DP, and a first multi-channel lens LS1 and a second multi-channel lens LS2 can be disposed on the front surfaces of the first lens frame OS1 and the second lens frame OS2. In one or more embodiments, at least one infrared camera can be disposed on at least one of the front surface DP_FS and the rear surface DP_RS of the display panel DP. The display panel DP can be combined with... Figure 1 The display panel 100 described above is basically the same.

[0210] The display panel DP can be built into the main frame MF with the first lens frame OS1 and the second lens frame OS2, as well as the first multi-channel lens LS1 and the second multi-channel lens LS2, installed and fixed, or it can be detachably assembled to the main frame MF. Depending on the design of the display device 10_1 (e.g., depending on the type of use of the display device 10_1), the display panel DP can be opaque, transparent, or translucent.

[0211] Each of the first lens frame OS1 and the second lens frame OS2 may have an area corresponding to the image display surface of the display panel DP, and may be formed in a shape corresponding to the shape of the image display surface. Furthermore, the first lens frame OS1 and the second lens frame OS2 may be formed with an area and shape respectively corresponding to the area and shape of the rear surfaces of the first multi-channel lens LS1 and the second multi-channel lens LS2. The rear surfaces of the first lens frame OS1 and the second lens frame OS2 may be attached to the image display surface of the display panel DP, and the first multi-channel lens LS1 and the second multi-channel lens LS2 may be attached to the front surfaces of the first lens frame OS1 and the second lens frame OS2, respectively. The first lens frame OS1 and the second lens frame OS2 refract image display light emitted from the image display surface of the display panel DP at an appropriate angle (e.g., a predetermined angle) and provide it to the first multi-channel lens LS1 and the second multi-channel lens LS2 respectively disposed on the front surfaces of the first lens frame OS1 and the second lens frame OS2.

[0212] Specifically, the first lens frame OS1 and the second lens frame OS2 can refract image display light emitted from the image display surface of the display panel DP towards the front side towards the outer side (or towards the outer peripheral side) compared to the front side, and provide it to the first multi-channel lens LS1 and the second multi-channel lens LS2 respectively disposed on the front surfaces of the first lens frame OS1 and the second lens frame OS2. Specifically, the first lens frame OS1 and the second lens frame OS2 can refract image display light incident on their rear surfaces towards the outer side (or towards the outer peripheral side) and provide it to the rear surfaces of the first multi-channel lens LS1 and the second multi-channel lens LS2 respectively.

[0213] The first multi-channel lens LS1 and the second multi-channel lens LS2 can form a path for light emitted through the first lens frame OS1 and the second lens frame OS2, so that the image display light is visible to the eyes of the user in front.

[0214] The first multi-channel lens LS1 and the second multi-channel lens LS2 can provide image display light emitted from the display panel DP through multiple channels (or paths). Multiple channels can provide image display light emitted from the display panel DP to the user via different paths. Image display light emitted through the first lens frame OS1 and the second lens frame OS2 can be incident on corresponding channels, and the image magnified through the corresponding channels can be focused onto the user's eyes.

[0215] The first multi-channel lens LS1 and the second multi-channel lens LS2 can be arranged on the front surfaces of the first lens frame OS1 and the second lens frame OS2, respectively, to correspond to the positions of the user's left and right eyes. The first multi-channel lens LS1 and the second multi-channel lens LS2 can be housed in the main frame MF.

[0216] The first multi-channel lens LS1 and the second multi-channel lens LS2 can refract and / or reflect image display light emitted through the first lens frame OS1 and the second lens frame OS2 at least once to form a path to the user's eye. At least one infrared light source can be further disposed at the main frame MF, or disposed on the side of each of the first multi-channel lens LS1 and the second multi-channel lens LS2 facing the user's eye.

[0217] The cover frame CF can be mounted on the rear surface DP_RS of the display panel DP to cover and protect the display panel DP. The cover frame CF can be attached to the main frame MF while covering the display panel DP.

[0218] In one or more embodiments, the display device 10_1 may further include a controller for controlling the overall operation of the display device 10_1, including the display panel DP. The controller can control the image display operation and audio devices of the display panel DP. Specifically, the controller performs image processing (e.g., image mapping) based on the magnification and image display path corresponding to the first lens frame OS1 and the second lens frame OS2, and the first multi-channel lens LS1 and the second multi-channel lens LS2, and controls the mapped image to be displayed on the display panel DP. The controller may be implemented as a dedicated processor including an embedded processor and / or a general-purpose processor including a central processing unit (CPU) or an application processor, but is not limited thereto.

[0219] Figure 10 This is a perspective view showing an augmented reality content providing device according to one or more embodiments. Figure 11 yes Figure 10 The augmented reality content provides an exploded perspective view of the back of the device. Figure 12 yes Figure 10 The augmented reality content provides a front exploded perspective view of the device.

[0220] Reference Figures 10 to 12 The augmented reality content providing device 1000_1 may include a support frame 1002 supporting at least one transparent lens 1001, at least one image display module 1010, an ambient environment detector 1040, and a control module 1020.

[0221] The support frame 1002 can be formed in the form of eyeglasses, which includes temples and an edge supporting at least one transparent lens 1001. The shape of the support frame 1002 is not limited to eyeglasses and can be formed as goggles or headband type including the transparent lens 1001.

[0222] The transparent lens 1001 may include an integrally formed left and right portion, or a separately formed first and second transparent lens. The transparent lens 1001, including the integral left and right portions or the separate first and second transparent lenses, may be made of transparent or translucent glass or plastic. Therefore, a user can view a real image through the transparent lens 1001, which includes the integral right and left portions or the separate first and second transparent lenses. Here, the transparent lens 1001 (i.e., the integral lens or the first and second transparent lenses) may have refractive power taking into account the user's vision.

[0223] The transparent lens 1001 may further include: at least one reflective member for reflecting an augmented reality content image provided by at least one image display module 1010 toward the transparent lens 1001 or the user's eye; and optical members for adjusting focus and size. One or more reflective members may be integrated into the transparent lens 1001 to be integral with the transparent lens 1001, and may be formed as a plurality of refractive lenses or a plurality of prisms having a suitable curvature (e.g., a predetermined curvature).

[0224] At least one image display module 1010 may include a microLED display device (microLED), a nanoLED display device (nanoLED), an organic light-emitting display device, an inorganic light-emitting display device (inorganic EL), a quantum dot light-emitting display device (QED), a cathode ray display (CRT), and / or a liquid crystal display (LCD), etc. The image display module 1010 may substantially include references... Figure 1 The display device 10 is described above.

[0225] An ambient environment detector 1040 is assembled or integrally formed with a support frame 1002 and detects the distance (or depth) of objects on the front side of the support frame 1002, illumination, the direction of movement, distance of movement, and / or tilt of the support frame 1002. For this purpose, the ambient environment detector 1040 includes a depth sensor 1041, such as an infrared sensor or a LiDAR sensor, and an image sensor 1050, such as a camera. Furthermore, the ambient environment detector 1040 may also include at least one motion sensor selected from an illumination sensor, a human detection sensor, a gyroscope sensor, a tilt sensor, and an accelerometer. Additionally, the ambient environment detector 1040 may also include a first biometric sensor 1031 and a second biometric sensor 1032 for detecting motion information of the user's eyes or pupils.

[0226] The ambient environment detector 1040 can transmit sensing signals generated by the depth sensor 1041 and at least one motion sensor to the control module 1020 in real time. Furthermore, the image sensor 1050 can transmit image data generated in real time, in units of at least one frame, to the control module 1020. The first biometric sensor 1031 and the second biometric sensor 1032 of the ambient environment detector 1040 can transmit detected pupil detection signals to the control module 1020.

[0227] The control module 1020 can be assembled together with at least one image display module 1010 to at least one side of the support frame 1002, or it can be integrally formed with the support frame 1002. The control module 1020 supplies augmented reality content data to at least one image display module 1010, causing the at least one image display module 1010 to display augmented reality content, such as an augmented reality image. Simultaneously, the control module 1020 can receive sensing signals, image data, and pupil detection signals from the ambient environment detector 1040 in real time.

[0228] Figure 13 This is a plan view illustrating a parent semiconductor substrate including a display unit according to one or more embodiments.

[0229] Apart from Figure 7 and Figure 8 In addition, refer to Figure 13 The parent semiconductor substrate (MSUB) can be constructed from a semiconductor wafer. The parent semiconductor substrate (MSUB) can contain group IV materials and / or group III-V compounds. In one or more embodiments, the parent semiconductor substrate (MSUB) can be constructed from a single-crystal wafer. For example, the parent semiconductor substrate (MSUB) can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate.

[0230] However, the mother semiconductor substrate (MSUB) is not limited to single-crystal wafers and can be any type of wafer such as epitaxial wafers, polished wafers, annealed wafers, and / or silicon-on-insulator (SOI) wafers. An epitaxial wafer refers to a wafer in which crystalline material is grown on a single-crystal silicon substrate.

[0231] The mother semiconductor substrate (MSUB) may include multiple display cells (DPCs). Each of the multiple display cells (DPCs) may constitute a reference. Figure 1 The preprocessing components are part of the display panel 100 as described above. For example, the mother semiconductor substrate MSUB can constitute the semiconductor substrate SSUB of the display panel 100, and multiple display units DPC can constitute the semiconductor backplane SBP, display element layer EML, and encapsulation layer TFE of the display panel 100.

[0232] Multiple display units (DPCs) can be formed using semiconductor devices or semiconductor processes, but are not limited thereto. After multiple display units (DPCs) are formed on a parent semiconductor substrate (MSUB), a display panel 100 can be formed by performing cell dicing on each display unit (DPC).

[0233] In one or more embodiments, each of the plurality of display units (DPCs) may include a plurality of pixels (PXs). Each of the plurality of pixels (PXs) included in each of the plurality of display units (DPCs) may include a plurality of light-emitting elements (LEs) (see...). Figure 7 ), and includes the light-emitting stack IL in the light-emitting element LE (see Figure 7 ) or luminescent layer 172 (see Figure 8 It can be formed through a deposition process.

[0234] like Figure 7 As shown, the light-emitting stack IL can be set across multiple pixel PXs, and as... Figure 8 As shown, the light-emitting layer 172 can be individually disposed in the emitting regions EA1, EA2, and EA3. Regardless of Figure 7 and Figure 8 Regardless of the specific implementation, a more precise deposition mask is required to form the light-emitting stack IL or light-emitting layer 172 in the high-resolution display device 10, and such a deposition mask for forming the high-resolution display device 10 will be described below.

[0235] Figure 14 This is a plan view showing a deposition mask according to one or more embodiments. Figure 15 It is along Figure 14 The sectional view taken by line X2-X2'.

[0236] Apart from Figure 13 In addition, refer to Figure 14 and Figure 15The deposition mask 800 according to one or more embodiments may be a deposition mask used in the fabrication of an ultra-high resolution display. For example, the deposition mask 800 according to one or more embodiments may be used in the fabrication of a display including a reference... Figures 9 to 12 The deposition mask used when displaying a head-mounted display 1000 or an augmented reality content providing device 1000_1.

[0237] In one or more embodiments, the deposition mask 800 can be used to perform pixel deposition processes on a silicon wafer rather than a large-area substrate used in conventional displays. For example, in the case of a display included in an extended reality device, because the screen is directly in front of the user's eyes, it can have a small screen rather than a large screen. Additionally, because the display is positioned close to the user's eyes, ultra-high resolution may be required. For example, the required resolution of a display included in an extended reality device may be approximately 1000 PPI or higher, and desirably, ultra-high resolution of 3000 PPI or higher may be required. The deposition mask 800 according to one or more embodiments can be a mask used in manufacturing such an ultra-high resolution display. In one or more embodiments, the deposition mask 800 can be a fine silicon mask (FSM).

[0238] The deposition mask 800 may include a mask substrate 810 and multiple mask units MSC.

[0239] The mask substrate 810 may be made of a semiconductor wafer. The mask substrate 810 may contain group IV materials and / or group III-V compounds. In one or more embodiments, the mask substrate 810 may be made of a single-crystal wafer. For example, the mask substrate 810 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0240] However, the mask substrate 810 is not limited to a single-crystal wafer, and can be any of various types of wafers such as epitaxial wafers, polished wafers, annealed wafers, and SOI (silicon-on-insulator) wafers. An epitaxial wafer is a wafer in which crystalline material is grown on a single-crystal silicon substrate.

[0241] The mask substrate 810 may have a shape corresponding to the silicon wafer of the ultra-high resolution display. For example, the mask substrate 810 may have the same size or shape as the parent semiconductor substrate MSUB that serves as the substrate of the ultra-high resolution display.

[0242] Multiple mask cells (MSCs) can be arranged to correspond to multiple display cells (DPCs) of a parent semiconductor substrate (MSUB). For example, in the fabrication of display device 10 (see... Figure 1In the deposition process, the deposition mask 800 can be located on the parent semiconductor substrate MSUB. At this time, multiple mask units MSC can be stacked with multiple display units DPC of the parent semiconductor substrate MSUB respectively.

[0243] To align multiple mask units MSC for stacking with multiple display units DPC, the mother semiconductor substrate MSUB may include a first alignment mark AMK1, and the deposition mask 800 may include a second alignment mark AMK2. Both the first alignment mark AMK1 and the second alignment mark AMK2 may contain metal, but are not limited thereto.

[0244] Multiple mask cells MSC can be formed using semiconductor equipment or through semiconductor processes, but are not limited thereto. By forming multiple mask cells MSC on a mask substrate 810 made of a semiconductor wafer using semiconductor equipment or through semiconductor processes, the deposition mask 800 according to this embodiment can be provided with an ultra-high resolution pattern. This ultra-high resolution pattern can be used to manufacture an ultra-high resolution display.

[0245] The deposition mask 800 may include a mask substrate 810, a first coating film 820, a second alignment mark AMK2, and a second coating film 830.

[0246] Since the mask substrate 810 has already been described above, the description of the mask substrate 810 will be omitted here.

[0247] The first coating film 820 can be disposed on the mask substrate 810. The first coating film 820 can be an inorganic film containing inorganic materials. For example, the first coating film 820 can contain silicon oxide (SiO2). x ).

[0248] The second alignment mark AMK2 may be disposed on the first coating film 820. However, this disclosure is not limited thereto, and the second alignment mark AMK2 may be disposed on the mask substrate 810 or the second coating film 830.

[0249] The second coating film 830 can be disposed on the second alignment mark AMK2 and the first coating film 820. The second coating film 830 can be an inorganic film containing inorganic materials. For example, the second coating film 830 can contain silicon nitride (SiN). x ).

[0250] In one or more embodiments, the second coating film 830 may contain low-stress nitride (LSN). When the second coating film 830 contains low-stress nitride, the second coating film 830 can be formed by a low-pressure chemical vapor deposition (LPCVD) process, but is not limited thereto. Because the second coating film 830 contains low-stress nitride, the durability of the deposition mask 800 can be improved by the low stress even when forming multiple mask patterns MPT and multiple hole patterns HPT, which will be described later.

[0251] In one or more embodiments, the first coating film 820 and the second coating film 830 may cover the top surface, bottom surface, and side surface of the mask substrate 810. For example, the first coating film 820 may include a first upper coating film 821 disposed on the top surface of the mask substrate 810, a first lower coating film 822 disposed on the bottom surface of the mask substrate 810, and a first side coating film 823 disposed on the side surface of the mask substrate 810. The second coating film 830 may include a second upper coating film 831 disposed on the top surface of the mask substrate 810, a second lower coating film 832 disposed on the bottom surface of the mask substrate 810, and a second side coating film 833 disposed on the side surface of the mask substrate 810. The second upper coating film 831 may be disposed on the first upper coating film 821, the second lower coating film 832 may be disposed on the first lower coating film 822, and the second side coating film 833 may be disposed on the first side coating film 823.

[0252] However, this disclosure is not limited thereto, and the first coating film 820 may include only the first upper coating film 821, and the second coating film 830 may include only the second upper coating film 831.

[0253] The deposition mask 800 may include a plurality of mask patterns MPT and a plurality of hole patterns HPT disposed in the second coating film 830. The plurality of mask patterns MPT and the plurality of hole patterns HPT may be disposed in a second upper coating film 831 of the second coating film 830.

[0254] Multiple mask patterns (MPTs) and multiple hole patterns (HPTs) can be arranged alternately. For example, multiple mask patterns (MPTs) and multiple hole patterns (HPTs) can be arranged alternately along a first direction DR1 and / or a second direction DR2.

[0255] Although multiple mask patterns MPTs are spaced apart from each other in a first direction DR1 or a second direction DR2 in a sectional view (e.g., spaced apart), they may be single patterns connected to each other in a plan view. In the following description, mask pattern MPT may refer to the entirety of multiple patterns positioned as a single component on mask base 810, or it may refer to each of the multiple patterns. That is, multiple mask patterns MPTs may be used interchangeably to refer to the entire group of multiple patterns as a single component, or to each of the multiple patterns.

[0256] The deposition mask 800 may include a mask opening MOP that penetrates the mask substrate 810, the first coating film 820, and the second coating film 830. For example, the mask opening MOP may penetrate the second lower coating film 832, the first lower coating film 822, the mask substrate 810, and the first upper coating film 821. In a cross-sectional view, the mask substrate 810 may be divided into a first portion 811 and a second portion 812 by the mask opening MOP that penetrates the mask substrate 810.

[0257] In one or more embodiments, when the first coating film 820 includes only the first top coating film 821 and the second coating film 830 includes only the second top coating film 831, the mask opening MOP can penetrate the mask substrate 810 and the first top coating film 821.

[0258] Although the inner surface of the mask opening MOP is depicted as a vertical plane in the accompanying drawings, it is not limited to this. For example, due to the isotropic nature of the wet etching process, the inner surface of the mask opening MOP can be inclined or curved.

[0259] The mask opening (MOP) can be connected to the hole pattern (HPT). Therefore, the mask opening (MOP) and the hole pattern (HPT) can provide a deposition source DSC (see [link to DSC]). Figure 17 The mask substrate 810 and the mask pattern MPT can block the deposition source DSC in areas other than the channels formed by the interconnection of the mask openings MOP and the hole pattern HPT (see [link]). Figure 17 ).

[0260] In one or more embodiments, the number of mask openings (MOPs) may correspond to multiple mask cells (MSCs). For example, multiple mask openings (MOPs) may be provided for each of the multiple mask cells (MSCs). However, this disclosure is not limited thereto, and in other embodiments, the mask opening (MOP) may be formed as one spanning multiple mask cells (MSCs).

[0261] Figure 16 yes Figure 15 A magnified view of region A.

[0262] Apart from Figure 15 In addition, refer to Figure 16 The mask pattern MPT can have an inverted cone shape. For example, the lower width MPT_W1 of the mask pattern MPT can be smaller than the upper width MPT_W2 of the mask pattern MPT.

[0263] Hole pattern HPT can have a positive conical shape. For example, the upper width HPT_W2 of hole pattern HPT can be smaller than the lower width HPT_W1 of hole pattern HPT.

[0264] The mask pattern MPT may include a first portion MPT1 and a second portion MPT2 located on the first portion MPT1. In this disclosure, although the first portion MPT1 and the second portion MPT2 are described separately for ease of illustration, the first portion MPT1 and the second portion MPT2 may be physically connected to each other as a single component.

[0265] The first part MPT1 may include a first surface MPT1a, a second surface MPT1b positioned opposite to the first surface MPT1a, and a first side surface MPT1c positioned between the first surface MPT1a and the second surface MPT1b. The first surface MPT1a of the first part MPT1 is the surface facing the mask substrate 810, the second surface MPT1b of the first part MPT1 is the surface facing the second part MPT2, and the first side surface MPT1c of the first part MPT1 is the surface that connects the first surface MPT1a to the second surface MPT1b and contacts the hole pattern HPT.

[0266] The first portion MPT1 may have an inverted conical shape. For example, the width of the first surface MPT1a of the first portion MPT1 may be smaller than the width of the second surface MPT1b of the first portion MPT1. That is, the width of the first portion MPT1 may narrow as it moves from the second surface MPT1b toward the first surface MPT1a. The first side surface MPT1c of the first portion MPT1 may be an inclined surface that slopes inward in the first portion MPT1 as it moves from the second surface MPT1b toward the first surface MPT1a. The first angle θ1, which is the interior angle formed by the first surface MPT1a and the first side surface MPT1c of the first portion MPT1, may be an obtuse angle. In one or more embodiments, the first angle θ1 may be approximately greater than 90 degrees and less than 100 degrees, and, desirably, the first angle θ1 may be approximately greater than or equal to 93 degrees and less than or equal to 97 degrees, but is not limited thereto.

[0267] The second part MPT2 can be located on the first part MPT1. The second part MPT2 can be positioned opposite the mask opening MOP, and the first part MPT1 is between the second part MPT2 and the mask opening MOP.

[0268] The second part MPT2 may include a first surface MPT2a, a second surface MPT2b positioned opposite to the first surface MPT2a, and a first side surface MPT2c positioned between the first surface MPT2a and the second surface MPT2b. The first surface MPT2a of the second part MPT2 is the surface facing the first part MPT1, the second surface MPT2b of the second part MPT2 is the surface opposite to the first surface MPT2a, and the first side surface MPT2c of the second part MPT2 is the surface that connects the first surface MPT2a and the second surface MPT2b of the second part MPT2 and contacts the hole pattern HPT.

[0269] In one or more embodiments, the second portion MPT2 may have an inverted conical shape. For example, the width of the first surface MPT2a of the second portion MPT2 may be smaller than the width of the second surface MPT2b of the second portion MPT2. That is, the width of the second portion MPT2 narrows from the second surface MPT2b toward the first surface MPT2a of the second portion MPT2. The first side surface MPT2c of the second portion MPT2 may be an inclined surface that slopes inward in the direction of the second portion MPT2 from the second surface MPT2b toward the first surface MPT2a of the second portion MPT2. The second angle θ2, which is the interior angle formed by the first surface MPT2a and the first side surface MPT2c of the second portion MPT2, may be an obtuse angle. In one or more embodiments, the second angle θ2 may be approximately greater than 90 degrees and less than or equal to 93 degrees, but is not limited thereto.

[0270] In one or more embodiments, the second portion MPT2 may have a vertical shape. For example, the width of the first surface MPT2a of the second portion MPT2 may be the same as the width of the second surface MPT2b of the second portion MPT2. In this case, the first side surface MTP2c of the second portion MPT2 may be a vertical plane, and the second angle θ2, which is the interior angle formed by the first surface MPT2a and the first side surface MPT2c of the second portion MPT2, may be a right angle.

[0271] In the deposition mask 800 according to this embodiment, the tilt angle of the first side surface MPT1c of the first portion MPT1 and the tilt angle of the first side surface MPT2c of the second portion MPT2 can be different. For example, the second angle θ2, which is the tilt angle of the first side surface MPT2c of the second portion MPT2, can be smaller than the first angle θ1, which is the tilt angle of the first side surface MPT1c of the first portion MPT1.

[0272] In one or more embodiments, the thickness 820_H of the first coating film 820 and the thickness 830_H of the second coating film 830 can be in the range of approximately 0.4 μm to 1.4 μm, but are not limited thereto. The height MPT1_H of the first portion MPT1 can be greater than the height MPT2_H of the second portion MPT2. For example, the height MPT1_H of the first portion MPT1 can be approximately 0.3 μm to 1 μm, and the height MPT2_H of the second portion MPT2 can be approximately 0.05 μm to 0.5 μm, but are not limited thereto.

[0273] Since the deposition mask 800 according to this embodiment includes an inverted cone-shaped mask pattern MPT and a positive cone-shaped aperture pattern HPT, the efficiency of the deposition process can be improved. (See below for further details.) Figure 17 and Figure 19 This will be described.

[0274] Figure 17 This is a cross-sectional view illustrating a process for manufacturing a display device using a deposition mask according to one or more embodiments. Figure 18 This is a schematic diagram showing the emission area and shadow area formed when manufacturing a display device using a deposition mask according to a comparative example. Figure 19 This is a schematic diagram showing the emission area formed when a display device is manufactured using a deposition mask according to one or more embodiments.

[0275] Reference Figures 17 to 19 A deposition mask 800 can be used to form a light-emitting layer 172 in each of the sub-pixels SP1, SP2, and SP3 of the display panel 100. The display panel 100 can be configured such that the semiconductor backplane SBP of the display panel 100 is positioned away from the deposition source supplier DSP. For example, the semiconductor backplane SBP can be configured to face upwards, and the light-emitting layers 172 in the sub-pixels SP1, SP2, and SP3 can be configured to face downwards.

[0276] When sub-pixels SP1, SP2, and SP3 are sub-pixels that achieve different colors, the materials of the light sources included in the light-emitting layers 172 of each sub-pixel SP1, SP2, and SP3 can be different. That is, the deposition source DSC used to form the light-emitting layers 172 of each sub-pixel SP1, SP2, and SP3 can be different.

[0277] Therefore, when forming a light-emitting layer 172 in one of the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1, SP2, or SP3 in which the light-emitting layer 172 is to be formed can be set to be superimposed with the hole pattern HPT, and the remaining sub-pixels SP1, SP2, or SP3 can be set to be superimposed with the mask pattern MPT.

[0278] Therefore, the deposition source DSC ejected from the deposition source supplier DSP can pass through the mask opening MOP and the hole pattern HPT only in the sub-pixels SP1, SP2 or SP3 where the light-emitting layer 172 is formed, and can be placed on the semiconductor backplane SBP of the display panel 100.

[0279] The deposition mask 800 can be placed on the spacer 191 of the display panel 100. For example, a second portion of the mask pattern MPT, MPT2, can be placed on the spacer 191. The second portion of the mask pattern MPT, MPT2, can be in direct contact with the spacer 91.

[0280] like Figure 18 As shown, the first angle θ1' between the side surface and the bottom surface of the mask pattern MPT in the deposition mask 800' according to the comparative example can be 90 degrees or less. For example, the mask pattern MPT of the deposition mask 800' according to the comparative example can have a normal conical shape with a width that narrows from its bottom surface toward its top surface, or it can have a vertical shape.

[0281] In this case, the first angle θ1' of the deposition mask 800' according to the comparative example can be smaller than the third angle θ3 of the jet deposition source DSC. Therefore, some of the deposition source DSC may accumulate on the side and bottom surfaces of the mask pattern MPT of the deposition mask 800' according to the comparative example, resulting in material loss. Consequently, a shadow region SHA may form around the emission region EA formed in the display panel 100'. The shadow region SHA refers to an area where the thickness of the deposition source DSC is less than or equal to a certain thickness (e.g., equal to 90% of the thickness of the deposition source DSC accumulated in the emission region EA).

[0282] like Figure 19As shown, in the deposition mask 800 according to one or more embodiments, the first angle θ1 between the side surface and the bottom surface of the mask pattern MPT (specifically, the first portion MPT1) can be greater than 90 degrees. For example, the mask pattern MPT of the deposition mask 800 according to one or more embodiments can have an inverted conical shape whose width widens from its bottom surface toward its top surface.

[0283] In this case, the first angle θ1 in the deposition mask 800 according to one or more embodiments can be greater than the third angle θ3, which is the angle of the jet deposition source DSC. Therefore, no shadow region SHA is formed around the emission region EA formed in the display panel 100, and the size of the emission region EA can be increased compared to the size of the emission region EA in the comparative example. As a result, material loss can be reduced or minimized, and the increased size of the emission region EA leads to improved efficiency of the deposition process.

[0284] In the following description, other embodiments of the deposition mask according to one or more embodiments will be described. In the following embodiments, the description of the same components indicated by the same reference numerals as those in the above embodiments will be omitted or simplified, and the differences will be mainly described.

[0285] Figure 20 This is a plan view showing a deposition mask according to one or more other embodiments.

[0286] Reference Figure 20 The deposition mask 800 according to this embodiment and the one according to reference Figure 16 The difference between the deposition mask 800 in the embodiments described above and the one described is that it also includes a third coating film 840 and a third portion MPT3.

[0287] In detail, the deposition mask 800 according to this embodiment may also include a third coating film 840.

[0288] The third coating film 840 may be disposed on the second coating film 830. In one or more embodiments, the third coating film 840 may be an inorganic film comprising an inorganic material. For example, the third coating film 840 may comprise silicon oxide (SiO2). x In one or more other embodiments, the third coating film 840 may be a metal layer containing metal.

[0289] The third coating film 840 can be achieved through the method S1 for manufacturing the deposition mask, which will be described later (see below). Figure 22 In step S500 of forming a mask pattern and a hole pattern in the second coated film (see) Figure 22 In the second coating film 830, a hard mask is placed with the photoresist PR (see...). Figure 30 It is formed by the residue of the hard mask between the two.

[0290] The mask pattern MPT may also include a third part, MPT3. Although the first part MPT1, the second part MPT2, and the third part MPT3 are described separately in this specification for ease of explanation, the first part MPT1, the second part MPT2, and the third part MPT3 may be physically connected to each other as a single component.

[0291] The third part MPT3 can be disposed on the second part MPT2. The third part MPT3 can be positioned opposite the first part MPT1, and the second part MPT2 is located between the third part MPT3 and the first part MPT1. The third part MPT3 can be a part of the third coating film 840.

[0292] In one or more embodiments, the third portion MPT3 may have an inverted conical shape. For example, the width of the bottom surface of the third portion MPT3 may be smaller than the width of the top surface of the third portion MPT3. That is, the width of the third portion MPT3 may narrow from the top surface of the third portion MPT3 toward the bottom surface. The side surface of the third portion MPT3 may be an inclined surface that slopes inward from the top surface of the third portion MPT3 toward the bottom surface. The fourth angle θ4, which is the interior angle formed by the bottom surface and the side surface of the third portion MPT3, may be an obtuse angle. In one or more embodiments, the fourth angle θ4 may be approximately greater than 90 degrees and less than or equal to 93 degrees, but is not limited thereto.

[0293] In another embodiment, the third portion MPT3 may have a vertical shape. For example, the width of the bottom surface of the third portion MPT3 may be the same as the width of its top surface. In this case, the side surface of the third portion MPT3 may be a vertical plane, and the fourth angle θ4, which is the interior angle formed by the bottom surface and the side surface of the third portion MPT3, may be a right angle.

[0294] In the deposition mask 800 according to this embodiment, the side tilt angles of the first part MPT1, the second part MPT2, and the third part MPT3 can be different from each other. For example, the fourth angle θ4, which is the side tilt angle of the third part MPT3, can be smaller than the second angle θ2, which is the side tilt angle of the second part MPT2, and the first angle θ1, which is the side tilt angle of the first part MPT1.

[0295] Figure 21 This is a cross-sectional view showing a deposition mask according to yet another embodiment.

[0296] Reference Figure 21 The deposition mask 800 according to this embodiment and the one according to reference Figure 16The difference between the deposition mask 800 in the embodiments described above is that the first portion MPT1 includes a first sub-portion MPT11 and a second sub-portion MPT12.

[0297] In detail, the first portion MPT1 of the mask pattern MPT may include a first sub-portion MPT11 and a second sub-portion MPT12. In this specification, although for ease of explanation, the first sub-portion MPT11 and the second sub-portion MPT12 and the second portion MPT2 of the first portion MPT1 are described separately, the first sub-portion MPT11 and the second sub-portion MPT12 and the second portion MPT2 of the first portion MPT1 may be physically connected to each other as a single component.

[0298] The first sub-part MPT11 may be located below the second sub-part MPT12. For example, the first sub-part MPT11 may be positioned opposite the second sub-part MPT2, and the second sub-part MPT12 may be located between the first sub-part MPT11 and the second sub-part MPT2.

[0299] The first sub-part MPT11 may include a first surface MPT11a, a second surface MPT11b positioned opposite to the first surface MPT11a, and a first side surface MPT11c positioned between the first surface MPT11a and the second surface MPT11b. The first surface MPT11a of the first sub-part MPT11 is the surface facing the mask substrate 810, the second surface MPT11b of the first sub-part MPT11 is the surface facing the second sub-part MPT12, and the first side surface MPT11c of the first sub-part MPT11 is the surface that connects the first surface MPT11a to the second surface MPT11b and contacts the hole pattern HPT.

[0300] The first sub-part MPT11 may have an inverted conical shape. For example, the width of the first surface MPT11a of the first sub-part MPT11 may be smaller than the width of the second surface MPT11b of the first sub-part MPT11. That is, the width of the first sub-part MPT11 may narrow as it moves from the second surface MPT11b toward its first surface MPT11a. The first side surface MPT11c of the first sub-part MPT11 may be an inclined surface that slopes inward in the first sub-part MPT11 in the inward direction as it moves from the second surface MPT11b toward the first surface MPT11a of the first sub-part MPT11. The first angle θ11, which is the interior angle formed by the first surface MPT11a and the first side surface MPT11c of the first sub-part MPT11, may be an obtuse angle. In one or more embodiments, the first-first angle θ11 may be approximately greater than 90 degrees and less than 100 degrees, and preferably, the first-first angle θ11 may be approximately greater than or equal to 95 degrees and less than or equal to 97 degrees, but is not limited thereto.

[0301] The second sub-part MPT12 can be located above the first sub-part MPT11. For example, the second sub-part MPT12 can be located between the first sub-part MPT11 and the second sub-part MPT2.

[0302] The second sub-part MPT12 may include a first surface MPT12a, a second surface MPT12b positioned opposite to the first surface MPT12a, and a first side surface MPT12c positioned between the first surface MPT12a and the second surface MPT12b. The first surface MPT12a of the second sub-part MPT12 is the surface facing the first sub-part MPT11, the second surface MPT12b of the second sub-part MPT12 is the surface facing the second sub-part MPT2, and the first side surface MPT12c of the second sub-part MPT12 is the surface that connects the first surface MPT12a to the second surface MPT12b and contacts the hole pattern HPT.

[0303] The second sub-part MPT12 may have an inverted conical shape. For example, the width of the first surface MPT12a of the second sub-part MPT12 may be smaller than the width of the second surface MPT12b of the second sub-part MPT12. That is, the width of the second sub-part MPT12 may narrow as it moves from the second surface MPT12b toward the first surface MPT12a of the second sub-part MPT12. The first side surface MPT12c of the second sub-part MPT12 may be an inclined surface that slopes inward in the direction of the second sub-part MPT12 as it moves from the second surface MPT12b toward the first surface MPT12a of the second sub-part MPT12. The first-second angle θ12, which is the interior angle formed by the first surface MPT12a and the first side surface MPT12c of the second sub-part MPT12, may be an obtuse angle. In one or more embodiments, the first-second angle θ12 may be approximately greater than 90 degrees and less than 100 degrees, and preferably, the first-second angle θ12 may be approximately greater than or equal to 93 degrees and less than or equal to 95 degrees, but is not limited thereto.

[0304] In the deposition mask 800 according to this embodiment, the tilt angles of the first side surface MPT11c of the first sub-part MPT11, the tilt angle of the first side surface MPT12c of the second sub-part MPT12, and the tilt angle of the first side surface MPT2c of the second sub-part MPT2 can be different from each other. For example, the second angle θ2, which is the tilt angle of the first surface MPT2c of the second sub-part MPT2, can be smaller than the first-second angle θ12, which is the tilt angle of the first side surface MPT12c of the second sub-part MPT12, and the first-first angle θ11, which is the tilt angle of the first side surface MPT11c of the first sub-part MPT11, can be larger than the first-second angle θ12, which is the tilt angle of the first side surface MPT12c of the second sub-part MPT12.

[0305] In this embodiment, although the first portion MPT1 is shown by way of example as being divided into two sub-parts such as a first sub-part MPT11 and a second sub-part MPT12, this disclosure is not limited thereto. For example, the first portion MPT1 may be divided into three or more sub-parts. The number of sub-parts of the first portion MPT1 may be determined according to the method S1 for manufacturing the deposition mask, which will be described later (see [link to method S1]). Figure 22 In step S500 of forming a mask pattern and a hole pattern in the second coated film (see) Figure 22 The middle part of the process mainly involves etching the second coating film to form the mask pattern and hole pattern in step S530 (see...). Figure 29 The number of repetitions varies.

[0306] The following describes a method for fabricating a mask pattern MPT for a deposition mask 800 in the shape of an inverted cone.

[0307] Figure 22 This is a flowchart illustrating a method for manufacturing a deposition mask according to one or more embodiments. Figure 23 It is shown Figure 22 The sectional view of step S100. Figure 24 It is shown Figure 22 The sectional view of step S200. Figure 25 It is shown Figure 22 The sectional view of step S300. Figure 26 It is shown Figure 22 The sectional view of step S400. Figure 27 It is shown Figure 22 The sectional view of step S500. Figure 28 It is shown Figure 22 The sectional view of step S600.

[0308] Apart from Figure 15 In addition, refer to Figures 22 to 28 A method S1 for manufacturing a deposition mask according to one or more embodiments may include: preparing a mask substrate (step S100); forming a first coating film on the mask substrate (step S200); forming a second alignment mark on the first coating film (step S300); forming a second coating film on the second alignment mark and the first coating film (step S400); forming a mask pattern and a hole pattern in the second coating film (step S500); and forming a mask opening (step S600).

[0309] First, such as Figure 23 As shown, in step S100 of preparing the mask substrate, a mask substrate 810 can be prepared. As described above, the mask substrate 810 can be made of a semiconductor wafer. Since the mask substrate 810 has already been described above, a description of the mask substrate 810 will be omitted here.

[0310] Second, such as Figure 24 As shown, in step S200 of forming the first coating film on the mask substrate, a first coating film 820 may be deposited on the mask substrate 810. The first coating film 820 may cover not only the top surface of the mask substrate 810, but also the bottom surface and side surfaces of the mask substrate 810.

[0311] The first coated film 820 can be an inorganic film containing inorganic materials as described above. For example, the first coated film 820 can contain silicon oxide (SiO2). x ).

[0312] Third, such as Figure 25As shown, in step S300 of forming the second alignment mark on the first coating film, the alignment mark material layer can be patterned on the first coating film 820.

[0313] For example, after forming an alignment mark material layer for forming the second alignment mark AMK2 on the first coating film 820, the alignment mark material layer can be patterned by a photolithography process to form the second alignment mark AMK2. The alignment mark material layer may contain, but is not limited to, metal.

[0314] Fourth, such as Figure 26 As shown, in step S400, where a second coating film is formed on the second alignment mark AMK2 and the first coating film 820, a second coating film 830 can be deposited on the second alignment mark AMK2 and the first coating film 820. The second coating film 830 can cover not only the top surface of the mask substrate 810, but also the bottom surface and side surfaces of the mask substrate 810.

[0315] The second coating film 830 can be an inorganic film containing inorganic materials as described above. For example, the second coating film 830 can contain silicon nitride (SiN). x ).

[0316] In one or more embodiments, the second coating film 830 may contain low-stress nitride (LSN). When the second coating film 830 contains low-stress nitride, the second coating film 830 may be formed by a low-pressure chemical vapor deposition (LPCVD) process, but is not limited thereto.

[0317] Fifth, such as Figure 27 As shown, in step S500 of forming a mask pattern and a hole pattern in the second coating film, the second coating film 830 can be patterned to form a mask pattern MPT and a hole pattern HPT.

[0318] Patterning of the second coating film 830 can be performed using a dry etching process. (See below for further details.) Figure 29 The steps of forming the mask pattern and hole pattern in the second coated film are described in further detail, such as S500.

[0319] Sixth, such as Figure 28 As shown, in step S600 of forming the mask opening, the portion of the deposited mask 800 below the hole pattern HPT and the mask pattern MPT can be etched to form the mask opening MOP. For example, as referenced above. Figure 15 As described, this can be achieved by etching the second undercoat 832, the first undercoat 822, the mask substrate 810, and the first topcoat 821 (e.g., see...). Figure 15 To form the mask opening MOP.

[0320] Mask opening MOPs can be formed using a wet etching process. Therefore, although the inner surface of the mask opening MOP is depicted as a vertical plane in the accompanying drawings, the shape of the mask opening MOP is not limited to this. For example, due to the isotropic nature of wet etching, the inner surface of the mask opening MOP can be inclined or curved.

[0321] Figure 29 It is shown Figure 22 The flowchart shows the detailed sub-steps of step S500. Figure 30 It is shown Figure 29 The sectional view of step S510. Figure 31 It is shown Figure 29 The sectional view of step S520. Figure 32 and Figure 33 It is shown Figure 29 The sectional view of step S530. Figures 30 to 33 Only a portion of the deposition mask 800 is shown; for example, it is shown with... Figure 27 An enlarged view of the part corresponding to part B shown in the diagram.

[0322] In addition to reference Figure 22 In addition, refer to Figures 29 to 33 Step S500, which involves forming a mask pattern and a hole pattern in the second coating film, may include: partially etching the second coating film to form a first trench (step S510); forming a passivation film on the side surface of the first trench (step S520); and primarily etching the second coating film to form a hole pattern and a mask pattern (step S530). Hereinafter, step S510, which involves partially etching the second coating film to form the first trench, may be referred to as a partial etching step, and step S530, which involves primarily etching the second coating film to form a hole pattern and a mask pattern, may be referred to as a main etching step.

[0323] First, such as Figure 30 As shown, in step S510 (partial etching step) of forming the first trench by partially etching the second coating film, a photoresist PR can be placed on the second coating film 830. The photoresist PR can be configured to overlap with the portion where the mask pattern MPT is to be formed, and can be configured not to overlap with the portion where the hole pattern HPT is to be formed.

[0324] In one or more other embodiments, a hard mask may be further disposed between the second coating film 830 and the photoresist PR. In this case, the hard mask can be retained and formed according to the above reference. Figure 20 The third coating film 840 of the deposition mask 800 described in another embodiment. In yet another embodiment, a hard mask may be used instead of the photoresist PR.

[0325] Next, a portion of the second coating film 830 can be etched using an etching apparatus (HD) to form the first trench GRV1. For example, the portion of the second coating film 830 without photoresist PR can be etched to form the first trench GRV1. The local etching step can be performed using a dry etching process, and in the local etching step, the second coating film 830 can be etched only to a certain depth of its entire depth.

[0326] Secondly, such as Figure 31 As shown, in step S520, when a passivation film is formed on the side surface of the first trench, a passivation film PVX can be formed on the side surface of the first trench GRV1 and the side surface of the photoresist PR.

[0327] The passivation film PVX can contain fluorocarbons (C) x F y Polymers of this type. For example, PVX passivation films can use fluorocarbons (C4F8) such as octafluorocyclobutane or octafluorocyclopentene. x F y Formation of source gases.

[0328] The passivation film PVX can prevent the second part of the mask pattern MPT, MPT2 (see...). Figure 33 The photoresist PR is etched during the main etching step.

[0329] Third, such as Figure 32 and Figure 33 As shown, in step S530 (main etching step), where the second coating film is primarily etched to form the hole pattern HPT and mask pattern, the second coating film 830 can be completely etched by the etching apparatus HD to form the hole pattern HPT and mask pattern MPT. For example, the portion of the second coating film 830 disposed below the first trench GRV1 can be etched to form the second trench GRV2, and the portion of the second coating film 830 disposed below the second trench GRV2 can be etched to form the third trench GRV3. The main etching step can be performed by a dry etching process, and in the main etching step, the second coating film 830 can ultimately be etched to its full depth.

[0330] For example, the second portion MPT2 of the mask pattern MPT can be formed on one side of the first trench GRV1 formed by the local etching step, the second sub-portion MPT12 of the first portion MPT1 of the mask pattern MPT can be formed on one side of the second trench GRV2 formed by the first main etching step S530a, and the first sub-portion MPT11 of the first portion MPT1 of the mask pattern MPT can be formed on one side of the third trench GRV3 formed by the second main etching step S530b.

[0331] The accompanying drawings illustrate an example of performing two main etching steps. However, this is not a limitation; the main etching steps can be performed once or more than twice, and in this case, the number of trenches or the number of sub-parts of the first portion MPT1 of the mask pattern MPT can vary. For example, when two main etching steps are performed, a reference can be formed. Figure 21 The described deposition mask, according to another embodiment, can form a reference when a primary etching step is performed. Figure 16 Deposition masks described according to one or more embodiments.

[0332] A portion of the first coating film 820 may be etched by over-etching during the main etching step. In this case, a fourth trench GRV4 can be formed in the first coating film 820.

[0333] In the method S1 for manufacturing a deposition mask according to this embodiment, the etching apparatus HD can generate plasma using an inductively coupled plasma (ICP) method. This method increases the plasma density and relatively reduces the energy of charged particles, thereby increasing isotropic properties.

[0334] In the method S1 for manufacturing a deposition mask according to this embodiment, the etching apparatus HD can apply different pressures, source power (or RF power), and bias power in the chamber during the local etching step and the main etching step.

[0335] For example, the pressure inside the chamber during the local etching step can be lower than the pressure inside the chamber during the main etching step. The source power during the local etching step can be lower than the source power during the main etching step. The bias power during the local etching step can be higher than the bias power during the main etching step. Therefore, the lateral tilt angle of the second portion MPT2 of the mask pattern MPT can be formed to be smaller than the lateral tilt angle of the first portion MPT1.

[0336] In another example, even during the main etching step, the etching apparatus HD can change the pressure, source power (or RF power), and bias power within the chamber. For example, the pressure within the chamber in the first main etching step S530a can be lower than the pressure within the chamber in the second main etching step S530b. The source power in the first main etching step S530a can be lower than the source power in the second main etching step S530b. The bias power in the first main etching step S530a can be greater than the bias power in the second main etching step S530b. Therefore, the lateral tilt angle of the second sub-part MPT12 of the mask pattern MPT can be formed to be smaller than the lateral tilt angle of the first sub-part MPT11.

[0337] According to the method S1 for manufacturing a deposition mask based on this embodiment, the shapes of the mask pattern MPT and the hole pattern HPT can be controlled by controlling the pressure inside the chamber, the source power, and the bias power of the etching apparatus HD. Therefore, a deposition mask 800 including a mask pattern MPT having an inverted conical shape can be formed.

[0338] Specifically, as the pressure within the chamber increases, the number of collisions between ions and neutral particles can increase, thus reducing the directionality of the ions and consequently increasing isotropy. Additionally, as the source power increases, the plasma density can increase, allowing isotropy to increase due to the relatively low energy of the charged particles. Furthermore, as the bias power decreases, the energy of the charged particles can decrease, further increasing isotropy.

[0339] During the main etching step, a fluorine-based reactive gas can be additionally injected into the chamber by the etching apparatus HD. For example, the fluorine-based reactive gas can be sulfur hexafluoride (SF6), tetrafluoromethane (CF4), trifluoromethane (CHF3), octafluorocyclobutane (C4F8), and / or nitrogen trifluoride (NF3).

[0340] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles and scope of this disclosure. Therefore, the embodiments of this disclosure are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A deposition mask, the deposition mask comprising: Mask substrate, including semiconductor wafers; A first coating film is applied to the mask substrate; as well as A second coating film is applied to the first coating film and includes alternating hole patterns and mask patterns. The upper width of the hole pattern is smaller than the lower width of the hole pattern.

2. The deposition mask according to claim 1, wherein, The first coating film comprises silicon oxide.

3. The deposition mask according to claim 1, wherein, The second coating film comprises silicon nitride.

4. The deposition mask according to claim 3, wherein, The second coating film comprises a low-stress nitride.

5. The deposition mask of claim 1, further comprising a mask opening penetrating at least a portion of the mask substrate and at least a portion of the first coating film. in, The mask opening is connected to the hole pattern.

6. The deposition mask according to claim 5, wherein, The mask substrate includes a first surface and a second surface opposite to the first surface. The first coating film includes a first upper coating film on the first surface and a first lower coating film on the second surface. The second coating film includes a second upper coating film on the first surface and a second lower coating film on the second surface, and The mask opening penetrates the second lower coating film, the first lower coating film, the mask substrate, and the first upper coating film.

7. The deposition mask according to claim 1, wherein, The mask pattern includes a first portion and a second portion on the first portion, and The upper width of the first part is greater than the lower width of the first part.

8. The deposition mask according to claim 7, wherein, The first angle between the bottom surface and the side surface of the first part is different from the second angle between the bottom surface and the side surface of the second part.

9. The deposition mask according to claim 8, wherein, The first angle is greater than the second angle.

10. The deposition mask according to claim 7, wherein, The angle between the bottom surface and the side surface of the first part is an obtuse angle.

11. The deposition mask according to claim 10, wherein, The side surface of the first portion is an inclined surface that slopes inward in the first portion from the top surface to the bottom surface.

12. The deposition mask according to claim 7, wherein, The upper width of the second part is greater than or equal to the lower width of the second part.

13. The deposition mask according to claim 12, wherein, The angle between the bottom surface and the side surface of the second part is a right angle or an obtuse angle.

14. The deposition mask according to claim 13, wherein, The side surface of the second part is an inclined surface that slopes inward in the second part from the top surface to the bottom surface.

15. The deposition mask according to claim 7, wherein, The first part includes a first sub-part and a second sub-part on the first sub-part, and The third angle between the bottom surface and the side surface of the first sub-part is different from the fourth angle between the bottom surface and the side surface of the second sub-part.

16. The deposition mask of claim 1, further comprising alignment marks on the mask substrate. in, The alignment mark is between the mask substrate and the first coating film or between the first coating film and the second coating film.

17. A method for manufacturing a deposition mask, the method comprising the steps of: A first coating film is formed on a mask substrate including a semiconductor wafer, and a second coating film is formed on the first coating film; A mask pattern and a hole pattern are formed in the second coating film; as well as Forming a mask opening that penetrates the mask substrate and the first coating film. The step of forming the mask pattern and the hole pattern in the second coating film includes: partially etching the second coating film to form a first trench; forming a passivation film on the side surface of the first trench; and primarily etching the remaining second coating film below the first trench to form the hole pattern and the mask pattern.

18. The method according to claim 17, wherein, The second coating film comprises a low-stress nitride, and The second coating film is formed by a low-pressure chemical vapor deposition process.

19. The method of claim 17, wherein, The passivation film comprises a fluorocarbon polymer.

20. An electronic device, the electronic device comprising: A processor used to provide input image data; as well as A display device for displaying an image based on the input image. The display device is manufactured using the deposition mask according to claim 1.

Images