Task synchronization method for virtual multi-core processor of satellite-borne soft platform

Abstract

The invention discloses a satellite-borne soft platform virtual multi-core processor task synchronization method, which belongs to the technical field of ground test virtual simulation, and comprises the following steps: determining a time reference of system operation; and each core performs task cycle scheduling by using a system running time reference. According to the method, the synchronization of the task level of the virtual multi-core processor of the satellite-borne soft platform is realized by determining the running time reference of the system and controlling the starting and periodic execution of the multi-core task.

Description

Technical Field

[0001] This invention belongs to the field of ground-based test virtual simulation technology, and in particular relates to a method for synchronizing virtual multi-core processor tasks on a spaceborne software platform. Background Technology

[0002] Due to the unique nature of spaceborne equipment, its application software requires thorough testing on the ground. However, it's difficult to have all the necessary hardware available for testing. Therefore, establishing a spaceborne software platform testing environment allows for testing using a desktop environment. The spaceborne software platform utilizes software virtual simulation technology to digitally model and simulate physical equipment. It establishes and drives a simulation model of the real physical equipment on a digital system, achieving a mapping from the physical system to the digital system. Software running on the real physical equipment can run directly on the digital simulation model without modification, and the software's operation process, intermediate states, and execution results are consistent with the real physical equipment. The virtual processor, simulating the spaceborne equipment's hardware processor, is a crucial component of the spaceborne software platform. The virtual processor primarily simulates a real spaceborne embedded CPU with a specific instruction set architecture, such as the Sparc V8 instruction set architecture. Its main function is to convert the binary machine instructions of the specific embedded processor (target platform) into binary machine instructions of the desktop processor (host platform) for direct execution.

[0003] With the rapid development of aerospace technology, aerospace missions are becoming increasingly complex. As a core component of spacecraft equipment, embedded processors are increasingly using multi-core processors with higher parallelism and stronger performance. Real physical devices use multiple phase-locked loops (PLLs) to provide independent and synchronized clock signals for each core as a time reference. Virtual processor models lack such corresponding components to achieve this function, necessitating a solution to the problem of inter-core task synchronization in virtual multi-core processors on spaceborne software platforms. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a method for synchronizing virtual multi-core processor tasks on a spaceborne software platform, thereby achieving task-level synchronization of virtual multi-core processors on a spaceborne software platform.

[0005] The objective of this invention is achieved through the following technical solution: a method for synchronizing virtual multi-core processor tasks on a spaceborne software platform, comprising: determining the system's operating time base; and each core using the system's operating time base for task cycle scheduling.

[0006] In the above-mentioned spaceborne software platform virtual multi-core processor task synchronization method, determining the system running time base includes: obtaining the instruction cycle number of each instruction according to the preset processor chip hardware manual, selecting one core as the master core, and defining the other cores as slave cores; the master core records the instruction cycle of each instruction executed in real time, and obtains the system running time base according to the instruction cycle of each instruction and the set clock frequency; the slave cores obtain the system running time base calculated by the master core in real time through inter-core communication.

[0007] In the above-mentioned virtual multi-core processor task synchronization method of the spaceborne software platform, core 0 is selected as the master core, and the cores other than the master core are slave cores.

[0008] In the above-mentioned method for synchronizing tasks using a virtual multi-core processor on a spaceborne software platform, the system's time base is obtained using the following formula:

[0009] Tm=(∑Cn) / F;

[0010] Where Tm is the system's operating time base, Cn is the instruction cycle of each instruction, and F is the set clock frequency.

[0011] In the above-mentioned virtual multi-core processor task synchronization method of the spaceborne software platform, the task periodic scheduling of each core using the system runtime base includes: Step S1: Preset the counting interrupt time Ti and the periodic scheduling time Tn of each task; Step S2: Each core determines whether the counting interrupt time has been reached according to the system runtime base. If it has been reached, proceed to step S3; Step S3: Increment the system counter by 1 and save the system runtime base at this moment; Step S4: Determine whether the increment of the system counter reaches Tn / Ti. If it has, proceed to step S5; Step S5: Call the periodic task.

[0012] In the above-mentioned virtual multi-core processor task synchronization method of the spaceborne software platform, the periodic scheduling time Tn of each task is an integer multiple of the counting interrupt time Ti.

[0013] A spaceborne software platform virtual multi-core processor task synchronization system includes: a first module for determining the system's operating time base; and a second module for each core to perform task cycle scheduling using the system's operating time base.

[0014] In the aforementioned spaceborne software platform virtual multi-core processor task synchronization system, determining the system's operating time reference includes: obtaining the instruction cycle number of each instruction according to the preset processor chip hardware manual, selecting one core as the master core, and defining the other cores as slave cores; the master core records the instruction cycle of each executed instruction in real time, and obtains the system's operating time reference based on the instruction cycle of each instruction and the set clock frequency; the slave cores obtain the system's operating time reference calculated by the master core in real time through inter-core communication.

[0015] In the aforementioned spaceborne software platform virtual multi-core processor task synchronization system, core 0 is selected as the master core, and the cores other than the master core are slave cores.

[0016] The system's operating time base is obtained using the following formula:

[0017] Tm=(∑Cn) / F;

[0018] Where Tm is the system's operating time base, Cn is the instruction cycle of each instruction, and F is the set clock frequency.

[0019] An electronic device includes: a memory for storing computer-readable instructions; and a processor for executing the computer-readable instructions to perform a spaceborne software platform virtual multi-core processor task synchronization method.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] (1) On the one hand, the present invention provides a unified system running time benchmark for the system as the source of interrupts for the scheduling of tasks of each core, and on the other hand, avoids the running consumption caused by each core calculating the simulation time at the same time, thereby improving the running efficiency of the slave core.

[0022] (2) Based on the system running time benchmark, this invention ensures that the execution cycle time of each core task is synchronized and is executed in full accordance with the timing of the original hardware design. Attached Figure Description

[0023] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0024] Figure 1 This is a flowchart of the virtual multi-core processor task synchronization method for a spaceborne software platform provided in this embodiment of the invention;

[0025] Figure 2 This is a flowchart of the virtual multi-core processor task scheduling provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of multi-core task runtime synchronization provided in an embodiment of the present invention;

[0027] Figure 4 This is a structural block diagram of an exemplary computing device provided in an embodiment of the present invention. Detailed Implementation

[0028] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] Figure 1 This is a flowchart of a method for synchronizing virtual multi-core processor tasks on a spaceborne software platform provided in an embodiment of the present invention. For example... Figure 1 As shown, the virtual multi-core processor task synchronization method of the spaceborne software platform includes: determining the system's operating time base; and each core using the system's operating time base for task cycle scheduling.

[0030] Determining the system's operating time base includes: obtaining the instruction cycle number of each instruction based on the preset processor chip hardware manual, selecting one core as the master core, and defining the other cores as slave cores; the master core records the instruction cycle of each executed instruction in real time, and obtains the system's operating time base based on the instruction cycle of each instruction and the set clock frequency; the slave cores obtain the system's operating time base calculated by the master core through inter-core communication.

[0031] Core 0 is selected as the master core, and all other cores are designated as slave cores.

[0032] The system's operating time base is obtained using the following formula:

[0033] Tm=(∑Cn) / F;

[0034] Where Tm is the system's operating time base, Cn is the instruction cycle of each instruction, and F is the set clock frequency.

[0035] Each core uses the system runtime base for task periodic scheduling, including: Step S1: Preset the counting interrupt time Ti and the periodic scheduling time Tn for each task; Step S2: Each core determines whether the counting interrupt time has been reached based on the system runtime base. If it has, proceed to step S3; Step S3: Increment the system counter by 1 and save the current system runtime base; Step S4: Determine whether the increment of the system counter reaches Tn / Ti. If it has, proceed to step S5; Step S5: Call the periodic task.

[0036] One core is defined as the master core, and the others are slave cores. Both the master and slave cores run embedded software, and the specific allocation method is specified by the software designer. If the multiple cores are completely equal, any core can be selected as the master core. Generally, core 0 is the default master core, and all other cores are slave cores.

[0037] The time reference for system operation is calculated using the master core, and the time reference for system operation calculated by the master core is obtained from the kernel through inter-core communication.

[0038] Processor instruction sets typically include several categories such as load / memory instructions, arithmetic / logical shift instructions, control transfer instructions, read / write control register instructions, floating-point operation instructions, and other instructions. For a specific instruction set architecture, the types of instructions are fixed, and the instruction cycle Cn of each instruction is also fixed. The master processor records the instruction cycle Cn of each instruction it has executed, and uses the model's set clock frequency F to calculate the current system running time base Tm.

[0039] Tm=(∑Cn) / F;

[0040] As execution progresses, Tm will start from 0 and gradually increase, which is equivalent to a system clock and serves as the time base for multi-core task scheduling.

[0041] Each core (including the master core) uses the system simulation time as the time base for periodic task execution scheduling. See the attached flowchart for the task scheduling process. Figure 2 .

[0042] Step 1. The system initializes a unified counting interrupt time Ti and a periodic scheduling time Tn for each task. The values ​​of Tn and Ti are determined by the system design. Generally, Tn is an integer multiple of Ti.

[0043] Step 2. Each verification time obtains the current system running time, determines whether the count interrupt time has been reached, and if it has been reached, proceeds to step 3. Regardless of whether it has been reached, proceeds to the next time step for judgment.

[0044] Step 3. The counting interrupt time has been reached. The system counter increments by 1 and saves the current system running time base for calculating the conditions for the next counting interrupt.

[0045] Step 4. Use the system counter value for task scheduling. When the increment of the system counter reaches Tn / Ti, proceed to step 5; otherwise, do not process.

[0046] Step 5. Indicates that the time interval has reached the task scheduling cycle, and calls the periodic task.

[0047] Since the system runtime baseline is calculated by the master core based on the instruction cycles it has executed, the actual execution time of a master core task is generally equal to the expected execution time. Slave cores, running at full speed without constraints or additional overhead waiting during their task cycles, will have actual execution times shorter than their expected execution times. However, regardless of the execution time of each core, the scheduling of each cycle is controlled by the system runtime baseline, ensuring that the task cycle scheduling of each core is completed according to the system's designed timing sequence.

[0048] Taking a certain type of spaceborne software platform virtual multi-core processor as an example, it uses the SPARCV8 instruction set architecture, has 4 cores, and its main frequency is 400MHz.

[0049] Step 1: Determine the system runtime baseline

[0050] Sub-step 1: According to the processor chip hardware manual, the instruction cycle count of each instruction can be obtained, and the instruction cycle count of all instructions can be formed and recorded; select core 0 as the main core, and initialize the cumulative instruction cycle count to 0.

[0051] Sub-step 2: When verifying the main function, record the currently executed instruction and obtain its instruction cycle count. Then, the current cumulative instruction cycle count = the previous cumulative instruction cycle count + the instruction cycle count of the currently executed instruction.

[0052] Sub-step 3: The main core calculates the current system runtime baseline in real time. Here, "real time" is a conceptual definition; the specific calculation frequency depends on the host machine's performance and the runtime of the virtual multi-core processor. In this example, the main core allocates a separate thread to calculate the current system runtime baseline.

[0053] At a certain calculation moment, the current cumulative instruction cycles are 1200 instruction cycles. Therefore, the current system runtime base Tm = 1200 / 400MHz = 3 × 10⁻⁶. -6 s = 3μm, meaning the current system runtime base is 3μm; at another calculation point, the current cumulative instruction cycles are 20,000, then the current system runtime base Tm = 20,000 / 400MHz = 5 × 10 -5 s = 50μm, meaning the current system running time base is 50μm; and so on.

[0054] Sub-step 4: Each slave core obtains the current system runtime base through inter-core communication. Inter-core communication is implemented using shared memory. The master core stores the current system runtime base in the shared memory address in real time, and each slave core accesses the shared memory address to obtain the current system runtime base.

[0055] Step 2: Each core uses the system runtime base to perform task cycle scheduling.

[0056] Sub-step 1: Initialization. According to the system design, the counting interrupt time Ti is determined to be 5ms. Tasks and task cycles are allocated to each core. The master core (core 0) executes task T0 with a designed task cycle of 50ms. The slave core (taking core 1 as an example) executes task T1 with a designed task cycle of 100ms.

[0057] Sub-step 2: Each core determines whether the counting interrupt time has arrived based on the system running time base. That is, it determines whether the difference between the current system running time base and the system running time base at the last counting interrupt time is greater than or equal to the counting interrupt time. The reason for using "greater than or equal to" is that it cannot be guaranteed that the difference is exactly an integer multiple. Also, because the time precision of this difference is higher than that of the counting interrupt event, even if it is not an integer multiple, the difference can be ignored.

[0058] Sub-step 3: If the interrupt timer is reached, the system counter will be incremented by 1, and the system runtime baseline for this interrupt timer will be saved to determine the conditions for the next interrupt timer. Regardless of whether the interrupt timer is reached,

[0059] extern long sys_time; / / Real-time system runtime benchmark

[0060] extern long sys_time_pre; / / The system runtime baseline at the time of the last counter increment.

[0061] if(long sys_time-long sys_time_pre==Ti)

[0062] {

[0063] long sys_time_pre=sys_time;

[0064] counter = +counter;

[0065] }

[0066] Sub-step 4: Determine whether the time period for the periodic task execution has been reached based on the system counter. For the master core task T0, T0 executes once every 10 intervals (task period 50ms / count interrupt time 5ms). For the slave core task T1, T1 executes once every 20 intervals (task period 100ms / count interrupt time 5ms). If the time period is reached, proceed to step 5.

[0067] Sub-step 5: Invoke the periodic task.

[0068] Execution result as follows Figure 3The expected execution time of T0 is 20ms, and the actual execution time is 20ms. The designed execution time of T1 is 60ms, and the actual execution time is 30ms. However, both T0 and T1 are scheduled according to their respective design cycles (50ms and 100ms).

[0069] This embodiment also provides a spaceborne software platform virtual multi-core processor task synchronization system, which includes: a first module for determining the system's operating time base; and a second module for each core to use the system's operating time base for task cycle scheduling.

[0070] This embodiment also provides an electronic device, including: a memory for storing computer-readable instructions; and a processor for running the computer-readable instructions and executing a spaceborne software platform virtual multi-core processor task synchronization method.

[0071] This embodiment achieves task-level synchronization of the virtual multi-core processor on the spaceborne software platform by determining the system's runtime baseline and controlling the startup and periodic execution of multi-core tasks.

[0072] This embodiment provides a unified system runtime benchmark as the source of interrupts for task scheduling of each core, and avoids the runtime overhead caused by each core calculating its own simulation time at the same time, thus improving the running efficiency of the slave cores. Based on the system runtime benchmark, this embodiment ensures that the execution cycle time of each core task is synchronized and executed completely in accordance with the timing of the original hardware design.

[0073] Figure 4 A structural block diagram of an exemplary computing device that can be used to practice embodiments of the present invention is shown. It will be understood that the clients, agents, and / or servers described in this disclosure can utilize... Figure 4 The computing device shown is used to implement this. For example... Figure 4As shown, the computing device may include: a CPU (Central Processing Unit) 401, RAM (Random Access Memory) 402, ROM (Read-Only Memory) 403, a system bus 404, a hard disk controller 405, a keyboard controller 406, a serial interface controller 407, a parallel interface controller 408, a display controller 409, a hard disk 410, a keyboard 411, a serial external device 412, a parallel external device 413, and a display 414. Among these components, the CPU 401, RAM 402, ROM 403, hard disk controller 405, keyboard controller 406, serial interface controller 407, parallel interface controller 408, and display controller 409 are coupled to the system bus 404. The hard disk 410 is coupled to the hard disk controller 405, the keyboard 411 is coupled to the keyboard controller 406, the serial external device 412 is coupled to the serial interface controller 407, the parallel external device 413 is coupled to the parallel interface controller 408, and the display 414 is coupled to the display controller 409.

[0074] Several embodiments of the invention have been described above by way of example. At least some of the different blocks, operations, and techniques described above can be executed by using hardware, with a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When executed by a processor executing firmware and software instructions, the software or firmware instructions can be stored in any computer-readable storage, such as a disk, optical disk, or other storage medium, in a RAM or ROM or flash memory, a processor, a hard disk, an optical disk, a magnetic disk, etc. Similarly, the software and firmware instructions can be transmitted to a user or system by any known or desired transmission method, including, for example, on a computer-readable disk or other portable computer storage mechanism or via a communication medium. Communication media typically embody computer-readable instructions, data structures, program modules, or other data in modulated data signals, such as carrier waves or other transmission mechanisms. By way of example, and not limitation, communication media include wired media such as wired networks or single-wire connections, and wireless media such as sound, radio frequencies, infrared, and other wireless media. Thus, software and firmware instructions can be transmitted to the user or system via communication channels such as telephone lines, DSL lines, cable television lines, fiber optic cables, wireless channels, the Internet, etc. (such software is provided via portable storage media, which are considered identical or interchangeable). Software or firmware instructions may include readable instructions that, when executed by the processor, cause the processor to perform different actions.

[0075] It should be noted that embodiments of the present invention can be implemented using software, hardware, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the methods and systems described above can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of this embodiment can be implemented using hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or can be implemented using software executed by various types of processors, or a combination of the aforementioned hardware circuitry and software, such as firmware.

[0076] The communication networks mentioned in the specification may include various types of networks, including but not limited to local area networks (“LAN”), wide area networks (“WAN”), IP-based networks (e.g., the Internet) and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

[0077] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Rather, the steps depicted in the flowchart may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, or one step may be broken down into multiple steps.

[0078] While the invention has been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A method for synchronizing tasks using a virtual multi-core processor on a spaceborne software platform, characterized in that... include: Determine the time base for system operation; Each core uses the system runtime base for task cycle scheduling.

2. The method for synchronizing virtual multi-core processor tasks on a spaceborne software platform according to claim 1, characterized in that: Determining the time base for system operation includes: Based on the instruction cycle number of each instruction obtained from the preset processor chip hardware manual, one core is selected as the master core, and the other cores are defined as slave cores; The master verifier records the instruction cycle of each executed instruction and obtains the system's operating time base based on the instruction cycle of each instruction and the set clock frequency. The system's operating time reference is obtained from the master core through inter-core communication.

3. The method for synchronizing virtual multi-core processor tasks on a spaceborne software platform according to claim 2, characterized in that: Core 0 is selected as the master core, and all other cores are designated as slave cores.

4. The method for synchronizing virtual multi-core processor tasks on a spaceborne software platform according to claim 2, characterized in that: The system's operating time base is obtained using the following formula: Tm=(∑Cn) / F; Where Tm is the system's operating time base, Cn is the instruction cycle of each instruction, and F is the set clock frequency.

5. The method for synchronizing virtual multi-core processor tasks on a spaceborne software platform according to claim 1, characterized in that: Each core uses the system runtime base for task cycle scheduling, including: Step S1: Preset the counting interrupt time Ti and the periodic scheduling time Tn for each task; Step S2: Each core determines whether the count interrupt time has been reached based on the system runtime baseline. If it has been reached, proceed to step S3. Step S3: Increment the system counter by 1 and save the current system running time baseline; Step S4: Determine if the increment of the system counter reaches Tn / Ti. If it does, proceed to step S5. Step S5: Invoke the periodic task.

6. The method for synchronizing virtual multi-core processor tasks on a spaceborne software platform according to claim 5, characterized in that: The periodic scheduling time Tn of each task is an integer multiple of the counting interrupt time Ti.

7. A spaceborne software platform virtual multi-core processor task synchronization system, characterized in that... include: The first module is used to determine the time base for system operation; The second module is used by each core to perform task cycle scheduling based on the system runtime time.

8. The spaceborne software platform virtual multi-core processor task synchronization system according to claim 7, characterized in that: Determining the time base for system operation includes: Based on the instruction cycle number of each instruction obtained from the preset processor chip hardware manual, one core is selected as the master core, and the other cores are defined as slave cores; The master verifier records the instruction cycle of each executed instruction and obtains the system's operating time base based on the instruction cycle of each instruction and the set clock frequency. The system's operating time reference is obtained from the master core through inter-core communication.

9. The spaceborne software platform virtual multi-core processor task synchronization system according to claim 8, characterized in that: Select core 0 as the master core, and all other cores as slave cores; The system's operating time base is obtained using the following formula: Tm=(∑Cn) / F; Where Tm is the system's operating time base, Cn is the instruction cycle of each instruction, and F is the set clock frequency.

10. An electronic device, characterized in that, include: Memory: Used to store computer-readable instructions; as well as Processor: for executing the computer-readable instructions to perform the method as described in any one of claims 1 to 6.

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