Configurable VCO tuning voltage buffer for phase-locked loop

Abstract

The invention discloses a configurable VCO (Voltage Controlled Oscillator) tuning voltage buffer for a phase-locked loop. The configurable VCO tuning voltage buffer comprises a rail-to-rail differential input stage, a differential-to-single-ended circuit, a class AB common-source output stage, a capacitor Cf, a capacitor CL and a VCO tuning voltage control circuit, wherein the rail-to-rail differential input stage is respectively connected with the differential-to-single-ended circuit and the class AB common source output stage; the VCO tuning voltage control circuit is respectively connected with the class AB common-source output stage and the differential-to-single-ended circuit; one end of the capacitor Cf is respectively connected with the VCO tuning voltage control circuit and the class AB common source output stage; and one end of the capacitor CL is respectively connected with the VCO tuning voltage control circuit and the class AB common source output stage. Gate leakage is effectively suppressed, and phase-locked loop output clock jitter is remarkably reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of operational amplifier for phase-locked loop, and particularly relates to a configurable VCO tuning voltage buffer for phase-locked loop. BACKGROUND

[0002] With the CMOS process node shrinking, the MOS transistor gate oxide layer is thinner and thinner, and the gate leakage phenomenon is more and more significant, especially for the CMOS process below 130 nm, the gate leakage becomes a key factor that must be considered in circuit design. In the design of phase-locked loop, in order to reduce the layout area, MOS capacitors are often used, and the large-area MOS capacitors generate great gate leakage. The loop filter output control voltage V LPF generates great ripples. Since the output frequency of the voltage-controlled oscillator is proportional to the control voltage, the output clock frequency of the voltage-controlled oscillator will change with the ripples of the control voltage, which seriously affects the jitter performance of the phase-locked loop output clock. The prior art uses thick-oxide MOS devices to replace thin-oxide MOS devices. The thick-oxide MOS devices have smaller capacitance than the thin-oxide MOS devices, and need larger area. At the same time, the threshold voltage of the thick-oxide MOS devices is much larger than that of the thin-oxide MOS devices, and needs a larger V LPF control level. In a circuit designed for a low supply voltage of 1.2V, the control voltage design margin is insufficient. The control voltage V LPF often does not directly control the VCO, but adjusts the control level to a direct current level suitable for the VCO through an operational amplifier buffer or a current mirror circuit to control the VCO oscillation frequency. In order to ensure that the buffer output voltage accurately follows the control voltage V LPF , the operational amplifier needs to have a large gain. In order to avoid harmonic distortion, the operational amplifier needs to have good linearity. The existing operational amplifier buffer and current mirror circuit can only realize the following effect of the control voltage V LPF . Under the conditions of process and determined phase-locked loop output frequency, the control voltage V LPF shows a certain fixed level. When the voltage is much larger than the threshold voltage of the thin-oxide device, the MOS capacitor will have a great gate leakage problem. SUMMARY

[0003] The technical problem solved by the application is to overcome the shortcomings of the prior art and provide a configurable VCO tuning voltage buffer for phase-locked loop, which effectively suppresses gate leakage and significantly reduces the jitter of the phase-locked loop output clock.

[0004] The objective of this invention is achieved through the following technical solution: a configurable VCO tuned voltage buffer for a phase-locked loop, comprising: a rail-to-rail differential input stage, a differential-to-single-ended circuit, a Class AB common-source output stage, a capacitor Cf, a capacitor CL, and a VCO tuning voltage control circuit; wherein, the rail-to-rail differential input stage is connected to both the differential-to-single-ended circuit and the Class AB common-source output stage; the VCO tuning voltage control circuit is connected to both the Class AB common-source output stage and the differential-to-single-ended circuit; one end of the capacitor Cf is connected to both the VCO tuning voltage control circuit and the Class AB common-source output stage; and one end of the capacitor CL is connected to both the VCO tuning voltage control circuit and the Class AB common-source output stage.

[0005] In the aforementioned phase-locked loop using a configurable VCO tuned voltage buffer, the rail-to-rail differential input stage includes a resistor R. S1 NMOS transistor M1, NMOS transistor M2, resistor R S2 The circuit consists of PMOS transistors M5, M6, M3, and M4, resistors R1 and R2, and NMOS transistors M7 and M8, resistors R3 and R4. One end of resistor R1 and one end of resistor R2 are connected to the power supply. The other end of resistor R1 is connected to the source of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the source of PMOS transistor M3, the drain of NMOS transistor M1, and a class AB common-source output stage. The source of NMOS transistor M1 is connected to resistor R4. S1 One end is connected to the bias current I1; the gates of the NMOS transistor M1 and the PMOS transistor M5 are both connected to the voltage V. P Connected; the source of the PMOS transistor M5 is connected to the resistor R respectively. S2 One end of the resistor R2 is connected to the bias current I3; the drain of the PMOS transistor M5 is connected to the drain of the NMOS transistor M7 and the differential-to-single-ended circuit, respectively; the gate of the NMOS transistor M7 is connected to the drain of the NMOS transistor M7; the source of the NMOS transistor M7 is connected to one end of the resistor R3; one end of the resistor R2 is connected to the source of the PMOS transistor M4; the drain of the PMOS transistor M4 is connected to the source of the PMOS transistor M4, the drain of the NMOS transistor M2, and the differential-to-single-ended circuit, respectively; the source of the NMOS transistor M2 is connected to one end of the resistor R3; one end of the resistor R2 is connected to the source of the PMOS transistor M4; the drain of the PMOS transistor M4 is connected to the source of the NMOS transistor M2 and the differential-to-single-ended circuit, respectively; the source of the NMOS transistor M2 is connected to the source of the NMOS transistor M4; the other end of the resistor R3 is connected to the source of the NMOS transistor M4; the drain of the NMOS transistor M2 is connected to the source of the NMOS transistor M4; the source of the NMOS transistor M2 is connected to the source of the NMOS transistor M4; the other end of the resistor R3 is connected to the source of the NMOS transistor M4; the drain of the NMOS transistor M4 is connected to the source of the NMOS transistor M5; the other end of the resistor R3 is connected to the source of the NMOS transistor M4; the drain of the NMOS transistor M4 is connected to the source of the NMOS transistor M5; the other end of the resistor R3 is connected to the source of the NMOS transistor M4; the drain of the NMOS transistor M5 ... S1 The other end is connected to the bias current I2; the gates of the NMOS transistor M2 and the PMOS transistor M6 are both connected to the voltage V. M Connected; the source of the PMOS transistor M6 is connected to the resistor R respectively. S2The other end is connected to the bias current I4; the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M5 and the class AB common source output stage respectively; the gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M5; the source of the NMOS transistor M5 is connected to one end of the resistor R4.

[0006] In the aforementioned phase-locked loop using a configurable VCO tuned voltage buffer, the differential-to-single-ended circuit includes resistor R6, NMOS transistor M9, resistor R5, and PMOS transistor M... 10 Wherein, one end of resistor R5 is connected to the power supply, and the other end of resistor R5 is connected to the PMOS transistor M. 10 The source of the PMOS transistor is connected; 10 The gate of the PMOS transistor M3 is connected to the drain of the PMOS transistor M3; the PMOS transistor M 10 The drain of the NMOS transistor M9 is connected to the common-source output stage of the class AB transistor; the gate of the NMOS transistor M9 is connected to the source of the PMOS transistor M5; and the source of the NMOS transistor M9 is connected to one end of the resistor R6.

[0007] In the aforementioned phase-locked loop using a configurable VCO tuned voltage buffer, the Class AB common-source output stage includes a resistor R8 and an NMOS transistor M. 11 Resistor R7 and PMOS transistor M 12 Wherein, one end of resistor R7 is connected to the power supply, and the other end of resistor R7 is connected to the PMOS transistor M. 12 The source of the PMOS transistor is connected; 12 The gate of the transistor is connected to the drain of the PMOS transistor M4 and the drain of the NMOS transistor M9, respectively; the PMOS transistor M... 12 The drain of the capacitor is connected to the VCO tuning voltage control circuit, one end of the capacitor Cf, one end of the capacitor CL, and the NMOS transistor M. 11 The drains of the NMOS transistors are connected; 11 The gate of the PMOS transistor M 10 The drains of the NMOS transistors are connected; 11 The source of the resistor is connected to one end of the resistor R8.

[0008] In the aforementioned phase-locked loop using a configurable VCO tuned voltage buffer, the VCO tuned voltage control circuit includes an NMOS transistor M. 13 and load resistor array; wherein, the NMOS transistor M 13 The source of the NMOS transistor is connected to the power supply. 13 The gates of the PMOS transistor M are respectively connected to the gates of the PMOS transistor M. 12 drain of NMOS transistor M11 The drain of the capacitor, one end of the capacitor Cf, and one end of the capacitor CL are connected together; the NMOS transistor M 13 The drain and load resistor array are connected.

[0009] In the configurable VCO tuned voltage buffer used in the above phase-locked loop, the bias currents I1, I2, I3, and I4 are all equal.

[0010] In the configurable VCO tuned voltage buffer of the aforementioned phase-locked loop, the resistance values ​​of resistor R1 and resistor R2 are equal.

[0011] In the configurable VCO tuned voltage buffer of the aforementioned phase-locked loop, the resistance value of resistor R3 is equal to the resistance value of resistor R4.

[0012] In the configurable VCO tuned voltage buffer of the aforementioned phase-locked loop, the width-to-length ratio of NMOS transistor M1 is 40u / 0.2u, the width-to-length ratio of NMOS transistor M2 is 40u / 0.2u, the width-to-length ratio of PMOS transistor M5 is 40u / 0.2u, and the width-to-length ratio of PMOS transistor M6 is 40u / 0.2u.

[0013] In the aforementioned phase-locked loop using a configurable VCO tuned voltage buffer, the NMOS transistor M9 has a width-to-length ratio of 16µm / 0.5µm, and the PMOS transistor M... 10 The aspect ratio is 12u / 0.5u.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] (1) The present invention contains a VCO tuning voltage control circuit, which can adjust the VCO tuning voltage to the threshold voltage of the MOS capacitor by configuring the register according to process deviation and temperature change, effectively suppressing gate leakage current, significantly reducing the output clock jitter of the phase-locked loop, and supporting high-performance, low-jitter phase-locked loop design with power supply voltage as low as 1.2V and advanced process nodes.

[0016] (2) Compared with traditional operational amplifier buffers, although this invention is a four-stage operational amplifier, within the unity gain frequency range, this operational amplifier is a single-pole system, which meets the stability requirements.

[0017] (3) In this invention, the load resistance of the rail-to-rail differential input stage, differential to single-ended circuit and VCO tuning voltage control circuit is a diode-connected MOS transistor or a small resistor array. The load resistance values ​​are very small, and the corresponding poles are all extremely high frequency poles, which can achieve a large bandwidth of 40MHz.

[0018] (4) By working together with the rail-to-rail differential input stage and the Class AB common source output stage, this invention not only increases the input / output voltage range, but also achieves high gain and reduces the input / output signal magnitude error.

[0019] (5) The operational amplifier of the present invention adopts a source-level negative feedback common-source amplifier, which improves the linearity of the operational amplifier and reduces signal harmonic distortion. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0021] Figure 1 This is a schematic diagram of a configurable VCO tuned voltage buffer for a phase-locked loop provided in an embodiment of the present invention;

[0022] Figure 2 The present invention provides a gain-frequency Bode plot and a phase-frequency Bode plot for a configurable VCO tuned voltage operational amplifier for a phase-locked loop.

[0023] Figure 3 A schematic diagram of an application circuit for a configurable VCO tuned voltage buffer for a phase-locked loop provided in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram illustrating the gate leakage current characteristics, capacitance characteristics, and gate voltage relationship of a MOS capacitor provided in an embodiment of the present invention.

[0025] Figure 5 A schematic diagram of a single-sided equivalent circuit of a differential input stage circuit for a configurable VCO tuned voltage buffer for a phase-locked loop provided in an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of a small-signal model of voltage and current measurement of a diode-connected MOS transistor and a resistor connected in series at the source end, as seen from the output, provided in an embodiment of the present invention.

[0027] Figure 7 This is a schematic diagram of a small-signal model for voltage and current measurement of a MOS transistor operating in the saturation region and a resistor connected in series at the source, as seen from the output, provided in an embodiment of the present invention. Detailed Implementation

[0028] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] Figure 1 This is a schematic diagram of a configurable VCO tuned voltage buffer for a phase-locked loop provided in an embodiment of the present invention; Figure 2 The present invention provides a gain-frequency Bode plot and a phase-frequency Bode plot for a configurable VCO tuned voltage operational amplifier for a phase-locked loop. Figure 3 A schematic diagram of an application circuit for a configurable VCO tuned voltage buffer for a phase-locked loop provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the gate leakage current characteristics, capacitance characteristics, and gate voltage relationship of a MOS capacitor provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of a single-sided equivalent circuit of a differential input stage circuit for a configurable VCO tuned voltage buffer used in a phase-locked loop, provided in an embodiment of the present invention.

[0030] Figure 1 This is a schematic diagram of a configurable VCO tuned voltage buffer for a phase-locked loop provided in an embodiment of the present invention. Figure 1 As shown, the phase-locked loop (PLL) with a configurable VCO tuned voltage buffer includes: a rail-to-rail differential input stage, a differential-to-single-ended circuit, a Class AB common-source output stage, capacitor Cf, capacitor CL, and a VCO tuned voltage control circuit; wherein, the rail-to-rail differential input stage is connected to both the differential-to-single-ended circuit and the Class AB common-source output stage; the VCO tuned voltage control circuit is connected to both the Class AB common-source output stage and the differential-to-single-ended circuit; one end of capacitor Cf is connected to both the VCO tuned voltage control circuit and the Class AB common-source output stage; one end of capacitor CL is connected to both the VCO tuned voltage control circuit and the Class AB common-source output stage.

[0031] The rail-to-rail differential input stage includes resistor R S1 NMOS transistor M1, NMOS transistor M2, resistor R S2The transistors are: PMOS transistors M5, M6, M3, and M4; resistors R1 and R2; NMOS transistors M7 and M8; resistors R3 and R4. One end of resistor R1 and one end of resistor R2 are connected to the power supply. The other end of resistor R1 is connected to the source of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the source of PMOS transistor M3, the drain of NMOS transistor M1, and the class AB common-source output stage. The source of NMOS transistor M1 is connected to resistor R4. S1 One end is connected to the bias current I1; the gates of both NMOS transistor M1 and PMOS transistor M5 are connected to the voltage V. P Connected; the source of PMOS transistor M5 is connected to resistor R respectively. S2 One end of resistor R2 is connected to the bias current I3; the drain of PMOS transistor M5 is connected to the drain of NMOS transistor M7 and the differential-to-single-ended circuit, respectively; the gate of NMOS transistor M7 is connected to the drain of NMOS transistor M7; the source of NMOS transistor M7 is connected to one end of resistor R3; one end of resistor R2 is connected to the source of PMOS transistor M4; the drain of PMOS transistor M4 is connected to the source of PMOS transistor M4, the drain of NMOS transistor M2, and the differential-to-single-ended circuit, respectively; the source of NMOS transistor M2 is connected to one end of resistor R... S1 The other end is connected to the bias current I2; the gates of NMOS transistor M2 and PMOS transistor M6 are both connected to the voltage V. M Connected; the source of PMOS transistor M6 is connected to resistor R respectively. S2 The other end is connected to the bias current I4; the drain of PMOS transistor M6 is connected to the drain of NMOS transistor M5 and the class AB common source output stage respectively; the gate of NMOS transistor M5 is connected to the drain of NMOS transistor M5; the source of NMOS transistor M5 is connected to one end of resistor R4.

[0032] The differential-to-single-ended circuit includes resistor R6, NMOS transistor M9, resistor R5, and PMOS transistor M. 10 One end of resistor R5 is connected to the power supply, and the other end of resistor R5 is connected to the PMOS transistor M. 10 The source terminals are connected; PMOS transistor M 10 The gate of the transistor is connected to the drain of the PMOS transistor M3; PMOS transistor M 10 The drain of the NMOS transistor M9 is connected to the common-source output stage of the class AB transistor; the drain of the NMOS transistor M9 is connected to the common-source output stage of the class AB transistor; the gate of the NMOS transistor M9 is connected to the source of the PMOS transistor M5; and the source of the NMOS transistor M9 is connected to one end of the resistor R6.

[0033] The Class AB common-source output stage includes resistor R8 and NMOS transistor M. 11 Resistor R7 and PMOS transistor M12 One end of resistor R7 is connected to the power supply, and the other end of resistor R7 is connected to the PMOS transistor M. 12 The source terminals are connected; PMOS transistor M 12 The gates of the transistors are connected to the drains of PMOS transistor M4 and NMOS transistor M9, respectively; PMOS transistor M... 12 The drain of the capacitor is connected to the VCO tuning voltage control circuit, one end of capacitor Cf, one end of capacitor CL, and NMOS transistor M, respectively. 11 The drains of the NMOS transistor are connected; 11 The gate of the PMOS transistor M 10 The drains of the NMOS transistor are connected; 11 The source of the resistor is connected to one end of the resistor R8.

[0034] The VCO tuning voltage control circuit includes an NMOS transistor M. 13 and load resistor array; wherein, NMOS transistor M 13 The source is connected to the power supply, and the NMOS transistor M... 13 The gates of the PMOS transistor M are respectively connected to the gate of the PMOS transistor M. 12 drain of NMOS transistor M 11 The drain of the NMOS transistor is connected to one end of capacitor Cf and one end of capacitor CL; 13 The drain and load resistor array are connected.

[0035] Specifically, the phase-locked loop uses a configurable VCO tuned voltage buffer, which consists of a rail-to-rail differential input stage 32, a differential-to-single-ended circuit 24, a class AB common-source output stage 21, and a VCO tuned voltage control circuit 18. The output voltage of the class AB common-source output stage 21 is V. vco_ctrl The relationship between f and the output clock frequency of VCO47 is f VCO =k VCO *V vco_ctrl Under the given conditions of circuit structure and process, VCO47, K VCO The constant is the output clock frequency f of VCO47. VCO Under certain conditions, V vco_ctrl For a fixed value, transistor M 13 The drain-source current of 16 is a constant value. By configuring the register, the resistance of resistor array 17 is adjusted, thereby adjusting the output voltage Vo of the buffer. Since the output voltage Vo is negatively fed back to the negative input terminal V of the op-amp, M The output voltage V of the loop filter LPF50 can be adjusted by utilizing the high gain characteristics of the operational amplifier. LPF and V M To maintain consistency, considering that capacitors C141 and C243 of the loop filter LPF50 are often composed of MOS capacitor 51, MOS capacitor 51 and V LPFThe relationship between the gate leakage current of the MOS capacitor and V is shown in curve 52. LPF The relationship is shown in curve 53. In order to balance the MOS capacitance and gate leakage characteristics, V LPF Adjust the DC level to the threshold voltage Vth of the MOS capacitor.

[0036] The phase-locked loop VCO tuning voltage is configurable: Class AB common-source output stage output voltage V vco ctrl The relationship with the VCO output clock frequency is f VCO =k VCO *V vco_ctrl Under the condition that the circuit structure and process of VCO are determined, K VCO The constant is the frequency f at the VCO output clock frequency. VCO Under certain conditions, it can be known that V vco_ctrl For a fixed value, the relationship between the source-drain current and the gate-source voltage when the transistor is operating in the saturation region is I. ds =0.5*K p (V vco_ctrl -Vth) 2 transistor M 13 The drain-source current of 16 is a constant value. By adjusting the resistance of resistor array 17 through the configuration register, the output voltage Vo of the buffer can be adjusted. Since the output voltage Vo is negatively fed back to the negative input terminal V of the op-amp, M The output voltage V of the loop filter LPF50 can be adjusted by utilizing the high gain characteristics of the operational amplifier. LPF and V M To maintain consistency, considering that capacitors C141 and C243 of the loop filter LPF50 are often composed of MOS capacitor 51, MOS capacitor 51 and V LPF The relationship is shown in curve 52. When the gate voltage is less than the threshold voltage Vth, the MOS capacitance is small and exhibits a steep change. When the gate voltage is greater than the threshold voltage Vth, the MOS capacitance is large and remains basically unchanged. The MOS gate leakage current is related to Vth. LPF The relationship is shown in curve 53. When the gate voltage is less than the threshold voltage Vth, the gate leakage current is almost negligible. When the gate voltage is greater than the threshold voltage Vth, the gate leakage current increases sharply. In order to balance the characteristics of MOS capacitance and gate leakage current, a register is configured to set Vth... LPF The DC level is adjusted to the threshold voltage Vth to avoid the influence of MOS capacitor gate leakage, while achieving a large capacitance value.

[0037] The rail-to-rail differential input stage 32 consists of a powered negative feedback resistor R. S1 The 5-pin NMOS differential input pairs M12, M28 and the active stage negative feedback resistor R S2The PMOS differential input pair consists of two common-source amplifiers, M531 and M626, with a PMOS differential input pair. The load resistors for the NMOS differential input pair are PMOS transistors M33 and M47 connected by diodes and resistors R14 and R26, with bias currents I11 and I29. The load resistors for the PMOS differential input pair are NMOS transistors M734 and M827 connected by diodes and resistors R333 and R428, with bias currents I330 and I425. The bias currents I11, I29, I330, and I425 are equal, and the resistors R14 and R26 are of equal value, as are the resistors R333 and R428.

[0038] The differential-to-single-ended circuit 24 consists of a single-ended NMOS common-source amplifier M922 with active-stage negative feedback resistor R623 and a single-ended PMOS common-source amplifier M with active-stage negative feedback resistor R510. 10 The common-source amplifier M922 consists of 11 components. Its input comes from the rail-to-rail PMOS differential input to the positive input terminal (31). The output of the common-source amplifier M922 and the output of the rail-to-rail NMOS differential input to the negative input terminal (8) are summed and act on the next stage circuit. 10 11 inputs originate from rail-to-rail NMOS differential input to positive input terminal 2 output, common-source amplifier M 10 The 11 outputs and the rail-to-rail PMOS differential input to the negative input terminal of the 8 outputs work together to act on the next stage circuit.

[0039] Class AB common-source output stage 21 consists of a single-ended NMOS common-source amplifier M with active stage negative feedback resistor R820. 11 19 and a single-ended PMOS common-source amplifier M with active stage negative feedback resistor R712 12 Composed of 13 components, common-source amplifier M 11 19 and common-source amplifier M 12 The on-resistance of capacitor 13 is the load of each other. The output node capacitance to ground consists of the large capacitor Cf14, the load capacitor CL15, and transistor M. 11 19. M 12 The sum of 13 parasitic capacitances to ground.

[0040] The VCO tuning voltage control circuit 18 consists of a common-source amplifier M. 13 Composed of 16 and load resistor array 17, common-source amplifier M 13 16 has a large drive current I ds13 =0.5K p (V vco_ctrl -V th13 ) 2 , where V vco_ctrl V is the control voltage for the VCO output frequency. th13 For transistor M 13Threshold voltage.

[0041] Load resistor array 17 consists of R D R, R, 2R, 4R, ..., 2 N-1 R is connected in series, and the total resistance is R D +2 N R, where R is the unit resistance, and the minimum width and length of the constrained process, 2 N R*I ds13 R represents the maximum variation of the threshold voltage of a MOS capacitor with process and temperature. D +2 N-1 R)*I ds13 The threshold voltage of the MOS capacitor at room temperature and the TT process corner, and the switch S C S0, S1, S2, ..., S N-1 The corresponding resistor can be shorted. In room temperature, TT process corner circuit design, switch S N-1 When the switch is open and all other switches are closed, the sum of the resistances connected to the resistor array is R. D +2 N-1 R, adjust resistor R D Make the output voltage V O This is equal to the MOS capacitor threshold voltage Vth. To ensure the op-amp is a single-pole system within the unity-gain frequency, the total resistance R of the load resistor array is... D +2 N R must be less than the sum of the load of the MOS transistor connected to the differential input stage diode and the series resistor load.

[0042] The rail-to-rail differential input stage 32, the differential-to-single-ended circuit 24, and the class AB common-source output stage 21 all adopt a source-level negative feedback structure to increase the linearity of the operational amplifier and reduce signal harmonic distortion. S1 5 is the source-side negative feedback resistor for the 32NMOS input differential pair in the rail-to-rail differential input stage, R. S2 R29 is the source-side negative feedback resistor for the rail-to-rail differential input stage 32 PMOS input differential pair. R510 and R712 are the source-side negative feedback resistors for the common-source PMOS transistor. R14, R26, R510, and R712 have the same value. R14 and R26 are used to adapt to the subsequent circuit. R623 and R820 are the source-side negative feedback resistors for the common-source NMOS transistor. R333, R428, R623, and R820 have the same value. R333 and R428 are used to adapt to the subsequent circuit.

[0043] Buffer 48 is a four-stage operational amplifier. Within the unity-gain frequency range, it is a single-pole system containing one low-frequency dominant pole and multiple high-frequency secondary poles. The AC gain-phase curves are Bode plot curve 35 and phase Bode plot curve 36. The positions of the high-frequency secondary poles are all greater than the unity-gain frequency.

[0044] The buffer 48 works in conjunction with the rail-to-rail differential input stage circuit and the class AB common-source output stage circuit, which not only expands the input / output voltage range of the operational amplifier, but also improves the overall gain of the operational amplifier and reduces the magnitude error of the input and output signals.

[0045] Buffer 48 is used between the phase-locked loop filter 50 and the voltage-controlled oscillator VCO 47. Through the configuration register, it controls the output voltage V of the loop filter 50. LPF DC level feedback adjustment, V LPF The DC level is adjusted to the threshold voltage of the MOS capacitor to suppress the deterioration of PLL output clock jitter caused by the gate leakage current of the MOS capacitor while achieving a large MOS capacitor.

[0046] Operational amplifier buffers are used to transmit input signals to the output without distortion. To reduce input and output signal magnitude errors, the op-amp needs to achieve high gain. To ensure stable operation of the op-amp, an appropriate phase margin needs to be designed. To reduce signal harmonic distortion, the operational amplifier buffer needs to achieve high linearity.

[0047] This common source amplifier design involves three types of loads: a diode-connected MOSFET and a resistor connected in series at the source, a MOSFET operating in the saturation region and a resistor connected in series at the source, and a resistor array.

[0048] Figure 6 For a diode-connected MOSFET and a resistor connected in series with its source, consider the equivalent resistance seen from the output in a small-signal model. Based on this small-signal model, I... X R S +(I X -g m V1-g mb V bs )r ds =V X V1 = V X -I X R S V bs =-I X R S Among them, I X R is the total current flowing from the drain of the MOS transistor to ground. S g is the resistor connected in series with the source of the MOS transistor. m V1 is the transconductance of the MOS transistor, V1 is the gate-source voltage difference of the MOS transistor, and g is the transconductance of the MOS transistor. mb For the body effect transconductance of a MOS transistor, V bs r is the substrate-source voltage difference of a MOS transistor. ds V is the drain-source on-resistance of the MOS transistor. XThe DC voltage applied to the drain of the MOS transistor for voltage and current measurement.

[0049] United V X / I X =[R s (1+(g m +g mb )r ds )+r ds ] / (1+g m r ds ), considering R s Compared to r ds The resistance value is very small, R s Several kΩ, r ds tens of kΩ, due to R s The resistance value is relatively small, V bs The voltage is very small, g mb If the value is very small and can be ignored, then V X / I X ≈R s +1 / g m ; Figure 7 For a small-signal model of the equivalent resistance of a MOSFET operating in the saturation region and the resistor connected in series with its source, viewed from the output, we can obtain I. X R S +(I X -g m V1-g mb V bs )r ds =V X V1 = V bs =-I X R S ; combined V X / I X ≈(1+g m R s )r ds +R s .

[0050] The gain of an operational amplifier is obtained by multiplying the gains of each stage. The total transconductance G of the output current versus the input voltage in a source-stage negative feedback common-source amplifier is... m for:

[0051] (g m For the transconductance of a common-source transistor, R S (Source-level negative feedback resistor)

[0052] The half-equivalent circuit of the differential input stage is as follows: Figure 5 As shown, the gain of the rail-to-rail differential input stage is:

[0053]

[0054] Among them, A v1 For the gain of the rail-to-rail differential input stage 32, A v1n For the gain of the rail-to-rail differential input stage 32NMOS differential input stage, A v1p For the gain of the rail-to-rail differential input stage 32PMOS differential input stage, g m1,2 For NMOS differential input pair transistor M 1,2 Transconductance, g m3,4 For transistor M 3,4 Transconductance, g m5,6 For example, PMOS differential input pair transistor M 5,6 Transconductance, g m7,8 For transistor M 7,8 Transconductance, R 1,2 For transistor M 3,4 The resistor connected in series with the source, R 3,4 For transistor M 7,8 The resistor connected in series with the source.

[0055] The gain of the differential-to-single-ended circuit is:

[0056]

[0057] Among them, A v2n For the gain of the NMOS input transistor in the differential-to-single-ended circuit, g m9 For the transconductance of transistor M9, g m4 For the transconductance of transistor M4, A v2p For the gain of the PMOS input transistor in the differential-to-single-ended circuit, g m10 For transistor M 10 Transconductance, g m8 The transconductance of transistor M8 is given.

[0058] The gain of the Class AB common-source output stage circuit is:

[0059]

[0060] Among them, A v3 For the gain of a Class AB common-source output stage circuit, A v3n For the gain of the NMOS input transistor in the class AB common-source output stage, A v3p For the gain of the PMOS input transistor in the class AB common-source output stage, g m11 For transistor M 11 Transconductance, g m12 For transistor M 12 Transconductance, r ds12 For transistor M 12 Drain-source on-resistance, r ds11 For transistor M 11Drain-source on-resistance.

[0061] The gain of the VCO tuning voltage control circuit is:

[0062] A v4 =g m15 ×R array

[0063] Among them, A v4 For the gain of the VCO tuning voltage control circuit, g m15 For transistor M 15 Transconductance, R array For transistor M 15 Output equivalent resistance.

[0064] The overall gain of the operational amplifier is:

[0065] A v =(A v1n A v2p A v3n +A v1p A v2n A v3p A v4

[0066] Here, the differential input stage gain is approximately 2x, the differential-to-single-ended conversion gain is 1x, the common-source output stage gain is approximately 50x, the VCO tuning voltage control circuit gain is approximately 5x, and the overall gain is 500.

[0067] Operational amplifiers require stability design considerations. This circuit's signal path contains nodes X1, X2, Y1, Y2, Z1, and Z2. These nodes will generate corresponding poles in the signal path. The capacitance to ground of pole X1 is C. X1 =C db1 +C gd1 +C db3 +C gs3 +C gs10 +C gd10 , where C X1 Let C be the total capacitance of pole X1 to ground. db1 C is the drain-substrate parasitic capacitance of transistor M1. gd1 C is the gate-drain parasitic capacitance of transistor M1. db3 C is the drain-substrate parasitic capacitance of transistor M3. gs3 C is the gate-source parasitic capacitance of transistor M3. gs10 For transistor M 10 The gate-source parasitic capacitance, C gd10 For transistor M 10 The gate-drain parasitic capacitance and the resistance to ground are Among them, g m3The transconductance of transistor M3 is given; the capacitance of pole X2 to ground is C. X2 =C db2 +C gd2 +C db4 +C gs4 +C gs12 +C gd12 +C gd9 +C db9 , where C X2 Let C be the total capacitance of pole X2 to ground. db2 C is the drain-substrate parasitic capacitance of transistor M2. gd2 C is the gate-drain parasitic capacitance of transistor M2. db4 C is the drain-substrate parasitic capacitance of transistor M4. gs4 C is the gate-source parasitic capacitance of transistor M4. gs12 For transistor M 12 The gate-source parasitic capacitance, C gd12 For transistor M 12 The gate-drain parasitic capacitance, C gd9 C is the gate-drain parasitic capacitance of transistor M9. db9 The drain-substrate parasitic capacitance of transistor M9 has a resistance to ground of [value missing]. Among them, g m4 The transconductance of transistor M4 is given; the capacitance of pole Y1 to ground is C. Y1 =C db5 +C gd5 +C db7 +C gs7 +C gs9 +C gd9 , where C Y1 Let C be the total capacitance of pole Y1 to ground. db5 C is the drain substrate parasitic capacitance of transistor M5. gd5 C is the gate-drain parasitic capacitance of transistor M5. db7 C is the drain-substrate parasitic capacitance of transistor M7. gs7 C is the gate-source parasitic capacitance of transistor M7. gs9 C is the gate-source parasitic capacitance of transistor M9. gd9 The gate-drain parasitic capacitance of transistor M9 is [value missing], and its resistance to ground is [value missing]. Among them, g m7 The transconductance of transistor M7 is given; the capacitance of pole Y2 to ground is C. Y2 =C db6 +C gd6 +C db8 +C gs8 +C gs11 +C gd11 +C gd10 +C db10 , where C Y2 Let C be the total capacitance of pole Y2 to ground.db6 C is the drain-substrate parasitic capacitance of transistor M6. gd6 C is the gate-drain parasitic capacitance of transistor M6. db8 C is the drain-substrate parasitic capacitance of transistor M8. gs8 C is the gate-source parasitic capacitance of transistor M8. gs11 For transistor M 11 The gate-source parasitic capacitance, C gd11 For transistor M 11 The gate-drain parasitic capacitance, C gd10 For transistor M 10 The gate-drain parasitic capacitance, C db10 For transistor M 10 The leakage substrate parasitic capacitance and the resistance to ground are Among them, g m8 The transconductance of transistor M8 is given; the capacitance of pole Z1 to ground is C. Z1 =C db12 +C gd12 +C db11 +C gs11 +C gs15 +C gd15 +Cf+CL, where C z1 Let C be the total capacitance of pole Z1 to ground. db12 For transistor M 12 The parasitic capacitance of the leaky substrate, C gd12 For transistor M 12 The gate-drain parasitic capacitance, C db11 For transistor M 11 The parasitic capacitance of the leaky substrate, C gs11 For transistor M 11 The gate-source parasitic capacitance, C gs15 For transistor M 15 The gate-source parasitic capacitance, C gd15 For transistor M 15 The gate-drain parasitic capacitance, Cf is the output voltage regulator filter capacitor with a large resistance to ground, CL is the load capacitor of the subsequent circuit, and the resistance to ground is [(1+g m11 R8)r ds11 +R8]||[(1+g m12 R7)r ds12 +R7];The capacitance of pole Z2 to ground is C Z2 =C db15 +C gd15 +C gs2 +C gd2 +C gs6 +C gd6 , where C z2 Let C be the total capacitance of pole Z2 to ground. db15 For transistor M 15 The parasitic capacitance of the leaky substrate, Cgd15 For transistor M 15 The gate-drain parasitic capacitance, C gs2 C is the gate-source parasitic capacitance of transistor M2. gd2 C is the gate-drain parasitic capacitance of transistor M2. gs6 C is the gate-source parasitic capacitance of transistor M6. gd6 The gate-drain parasitic capacitance of transistor M6 is R, and its resistance to ground is R. array The capacitances to ground and resistances to ground of poles X1, X2, Y1, Y2, and Z2 are similar, with capacitances to ground of approximately tens of fF and resistances to ground of several kΩ. Pole Z1 has significantly larger capacitances to ground and resistances to ground than the other poles, with capacitances to ground of several pF and resistances to ground of tens of kΩ. The frequency of each pole is 1 / RC. Pole Z1 is a low-frequency dominant pole, while poles X1, X2, Y1, Y2, and Z2 are high-frequency secondary poles. The frequencies of these high-frequency secondary poles are similar. To ensure the phase margin of the operational amplifier, the frequencies of these high-frequency secondary poles must be located outside the unity-gain frequency of the operational amplifier, i.e., within the unity-gain frequency. This operational amplifier is equivalent to a single-pole system.

[0068] As a buffer, especially for the control voltage buffer of a phase-locked loop voltage-controlled oscillator, the output signal needs to follow the input signal without distortion. To reduce harmonic distortion, a high-linearity operational amplifier is required. This circuit uses a common-source stage circuit with active negative feedback in its differential input stage, differential-to-single-ended converter, and class AB common-source output stage. The gain of this circuit structure is... resistor R s It can reduce transistor gain A V Sensitivity to transconductance gm, maintaining constant in-band gain, and improving linearity.

[0069] like Figure 1 The diagram shows a configurable VCO tuned voltage buffer circuit for the phase-locked loop of the present invention. It consists of a rail-to-rail differential input stage 32, a differential-to-single-ended circuit 24, a class AB common-source output stage 21, and a VCO tuned voltage control circuit 18.

[0070] like Figure 1 As shown, the width-to-length ratio of the 32NMOS differential input pairs M12 and M28 in the rail-to-rail differential input stage is 40u / 0.2u, and the width-to-length ratio of the PMOS differential input pairs M531 and M626 is 40u / 0.2u. The source-stage negative feedback resistor R... S1 5 and R S2All 29 resistors have a value of 2.5kΩ. The PMOS transistors M33 and M47 connected by diodes have a width-to-length ratio of 12u / 0.5u. ​​The NMOS transistors M734 and M827 connected by diodes have a width-to-length ratio of 16u / 0.5u. ​​The resistors R14, R26, R333, and R428 have a value of 2kΩ. The bias currents I11, I29, I330, and I425 are 10uA.

[0071] The differential-to-single-ended circuit uses a 24-channel common-source NMOS transistor M922 with a width-to-length ratio of 16µm / 0.5µm, and a common-source PMOS transistor M... 10 The aspect ratio of transistor 11 is 12µm / 0.5µm, corresponding to a 2kΩ resistance value for resistors R623 and R510 connected in series at the source; the Class AB common-source output stage 21 common-source NMOS transistor M... 11 19mm aspect ratio, 16µm / 0.5µm, common-source PMOS transistor M 12 The aspect ratio of the 13 transistor is 12u / 0.5u, corresponding to a 2kΩ resistance between the resistors R820 and R712 connected in series at the source; the VCO tuning voltage control circuit uses an 18PMOS driver transistor M. 13 The aspect ratio of the 16-pin transistor is 100µm / 1.4µm, due to the PMOS driver transistor M... 13 The drain feedback output of the 16 is fed to the negative input of the op-amp, taking into account the transistor flicker noise V. n 2 =K / (C ox WL)*1 / f, the channel length L needs to be set relatively large. Additionally, considering the influence of parasitic capacitance on pole location, the channel length L needs to be relatively small. The channel length L should be as large as possible while still satisfying stability requirements. In the current circuit, L is 1.4µm. The threshold voltage of a 130nm process MOS device is largest at the low-temperature SS process corner and smallest at the high-temperature FF process corner, with a maximum-minimum difference of approximately 400mV. Therefore, 2 N R*I ds13 =400mV, the capacitance of a MOS device at room temperature and a threshold voltage of 400mV, then R D =2 N-1 R, where R is 250Ω, N = 3, R D +2 N R = 3kΩ.

[0072] This embodiment integrates a rail-to-rail differential input stage, a differential-to-single-ended circuit, a Class AB common-source output stage, and a VCO tuning voltage control circuit. The design employs a source-level negative feedback circuit structure to improve the operational amplifier's linearity and reduce signal harmonic distortion. A single-pole system design within the unity-gain frequency range ensures the stability of the multi-stage operational amplifier. The rail-to-rail differential input stage and the Class AB common-source output stage work together, not only expanding the operational amplifier's input / output voltage range but also providing high gain. The core VCO tuning voltage control circuit adjusts the VCO tuning voltage to the MOS capacitor threshold voltage through a configuration register based on process deviations and temperature variations, effectively suppressing gate leakage current and significantly reducing PLL output clock jitter. This embodiment features high bandwidth, high linearity, and strong process robustness, supporting high-performance, low-jitter PLL designs with power supply voltages as low as 1.2V and advanced process nodes.

[0073] This embodiment includes a VCO tuning voltage control circuit, which can adjust the VCO tuning voltage to the MOS capacitor threshold voltage through a configuration register according to process deviations and temperature changes. This effectively suppresses gate leakage current and significantly reduces PLL output clock jitter, supporting high-performance, low-jitter PLL designs with power supply voltages as low as 1.2V and advanced process nodes. Compared with traditional operational amplifier buffers, although this embodiment is a four-stage operational amplifier, it is a single-pole system within the unity-gain frequency range, meeting stability requirements. In this embodiment, the load resistors of the rail-to-rail differential input stage, differential-to-single-ended circuit, and VCO tuning voltage control circuit are diode-connected MOS transistors or small resistor arrays, with very small load resistance values. The corresponding poles are all extremely high-frequency poles, achieving a large bandwidth of 40MHz. This embodiment, through the coordinated operation of the rail-to-rail differential input stage and the class AB common-source output stage, not only increases the input / output voltage range but also achieves high gain and reduces input / output signal magnitude errors. The operational amplifier in this embodiment uses a source-level negative feedback common-source amplifier, improving operational amplifier linearity and reducing signal harmonic distortion.

[0074] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A configurable VCO tuned voltage buffer for a phase-locked loop, characterized in that... include: The circuit consists of a rail-to-rail differential input stage, a differential-to-single-ended converter, a class AB common-source output stage, capacitors Cf and CL, and a VCO tuning voltage control circuit. The rail-to-rail differential input stage is connected to the differential-to-single-ended circuit and the class AB common-source output stage, respectively. The VCO tuning voltage control circuit is connected to the Class AB common source output stage and the differential to single-ended circuit, respectively. One end of the capacitor Cf is connected to the VCO tuning voltage control circuit and the Class AB common source output stage, respectively; One end of the capacitor CL is connected to the VCO tuning voltage control circuit and the Class AB common source output stage, respectively.

2. The configurable VCO tuned voltage buffer for phase-locked loop according to claim 1, characterized in that: The rail-to-rail differential input stage includes a resistor R. S1 NMOS transistor M1, NMOS transistor M2, resistor R S2 PMOS transistors M5, M6, M3, and M4; resistors R1 and R2; NMOS transistors M7 and M8; resistors R3 and R4; among which, One end of resistor R1 and one end of resistor R2 are both connected to the power supply. The other end of resistor R1 is connected to the source of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the source of PMOS transistor M3, the drain of NMOS transistor M1, and the class AB common source output stage, respectively. The source of the NMOS transistor M1 is connected to the resistor R. S1 One end is connected to the bias current I1; The gates of both the NMOS transistor M1 and the PMOS transistor M5 are connected to voltage V. P Connected; The source of the PMOS transistor M5 is connected to the resistor R. S2 One end is connected to the bias current I3; The drain of the PMOS transistor M5 is connected to the drain of the NMOS transistor M7 and the differential-to-single-ended circuit, respectively. The gate of the NMOS transistor M7 is connected to the drain of the NMOS transistor M7. The source of the NMOS transistor M7 is connected to one end of the resistor R3; One end of the resistor R2 is connected to the source of the PMOS transistor M4, and the drain of the PMOS transistor M4 is connected to the source of the PMOS transistor M4, the drain of the NMOS transistor M2, and the differential-to-single-ended circuit, respectively. The source of the NMOS transistor M2 is connected to the resistor R. S1 The other end is connected to the bias current I2; The gates of both the NMOS transistor M2 and the PMOS transistor M6 are connected to voltage V. M Connected; The source of the PMOS transistor M6 is connected to the resistor R. S2 The other end is connected to the bias current I4; The drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M5 and the class AB common-source output stage, respectively. The gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M5. The source of the NMOS transistor M5 is connected to one end of the resistor R4.

3. The configurable VCO tuned voltage buffer for phase-locked loop according to claim 2, characterized in that: The differential-to-single-ended circuit includes resistor R6, NMOS transistor M9, resistor R5, and PMOS transistor M. 10 ;in, One end of resistor R5 is connected to the power supply, and the other end of resistor R5 is connected to the PMOS transistor M. 10 The source poles are connected; The PMOS transistor M 10 The gate of the transistor is connected to the drain of the PMOS transistor M3; The PMOS transistor M 10 The drain is connected to the class AB common-source output stage; The drain of the NMOS transistor M9 is connected to the common-source output stage of class AB, the gate of the NMOS transistor M9 is connected to the source of the PMOS transistor M5, and the source of the NMOS transistor M9 is connected to one end of the resistor R6.

4. The configurable VCO tuned voltage buffer for phase-locked loop according to claim 3, characterized in that: The Class AB common-source output stage includes resistor R8 and NMOS transistor M. 11 Resistor R7 and PMOS transistor M 12 ;in, One end of resistor R7 is connected to the power supply, and the other end of resistor R7 is connected to the PMOS transistor M. 12 The source poles are connected; The PMOS transistor M 12 The gate of the transistor is connected to the drain of the PMOS transistor M4 and the drain of the NMOS transistor M9, respectively. The PMOS transistor M 12 The drain of the capacitor is connected to the VCO tuning voltage control circuit, one end of the capacitor Cf, one end of the capacitor CL, and the NMOS transistor M. 11 The drains are connected; The NMOS transistor M 11 The gate of the PMOS transistor M 10 The drains are connected; The NMOS transistor M 11 The source of the resistor is connected to one end of the resistor R8.

5. The configurable VCO tuned voltage buffer for phase-locked loop according to claim 4, characterized in that: The VCO tuning voltage control circuit includes an NMOS transistor M. 13 and load resistor array; wherein, The NMOS transistor M 13 The source of the NMOS transistor is connected to the power supply. 13 The gates of the PMOS transistor M are respectively connected to the gates of the PMOS transistor M. 12 The drain of the NMOS transistor M 11 The drain of the capacitor, one end of the capacitor Cf, and one end of the capacitor CL are connected together; The NMOS transistor M 13 The drain and the load resistor array are connected.

6. The configurable VCO tuned voltage buffer for phase-locked loop according to claim 2, characterized in that: The bias currents I1, I2, I3, and I4 are all equal.

7. The configurable VCO tuned voltage buffer for phase-locked loop according to claim 2, characterized in that: The resistance value of resistor R1 is equal to the resistance value of resistor R2.

8. The configurable VCO tuned voltage buffer for phase-locked loop according to claim 2, characterized in that: The resistance value of resistor R3 is equal to the resistance value of resistor R4.

9. The configurable VCO tuned voltage buffer for phase-locked loop according to claim 2, characterized in that: The width-to-length ratio of NMOS transistor M1 is 40u / 0.2u, the width-to-length ratio of NMOS transistor M2 is 40u / 0.2u, the width-to-length ratio of PMOS transistor M5 is 40u / 0.2u, and the width-to-length ratio of PMOS transistor M6 is 40u / 0.2u.

10. The configurable VCO tuned voltage buffer for a phase-locked loop according to claim 2, characterized in that: The NMOS transistor M9 has a width-to-length ratio of 16µm / 0.5µm, while the PMOS transistor M... 10 The aspect ratio is 12u / 0.5u.

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