Multi-protocol video decoding dynamic configuration method and system based on FPGA

Abstract

The invention provides a multi-protocol video decoding dynamic configuration method and system based on an FPGA, and belongs to the technical field of video decoding. The method comprises the following steps of: constructing a hardware environment comprising a static logic region and a reconfigurable logic region in an FPGA (Field Programmable Gate Array); parsing syntactic elements of the input video stream and comparing the syntactic elements with a built-in protocol feature library to identify coding protocol types of the syntactic elements; comparing the identification result with the protocol type used by the current decoding logic, if the identification result is consistent with the protocol type used by the current decoding logic, directly decoding, and if the identification result is not consistent with the protocol type used by the current decoding logic, reading a corresponding part of bit stream from an external memory, partially reconfiguring the reconfigurable logic region and keeping the static logic region running; and switching the current video stream to the reconfigured logic region for decoding and outputting. According to the invention, seamless dynamic switching of multi-protocol video decoding is realized, high flexibility, high resource utilization rate and decoding performance close to ASIC (Application Specific Integrated Circuit) are realized, and the problems of low switching efficiency, system interruption and resource rigidity of the existing scheme are effectively solved.

Description

Technical Field

[0001] This invention belongs to the field of video decoding technology, and in particular relates to a dynamic configuration method and system for multi-protocol video decoding based on FPGA. Background Technology

[0002] As video applications evolve towards ultra-high definition (4K / 8K), high dynamic range (HDR), and high frame rates, the volume of video data is surging, making efficient video encoding and decoding technologies crucial. Simultaneously, the market exhibits multiple encoding standards, including SDI, H.265, RAW, YUV, and MJPEG, with varying video stream formats from different sources. Therefore, researching a high-performance, highly efficient decoding system that is compatible with multiple protocols and enables seamless switching is of great significance for fields requiring continuity and real-time performance, such as broadcast television, industrial vision, and medical imaging. It represents an important direction for overcoming existing technological bottlenecks and meeting future flexible needs.

[0003] The process in the prior art: 1. Application-Specific Integrated Circuit (ASIC) Decoding: Designing and manufacturing a dedicated decoding chip. The process involves embedding a specific decoding algorithm (such as H.264) into the hardware circuit. During operation, the encoded video stream is input into the ASIC, and its internal fixed logic units sequentially complete steps such as decoding, inverse quantization, inverse transform, and motion compensation, ultimately outputting the decoded pixel data.

[0004] 2. Software Decoding: This method relies on the general computing power of a central processing unit (CPU) or a graphics processing unit (GPU). The process involves the operating system calling a decoder software library to read the encoded video stream into memory. The CPU / GPU then executes the decoding algorithm instructions, performing frame-by-frame computation and reconstruction, and finally sending the result to the display buffer.

[0005] Problems with existing technology: 1. ASIC solutions have poor flexibility: once the hardware functions are manufactured, they are fixed and cannot support protocol upgrades or the addition of new protocols. They are difficult to adapt to multi-protocol environments, and the life cycle of the device is limited by the chip design.

[0006] 2. Significant performance bottlenecks in software decoding solutions: When processing high-resolution videos, the computational pressure is enormous, resulting in excessive CPU / GPU load, high power consumption, and difficulty in ensuring real-time performance. Furthermore, stuttering is prone to occur in high frame rate scenarios.

[0007] 3. Low switching efficiency of existing FPGA solutions: When switching decoding protocols, traditional FPGA solutions often require a complete system reset and reloading of the complete configuration file, which takes a long time and will cause video stream interruption, failing to meet the application requirements for seamless switching.

[0008] 4. Rigid utilization of hardware resources: Whether it is an ASIC or a fixed-function FPGA, its hardware resources are statically allocated and cannot be dynamically adjusted according to actual task requirements, resulting in low resource utilization. Summary of the Invention

[0009] This invention addresses the problems existing in the prior art by providing a dynamic configuration method and system for multi-protocol video decoding based on FPGA.

[0010] In a first aspect, the present invention provides a dynamic configuration method for multi-protocol video decoding based on FPGA, comprising: Load the initial bitstream into the FPGA to build a hardware environment that includes a static logic region and at least one reconfigurable logic region; The target syntax elements of the current video stream entering the FPGA are parsed and compared with the built-in protocol feature library to obtain the encoding protocol type of the current video stream; wherein, the syntax elements include at least one of start code, sequence parameter set and video data type; A second comparison is made between the encoding protocol type of the current video stream and the protocol type corresponding to the current decoding logic active in the reconfigurable logic region of the FPGA; If the second comparison results are consistent, the current video stream is decoded according to the current decoding logic to obtain the decoded first video data; If the results of the second comparison are inconsistent, a portion of the bitstream corresponding to the encoding protocol type of the current video stream is read from the external configuration memory to reconfigure the reconfigurable logical region while keeping the operation of the static logical region unaffected. The current video stream is switched to the reconfigured reconfigurable logical region for decoding to obtain the decoded second video data; Use either the first video data or the second video data as the final video data after decoding.

[0011] Optionally, the first aspect also includes: The protocol of the current video stream entering the FPGA is continuously identified to form a continuous closed-loop control for protocol changes.

[0012] Optionally, the first aspect also includes: Add a portion of the bitstream file for the new protocol type to the external configuration memory to update the built-in protocol feature library.

[0013] Optionally, in the event of a discrepancy in the results of the second comparison, reading a portion of the bitstream corresponding to the encoding protocol type of the current video stream from an external configuration memory to reconfigure the reconfigurable logical region while keeping the operation of the static logical region unaffected includes: The storage address of the corresponding portion of the bitstream in the external configuration memory is determined based on the encoding protocol type of the current video stream; Read the portion of bitstream data corresponding to the encoding protocol type of the current video stream based on the storage address.

[0014] Secondly, the present invention provides an FPGA-based multi-protocol video decoding dynamic configuration system, comprising: The loading module is used to load an initial bit stream into the FPGA to build a hardware environment containing a static logic region and at least one reconfigurable logic region. The first comparison module is used to parse the target syntax elements of the current video stream entering the FPGA and perform a first comparison with the built-in protocol feature library to obtain the encoding protocol type of the current video stream; wherein, the syntax elements include at least one of start code, sequence parameter set and video data type; The second comparison module is used to perform a second comparison between the encoding protocol type of the current video stream and the protocol type corresponding to the current decoding logic active in the reconfigurable logic region of the FPGA; The first decoding module is used to decode the current video stream according to the current decoding logic when the second comparison result is consistent, so as to obtain the decoded first video data. The reconfiguration module is used to read a portion of the bitstream corresponding to the encoding protocol type of the current video stream from the external configuration memory when the results of the second comparison are inconsistent, so as to reconfigure the reconfigurable logical region and keep the operation of the static logical region unaffected. The second decoding module is used to switch the current video stream to the reconfigured reconfigurable logical region for decoding, and obtain the decoded second video data; The determination module is used to take the first video data or the second video data as the final video data after decoding.

[0015] Optionally, the first comparison module is further configured to continuously identify the protocol of the current video stream entering the FPGA in order to form a continuous closed-loop control for protocol changes.

[0016] Optionally, the second aspect also includes: The update module is used to add partial bitstream files of new protocol types to the external configuration memory to update the built-in protocol feature library.

[0017] Optionally, the reconfiguration module includes: The determining unit is used to determine the storage address of the corresponding portion of the bit stream in the external configuration memory based on the encoding protocol type of the current video stream; The reading unit is used to read a portion of the bitstream data corresponding to the encoding protocol type of the current video stream based on the storage address.

[0018] Thirdly, the present invention provides a computer device, including a processor and a memory; wherein, when the processor executes a computer program stored in the memory, it implements the steps of the FPGA-based multi-protocol video decoding dynamic configuration method described in the first aspect.

[0019] Fourthly, the present invention provides a computer-readable storage medium for storing a computer program; when the computer program is executed by a processor, it implements the steps of the FPGA-based multi-protocol video decoding dynamic configuration method described in the first aspect.

[0020] This invention provides a dynamic configuration method and system for multi-protocol video decoding based on FPGA. The method can accurately identify the encoding protocol type of the current video stream by real-time parsing of the syntax elements of the video stream (such as start code, sequence parameter set, etc.) and comparing them with the built-in protocol feature library.

[0021] When a protocol change is detected, only the reconfigurable logic area of ​​the FPGA is partially reconfigured, while the static logic area continues to operate without being affected. This achieves protocol switching at the millisecond or even microsecond level, effectively avoiding video stream interruption.

[0022] By adopting a partial bitstream reconfiguration mechanism, only hardware resources related to the decoding logic are replaced, rather than the entire FPGA is reconstructed, which significantly reduces configuration time and resource overhead.

[0023] FPGA hardware resources can be dynamically allocated and released according to actual decoding needs, avoiding the problems of resource rigidity and low utilization in traditional ASIC or fixed FPGA solutions.

[0024] New video coding standards can be supported by adding new partial bitstream files to an external configuration storage device without requiring hardware modifications or downtime upgrades.

[0025] Continuously monitor protocol changes in the input video stream, automatically trigger a reconfiguration process, form an adaptive multi-protocol decoding, and improve the robustness of video decoding. Attached Figure Description

[0026] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A flowchart illustrating a dynamic configuration method for multi-protocol video decoding based on FPGA provided in an embodiment of the present invention; Figure 2This is a schematic diagram of the structure of a multi-protocol video decoding dynamic configuration system based on FPGA provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] like Figure 1 As shown, this embodiment of the invention provides a dynamic configuration method for multi-protocol video decoding based on FPGA, including: Step 101: Load the initial bit stream into the FPGA to build a hardware environment containing a static logic region and at least one reconfigurable logic region.

[0030] After the FPGA is powered on, it first performs an initialization operation. The key to this process is loading an initial or default functional bitstream for the FPGA. This default functional bitstream can be a basic video path (such as video stream pass-through) or decoding logic for a most commonly used protocol (such as MIPI). At the same time, it ensures that the FPGA's static logic areas (such as video input / output interfaces, memory controllers, and the dynamic configuration controller itself) are correctly configured and operating stably.

[0031] Step 102: Parse the target syntax elements of the current video stream entering the FPGA and perform a first comparison with the built-in protocol feature library to obtain the encoding protocol type of the current video stream; wherein, the syntax elements include at least one of start code, sequence parameter set and video data type.

[0032] The current video stream enters the FPGA through an input interface (such as MIPI, SDI, LVDS, etc.). The FPGA parses the data packet header information or specific identifiers of the video stream in real time to determine the decoding protocol required for the current video stream. For example, this module detects specific syntax elements such as the Start Code, Sequence Parameter Set (SPS), and Data Type, and compares them with the built-in protocol feature library to quickly and accurately determine the encoding standard (such as LVDS, MIPI, etc.) and its key parameters (such as resolution, frame rate, color depth, etc.) used by the current video stream. The real-time performance and accuracy of this process are crucial, as they are prerequisites for triggering subsequent dynamic reconfiguration.

[0033] The core area of ​​an FPGA consists of programmable logic blocks (CLBs), block RAM (BRAM), digital signal processor (DSP) chips, and other resources, which are used to implement the hardware acceleration logic (such as decoding, dequantization, and inverse transformation) required by different video decoding protocols.

[0034] Step 103: Perform a second comparison between the encoding protocol type of the current video stream and the protocol type corresponding to the current decoding logic active in the reconfigurable logic region of the FPGA.

[0035] The identification result (protocol type identifier, such as RAW10, YUV, MJPEG, etc.) in step 102 is compared with the protocol type identifier corresponding to the decoding logic currently active in the FPGA reconfigurable partition (reconfigurable logic area). If they match, it means that the current hardware logic has been matched, no reconfiguration is triggered, the video stream is directly transmitted to the existing decoding logic for processing, and the operation in step 104 is executed. If they do not match, a reconfiguration trigger signal is immediately generated, and the operation in step 105 is executed.

[0036] Step 104: If the results of the second comparison are consistent, decode the current video stream according to the current decoding logic to obtain the decoded first video data.

[0037] Step 105: If the results of the second comparison are inconsistent, read a portion of the bitstream corresponding to the encoding protocol type of the current video stream from the external configuration memory to reconfigure the reconfigurable logical region and keep the operation of the static logical region unaffected.

[0038] In this embodiment, the reconfiguration of the reconfigurable logical region is called partial reconfiguration. When partial reconfiguration is triggered, the storage address of the corresponding bitstream file in the external configuration memory is calculated based on the protocol type identifier, and the partial bitstream data is read through the memory controller (such as an AXI interface). Subsequently, the new bitstream data is precisely written into the pre-divided reconfigurable partition through the internal configuration access port inside the FPGA. It is important to note that partial reconfiguration technology means that this process only rewrites the configuration memory cells of a specified area in the FPGA, while the static logical partition and other running functions are completely unaffected. This achieves "hot-plugging" of hardware functions, ensuring uninterrupted or only extremely brief micro-interruptions in video stream processing, and greatly shortening the configuration time.

[0039] The external configuration memory is used to store complete or partial bitstream files for various video decoding protocols. In this step, the storage address of the corresponding partial bitstream in the external configuration memory is determined according to the encoding protocol type of the current video stream; the partial bitstream data corresponding to the encoding protocol type of the current video stream is read according to the storage address.

[0040] Step 106: Switch the current video stream to the reconfigured reconfigurable logical region for decoding to obtain the decoded second video data.

[0041] After the partial reconfiguration process is completed, the logic functions within the reconfigurable partition of the FPGA are immediately updated to the new video decoder. The input video stream is switched to the newly generated hardware decoding logic for real-time, high-speed decoding operations. The decoded raw pixel data is buffered and post-processed by the frame buffer controller (used to store the input encoded frames and the decoded reconstructed frames, providing data buffering for operations such as motion compensation. It typically uses external DDR memory or pattern data), and finally output to the display device or subsequent processing unit according to standard timing through the video output interface (used to convert the decoded raw video data (such as YUV format) for format conversion and timing adjustment).

[0042] Step 107: Use either the first video data or the second video data as the final video data after decoding.

[0043] For example, this embodiment also includes continuously identifying the protocol of the current video stream entering the FPGA to form a continuous closed-loop control for protocol changes.

[0044] Add a portion of the bitstream file for the new protocol type to the external configuration memory to update the built-in protocol feature library.

[0045] For example, steps 102-107 are not completed all at once, but constitute a continuous, closed-loop automatic control method. The method continuously monitors the protocol characteristics of the input video stream. Once a protocol change is detected, steps 102-107 are automatically repeated, achieving dynamic and seamless switching between different decoding protocols. This design gives the method provided in this embodiment long-term adaptability and scalability; by adding bitstream files of new protocol types to an external configuration memory, it can support new video coding standards in the future.

[0046] In summary, the FPGA-based multi-protocol video decoding dynamic configuration method provided in this embodiment combines partial dynamic reconfiguration technology of the FPGA with a real-time protocol identification mechanism to achieve high-performance, seamless switching of multi-protocol video decoding. Its core is the ability to identify the encoding protocol of the input video stream in real time, and only when the protocols mismatch, to perform a "hot-swap" update of the reconfigurable logic area of ​​the FPGA by dynamically loading a portion of the bitstream, while maintaining the continuous operation of the static logic. This mechanism completely avoids the video stream interruption problem caused by the need for a complete reset during protocol switching in traditional solutions. Simultaneously, it achieves on-demand dynamic allocation of hardware resources, thus significantly improving the system's resource utilization, real-time performance, and multi-protocol adaptability while maintaining near-ASIC decoding performance and software-level flexibility. This effectively overcomes the technical bottlenecks of existing ASIC, software decoding, and traditional FPGA solutions in terms of flexibility, switching efficiency, and resource utilization.

[0047] Example 2 Based on the same inventive concept as Embodiment 1, this embodiment provides a dynamic configuration system for multi-protocol video decoding based on FPGA. Since the principle of solving the problem in this system is similar to that of the aforementioned dynamic configuration method for multi-protocol video decoding based on FPGA, the implementation of this system can refer to the implementation of the dynamic configuration method for multi-protocol video decoding based on FPGA.

[0048] like Figure 2 As shown, the FPGA-based multi-protocol video decoding dynamic configuration system includes: Loading module 10 is used to load an initial bit stream in the FPGA to build a hardware environment containing a static logic region and at least one reconfigurable logic region.

[0049] The first comparison module 20 is used to parse the target syntax elements of the current video stream entering the FPGA and perform a first comparison with the built-in protocol feature library to obtain the encoding protocol type of the current video stream; wherein, the syntax elements include at least one of start code, sequence parameter set and video data type.

[0050] The second comparison module 30 is used to perform a second comparison between the encoding protocol type of the current video stream and the protocol type corresponding to the current decoding logic active in the reconfigurable logic region of the FPGA.

[0051] The first decoding module 40 is used to decode the current video stream according to the current decoding logic when the second comparison result is consistent, so as to obtain the decoded first video data.

[0052] The reconfiguration module 50 is used to read a portion of the bitstream corresponding to the encoding protocol type of the current video stream from the external configuration memory when the results of the second comparison are inconsistent, so as to reconfigure the reconfigurable logical region and keep the operation of the static logical region unaffected.

[0053] The second decoding module 60 is used to switch the current video stream to a reconfigured reconfigurable logical region for decoding, so as to obtain the decoded second video data.

[0054] The determination module 70 is used to take the first video data or the second video data as the final video data after decoding.

[0055] For example, the first comparison module is further configured to continuously identify the protocol of the current video stream entering the FPGA in order to form a continuous closed-loop control of protocol changes.

[0056] For example, the multi-protocol video decoding dynamic configuration system provided in this embodiment further includes: The update module is used to add partial bitstream files of new protocol types to the external configuration memory to update the built-in protocol feature library.

[0057] For example, the reconfiguration module includes: The determining unit is used to determine the storage address of the corresponding portion of the bit stream in the external configuration memory based on the encoding protocol type of the current video stream; The reading unit is used to read a portion of the bitstream data corresponding to the encoding protocol type of the current video stream based on the storage address.

[0058] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in Example 1, which will not be repeated here.

[0059] Example 3 This embodiment provides a computer device, including a processor and a memory; wherein, when the processor executes a computer program stored in the memory, it implements the steps of the FPGA-based multi-protocol video decoding dynamic configuration method described in Embodiment 1.

[0060] For a more detailed explanation of the above method, please refer to the relevant content disclosed in Example 1, which will not be repeated here.

[0061] Example 4 This embodiment provides a computer-readable storage medium for storing a computer program; when the computer program is executed by a processor, it implements the steps of the FPGA-based multi-protocol video decoding dynamic configuration method described in Embodiment 1.

[0062] For a more detailed explanation of the above method, please refer to the relevant content disclosed in Example 1, which will not be repeated here.

[0063] Example 5 This embodiment provides a computer program product, including computer-executable instructions or a computer program. When the computer-executable instructions or the computer program are executed by a processor, they implement the steps of the FPGA-based multi-protocol video decoding dynamic configuration method described in Embodiment 1.

[0064] For a more detailed explanation of the above method, please refer to the relevant content disclosed in Example 1, which will not be repeated here.

[0065] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems, devices, storage media, and computer program products disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0066] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0067] In some embodiments, computer-executable instructions may take the form of programs, software, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

[0068] As an example, computer-executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple co-located files (e.g., files that store one or more modules, subroutines, or code sections).

[0069] As an example, computer-executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located at one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0070] The present invention has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present invention. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and embodiments of the present invention without departing from the spirit and scope of the invention, and all such modifications and improvements fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims.

Claims

1. A dynamic configuration method for multi-protocol video decoding based on FPGA, characterized in that, include: Load the initial bitstream into the FPGA to build a hardware environment that includes a static logic region and at least one reconfigurable logic region; The target syntax elements of the current video stream entering the FPGA are parsed and compared with the built-in protocol feature library to obtain the encoding protocol type of the current video stream; wherein, the syntax elements include at least one of start code, sequence parameter set and video data type; A second comparison is made between the encoding protocol type of the current video stream and the protocol type corresponding to the current decoding logic active in the reconfigurable logic region of the FPGA; If the second comparison results are consistent, the current video stream is decoded according to the current decoding logic to obtain the decoded first video data; If the results of the second comparison are inconsistent, a portion of the bitstream corresponding to the encoding protocol type of the current video stream is read from the external configuration memory to reconfigure the reconfigurable logical region while keeping the operation of the static logical region unaffected. The current video stream is switched to the reconfigured reconfigurable logical region for decoding to obtain the decoded second video data; Use either the first video data or the second video data as the final video data after decoding.

2. The multi-protocol video decoding dynamic configuration method according to claim 1, characterized in that, Also includes: The protocol of the current video stream entering the FPGA is continuously identified to form a continuous closed-loop control for protocol changes.

3. The multi-protocol video decoding dynamic configuration method according to claim 1, characterized in that, Also includes: Add a portion of the bitstream file for the new protocol type to the external configuration memory to update the built-in protocol feature library.

4. The multi-protocol video decoding dynamic configuration method according to claim 1, characterized in that, In the event of a discrepancy in the second comparison result, a portion of the bitstream corresponding to the encoding protocol type of the current video stream is read from the external configuration memory to reconfigure the reconfigurable logical region while ensuring that the operation of the static logical region remains unaffected, including: The storage address of the corresponding portion of the bitstream in the external configuration memory is determined based on the encoding protocol type of the current video stream; Read the portion of bitstream data corresponding to the encoding protocol type of the current video stream based on the storage address.

5. A dynamic configuration system for multi-protocol video decoding based on FPGA, characterized in that, include: The loading module is used to load an initial bit stream into the FPGA to build a hardware environment containing a static logic region and at least one reconfigurable logic region. The first comparison module is used to parse the target syntax elements of the current video stream entering the FPGA and perform a first comparison with the built-in protocol feature library to obtain the encoding protocol type of the current video stream; wherein, the syntax elements include at least one of start code, sequence parameter set and video data type; The second comparison module is used to perform a second comparison between the encoding protocol type of the current video stream and the protocol type corresponding to the current decoding logic active in the reconfigurable logic region of the FPGA; The first decoding module is used to decode the current video stream according to the current decoding logic when the second comparison result is consistent, so as to obtain the decoded first video data. The reconfiguration module is used to read a portion of the bitstream corresponding to the encoding protocol type of the current video stream from the external configuration memory when the results of the second comparison are inconsistent, so as to reconfigure the reconfigurable logical region and keep the operation of the static logical region unaffected. The second decoding module is used to switch the current video stream to the reconfigured reconfigurable logical region for decoding, and obtain the decoded second video data; The determination module is used to take the first video data or the second video data as the final video data after decoding.

6. The multi-protocol video decoding dynamic configuration system according to claim 5, characterized in that, The first comparison module is also used to continuously identify the protocol of the current video stream entering the FPGA in order to form a continuous closed-loop control for protocol changes.

7. The multi-protocol video decoding dynamic configuration system according to claim 5, characterized in that, Also includes: The update module is used to add partial bitstream files of new protocol types to the external configuration memory to update the built-in protocol feature library.

8. The multi-protocol video decoding dynamic configuration system according to claim 5, characterized in that, The reconfiguration module includes: The determining unit is used to determine the storage address of the corresponding portion of the bit stream in the external configuration memory based on the encoding protocol type of the current video stream; The reading unit is used to read a portion of the bitstream data corresponding to the encoding protocol type of the current video stream based on the storage address.

9. A computer device, characterized in that, It includes a processor and a memory; wherein, when the processor executes the computer program stored in the memory, it implements the steps of the FPGA-based multi-protocol video decoding dynamic configuration method according to any one of claims 1-4.

10. A computer-readable storage medium, characterized in that, Used to store computer programs; when the computer programs are executed by a processor, they implement the steps of the FPGA-based multi-protocol video decoding dynamic configuration method as described in any one of claims 1-6.

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