Semiconductor device and preparation method thereof, memory and memory system
By forming a multi-layer protective layer structure on the sidewall of the gating layer in the phase-change memory, the problem of insufficient protection of the gating layer sidewall is solved, and the stability of the gating layer and the reliability of the semiconductor device are improved.
Patent Information
- Application Number
- CN202311784675.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-22
- Publication Date
- 2026-01-13
AI Technical Summary
The sidewall protection layer of the gated layer in existing phase-change memories is insufficient to support their stability during long-term use.
A multi-layer protective layer structure is formed around the sidewalls of the gate layer, including a first protective layer, a second protective layer, and a third protective layer. The oxide and nitride protective layers are formed by chemical vapor deposition and plasma etching processes to avoid damage to the gate layer during the cleaning process.
This enhances the protection of the sidewalls of the gate layer, improves the stability of the gate layer, prevents damage during subsequent processes, and improves the reliability of semiconductor devices.
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Figure CN121335104A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of electronic devices, and more particularly, to a semiconductor device and a preparation method thereof, a memory and a storage system. BACKGROUND
[0002] Semiconductor memory is the foundation of information technology, with a market of hundreds of billions of dollars worldwide. As a candidate for the next generation of non-volatile semiconductor memory, phase change random access memory (PCRAM) has received widespread attention due to its high-speed reading, high erasable number of times, non-volatility, small component size, low power consumption, resistance to strong vibration and radiation, and other advantages.
[0003] Phase change memory is a semiconductor memory based on a phase change material, which is a material that can be electrically converted between amorphous and polycrystalline states. The basic principle of phase change memory is to use an electric pulse signal to act on a device cell, causing the phase change material to undergo reversible phase change between amorphous and polycrystalline states, and by distinguishing between high resistance in amorphous state and low resistance in polycrystalline state, the operation of information writing, erasing and reading out is realized.
[0004] The protection layer of the gate layer sidewall in the current phase change memory is not sufficient to support its stability during subsequent long-term use.
[0005] SUMMARY
[0006] The purpose of the present application is to provide a semiconductor device and a preparation method thereof, a memory and a storage system, aiming to increase the protection of the gate layer sidewall.
[0007] In a first aspect, the present application provides a semiconductor device, comprising:
[0008] a plurality of memory cells, the memory cell comprising a first electrode, a gate layer, a second electrode, a phase change layer and a third electrode stacked in sequence;
[0009] a first protection layer surrounding the sidewall of the gate layer;
[0010] a second protection layer surrounding the sidewall of the memory cell, and the first protection layer is located between the second protection layer and the gate layer;
[0011] a third protection layer surrounding the sidewall of the memory cell, and the second protection layer is located between the third protection layer and the first protection layer.
[0012] In some embodiments, the first protection layer comprises an oxide.
[0013] In some embodiments, the second protective layer comprises nitride, and the third protective layer comprises oxide.
[0014] In some embodiments, the first protective layer is located between the first electrode and the second electrode.
[0015] In some embodiments, the first electrode and the second electrode protrude from the gate layer in a first direction, and the first protective layer is connected to the second protective layer away from the sidewall of the gate layer.
[0016] In some embodiments, the semiconductor device further comprises:
[0017] a fourth protective layer surrounding the sidewall of the first protective layer away from the gate layer, the sidewall of the first electrode, the sidewall of the second electrode, the sidewall of the phase change layer, and the sidewall of the third electrode;
[0018] wherein the second protective layer is located between the fourth protective layer and the third protective layer.
[0019] In some embodiments, the semiconductor device further comprises:
[0020] a metal layer located on a side of the first electrode away from the gate layer;
[0021] wherein the second protective layer and the third protective layer further extend to the sidewall of the metal layer, and the fourth protective layer is located on a side of the metal layer close to the first electrode.
[0022] In some embodiments, the semiconductor device further comprises:
[0023] a fifth protective layer surrounding the sidewall of the third electrode and the sidewall of the phase change layer;
[0024] a sixth protective layer surrounding the sidewall of the fifth protective layer and located between the fifth protective layer and the second protective layer;
[0025] wherein the fifth protective layer and the sixth protective layer are located on a side of the second electrode away from the gate layer.
[0026] In some embodiments, the fifth protective layer comprises nitride, and the sixth protective layer comprises oxide.
[0027] In a second aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising:
[0028] forming a plurality of memory cells, each memory cell comprising a first electrode, a gate layer, a second electrode, a phase change layer, and a third electrode stacked in sequence;
[0029] forming a first protective layer around sidewalls of the storage unit;
[0030] forming a second protective layer around sidewalls of the storage unit, the first protective layer being between the second protective layer and the gate layer;
[0031] forming a third protective layer around sidewalls of the storage unit, the second protective layer being between the third protective layer and the first protective layer.
[0032] In some embodiments, the step of forming a plurality of storage units comprises:
[0033] providing a substrate;
[0034] forming a first conductive layer, a gate material layer, a second conductive layer, a phase change material layer and a third conductive layer on the substrate in sequence;
[0035] etching the third conductive layer and the phase change material layer to form the third electrode and the phase change layer;
[0036] etching the second conductive layer, the gate material layer and the first conductive layer to form the second electrode, the gate layer and the first electrode, the gate layer being recessed inwardly relative to the second electrode and the first electrode along a first direction, the first direction being parallel to the substrate.
[0037] In some embodiments, the step of forming a first protective layer around sidewalls of the gate layer comprises:
[0038] generating silicon by introducing silicon tetrachloride and hydrogen into a process cavity through a decoupled plasma process;
[0039] introducing oxygen to react with the silicon to form silicon oxide as a protective material layer on sidewalls of the recess and the storage unit, the protective material layer in the recess being a first protective layer.
[0040] In some embodiments, the method for manufacturing a semiconductor device further comprises:
[0041] forming a metal material layer between the substrate and the first conductive layer;
[0042] etching the metal material layer and the protective material layer to form a metal layer extending along a second direction and remove part or all of the protective material layer on the sidewalls of the storage unit, part of the protective material layer on the sidewalls of the storage unit remaining as a fourth protective layer, the second direction being parallel to the substrate and intersecting the first direction.
[0043] In some embodiments, the step of etching the metal material layer and the protective material layer comprises:
[0044] plasma etching the metal material layer and the protective material layer by introducing oxygen and fluorides;
[0045] The oxygen introduced for forming the protective material layer is the same process as the oxygen introduced for the plasma etching.
[0046] In some embodiments, before the step of etching the second conductive layer, the gating material layer and the first conductive layer, the method for manufacturing the semiconductor device further comprises:
[0047] A fifth protective layer and a sixth protective layer are formed in sequence on the sidewall of the third electrode and the phase change layer.
[0048] In some embodiments, the step of forming the second protective layer and the step of forming the third protective layer comprise:
[0049] When the protective material layer of the sidewall of the memory cell is completely removed, a second protective layer is deposited on the sidewall of the sixth protective layer, the second electrode, the first protective layer, the first electrode and the metal layer;
[0050] A third protective layer is deposited on the sidewall of the second protective layer.
[0051] In some embodiments, the step of forming the second protective layer and the step of forming the third protective layer comprise:
[0052] When the protective material layer of the sidewall of the memory cell is partially removed, a second protective layer is deposited on the sidewall of the fourth protective layer and the metal layer;
[0053] A third protective layer is deposited on the sidewall of the second protective layer.
[0054] In some embodiments, before the step of forming the second protective layer and the step of forming the third protective layer, the method for manufacturing the semiconductor device further comprises:
[0055] After the step of etching the metal material layer and the protective material layer, a cleaning process is performed on the memory cell.
[0056] In a third aspect, the present application provides a memory, comprising:
[0057] The semiconductor device in any of the above embodiments;
[0058] A peripheral circuit, which is electrically connected with the semiconductor device.
[0059] In a fourth aspect, the present application provides a memory system, comprising:
[0060] The memory provided by the third aspect;
[0061] A controller, electrically connected with the memory, configured to control the memory to store data.
[0062] The present application provides a semiconductor device and a preparation method thereof, a memory and a storage system. The semiconductor device comprises a plurality of memory cells, a first protective layer, a second protective layer and a third protective layer. The memory cell comprises a first electrode, a gating layer, a second electrode, a phase change layer and a third electrode which are stacked in sequence; the first protective layer surrounds the sidewall of the gating layer; the second protective layer surrounds the sidewall of the memory cell, and the first protective layer is located between the second protective layer and the gating layer; and the third protective layer surrounds the sidewall of the memory cell, and the second protective layer is located between the third protective layer and the first protective layer. Since the sidewall of the gating layer is provided with the first protective layer, the second protective layer and the third protective layer, the protection of the gating sidewall can be increased, and the stability of the gating layer can be improved. BRIEF DESCRIPTION OF DRAWINGS
[0063] The technical solutions and other beneficial effects of the present application will become apparent from the following detailed description of the specific embodiments of the present application, taken in conjunction with the accompanying drawings.
[0064] Figure 1 is a structural schematic diagram of a semiconductor device provided by some embodiments of the present application;
[0065] Figure 2 is a structural schematic diagram of a semiconductor device provided by some embodiments of the present application;
[0066] Figure 3 is a flowchart of a preparation method of a semiconductor device provided by some embodiments of the present application;
[0067] Figures 4a-4i is a structural schematic diagram of a semiconductor device in a preparation process provided by some embodiments of the present application;
[0068] Figures 5a-5c is a structural schematic diagram of a semiconductor device in a preparation process provided by some embodiments of the present application;
[0069] Figure 6 is a structural schematic diagram of a memory provided by some embodiments of the present application;
[0070] Figure 7 is a structural schematic diagram of a storage system provided by some embodiments of the present application. DETAILED DESCRIPTION
[0071] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0072] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.
[0073] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.
[0074] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.
[0075] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0076] This paper uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the third direction. The first, second, and third directions intersect each other, that is, X, Y, and Z intersect each other, for example, they can be perpendicular to each other or form a certain angle.
[0077] Please see Figure 1 ,Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application. The semiconductor device 100 can be a wafer, which can be diced to form multiple chips, such as a three-dimensional memory. Three-dimensional memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.
[0078] Semiconductor device 100 includes a plurality of memory cells 10, a first protective layer 20, a second protective layer 30, and a third protective layer 40. Each memory cell 10 includes a first electrode 11, a gate layer 12, a second electrode 13, a phase change layer 14, and a third electrode 15 stacked sequentially. The first protective layer 20 surrounds the sidewall of the gate layer 12; the second protective layer 30 surrounds the sidewall of the memory cell 10, and the first protective layer 20 is located between the second protective layer 30 and the gate layer 12; the third protective layer 40 surrounds the sidewall of the memory cell 10, and the second protective layer 30 is located between the third protective layer 40 and the first protective layer 20.
[0079] The semiconductor device 100 also includes a substrate 50, which may include a substrate and peripheral circuitry (not shown) located on the substrate, with the memory cell 10 located on the substrate 50.
[0080] The storage cell 10, from bottom to top (along the third direction (Z)), includes a first electrode 11, a gate layer 12, a second electrode 13, a phase change layer 14, and a third electrode 15. The first electrode 11, the second electrode 13, and the third electrode 15 can be made of the same material, all of which can include carbon. The material of the gate layer 12 can include Zn. x Te y 、Ge x Te y 、Nb x O y Si x As y As x Te y The material of phase transition layer 14 may include, for example, chalcogenide-based materials, which comprise any one of the four elements forming part of Group VIA of the periodic table: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). Materials of phase transition layer 14 may include, for example, compounds of chalcogenides with more electropositive elements or radicals, combinations of chalcogenides with other materials (such as transition metals), and chalcogenide alloys. Chalcogenide alloys typically contain one or more elements from Group IVA of the periodic table, such as germanium (Ge) and tin (Sn). Typically, chalcogenide alloys include combinations of one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag).
[0081] The semiconductor device 100 may further include a metal layer 60 located on the side of the first electrode 11 opposite to the gate layer 12, i.e., between the substrate 50 and the first electrode 11. In some embodiments, the metal layer 60 may be a bit line extending along a second direction (Y), and the material of the metal layer 60 may include tungsten.
[0082] The second protective layer 30 and the third protective layer 40 also extend to the sidewall of the metal layer 60.
[0083] The semiconductor device 100 may also include a word line 70 located on the side of the third electrode 15 away from the phase change layer 14 and extending along a first direction (X).
[0084] In some embodiments, the first protective layer 20 comprises an oxide, such as silicon oxide; the second protective layer 30 comprises a nitride, such as silicon nitride; and the third protective layer 40 comprises an oxide, such as silicon oxide.
[0085] Since the second protective layer 30 surrounds the sidewalls of the first electrode 11, the gate layer 12, the second electrode 13, the phase change layer 14, and the third electrode 15, and the third protective layer 40 surrounds the sidewalls of the first electrode 11, the gate layer 12, the second electrode 13, the phase change layer 14, and the third electrode 15, the sidewall of the gate layer 12 has three protective layers (OX-SiN-OX), which can enhance the protection of the sidewall of the gate layer 12.
[0086] In some embodiments, the first protective layer 20 is located between the first electrode 11 and the second electrode 13, so the second protective layer 30 can be connected to the sidewalls of the first electrode 11 and the second electrode 13.
[0087] In some embodiments, the first electrode 11 and the second electrode 13 protrude from the gate layer 12 along a first direction (X), and the first protective layer 20 is connected to the second protective layer 30 away from the sidewall of the gate layer 12. Specifically, the dimensions of the first electrode 11 and the second electrode 13 along the first direction (X) are larger than the dimensions of the gate layer 12 along the first direction (X), and the difference between the dimensions of the first electrode 11 or the second electrode 13 and the gate layer 12 along the first direction (X) is equal to the dimension of the first protective layer 20 along the first direction (X).
[0088] In some embodiments, the gate layer 12 is square, the first protective layer 20 surrounds the gate layer 12, and the second protective layer 30 and the third protective layer 40 surround the first protective layer 20.
[0089] In some embodiments, the semiconductor device 100 further includes a fifth protective layer 80 and a sixth protective layer 90. The fifth protective layer 80 surrounds the sidewall of the third electrode 15 and the sidewall of the phase change layer 14, and the sixth protective layer 90 surrounds the sidewall of the fifth protective layer 80 and is located between the fifth protective layer 80 and the second protective layer 30. The fifth protective layer 80 and the sixth protective layer 90 are located on the side of the second electrode 13 away from the gate layer 12. Therefore, the sidewall of the phase change layer 14 has four protective layers (the fifth protective layer 80, the sixth protective layer 90, the second protective layer 30, and the third protective layer 40), which increases the protection of the phase change layer 14.
[0090] Specifically, the second electrode 13 protrudes from the phase change layer 14 and the third electrode 15 along the first direction (X), meaning that the dimension of the second electrode 13 along the first direction (X) is larger than the dimensions of the phase change layer 14 and the third electrode 15 along the first direction (X). Further, the dimension of the second electrode 13 along the first direction (X) is equal to the sum of the dimensions of the fifth protective layer 80, the sixth protective layer 90, and the phase change layer 14 (or the third electrode 15) along the first direction (X). The second protective layer 30 is located on the sidewalls of the sixth protective layer 90, the second electrode 13, the first protective layer 20, the first electrode 11, and the metal layer 60.
[0091] In some embodiments, the fifth protective layer 80 comprises a nitride, such as silicon nitride; and the sixth protective layer 90 comprises an oxide, such as silicon oxide.
[0092] The semiconductor device also includes a thermal insulation layer located between the third protective layers 40, i.e., filling the spaces between each memory cell 10. The thermal insulation layer is a special material containing carbon (C), nitrogen (N), and oxygen (O), which has good filling and thermal insulation properties.
[0093] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application. For ease of understanding and brief description, the same structures in this embodiment and those in the above embodiments use the same reference numerals, and the same structures will not be described in detail.
[0094] The semiconductor device 200 includes a first protective layer 20, a second protective layer 30, a third protective layer 40, and a fourth protective layer 21. The fourth protective layer 21 surrounds the sidewall of the first protective layer 20 away from the gate layer 12, the sidewall of the first electrode 11, the sidewall of the second electrode 13, the sidewall of the phase transition layer 14, and the sidewall of the third electrode 15. The second protective layer 30 is located between the fourth protective layer 21 and the third protective layer 40.
[0095] In some embodiments, the fourth protective layer 21 is made of the same material as the first protective layer 20 and is interconnected. Compared to the semiconductor device 100, the gate layer 12 in the semiconductor device 200 has four protective layers on its sidewalls. If the fourth protective layer 21 and the first protective layer 20 are considered as a single film, it is equivalent to increasing the size of the first protective layer 20 along the first direction (X).
[0096] In some embodiments, the fourth protective layer 21 is located on the side of the metal layer 60 close to the first electrode 11, and the metal layer 60 protrudes from the first electrode 11 and the second electrode 13 along a first direction (X).
[0097] Specifically, the dimension of the metal layer 60 along the first direction (X) can be equal to the sum of the dimensions of the fourth protective layer 21 and the first electrode 11 (or the second electrode 13) along the first direction (X).
[0098] The second protective layer 30 and the third protective layer 40 can be formed by chemical vapor deposition, while the etching process for the memory cell 10 and the metal layer 60 can be carried out by plasma etching. Plasma etching has strong directionality and can etch the material along a third direction (Z). However, the equipment for chemical vapor deposition and plasma etching are different. There is a cleaning process between the plasma etching process and the chemical vapor deposition process. This cleaning process exposes the wafer to the atmospheric environment and a large amount of cleaning solution, which can easily cause material damage to the selector layer 12.
[0099] The semiconductor device provided in this application forms a first protective layer 20 on the sidewall of the gate layer 12 before forming the second protective layer 30 and the third protective layer 40 using a chemical vapor deposition process. Therefore, the first protective layer 20 can be formed before the cleaning process, thus avoiding damage to the gate layer 12 caused by the cleaning process. Furthermore, a stable protective layer (OX-SiN-OX) is formed on the sidewall of the gate layer 12, increasing the protection of the sidewall and improving the stability of the gate layer 12.
[0100] Please see Figure 3 , Figure 3 This is a schematic flowchart illustrating the fabrication method of the semiconductor device provided in some embodiments of the application. Please also refer to... Figures 4a-4i and Figures 5a-5c , Figures 4a-4i These are schematic diagrams illustrating the fabrication process of semiconductor devices provided in some embodiments of this application. Figures 5a-5c This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application during the fabrication process. This embodiment uses the fabrication of semiconductor devices 100 and 200 as examples to illustrate the fabrication method of the semiconductor device. Therefore, please refer to... Figures 1-2 The method for fabricating this semiconductor device includes the following steps S1-S4.
[0101] Step S1: Form a plurality of storage cells 10, wherein the storage cells 10 include a first electrode 11, a gate layer 12, a second electrode 13, a phase change layer 14 and a third electrode 15 stacked in sequence.
[0102] Specifically, step S1 may include the following steps.
[0103] 1) such as Figure 4a As shown, a substrate 50 is provided, on which a first conductive layer 11a, a gate material layer 12a, a second conductive layer 13a, a phase change material layer 14a, a third conductive layer 15a and a hard mask layer 16a are sequentially formed.
[0104] 2) such as Figure 4b As shown, a plasma etching process is performed on the hard mask layer 16a, the third conductive layer 15a and the phase change material layer 14a to form the hard mask pattern layer 16, the third electrode 15 and the phase change layer 14.
[0105] 3) such as Figure 4d and Figure 4e As shown, the second conductive layer 13a, the gate material layer 12a and the first conductive layer 11a are etched to form the second electrode 13, the gate layer 12 and the first electrode 11. The gate layer 12 is recessed relative to the second electrode 13 and the first electrode 11 along a first direction (X) to form a groove R. The first direction (X) is parallel to the substrate 50.
[0106] Specifically, such as Figure 4d As shown, the second conductive layer 13a, the gate material layer 12a, and the first conductive layer 11a can be sequentially subjected to plasma etching to form the second electrode 13, the initial gate layer 12b, and the first electrode 11; as Figure 4e As shown, the initial gate layer 12b is then etched to form a groove R and a gate layer 12 that are recessed relative to the first electrode 11 and the second electrode 13.
[0107] In some embodiments, the etching gas for the third conductive layer 15a, the second conductive layer 13a, and the first conductive layer 11a may include oxygen and nitrogen, and the etching gas for the gate layer 12 may include methane, nitrogen, and hydrogen.
[0108] In some embodiments, the second conductive layer 13a may be etched first, then the gate material layer 12a may be etched to form a groove R and a gate layer 12 that are recessed relative to the second electrode 13, and finally the first electrode 11 may be etched.
[0109] In some embodiments, such as Figure 4cAs shown, prior to the etching steps of the second conductive layer 13a, the gate material layer 12a, and the first conductive layer 11a, the fabrication method of the semiconductor device further includes: sequentially forming a fifth protective layer 80 and a sixth protective layer 90 on the sidewalls of the third electrode 15 and the phase change layer 14. Specifically, the fifth protective layer 80 and the sixth protective layer 90 can be formed using a chemical vapor deposition process.
[0110] Step S2: Form a first protective layer 20 around the sidewall of the gate layer 12.
[0111] Specifically, step S2 may include: 1) introducing silicon tetrachloride and hydrogen into the process chamber through a decoupled plasma process to generate silicon; 2) introducing oxygen to react with the silicon, thereby forming silicon oxide as a protective material layer 20a on the recess R and the sidewalls of the storage unit 10. Figure 4f As shown, a protective material layer 20a is formed on all sidewalls of the storage unit 10, and the protective material layer 20a in the groove R is the first protective layer 20.
[0112] For example, SiCl4 and H2 in a volume ratio of 1:2 can be introduced into the process chamber as reactant gases, with the pressure set at 10 mT and the reaction temperature at 65 degrees Celsius. Then, oxygen is introduced to react with silicon to generate silicon oxide. Silicon oxide can be directly produced by introducing gases using a plasma etching process without changing the equipment. Moreover, the first protective layer 20 can be generated after the etching process of the memory cell 10 is completed.
[0113] The method for fabricating this semiconductor device also includes: Figure 4a As shown, a metal material layer 60a is formed between the substrate 50 and the first conductive layer 11a; as Figure 4g As shown, the metal material layer 60a and the protective material layer 20a are etched to form a metal layer 60 extending along the second direction (Y) and part or all of the protective material layer 20a (referring to the protective material layer 20a other than the first protective layer 20) on the sidewall of the storage cell 10 are removed. The part of the protective material layer 20a remaining on the sidewall of the storage cell 10 becomes the fourth protective layer 21. The second direction (Y) is parallel to the substrate 50 and intersects the first direction (X).
[0114] Specifically, oxygen and fluorides are introduced to perform plasma etching on the metal material layer 60a and the protective material layer 20a. The etching gas for the metal material layer 60a includes fluorides (CF4, NF3) and oxygen, and this etching gas also etches the protective material layer 20a. Since fluorides can also cause some damage to the gate layer 12, a first protective layer 20 is formed on the sidewall of the gate layer 12 before etching the metal material layer 60a. This also prevents the etching process of the metal material layer 60a from damaging the gate layer 12.
[0115] In some embodiments, the oxygen introduced to form the protective material layer 20a and the oxygen introduced during plasma etching are performed in one process. That is, in step S2, SiCl4 and H2 can be introduced first, but oxygen is not introduced. Instead, the oxygen in the etching gas of the metal material layer 60a is used to form the protective material layer 20a, i.e., the protective material layer 20a is formed and etched simultaneously.
[0116] The method for fabricating this semiconductor device further includes: after etching the metal material layer 60a and the protective material layer 20a, performing a cleaning process on the memory cell 10. Then, a second protective layer 30 and a third protective layer 40 are deposited. Therefore, the first protective layer 20 can be formed when the etching process of the memory cell 10 and the metal layer 60 is completed, followed by a cleaning process, and finally the deposition of the second protective layer 30 and the third protective layer 40. The cleaning solution for the cleaning process includes citric acid and hydrofluoric acid, and the first protective layer 20 can prevent the selection layer 12 from being damaged during the cleaning process.
[0117] Step S3: Form a second protective layer 30 around the sidewall of the storage cell 10, wherein the first protective layer 20 is located between the second protective layer 30 and the gate layer 12.
[0118] Step S4: Form a third protective layer 40 around the sidewall of the storage unit 10, wherein the second protective layer 30 is located between the third protective layer 40 and the first protective layer 20.
[0119] In some embodiments, such as Figure 4g and Figure 4h As shown, when the protective material layer 20a of the storage cell sidewall 10 is partially removed, a second protective layer 30 is deposited on the sidewall of the fourth protective layer 21 and the sidewall of the metal layer 60; a third protective layer 40 is deposited on the sidewall of the second protective layer 30.
[0120] In some embodiments, such as Figure 5a and 5bAs shown, when the protective material layer 20a on the sidewall of the storage cell 10 is completely removed, a second protective layer 30 is deposited on the sidewall of the sixth protective layer 90, the second electrode 13, the first protective layer 20, the first electrode 11, and the sidewall of the metal layer 60; a third protective layer 40 is deposited on the sidewall of the second protective layer 30.
[0121] Specifically, after the cleaning process, a second protective layer 30 and a third protective layer 40 are formed sequentially using a chemical vapor deposition process.
[0122] The method for fabricating this semiconductor device also includes: Figure 4i and Figure 5c As shown, a heat insulation layer 17 is filled between each storage cell 10, that is, the heat insulation layer 17 is located between the third protective layers 40. The heat insulation layer 17 is a special material containing carbon (C), nitrogen (N), and (O), which has good filling and heat insulation effects.
[0123] The method for fabricating this semiconductor device also includes: Figure 1 and Figure 2 As shown, the hard mask pattern layer 16 on top of the memory cell 10 can be removed by chemical mechanical polishing process, and word lines 70 extending in the second direction (Y) can be formed above the third electrode 15.
[0124] The semiconductor device fabrication method provided in this application incorporates a decoupling plasma process before the etching process of the metal material layer 60a. After etching is completed, a first protective layer 20 is formed on the sidewall of the gate layer 12, thus protecting the gate layer 12 from damage during the cleaning process. Furthermore, after forming the second protective layer 30 and the third protective layer 40, a stable three-layer protective layer is formed on the sidewall of the gate layer 12, improving the stability of the gate layer 12.
[0125] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a memory provided in some embodiments of this application. The memory 300 can be a three-dimensional memory, such as a phase-change memory.
[0126] The memory 300 includes a semiconductor device 301 and peripheral circuitry 302. The semiconductor device 301 can be any of the semiconductor devices described in the above embodiments, and the peripheral circuitry 302 can be various control structures made of CMOS (Complementary Metal-Oxide-Semiconductor). The peripheral circuitry 302 is electrically connected to the semiconductor device 301 to transmit signals. The peripheral circuitry 302 can be used for logic operations and to control and detect the switching states of each memory cell in the semiconductor device 301 via metal interconnects, thereby enabling data storage and retrieval.
[0127] The semiconductor device 301 includes: a plurality of memory cells, each memory cell including a first electrode, a gate layer, a second electrode, a phase change layer and a third electrode stacked sequentially; a first protective layer surrounding the sidewall of the gate layer; a second protective layer surrounding the sidewall of the memory cell, with the first protective layer located between the second protective layer and the gate layer; and a third protective layer surrounding the sidewall of the memory cell, with the second protective layer located between the third protective layer and the first protective layer.
[0128] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. The storage system 400 includes a memory 401 and a controller 402. The memory 401 can be the memory in any of the above embodiments, and the memory 401 can include any of the semiconductor devices in the above embodiments. The controller 402 is electrically connected to the memory 401 and is used to control the memory 401 to store data. The memory 401 can perform data storage operations based on the control of the controller 402.
[0129] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.
[0130] The semiconductor device in the memory 401 includes: a plurality of memory cells, each memory cell including a first electrode, a gate layer, a second electrode, a phase change layer and a third electrode stacked sequentially; a first protective layer surrounding the sidewall of the gate layer; a second protective layer surrounding the sidewall of the memory cell, with the first protective layer located between the second protective layer and the gate layer; and a third protective layer surrounding the sidewall of the memory cell, with the second protective layer located between the third protective layer and the first protective layer.
[0131] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes: Multiple storage cells, each storage cell comprising a first electrode, a gating layer, a second electrode, a phase change layer, and a third electrode stacked sequentially; A first protective layer surrounds the sidewall of the gated layer; A second protective layer surrounds the sidewall of the storage cell, and the first protective layer is located between the second protective layer and the gate layer; A third protective layer surrounds the sidewall of the storage cell, and a second protective layer is located between the third protective layer and the first protective layer.
2. The semiconductor device according to claim 1, characterized in that, The first protective layer comprises oxides.
3. The semiconductor device according to claim 1, characterized in that, The second protective layer comprises a nitride, and the third protective layer comprises an oxide.
4. The semiconductor device according to claim 1, characterized in that, The first protective layer is located between the first electrode and the second electrode.
5. The semiconductor device according to claim 4, characterized in that, The first electrode and the second electrode protrude from the gate layer along a first direction, and the sidewall of the first protective layer away from the gate layer is connected to the second protective layer.
6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A fourth protective layer surrounds the sidewall of the first protective layer away from the gate layer, the sidewall of the first electrode, the sidewall of the second electrode, the sidewall of the phase change layer, and the sidewall of the third electrode; The second protective layer is located between the fourth protective layer and the third protective layer.
7. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes: A metal layer is located on the side of the first electrode opposite to the gate layer; The second and third protective layers extend to the sidewall of the metal layer, and the fourth protective layer is located on the side of the metal layer near the first electrode.
8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The fifth protective layer surrounds the sidewall of the third electrode and the sidewall of the phase transition layer; A sixth protective layer surrounds the sidewall of the fifth protective layer and is located between the fifth protective layer and the second protective layer; The fifth protective layer and the sixth protective layer are located on the side of the second electrode away from the gate layer.
9. The semiconductor device according to claim 8, characterized in that, The fifth protective layer comprises nitrides, and the sixth protective layer comprises oxides.
10. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes: Multiple memory cells are formed, each memory cell comprising a first electrode, a gating layer, a second electrode, a phase change layer, and a third electrode stacked sequentially. A first protective layer is formed around the sidewalls of the gated layer; A second protective layer is formed around the sidewall of the memory cell, and the first protective layer is located between the second protective layer and the gate layer; A third protective layer is formed around the sidewall of the storage cell, and the second protective layer is located between the third protective layer and the first protective layer.
11. The method for fabricating the semiconductor device according to claim 10, characterized in that, The step of forming multiple storage cells includes: Provide a base; A first conductive layer, a gated material layer, a second conductive layer, a phase change material layer, and a third conductive layer are sequentially formed on the substrate. The third conductive layer and the phase change material layer are etched to form the third electrode and the phase change layer; The second conductive layer, the gate material layer, and the first conductive layer are etched to form the second electrode, the gate layer, and the first electrode. The gate layer is recessed relative to the second electrode and the first electrode along a first direction to form a groove, and the first direction is parallel to the substrate.
12. The method for fabricating the semiconductor device according to claim 11, characterized in that, The step of forming a first protective layer surrounding the sidewalls of the gated layer includes: Silicon is generated by introducing silicon tetrachloride and hydrogen into the process chamber through decoupled plasma technology. Oxygen is introduced to react with the silicon to form silicon oxide as a protective material layer in the groove and the sidewall of the storage unit, wherein the protective material layer in the groove is a first protective layer.
13. The method for fabricating the semiconductor device according to claim 12, characterized in that, The method for fabricating the semiconductor device further includes: A metal material layer is formed between the substrate and the first conductive layer; The metal material layer and the protective material layer are etched to form a metal layer extending along the second direction and to remove part or all of the protective material layer on the sidewall of the storage cell. The portion of the protective material layer remaining on the sidewall of the storage cell becomes the fourth protective layer. The second direction is parallel to the substrate and intersects the first direction.
14. The method for fabricating the semiconductor device according to claim 13, characterized in that, The step of etching the metal material layer and the protective material layer includes: The metal material layer and the protective material layer are plasma etched by introducing oxygen and fluoride. The oxygen introduced to form the protective material layer and the oxygen introduced during plasma etching are considered as one process.
15. The method for fabricating a semiconductor device according to claim 13, characterized in that, Prior to the step of etching the second conductive layer, the gate material layer, and the first conductive layer, the method for fabricating the semiconductor device further includes: A fifth protective layer and a sixth protective layer are sequentially formed on the sidewalls of the third electrode and the phase change layer.
16. The method for fabricating the semiconductor device according to claim 15, characterized in that, The steps of forming the second protective layer and forming the third protective layer include: When the protective material layer on the sidewall of the storage cell is completely removed, a second protective layer is deposited on the sixth protective layer, the second electrode, the first protective layer, the sidewall of the first electrode, and the sidewall of the metal layer. A third protective layer is deposited on the sidewall of the second protective layer.
17. The method for fabricating a semiconductor device according to claim 15, characterized in that, The steps of forming the second protective layer and forming the third protective layer include: When the protective material layer on the sidewall of the storage cell is partially removed, a second protective layer is deposited on the sidewall of the fourth protective layer and the sidewall of the metal layer. A third protective layer is deposited on the sidewall of the second protective layer.
18. The method for fabricating a semiconductor device according to claim 13, characterized in that, Before the steps of forming the second protective layer and forming the third protective layer, the method for fabricating the semiconductor device further includes: After etching the metal material layer and the protective material layer, the memory cell is cleaned.
19. A memory, characterized in that, include: The semiconductor device as described in any one of claims 1-9; The peripheral circuit is electrically connected to the semiconductor device.
20. A storage system, characterized in that, include: The memory as described in claim 19; A controller, electrically connected to the memory, is used to control the memory to store data.