Semiconductor structure and forming method thereof
By employing specific process steps to form the gate structure in a VFET, the surface roughness problem during the VFET gate metal etch-back process is solved, thereby improving the reliability and performance of the device.
Patent Information
- Application Number
- CN202410889435.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-03
- Publication Date
- 2026-01-13
AI Technical Summary
In the current VFET gate metal etch-back process, the metal surface roughness is relatively large, which affects the reliability of device performance.
The gate structure is formed using specific process steps, including forming a fin structure and a spacer layer on a semiconductor substrate, and forming a gate dielectric layer, a work function layer and a gate metal layer through etching and deposition processes, ensuring that the contact area between the gate structure and the fin structure is not affected by etching.
This improved the formation quality of the VFET gate, enhanced device reliability, reduced the roughness of the contact area between the gate structure and the fin structure, and improved device performance.
Smart Images
Figure CN121335128A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] The increased integration density of integrated circuits is due to the miniaturization of the underlying field-effect transistors (FETs). However, in recent years, with the evolution of process nodes, lateral fin field-effect transistors (FinFETs) can no longer meet the process requirements below 5nm. The new generation of vertical gate-around field-effect transistors (VFETs) overcomes the limitations of lateral gate spacing and can meet the requirements of sub-5nm processes, making them an ideal replacement for lateral FinFETs.
[0003] Current VFET gate stack fabrication processes require etch-back of the gate metal. The etching depth of this etch-back step plays a decisive role in defining the gate length and the thickness of the top spacer layer. However, due to the large metal grain size, the surface roughness of the etch-back gate metal is relatively large, which reduces the reliability of device performance.
[0004] Therefore, it is necessary to provide a more efficient and reliable technical solution to improve the formation quality of VFET gates and enhance the reliability of VFET device performance. Summary of the Invention
[0005] This application provides a semiconductor structure and a method for forming the same, which can improve the formation quality of the VFET gate and enhance the reliability of the VFET device performance.
[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a first doped layer is formed on the surface of the semiconductor substrate, a fin structure and a hard mask layer located on the top surface of the fin structure are formed on the surface of the first doped layer, and bottom spacer layers are further formed on the surfaces of the first doped layer on both sides of the fin structure; a sacrificial layer and a first dielectric layer are sequentially formed on the surface of the bottom spacer layer, the top surface of the first dielectric layer being flush with the top surface of the hard mask layer; removing the hard mask layer to form a first opening; forming a top spacer layer on the sidewall of the first opening; forming a second doped layer in the first opening, filling the first opening and extending to the surface of the first dielectric layer; forming a second dielectric layer on the surfaces of the first dielectric layer and the second doped layer; etching portions of the first dielectric layer and the second dielectric layer to expose the sacrificial layer; removing the sacrificial layer to expose the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer; and forming a gate structure on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer.
[0007] In some embodiments of this application, the top surface of the gate structure is lower than the top surface of the fin structure.
[0008] In some embodiments of this application, the top surface of the gate structure is higher than the top surface of the fin structure.
[0009] In some embodiments of this application, the gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer.
[0010] In some embodiments of this application, the method of forming a gate structure on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer includes: sequentially forming a gate dielectric layer, a work function layer, and a gate metal layer on the surface of the bottom spacer layer, the sidewall of the fin structure, the surface of the first dielectric layer, and the surface of the second dielectric layer; and removing a portion of the gate dielectric layer, the work function layer, and the gate metal layer that is higher than the bottom surface of the first dielectric layer.
[0011] In some embodiments of this application, the method of sequentially forming a gate dielectric layer and a work function layer on the surface of the bottom spacer layer, the sidewall of the fin structure, the surface of the first dielectric layer, and the surface of the second dielectric layer includes an atomic layer deposition process, and the method of forming a gate metal layer on the surface of the work function layer includes a chemical vapor deposition process.
[0012] Another aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate, a first doped layer formed on the surface of the semiconductor substrate, a fin structure formed on the surface of the first doped layer, and bottom spacer layers further formed on the surfaces of the first doped layer on both sides of the fin structure; a top spacer layer formed on the top surface of the sidewall of the fin structure, the sidewall of the top spacer layer being flush with the sidewall of the fin structure, a first dielectric layer formed on the sidewall of the top spacer layer or on the sidewall of the top spacer layer and part of the sidewall of the fin structure, a second doped layer formed on the top surface of the fin structure between the top spacer layers, the second doped layer extending to the surface of the first dielectric layer; a second dielectric layer formed on the surfaces of the first dielectric layer and the second doped layer; and a gate structure formed on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer.
[0013] In some embodiments of this application, the top surface of the gate structure is lower than the top surface of the fin structure.
[0014] In some embodiments of this application, the top surface of the gate structure is higher than the top surface of the fin structure.
[0015] In some embodiments of this application, the gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer.
[0016] This application provides a semiconductor structure and a method for forming the same, which can improve the formation quality of the VFET gate and enhance the reliability of the VFET device performance. Attached Figure Description
[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0018] in:
[0019] Figures 1 to 10 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to some embodiments of this application;
[0020] Figure 11 This is a schematic diagram of the semiconductor structure described in other embodiments of this application. Detailed Implementation
[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0023] Figures 1 to 10 These are schematic diagrams illustrating the steps in the method for forming a semiconductor structure according to some embodiments of this application. The method for forming a semiconductor structure according to embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0024] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, on which a first doped layer 110 is formed. A fin structure 120 and a hard mask layer 121 located on the top surface of the fin structure 120 are formed on the surface of the first doped layer 110. Bottom spacer layers 130 are also formed on the surfaces of the first doped layer 110 on both sides of the fin structure 120.
[0025] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0026] In some embodiments of this application, the first doped layer 110 serves as the bottom source / drain of the VFET device. The first doped layer 110 can be formed by ion implantation followed by annealing of the semiconductor substrate 100. Alternatively, the first doped layer 110 can be formed by etching the semiconductor substrate 100 followed by in-situ doping and epitaxial growth, and then annealing. The doping type of the first doped layer 110 is determined according to device requirements and can be P-type or N-type.
[0027] In some embodiments of this application, the fin structure 120 may be formed by etching the semiconductor substrate 100. Alternatively, the fin structure 120 may be formed by epitaxial growth of an epitaxial layer on the surface of the semiconductor substrate 100 followed by etching the epitaxial layer. The hard mask layer 121 serves as a mask during the etching process of the fin structure 120.
[0028] In some embodiments of this application, the material of the bottom spacer layer 130 includes insulating materials such as silicon oxide or silicon nitride.
[0029] refer to Figure 2 As shown, a sacrificial layer 131 and a first dielectric layer 140 are sequentially formed on the surface of the bottom spacer layer 130, and the top surface of the first dielectric layer 140 is flush with the top surface of the hard mask layer 121.
[0030] In some embodiments of this application, the material of the sacrificial layer 131 includes amorphous silicon, etc.
[0031] In some embodiments of this application, the material of the first dielectric layer 140 includes TEOS, etc.
[0032] In some embodiments of this application, the top surface of the sacrificial layer 131 is lower than the top surface of the fin structure 120. In some embodiments of this application, the top surface of the sacrificial layer 131 is higher than the top surface of the fin structure 120. The height of the sacrificial layer 131 determines the subsequent gate height, and different gate heights affect different parameters of the device. Specifically, when the top surface of the sacrificial layer 131 is lower than the top surface of the fin structure 120, the top surface of the subsequently formed gate structure is also lower than the top surface of the fin structure 120. When the top surface of the sacrificial layer 131 is higher than the top surface of the fin structure 120, the top surface of the subsequently formed gate structure is also higher than the top surface of the fin structure 120.
[0033] refer to Figure 3 As shown, the hard mask layer 121 is removed to expose the top surface of the fin structure 120, thereby forming a first opening 122.
[0034] refer to Figure 4 As shown, a top spacer layer 150 is formed on the sidewall of the first opening 122.
[0035] In some embodiments of this application, the material of the top spacer layer 150 is the same as the material of the bottom spacer layer 130.
[0036] refer to Figure 5 As shown, a second doped layer 160 is formed in the first opening 122, filling the first opening 122 and extending to the surface of the first dielectric layer 140.
[0037] In some embodiments of this application, the second doped layer 160 serves as the top source / drain of the VFET device. The second doped layer 160 can be formed by in-situ doping epitaxial growth. The doping type of the second doped layer 160 is set according to device requirements and can be P-type or N-type.
[0038] refer to Figure 6 As shown, a second dielectric layer 170 is formed on the surface of the first dielectric layer 140 and the second doped layer 160.
[0039] In some embodiments of this application, the material of the second dielectric layer 170 may be the same as the material of the first dielectric layer 140, such as TEOS.
[0040] refer to Figure 7 As shown, the first dielectric layer 140 and the second dielectric layer 170 are etched to expose the sacrificial layer 131.
[0041] In some embodiments of this application, when the first dielectric layer 140 and the second dielectric layer 170 are etched to expose the sacrificial layer 131, the etching selectivity of the first dielectric layer 140, the second dielectric layer 170 and the sacrificial layer 131 is relatively high, for example greater than 10. Therefore, the sacrificial layer 131 will not be damaged during the etching of the first dielectric layer 140 and the second dielectric layer 170.
[0042] refer to Figure 8 As shown, the sacrificial layer 131 is removed to expose the surface of the bottom spacer layer 130, the sidewalls of the fin structure 120, and the bottom surface of the first dielectric layer 140.
[0043] In some embodiments of this application, the method for removing the sacrificial layer 131 includes wet etching.
[0044] In some embodiments of this application, when the sacrificial layer 131 is removed by wet etching, the etching selectivity of the sacrificial layer 131 and the first dielectric layer 140, the second dielectric layer 170, the bottom spacer layer 130, and the fin structure 120 is relatively high, for example greater than 10. Therefore, the first dielectric layer 140, the second dielectric layer 170, the bottom spacer layer 130, and the fin structure 120 will not be damaged during the etching of the sacrificial layer 131.
[0045] refer to Figure 9 and Figure 10 As shown, a gate structure 180 is formed on the surface of the bottom spacer layer 130, the sidewall of the fin structure 120, and the bottom surface of the first dielectric layer 140.
[0046] In some embodiments of this application, the gate structure 180 includes a gate dielectric layer 181, a work function layer 182, and a gate metal layer 183, which are sequentially located on the surface of the bottom spacer layer 130, the sidewall of the fin structure 120, and the bottom surface of the first dielectric layer 140.
[0047] In some embodiments of this application, the method of forming a gate structure 180 on the surface of the bottom spacer layer 130, the sidewalls of the fin structure 120, and the bottom surface of the first dielectric layer 140 includes: referring to Figure 9 As shown, a gate dielectric layer 181, a work function layer 182, and a gate metal layer 183 are sequentially formed on the surface of the bottom spacer layer 130, the sidewall of the fin structure 120, the surface of the first dielectric layer 140, and the surface of the second dielectric layer 170; Reference Figure 10 As shown, the portion of the gate dielectric layer 181, work function layer 182, and gate metal layer 183 above the bottom surface of the first dielectric layer 140 is removed.
[0048] In some embodiments of this application, the method of sequentially forming a gate dielectric layer 181 and a work function layer 182 on the surface of the bottom spacer layer 130, the sidewall of the fin structure 120, the surface of the first dielectric layer 140, and the surface of the second dielectric layer 170 includes an atomic layer deposition process, and the method of forming a gate metal layer 183 on the surface of the work function layer 182 includes a chemical vapor deposition process.
[0049] In some embodiments of this application, the top surface height of the gate structure 180 is related to the parasitic capacitance and channel resistance of the device. When... Figure 10 As shown, when the top surface of the gate structure 180 is lower than the top surface of the fin structure 120, the channel resistance of the device can be reduced, but the parasitic capacitance increases. In other embodiments, for example... Figure 11 As shown, when the top surface of the gate structure 180 is higher than the top surface of the fin structure 120, the parasitic capacitance of the device can be reduced, but the channel resistance increases. Specifically, a suitable structure can be selected according to the requirements for device parameters. Figure 11The semiconductor structure shown is Figure 10 Another embodiment of the semiconductor structure shown is different in that the top surface height of the gate structure 180 is different, while the other structures are the same.
[0050] In the technical solution of this application, the part of the gate structure 180 that is in contact with the fin structure 120 is not etched. This part of the gate structure 180 will not have excessively high surface roughness due to etching, which would affect the contact area between the gate structure 180 and the fin structure 120 and improve the reliability of the device performance.
[0051] This application provides a method for forming a semiconductor structure, which can improve the formation quality of the VFET gate and improve the reliability of the VFET device performance.
[0052] Embodiments of this application provide a semiconductor structure, with reference to... Figure 9 As shown, it includes: a semiconductor substrate 100, on the surface of which a first doped layer 110 is formed, and a fin structure 120 is formed on the surface of the first doped layer 110. Bottom spacer layers 130 are also formed on the surfaces of the first doped layers 110 on both sides of the fin structure 120. A top spacer layer 150 is formed on the top surface of the sidewall of the fin structure 120, and the sidewall of the top spacer layer 150 is flush with the sidewall of the fin structure 120. A first dielectric layer 140 is formed on the sidewalls of the partial spacer layer 150 and the partial fin structure 120. A second doped layer 160 is formed on the top surface of the fin structure 120 between the top spacer layer 150, and the second doped layer 160 extends to the surface of the first dielectric layer 140. A second dielectric layer 170 is formed on the surfaces of the first dielectric layer 140 and the second doped layer 160. A gate structure 180 is formed on the surface of the bottom spacer layer 130, the sidewalls of the fin structure 120, and the bottom surface of the first dielectric layer 140.
[0053] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0054] In some embodiments of this application, the first doped layer 110 serves as the bottom source / drain of the VFET device. The doping type of the first doped layer 110 is set according to device requirements and can be P-type or N-type.
[0055] In some embodiments of this application, the material of the bottom spacer layer 130 includes insulating materials such as silicon oxide or silicon nitride.
[0056] In some embodiments of this application, the material of the first dielectric layer 140 includes TEOS, etc.
[0057] In some embodiments of this application, the material of the top spacer layer 150 is the same as the material of the bottom spacer layer 130.
[0058] In some embodiments of this application, the second doped layer 160 serves as the top source / drain of the VFET device. The doping type of the second doped layer 160 is set according to device requirements and can be P-type or N-type.
[0059] In some embodiments of this application, the material of the second dielectric layer 170 may be the same as the material of the first dielectric layer 140, such as TEOS.
[0060] In some embodiments of this application, the gate structure 180 includes a gate dielectric layer 181, a work function layer 182, and a gate metal layer 183, which are sequentially located on the surface of the bottom spacer layer 130, the sidewall of the fin structure 120, and the bottom surface of the first dielectric layer 140.
[0061] In some embodiments of this application, the top surface of the gate structure 180 is lower than the top surface of the fin structure 120. In other embodiments of this application, the top surface of the gate structure 180 is higher than the top surface of the fin structure 120. The height of the top surface of the gate structure 180 is related to the parasitic capacitance and channel resistance of the device. Figure 10 As shown, when the top surface of the gate structure 180 is lower than the top surface of the fin structure 120, the channel resistance of the device can be reduced, but the parasitic capacitance increases. In other embodiments, such as... Figure 11 As shown, when the top surface of the gate structure 180 is higher than the top surface of the fin structure 120, the parasitic capacitance of the device can be reduced, but the channel resistance increases. Specifically, a suitable structure can be selected according to the requirements for device parameters.
[0062] In the technical solution of this application, the part of the gate structure 180 that is in contact with the fin structure 120 is not etched. This part of the gate structure 180 will not have excessively high surface roughness due to etching, which would affect the contact area between the gate structure 180 and the fin structure 120 and improve the reliability of the device performance.
[0063] This application provides a semiconductor structure and a method for forming the same, which can improve the formation quality of the VFET gate and enhance the reliability of the VFET device performance.
[0064] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0065] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0066] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0067] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0068] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a first doped layer is formed on the surface of the semiconductor substrate, a fin structure and a hard mask layer located on the top surface of the fin structure are formed on the surface of the first doped layer, and bottom spacer layers are also formed on the surfaces of the first doped layer on both sides of the fin structure. A sacrificial layer and a first dielectric layer are sequentially formed on the surface of the bottom spacer layer, with the top surface of the first dielectric layer being flush with the top surface of the hard mask layer. The hard mask layer is removed to form the first opening; A top spacer layer is formed on the sidewall of the first opening; A second doped layer is formed in the first opening, filling the first opening and extending to the surface of the first dielectric layer; A second dielectric layer is formed on the surface of the first dielectric layer and the second doped layer; The first and second dielectric layers are etched to expose the sacrificial layer. Remove the sacrificial layer to expose the surface of the bottom spacer layer, the sidewalls of the fin structure, and the bottom surface of the first dielectric layer; A gate structure is formed on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The top surface of the gate structure is lower than the top surface of the fin structure.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The top surface of the gate structure is higher than the top surface of the fin structure.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method of forming a gate structure on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer includes: A gate dielectric layer, a work function layer, and a gate metal layer are sequentially formed on the surface of the bottom spacer layer, the sidewall of the fin structure, the surface of the first dielectric layer, and the surface of the second dielectric layer. Remove the portion of the gate dielectric layer, work function layer, and gate metal layer that is above the bottom surface of the first dielectric layer.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method of sequentially forming a gate dielectric layer and a work function layer on the surface of the bottom spacer layer, the sidewall of the fin structure, the surface of the first dielectric layer, and the surface of the second dielectric layer includes atomic layer deposition, and the method of forming a gate metal layer on the surface of the work function layer includes chemical vapor deposition.
7. A semiconductor structure, characterized in that, include: A semiconductor substrate, wherein a first doped layer is formed on the surface of the semiconductor substrate, a fin structure is formed on the surface of the first doped layer, and bottom spacer layers are formed on the surfaces of the first doped layer on both sides of the fin structure. A top spacer layer is formed on the top surface of the sidewall of the fin structure. The sidewall of the top spacer layer is flush with the sidewall of the fin structure. A first dielectric layer is formed on the sidewall of the top spacer layer or on the sidewall of the top spacer layer and part of the sidewall of the fin structure. A second doped layer is formed on the top surface of the fin structure between the top spacers. The second doped layer extends to the surface of the first dielectric layer. A second dielectric layer is formed on the surface of the first dielectric layer and the second doped layer; A gate structure is formed on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer.
8. The semiconductor structure as described in claim 7, characterized in that, The top surface of the gate structure is lower than the top surface of the fin structure.
9. The semiconductor structure as described in claim 7, characterized in that, The top surface of the gate structure is higher than the top surface of the fin structure.
10. The semiconductor structure as claimed in claim 7, characterized in that, The gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer, the sidewall of the fin structure, and the bottom surface of the first dielectric layer.