Transverse MOSFET device based on beta-Ga2O3 substrate, preparation method thereof and semiconductor equipment

Abstract

The invention belongs to the technical field of semiconductor equipment, and particularly relates to a transverse MOSFET device based on a beta-Ga2O3 substrate, a preparation method of the transverse MOSFET device and semiconductor equipment. The transverse MOSFET device comprises a substrate, a lightly doped region, a first heavily doped region, a second heavily doped region, a first metal layer, a second metal layer, a gate dielectric layer and a gate metal layer. The transverse MOSFET device has the characteristics of high switch ratio and strong grid control capability, does not need to be etched, and is relatively low in cost.

Description

Technical Field

[0001] This application belongs to the field of semiconductor equipment technology, specifically relating to a lateral MOSFET device based on a β-Ga2O3 substrate, its fabrication method, and semiconductor equipment. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) possess numerous advantages, including fast switching speed, low on-resistance, low power consumption, and high reliability, making them an ideal choice for next-generation high-performance power devices. However, existing lateral MOSFET devices mostly employ trench gate structures, and their fabrication processes rely on etching technology. The instability of the etching process can easily lead to poor device uniformity, affecting device consistency. Furthermore, etching introduces lattice damage and surface defects, reducing device performance (such as increasing source-drain current and reducing reliability). In addition, the etching process increases the complexity of the process flow, raises manufacturing costs, and leads to a decrease in device manufacturing yield. Therefore, further improvements are needed in the structure and fabrication methods of lateral MOSFET devices. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in related technologies. To this end, this application proposes a lateral MOSFET device based on a β-Ga2O3 substrate, its fabrication method, and a semiconductor device thereof. This lateral MOSFET device features a high on / off ratio, strong gate control capability, and requires no etching, resulting in lower cost.

[0004] A first aspect of this application provides a lateral MOSFET device based on a β-Ga2O3 substrate, comprising:

[0005] A substrate having a protrusion in the middle, the substrate being made of β-Ga2O3;

[0006] A lightly doped region, the lightly doped region being located on the upper surface of the substrate, and the protrusion being embedded in the lightly doped region;

[0007] The first heavily doped region and the second heavily doped region are disposed on the upper surface of the substrate and are located on opposite sides of the lightly doped region;

[0008] A first metal layer is disposed on the upper surface of the first heavily doped region;

[0009] A second metal layer is disposed on the upper surface of the second heavily doped region;

[0010] A gate dielectric layer is disposed on the upper surface of the lightly doped region and located between the first metal and the second metal;

[0011] A gate metal layer is disposed on the upper surface of the gate dielectric layer and is disposed corresponding to the protrusion.

[0012] Therefore, this application provides a protrusion in the middle of the substrate of the lateral MOSFET device. In the on-state, the lightly doped region is conductive, serving as a conductive channel to allow current to flow smoothly. In the off-state, the gate electric field effectively depletes the charge carriers in the shallow conductive channel below the gate, ensuring the MOSFET device is completely turned off, thereby maintaining a high on / off ratio. Furthermore, with the same gate metal layer width, the protrusion brings the gate closer to the core of the channel, allowing the gate electric field to uniformly penetrate and modulate the channel, enhancing gate control capability and thus increasing transconductance. At the same time, stronger gate control capability accelerates switching and reduces switching delay.

[0013] According to an embodiment of this application, the width of the protrusion is 0.2 μm-10 μm; the height of the protrusion is 100 nm-200 nm. Thus, within the aforementioned width and height range of the protrusion, it helps to balance the channel area of ​​charge carriers with the gate control capability; the protrusion can form a reasonable potential gradient with the surrounding area, avoiding local electric field concentration, thereby improving breakdown voltage and power withstand capability.

[0014] According to an embodiment of this application, the composition of the first metal layer includes Ti / Au. Therefore, this composition allows the first metal layer to bond tightly with the first heavily doped region, preventing delamination during use, and also facilitating the formation of ohmic contacts between the first metal layer and the first heavily doped region.

[0015] According to an embodiment of this application, the composition of the second metal layer includes Ti / Au. Therefore, this composition allows the second metal layer to bond tightly with the second heavily doped region, preventing delamination during use, and also facilitating the formation of ohmic contacts between the second metal layer and the second heavily doped region.

[0016] According to embodiments of this application, at least one of the following conditions is met: the electron concentration of the lightly doped region is 3 × 10⁻⁶. 17 cm -3 -5×10 18 cm -3 The electron concentrations of the first heavily doped region and the second heavily doped region are each independently 1 × 10⁻⁶. 19 -5×10 19 cm -3 Therefore, within the aforementioned range, it is possible to ensure that there are sufficient charge carriers in the channel, ensuring that the current density of the lateral MOSFET device in the on-state meets the usage requirements, while also strengthening the control of the gate electric field on the channel charge carriers.

[0017] According to embodiments of this application, the gate dielectric layer is made of at least one of aluminum oxide, silicon oxide, hafnium oxide, or zirconium oxide, specifically aluminum oxide. Therefore, all of these materials are wide bandgap materials with excellent insulation properties, effectively reducing leakage current between the gate and the channel, thereby reducing the energy consumption of the lateral MOSFET device in the off state.

[0018] According to an embodiment of this application, the thickness of the gate dielectric layer is 15nm-40nm. Therefore, within this thickness range, the leakage current between the gate and the channel can be effectively reduced, thereby lowering the power consumption of the lateral MOSFET device in the non-operating state.

[0019] According to embodiments of this application, the gate metal layer is made of Cr / Au. This material strengthens the bond between the gate metal layer and the gate dielectric layer, preventing peeling or detachment of the gate metal layer during use, thereby ensuring the structural stability of the lateral MOSFET device.

[0020] According to embodiments of this application, the substrate is doped with at least one of Fe and Mg. Therefore, β-GaO is a wide-bandgap semiconductor with a certain conductivity. Doping with the aforementioned elements significantly reduces the carrier concentration of the substrate, thereby transforming the substrate into a semi-insulating state and preventing current leakage in the off-state.

[0021] A second aspect of this application provides a method for fabricating a lateral MOSFET device based on a β-Ga2O3 substrate, the method comprising:

[0022] A β-Ga2O3 substrate is provided, and a first region, a second region, a third region, a fourth region and a fifth region are defined on the β-Ga2O3 substrate. The second region and the third region are respectively located on opposite sides of the first region. The fourth region is located on the side of the second region away from the first region. The fifth region is located on the side of the third region away from the first region.

[0023] The upper surface of the β-Ga2O3 substrate is subjected to low-energy donor ion implantation and a first annealing treatment in sequence to obtain a first intermediate device;

[0024] The second region, the third region, the fourth region, and the fifth region are sequentially subjected to a first multi-energy donor ion implantation and a second annealing process to form a lightly doped region, thereby obtaining a second intermediate device;

[0025] The fourth region and the fifth region are subjected to a second multi-energy donor ion implantation and a third annealing process in sequence to form a first heavily doped region and a second heavily doped region;

[0026] A first metal layer and a second metal layer are formed on the upper surfaces of the first heavily doped region and the second heavily doped region, respectively, to obtain a third intermediate device;

[0027] A gate dielectric layer is formed on the upper surface of the lightly doped region to obtain a fourth intermediate device;

[0028] A gate metal layer is formed on the upper surface of the gate dielectric layer to obtain a lateral MOSFET device based on a β-Ga2O3 substrate.

[0029] Therefore, this method eliminates the need for etching; instead, it directly modulates the electrical performance of lateral MOSFET devices by creating protrusions on the β-Ga2O3 crystal substrate. This method not only significantly simplifies the process flow and reduces manufacturing costs, but also avoids the problems of lattice damage, surface defects, and difficulty in controlling etching uniformity that may be introduced by etching processes, thereby improving the manufacturing yield of lateral MOSFET devices.

[0030] According to embodiments of this application, the donor ions mentioned above include at least one of Si ions, Sn ions, and Ge ions. Therefore, these donor ions exhibit good compatibility with the substrate, reducing lattice damage; and their chemical properties are relatively stable, contributing to improved long-term device reliability.

[0031] According to embodiments of this application, the concentrations of donor ions in the first heavily doped region and the second heavily doped region are each independently 1 × 10⁻⁶. 19 cm -3 -5×10 19 cm -3 Therefore, within the aforementioned range, it helps to balance contact resistance and carrier mobility, suppress short-channel effects, and thus ensure the stability of lateral MOSFET devices.

[0032] According to embodiments of this application, at least one of the following conditions is satisfied:

[0033] The energy of the implantation source for the low-energy donor ion implantation is 30keV-40keV;

[0034] The dose of the implantation source for the low-energy donor ion implantation is 5 × 10⁻⁶. 13 ions / cm 2 -2×10 14 ions / cm 2 ;

[0035] The energy of the implantation source for the first multi-energy donor ion implantation is 40keV-150keV;

[0036] The dose of the implantation source for the first multi-energy donor ion implantation is 2 × 10⁻⁶. 12 -2×1013 ions / cm 2 ;

[0037] The energy of the implantation source for the second multi-energy donor ion implantation is 10keV-150keV;

[0038] The dose of the implantation source for the second multi-energy donor ion implantation is 6 × 10⁻⁶. 13 ions / cm 2 -5×10 14 ions / cm 2 .

[0039] A third aspect of this application provides a semiconductor device comprising the lateral MOSFET device based on a β-Ga2O3 substrate described above, or a lateral MOSFET device fabricated by the method described above for fabricating a lateral MOSFET device based on a β-Ga2O3 substrate. All features and parameters of this semiconductor device are identical to those of the lateral MOSFET device based on a β-Ga2O3 substrate described above, and will not be repeated here. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of a lateral MOSFET device based on a β-Ga2O3 substrate according to an embodiment of this application.

[0041] Figure 2 This is a flowchart of a method for fabricating a lateral MOSFET device based on a β-Ga2O3 substrate according to an embodiment of this application.

[0042] Reference numerals: 10: Substrate; 11: Protrusion; 12: First photoresist; 13: Second photoresist; 14: Third photoresist; 15: Fourth photoresist; 16: Fifth photoresist; 20: Lightly doped region; 21: Low-energy doped region; 30: First heavily doped region; 40: Second heavily doped region; 50: First metal layer; 60: Second metal layer; 70: Gate dielectric layer; 80: Gate metal layer; 90: β-Ga2O3 substrate; 91: First region; 92: Second region; 93: Third region; 94: Fourth region; 95: Fifth region. Detailed Implementation

[0043] The embodiments of this application are described in detail below, with examples of these embodiments illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0044] The first aspect of this application proposes a lateral MOSFET device based on a β-Ga2O3 substrate, with reference to... Figure 1The lateral MOSFET device includes the following structure:

[0045] Substrate 10, wherein a protrusion 11 is provided in the middle of the substrate, and the substrate is made of β-Ga2O3;

[0046] The lightly doped region 20 is located on the upper surface of the substrate 10, and the protrusion 11 is embedded in the lightly doped region 20.

[0047] The first heavily doped region 30 and the second heavily doped region 40 are disposed on the upper surface of the substrate 10 and are located on opposite sides of the lightly doped region 20.

[0048] A first metal layer 50 is disposed on the upper surface of the first heavily doped region 30;

[0049] A second metal layer 60 is disposed on the upper surface of the second heavily doped region 40;

[0050] A gate dielectric layer 70 is disposed on the upper surface of the lightly doped region 20 and is located between the first metal layer 50 and the second metal layer 60.

[0051] A gate metal layer 80 is disposed on the upper surface of the gate dielectric layer 70 and is disposed corresponding to the protrusion 11 (that is, the orthogonal projection of the gate metal layer 80 on the substrate 10 at least partially overlaps with the substrate 11).

[0052] Therefore, this application provides a protrusion 11 in the middle of the substrate of the lateral MOSFET device. In the on-state, the lightly doped region is conductive, serving as a conductive channel to allow current to flow smoothly. In the off-state, the gate electric field effectively depletes the charge carriers in the shallow conductive channel below the gate, ensuring that the MOSFET device is completely turned off, thereby maintaining a high on / off ratio. Furthermore, with the same width of the gate metal layer 80, the protrusion 11 brings the gate closer to the core of the channel, allowing the gate electric field to uniformly penetrate and modulate the channel, enhancing gate control capability and thus increasing transconductance. At the same time, the stronger gate control capability accelerates switching and reduces switching delay.

[0053] In this paper, the on / off ratio refers to the ratio of the current in the on-state to the current in the off-state of a lateral MOSFET device, reflecting the device's ability to regulate current. The on / off ratio can be obtained by measuring the device's transfer characteristic curve.

[0054] A channel is a carrier transport path formed by a semiconductor conductive layer that is modulated by a gate electric field, connecting the first heavily doped region and the second heavily doped region.

[0055] Transconductance refers to the rate of change of source-drain current (i.e., the current flowing through the first metal layer 50 and the second metal layer 60) with respect to the gate voltage, reflecting the switching speed of the device. Transconductance is obtained by measuring the transfer characteristic curve of the device.

[0056] According to embodiments of this application, the width of the protrusion 11 is 0.2 μm-10 μm, specifically within the range of 0.2 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, or any two of these ranges. This width range helps to balance the channel area of ​​charge carriers with the gate control capability. If the width of the protrusion 11 is too large, it will increase the on-resistance and decrease the current density; if the width of the protrusion 11 is too small, it may lead to insufficient gate control capability, reducing the on / off ratio and transconductance.

[0057] According to an embodiment of this application, the height of the protrusion 11 is 100nm-200nm, specifically such as 100nm, 120nm, 140nm, 160nm, 180nm, 200nm or any two of them.

[0058] According to embodiments of this application, the substrate may contain doping elements, and the type of doping element is not specifically limited, as long as it enables the substrate to achieve semi-insulation. According to embodiments of this application, the substrate is doped with at least one of Fe, Mg, and N. As an example, Fe is used as the doping atom. Therefore, β-Ga2O3 is a wide bandgap semiconductor with a certain conductivity. Doping with the above elements significantly reduces the carrier concentration of the substrate, thereby transforming the substrate into a semi-insulating state and preventing current leakage in the off-state.

[0059] According to an embodiment of this application, the first metal layer 50 is composed of Ti / Au, and the first metal layer 50 is a two-layer structure stacked on top of each other (not shown in the figure). As an example, the lower layer, which is in contact with the first heavily doped region 30, is composed of Ti, and the upper layer is composed of Au. Thus, the above composition allows the first metal layer 50 to be tightly bonded to the first heavily doped region 30, preventing delamination during use, and also facilitating the formation of ohmic contacts between the first metal layer 50 and the first heavily doped region 30.

[0060] According to an embodiment of this application, the second metal layer 60 is composed of Ti / Au, and the second metal layer 60 is a two-layer structure stacked on top of each other (not shown in the figure). As an example, the lower layer, which is in contact with the second heavily doped region 40, is composed of Ti, and the upper layer is composed of Au. Thus, the above composition allows the second metal layer 60 to be tightly bonded to the second heavily doped region 40, preventing delamination during use, and also facilitating the formation of ohmic contacts between the second metal layer 60 and the second heavily doped region 40.

[0061] According to an embodiment of this application, the electron concentration of the lightly doped region 20 is 3 × 10⁻⁶. 17 cm -3 -5×10 18 cm -3 For example, 3×10 17 cm -3 6×10 17 cm -3 9×10 17 cm -3 1×10 18 cm -3 2×10 18 cm -3 5×10 18 cm -3 Or a range between or equal to either of these. Therefore, within this range, sufficient charge carriers in the channel are ensured to meet the required current density during the on-state of the lateral MOSFET device, while also guaranteeing the control of the channel charge carriers by the gate electric field. If the electron concentration in the lightly doped region 20 is too low, the channel resistance will be too high, reducing the on-state current; if the electron concentration in the lightly doped region 20 is too high, the gate electric field may not be able to effectively modulate the channel carrier concentration, leading to a decrease in the on-off ratio.

[0062] According to the embodiments of this application, the electron concentrations of the first heavily doped region 30 and the second heavily doped region 40 are each independently 1×10⁻⁶. 19 cm -3 -5×10 19 cm -3 For example, 1×10 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 Or a range between or equal to either of these. Within this range, ohmic contact can be achieved, and good ohmic contact facilitates current input and output. If the electron concentration is too low, ohmic contact will not be possible; if the electron concentration is too high, it may increase contact resistance and reduce the on-state current.

[0063] According to embodiments of this application, the gate dielectric layer 70 is made of at least one of aluminum oxide, silicon oxide, hafnium oxide, or zirconium oxide, specifically aluminum oxide. Therefore, all of these materials are wide bandgap materials with excellent insulation properties, effectively reducing leakage current between the gate and the channel, thereby reducing the energy consumption of the lateral MOSFET device in the off state.

[0064] According to embodiments of this application, the thickness of the gate dielectric layer 70 is 15nm-40nm, specifically within the range of 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, or any two thereof. Therefore, within this thickness range, the leakage current between the gate and the channel can be effectively reduced, thereby lowering the power consumption of the lateral MOSFET device in its non-operating state. If the thickness is too large, it may weaken the modulation effect of the gate voltage on the channel, leading to an increase in threshold voltage and a decrease in transconductance; if the thickness is too small, the electric field strength is too high, which may make electrical breakdown more likely, reducing the reliability and lifespan of the lateral MOSFET device.

[0065] According to embodiments of this application, the gate metal layer 80 is made of Cr / Au. As an example, Cr / Au is used as the gate metal layer. Therefore, this material strengthens the bond between the gate metal layer and the gate dielectric layer, preventing peeling or detachment of the gate metal layer during use, thereby ensuring the structural stability of the lateral MOSFET device.

[0066] A second aspect of this application provides a method for fabricating a lateral MOSFET device based on a β-Ga2O3 substrate, comprising the following steps:

[0067] S10: A β-Ga2O3 substrate 90 is provided, on which a first region 91, a second region 92, a third region 93, a fourth region 94, and a fifth region 95 are defined. The second region 92 and the third region 93 are located on opposite sides of the first region 91, the fourth region 94 is located on the side of the second region 92 away from the first region 91, and the fifth region 95 is located on the side of the third region 93 away from the first region 91. (See schematic diagram below.) Figure 2 (a) in the middle.

[0068] S20: The upper surface of the β-Ga2O3 substrate 90 is sequentially subjected to low-energy donor ion implantation and a first annealing treatment to obtain a first intermediate device. See the schematic diagram below. Figure 2 (b) in the middle.

[0069] Therefore, ion implantation is performed directly on the upper surface of the β-Ga2O3 substrate 90 to form a low-energy doped region 21. This structure allows for precise control of carrier concentration and provides a transport path for carriers. The first annealing treatment can eliminate lattice damage during the ion implantation process and activate donor ions.

[0070] According to embodiments of this application, the energy of the implantation source for low-energy donor ion implantation is 30keV-40keV, specifically within the ranges of 30keV, 31keV, 32keV, 33keV, 34keV, 35keV, 36keV, 37keV, 38keV, 39keV, 40keV, or any two of these ranges. Therefore, within this range, it is beneficial for donor ions to be precisely implanted to a shallower depth.

[0071] According to an embodiment of this application, the dose of the implantation source for the low-energy donor ion implantation is 5 × 10⁻⁶. 13 ions / cm 2 -2×10 14 ions / cm 2 For example, 5×10 13 ions / cm 2 6×10 13 ions / cm 2 7×10 13 ions / cm 2 8×10 13 ions / cm 2 9×10 13 ions / cm 2 1×10 14 ions / cm 2 2×10 14 ions / cm 2 Or a range between or any two of these. Thus, within the aforementioned range, a suitable number of donor ions can be provided, thereby achieving an appropriate carrier concentration level after annealing. If the dose is too high, it may result in an excessively high carrier concentration, making complete turn-off difficult; if the dose is too low, insufficient donor ion implantation may result in an insufficient carrier concentration, reducing the conductivity of the lateral MOSFET device.

[0072] According to embodiments of this application, the first annealing temperature is 1000℃-1100℃, specifically 1000℃, 1020℃, 1040℃, 1060℃, 1080℃, 1100℃, or any range between two of these. Within this temperature range, donor ions are effectively activated, providing a sufficient number of charge carriers. Simultaneously, this temperature range also helps repair lattice damage caused during ion implantation, reducing lattice defects and thus improving the reliability of the lateral MOSFET device. If the first annealing temperature is too high, donor ion diffusion will occur, causing the donor ion distribution to deviate from the expected distribution. If the first annealing temperature is too low, lattice damage caused by ion implantation may not be completely repaired, and donor ions may not be sufficiently activated, thereby reducing carrier concentration and mobility, and similarly reducing the performance and reliability of the lateral MOSFET device.

[0073] According to embodiments of this application, the first annealing time is 110s-130s, specifically 110s, 115s, 120s, 125s, 130s, or any range between two of these. This time range allows for sufficient repair of lattice damage caused during ion implantation and activation of the implanted donor ions. If the first annealing time is too long, it may lead to excessive diffusion of donor ions, causing the low-energy doped region 21 to become deeper, preventing the achievement of the desired shallow junction structure and thus affecting the performance of the lateral MOSFET device. If the first annealing time is too short, it may not be able to completely repair the lattice damage caused by ion implantation, resulting in residual lattice defects, which also affects the device performance.

[0074] As a specific example, a β-Ga2O3 substrate 90 was placed in an ion implantation chamber, and the implantation parameters were adjusted so that the energy of the implantation source was 30keV-40keV and the dose of the implantation source was 5×10⁻⁶. 13 ions / cm 2 -2×10 14 ions / cm 2 A low-energy donor ion implantation step is performed. After implantation, a first annealing treatment is carried out at 1000℃-1100℃ for 110s-130s to form a low-energy doped region 21, thus obtaining the first intermediate device.

[0075] S30: Coat the upper surface of the β-Ga2O3 substrate corresponding to the first region 91 with a first photoresist 12. Perform first multi-energy donor ion implantation and second annealing treatment on the second region 92, the third region 93, the fourth region 94 and the fifth region 95 in sequence to form a lightly doped region 20. See the schematic diagram below. Figure 2 (c) In the diagram, the first photoresist 12 is removed to obtain the second intermediate device. (See schematic diagram below.) Figure 2 (d) in the middle.

[0076] In this step, a first photoresist 12 is coated on the upper surface of the β-Ga2O3 substrate corresponding to the first region 91. Donor ion implantation is performed multiple times on the second region 92, the third region 93, the fourth region 94, and the fifth region 95 using different energies, forming a lightly doped region 20 together with the low-energy doped region 21, and simultaneously forming a protrusion 11. Then, a second annealing process is performed, and the first photoresist 12 is removed to obtain the second intermediate device. The superposition of ion concentration distributions with different energies can form a continuous and relatively flat carrier concentration distribution over a wide depth range, thereby reducing the on-resistance and avoiding current concentration.

[0077] In this application, the height of the protrusion 11 is determined by the difference between the maximum depth of the first multi-energy donor ion implantation and the depth of the low-energy donor ion implantation region. The depth of the first multi-energy donor ion implantation region can be freely adjusted according to actual needs and donor ion implantation conditions. To ensure good switching performance, the depth of the low-energy donor ion implantation region needs to be less than the width of the maximum depletion layer under the carrier distribution in that region.

[0078] In this paper, the depletion layer refers to a space charge region that forms near the semiconductor surface when a metal and a semiconductor are in close contact. Due to the difference in their work functions, this region contains very few free carriers and is difficult to conduct electricity; this region is called the depletion layer. The width of the depletion layer is related to the work function of the metal and semiconductor, the doping concentration of the semiconductor, and the magnitude of the bias voltage.

[0079] According to an embodiment of this application, the energy of the implantation source for the first multi-energy donor ion implantation is 40keV-150keV, and the dose of the implantation source for the first multi-energy donor ion implantation is 2×10⁻⁶. 12 ions / cm 2 -2×10 13 ions / cm 2 Multi-energy implantation typically uses three different energies to implant different doses, ensuring a uniform concentration distribution of donor ions within a certain range. The energy and dose of the first multi-energy implantation are not strictly limited and can be freely adjusted according to the desired doping concentration and depth. As an example, an energy of 40 keV is used to implant a dose of 2.1 × 10⁻⁶ kilovolts. 12 ions / cm 2 The donor ions were then injected with an energy of 60 keV at a dose of 3.5 × 10⁻⁶. 12 ions / cm 2 The donor ions were finally injected with an energy of 115 keV at a dose of 1.75 × 10⁻⁶. 13 ions / cm 2 Donor ions, under these conditions, can achieve 2×10⁻⁶ at a depth of approximately 100 nm. 18 ions / cm 3 The donor ion concentration is uniformly distributed.

[0080] According to an embodiment of this application, the temperature of the second annealing is 1000℃-1100℃, specifically such as 1000℃, 1020℃, 1040℃, 1060℃, 1080℃, 1100℃, or any range between two of them. Therefore,

[0081] Within the aforementioned temperature range, donor ions are effectively activated, providing sufficient charge carriers. This range also helps repair lattice damage caused during ion implantation. If the second annealing temperature is too high, donor ions may diffuse, deviating from the expected donor ion distribution. If the second annealing temperature is too low, lattice damage caused by ion implantation may not be fully repaired, and donor ions may not be sufficiently activated, thus reducing the performance of the lateral MOSFET device.

[0082] According to embodiments of this application, the second annealing time is 110s-130s, specifically 110s, 115s, 120s, 125s, 130s, or any range between two of these. This time range allows for sufficient repair of lattice damage caused during ion implantation and full activation of donor ions. If the second annealing time is too long, it may lead to excessive diffusion of donor ions, causing the lightly doped region 20 to deepen, thereby reducing the gate's modulation capability to the channel. If the second annealing time is too short, it may not be able to completely repair the lattice damage caused by ion implantation, and the donor ions may not be fully activated, similarly affecting device performance.

[0083] As a specific example, a first photoresist 12 was coated on the upper surface of the β-Ga2O3 substrate 90 corresponding to the first region 91, and then placed in the ion implantation chamber. The implantation parameters were adjusted. The implantation source energies were sequentially used to be 40 keV, 60 keV, and 115 keV, and the implantation source dose was sequentially 2.1 × 10⁻⁶. 12 ions / cm 2 3.5×10 12 ions / cm 2 1.75×10 13 ions / cm 2 Multi-energy donor ion implantation was performed on regions 92, 93, 94, and 95. After the implantation step, a second annealing treatment was carried out at 1000℃-1100℃ for 110s-130s to form a lightly doped region 20. After removing the first photoresist 12, the second intermediate device was obtained.

[0084] S40: Photoresist 13 is coated onto the first region 91, the second region 92, and the third region 93 of the second intermediate device. The fourth region 94 and the fifth region 95 are sequentially subjected to second multi-energy donor ion implantation and third annealing treatment to form the first heavily doped region 30 and the second heavily doped region 40. (See schematic diagram below.) Figure 2 (e) in the middle.

[0085] According to embodiments of this application, the energy of the implantation source for the second multi-energy donor ion implantation is 10keV-150keV, specifically such as 10keV, 15keV, 20keV, 25keV, 30keV, 50keV, 70keV, 910keV, 110keV, 130keV, 150keV, or any range between two of these. Thus, within the aforementioned energy range, it is beneficial to form a first heavily doped region 30 and a second heavily doped region 40 of suitable depth, ensuring a high carrier concentration near the surface to ensure that the contact between the metal and the semiconductor is an ohmic contact.

[0086] According to an embodiment of this application, the dose of the implantation source for the second multi-energy donor ion implantation is 6 × 10⁻⁶. 13 ions / cm 2 -5×10 14 ions / cm 2 For example, 6×10 13 ions / cm 2 7×10 13 ions / cm 2 8×10 13 ions / cm 2 9×10 13 ions / cm 2 1×10 14 ions / cm 2 3×10 14 ions / cm 2 5×10 14 ions / cm 2 Or a range between either or both. Therefore, within the aforementioned dosage range, it helps to provide a higher carrier concentration, thus reducing ohmic contact resistance. If the dosage is too high, it may result in an excessive number of lattice damages, forming too many lattice defects and increasing contact resistance; if the dosage is too low, it may result in a low carrier concentration, making ohmic contact impossible.

[0087] As can be understood, similar to the first multi-energy donor ion implantation operation, the second multi-energy implantation also involves three separate donor ion implantations. The energy and dose of the second multi-energy implantation are not strictly limited and can be freely adjusted according to the desired doping concentration and depth. As an example, the first implantation is performed at an energy of 30 keV with a dose of 6.9 × 10⁻⁶. 13 ions / cm 2 Donor ions were then injected with an energy of 60 keV at a dose of 1 × 10⁻⁶. 14 ions / cm 2 The donor ions were finally injected with an energy of 115 keV at a dose of 4.2 × 10⁻⁶. 14 ions / cm2 donor ions.

[0088] According to embodiments of this application, the third annealing temperature is 1000℃-1100℃, specifically 1000℃, 1020℃, 1040℃, 1060℃, 1080℃, 1100℃, or any range between two of these. Therefore, within this temperature range, donor ions can be effectively activated to provide charge carriers; simultaneously, lattice damage caused during ion implantation can be repaired within this range. If the third annealing temperature is too high, donor ions may diffuse, deviating from the expected donor ion distribution; if the third annealing temperature is too low, lattice defects may not be completely repaired, and charge carriers may not be sufficiently activated, resulting in decreased conductivity.

[0089] According to embodiments of this application, the third annealing time is 110s-130s, specifically 110s, 115s, 120s, 125s, 130s, or any two of these ranges. Therefore, within this time range, lattice damage caused during ion implantation can be sufficiently repaired, thereby improving the performance of the lateral MOSFET device. If the third annealing time is too long, it may lead to excessive diffusion of donor ions, causing the first heavily doped region 30 and the second heavily doped region 40 to become deeper, damaging their interface with the β-Ga2O3 substrate 90, thus reducing the gate's modulation capability to the channel. If the third annealing time is too short, it may not be able to completely repair the lattice damage caused by ion implantation, failing to fully activate charge carriers, which also affects the device's performance and reliability.

[0090] According to embodiments of this application, the types of donor ions mentioned above include at least one of Si ions, Sn ions, and Ge ions.

[0091] According to embodiments of this application, the donor ion concentrations of the first heavily doped region 30 and the second heavily doped region 40 are each independently 1×10⁻⁶. 19 cm -3 -5×10 19 cm -3 For example, 1×10 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 or a range between either or both. Thus, within the aforementioned range, the carrier concentration in the heavily doped region can be guaranteed, ensuring that the metal-semiconductor contact is an ohmic contact, while also possessing a low specific contact resistance.

[0092] In this paper, specific contact resistance describes the contact resistance per unit area under zero bias. It can be obtained through transmission line model (TLM) testing.

[0093] As a specific example, a second photoresist 13 is coated on the surfaces of the first region 91, the second region 92, and the third region 93 of the second intermediate device. The device is then placed in an ion implantation chamber, and the implantation parameters are adjusted. Initially, an implantation dose of 6.9 × 10⁻⁶ keV is implanted. 13 ions / cm 2 Donor ions were then injected with an energy of 60 keV at a dose of 1 × 10⁻⁶. 14 ions / cm 2 The donor ions were finally injected with an energy of 115 keV at a dose of 4.2 × 10⁻⁶. 14 ions / cm 2 Donor ions were used to implant second multi-energy donor ions into regions 94 and 95. After the implantation step was completed, a third annealing treatment was performed at 1000℃-1100℃ for 110s-130s to form the first heavily doped region 30 and the second heavily doped region 40.

[0094] S50: A first metal layer 50 and a second metal layer 60 are formed on the upper surfaces of the first heavily doped region 30 and the second heavily doped region 40, respectively. See the schematic diagram below. Figure 2 (f) In the middle; remove the second photoresist 13 to obtain the third intermediate device, the structural schematic diagram is shown in the figure. Figure 2 (g) In this way, the first metal layer 50 and the second metal layer 60 form ohmic contacts with the first heavily doped region 30 and the second heavily doped region 40, respectively, thereby reducing the contact resistance and reducing energy loss.

[0095] According to embodiments of this application, the first metal layer 50 and the second metal layer 60 are formed by methods including, but not limited to, magnetron sputtering. This facilitates uniform deposition of the metal layers and allows for precise control of the metal layer thickness.

[0096] According to an embodiment of this application, the magnetron sputtering pressure is 2 × 10⁻⁶. -4 Pa-5×10 -4 Pa, specifically 2 × 10 -4 Pa, 3×10 -4 Pa, 4×10 -4 Pa, 5×10 -4 Pa or any two of the above ranges. Therefore, within the above range, it is beneficial to generate more metal atoms for deposition, while ensuring good density of the deposited metal layer.

[0097] According to embodiments of this application, the sputtering time of magnetron sputtering is 200s-400s, specifically 200s, 250s, 300s, 350s, 400s, or any range between two of these. Therefore, within this time range, it is beneficial to form a continuous, uniform, and appropriately thick metal layer. If the sputtering time is too long, the metal layer will be too thick, potentially leading to material waste and increased processing costs; if the sputtering time is too short, the metal layer may be too thin, making the metal electrodes prone to damage.

[0098] According to embodiments of this application, the deposition thickness of the first metal layer 50 and the second metal layer 60 are each independently 150nm-300nm, specifically within the range of 150nm, 200nm, 250nm, 300nm, or any two thereof. Thus, within the aforementioned thickness range, it is possible to avoid increasing the resistance due to excessively thick electrodes while also preventing damage to the metal electrodes due to excessively thin film thickness.

[0099] As a specific example, the third intermediate device is placed in the magnetron sputtering reaction chamber, and the pressure is reduced to 2 × 10⁻⁶. -4 Pa-5×10 -4 Pa is introduced, a certain flux of Ar is introduced, and DC power is turned on for sputtering. The sputtering time of metal atoms is 200s-400s to form the first metal layer 50 and the second metal layer 60. Then the second photoresist 13 is removed to obtain the third intermediate device.

[0100] S60: A third photoresist 14 is coated on the upper surfaces of the first metal layer 50 and the second metal layer 60, and a gate dielectric layer 70 is formed on the upper surface of the lightly doped region 20. (See schematic diagram below.) Figure 2 In step (h), the third photoresist 14 is removed to obtain the fourth intermediate device. See the schematic diagram below. Figure 2 In (i), the gate dielectric layer 70 can physically isolate the gate and the channel, preventing them from conducting electricity directly, while controlling the switching of the device by regulating the depletion layer width of the channel through the electric field formed by the gate.

[0101] According to embodiments of this application, the gate dielectric layer 70 can be formed by methods including, but not limited to, atomic layer deposition. This allows for the layer-by-layer growth of single atomic layers, resulting in a uniform gate dielectric layer with precise thickness.

[0102] As a specific example, a third photoresist 14 is first coated on the upper surfaces of the first metal layer 50 and the second metal layer 60, exposing the upper surface of the lightly doped region 20. Then, an atomic layer deposition method is used to form a gate dielectric layer 70 on the upper surface of the lightly doped region 20, and then the third photoresist 14 is removed to obtain the fourth intermediate device.

[0103] S70: A fourth photoresist 15 is coated on the upper surfaces of the second region 92 and the third region 93, respectively; a fifth photoresist 16 is coated on the upper surfaces of the fourth region 94 and the fifth region 95, respectively. See the structural schematic diagram. Figure 2 (j) ; A gate metal layer 80 is formed on the upper surface of the gate dielectric layer 70, as shown in the schematic diagram. Figure 2 (k) In the middle; remove the fourth photoresist 15 and the fifth photoresist 16 to obtain the lateral MOSFET device. See the schematic diagram below. Figure 2 (l) In this way, the gate metal layer can control the carrier concentration in the channel through a vertical electric field, thereby realizing the switching function of the lateral MOSFET device.

[0104] According to embodiments of this application, the deposition of the gate metal layer 80 includes, but is not limited to, thermal evaporation deposition. Therefore, this method is simple and low-cost.

[0105] According to embodiments of this application, the current for the thermal evaporation deposition method is 130A-150A, specifically 130A, 135A, 140A, 145A, 150A, or any two of these ranges. Therefore, within this current range, it is helpful to precisely control the thermal evaporation temperature, ensure a uniform deposition rate, and thus guarantee the compositional stability of the gate metal layer.

[0106] According to embodiments of this application, the evaporation rate is 0.15 nm / s to 0.25 nm / s, specifically within the range of 0.15 nm / s, 0.2 nm / s, 0.25 nm / s, or any two thereof. This range facilitates the formation of a gate metal layer with uniform and dense thickness.

[0107] According to embodiments of this application, the thickness of the gate metal layer is 60nm-100nm, specifically within the range of 60nm, 70nm, 80nm, 90nm, 100nm, or any two thereof. Therefore, within this range, the adhesion between the gate dielectric layer and the gate metal layer is good, the internal stress is low, and problems such as cracking and peeling are less likely to occur.

[0108] As a specific example, a fourth photoresist 15 is coated on the upper surfaces of the second region 92 and the third region 93, respectively, and a fifth photoresist 16 is coated on the upper surfaces of the fourth region 94 and the fifth region 95, respectively. A gap is left between the fourth photoresist 15 and the fifth photoresist 16, exposing a portion of the upper surface of the gate dielectric layer 70. A gate metal layer 80 is deposited on the portion of the upper surface of the gate dielectric layer 70 using a thermal evaporation deposition method. The fourth photoresist 15 and the fifth and sixth photoresists 16 are then removed, finally yielding a lateral MOSFET device.

[0109] A third aspect of this application provides a semiconductor device comprising the lateral MOSFET device based on a β-Ga2O3 substrate described above, or a lateral MOSFET device fabricated by the method described above for fabricating a lateral MOSFET device based on a β-Ga2O3 substrate. All features and parameters of this semiconductor device are identical to those of the lateral MOSFET device based on a β-Ga2O3 substrate described above, and will not be repeated here.

[0110] It is understood that there is no limitation on the type of semiconductor device; it can be any semiconductor device that requires the use of lateral MOSFET devices. Examples include, but are not limited to, digital circuits (e.g., microprocessors, microcontrollers, dynamic random access memory, static random access memory, etc.), amplifiers (e.g., operational amplifiers, audio amplifiers, etc.), optoelectronic devices, switching power supplies, and so on.

[0111] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0112] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0113] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0114] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A lateral MOSFET device based on a β-Ga2O3 substrate, characterized in that, include: A substrate having a protrusion in the middle, the substrate being made of β-Ga2O3; A lightly doped region, the lightly doped region being located on the upper surface of the substrate, and the protrusion being embedded in the lightly doped region; The first heavily doped region and the second heavily doped region are disposed on the upper surface of the substrate and are located on opposite sides of the lightly doped region; A first metal layer is disposed on the upper surface of the first heavily doped region; A second metal layer is disposed on the upper surface of the second heavily doped region; A gate dielectric layer is disposed on the upper surface of the lightly doped region and located between the first metal and the second metal; A gate metal layer is disposed on the upper surface of the gate dielectric layer and is disposed corresponding to the protrusion.

2. The lateral MOSFET device according to claim 1, characterized in that, The width of the protrusion is 0.2μm-10μm; The height of the protrusion is 100nm-200nm.

3. The lateral MOSFET device according to claim 1, characterized in that, At least one of the following conditions must be met: The composition of the first metal layer includes Ti / Au; The composition of the second metal layer includes Ti / Au.

4. The lateral MOSFET device according to claim 1, characterized in that, At least one of the following conditions must be met: The electron concentration of the lightly doped region is 3 × 10⁻⁶. 17 cm -3 -5×10 18 cm -3 ; The electron concentrations of the first heavily doped region and the second heavily doped region are each independently 1 × 10⁻⁶. 19 cm -3 -5×10 19 cm -3 .

5. The lateral MOSFET device according to claim 1, characterized in that, At least one of the following conditions must be met: The material of the gate dielectric layer includes at least one of aluminum oxide, silicon oxide, hafnium oxide, or zirconium oxide, preferably aluminum oxide; The thickness of the gate dielectric layer is 15nm-40nm; The material of the gate metal layer includes Cr / Au; The substrate is doped with at least one of Fe, Mg, and N.

6. A method for fabricating a lateral MOSFET device based on a β-Ga2O3 substrate, characterized in that, include: A β-Ga2O3 substrate is provided, and a first region, a second region, a third region, a fourth region and a fifth region are defined on the β-Ga2O3 substrate. The second region and the third region are respectively located on opposite sides of the first region. The fourth region is located on the side of the second region away from the first region. The fifth region is located on the side of the third region away from the first region. The upper surface of the β-Ga2O3 substrate is subjected to low-energy donor ion implantation and a first annealing treatment in sequence to obtain a first intermediate device; The second region, the third region, the fourth region, and the fifth region are sequentially subjected to a first multi-energy donor ion implantation and a second annealing process to form a lightly doped region, thereby obtaining a second intermediate device; The fourth region and the fifth region are subjected to a second multi-energy donor ion implantation and a third annealing process in sequence to form a first heavily doped region and a second heavily doped region; A first metal layer and a second metal layer are formed on the upper surfaces of the first heavily doped region and the second heavily doped region, respectively, to obtain a third intermediate device; A gate dielectric layer is formed on the upper surface of the lightly doped region to obtain a fourth intermediate device; A gate metal layer is formed on the upper surface of the gate dielectric layer to obtain a lateral MOSFET device based on a β-Ga2O3 substrate.

7. The method according to claim 6, characterized in that, At least one of the following conditions must be met: The donor ions include at least one of Si ions, Sn ions, and Ge ions; The donor ion concentrations in the first and second heavily doped regions are the same, both being 1 × 10⁻⁶. 19 cm -3 -5×10 19 cm -3 .

8. The method according to claim 6, characterized in that, At least one of the following conditions must be met: The energy of the implantation source for the low-energy donor ion implantation is 30keV-40keV; The dose of the implantation source for the low-energy donor ion implantation is 5 × 10⁻⁶. 13 ions / cm 2 -2×10 14 ions / cm 2 ; The energy of the implantation source for the first multi-energy donor ion implantation is 40keV-150keV; The dose of the implantation source for the first multi-energy donor ion implantation is 2 × 10⁻⁶. 12 ions / cm 2 -2×10 13 ions / cm 2 ; The energy of the implantation source for the second multi-energy donor ion implantation is 10keV-150keV; The dose of the implantation source for the second multi-energy donor ion implantation is 6 × 10⁻⁶. 13 ions / cm 2 -5×10 14 ions / cm 2 .

9. A semiconductor device, characterized in that, Includes the lateral MOSFET device based on a β-Ga2O3 substrate as described in any one of claims 1-5, or the lateral MOSFET device based on a β-Ga2O3 substrate prepared by the method of any one of claims 6-8.

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