Terminal structure of shield gate trench type MOSFET device and manufacturing method thereof

Abstract

The invention discloses a terminal structure of a shield gate trench type MOSFET device and a manufacturing method thereof, and the scheme employs a group of special peripheral trench arrays in a terminal region, and carries out the one-time P-type ion implantation at the bottom of the special peripheral trench arrays. The P-type injected ions are driven under the condition of a subsequent device manufacturing thermal process, so that the expected uniform junction depth is achieved, the transverse electric field of a device terminal area is relieved, and the expected breakdown voltage is obtained; moreover, the distance between the grooves of the peripheral groove array is not greater than 3.1 [mu] m, so that the finally obtained target terminal structure has a smaller terminal size, and the chip area is saved. In addition, the manufacturing process is compatible with the process of the existing shield gate trench type MOSFET device, the process is simple, and the manufacturing cost is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a terminal structure of a shield gate trench MOSFET device and a manufacturing method thereof. BACKGROUND

[0002] The shield gate trench MOSFET device is composed of a cell region and a terminal region, the design of the cell region affects the threshold voltage, on-resistance, capacitance, breakdown voltage and other parameters of the device, and the design of the terminal region mainly affects the breakdown voltage of the device. When the voltage reaches 200V, a relatively thick epitaxial layer is needed to bear the reverse voltage, which is much thicker than the depth of the shield gate trench. At this time, the longitudinal electric field modulation effect brought by the deep trench cannot effectively modulate all the epitaxial layer regions. The epitaxial layer outside the trench has no electric field shielding effect, and the breakdown voltage in the terminal region is obviously reduced, which is much lower than the breakdown voltage in the cell region of the device, thereby reducing the overall device breakdown voltage.

[0003] Therefore, the terminal structure of the shield gate trench MOSFET device is particularly important, and an improperly designed terminal structure will result in excessively low breakdown voltage and cannot achieve the best breakdown voltage. Therefore, a voltage dividing structure needs to be designed at the edge of the device to reduce the curvature of the electric field at the edge of the cell region, i.e. the terminal region, so as to extend the depletion layer laterally and enhance the horizontal breakdown voltage.

[0004] At present, the 200V shield gate trench MOSFET uses a method of gradually reducing the depth of the breakdown voltage ring from the active region to the terminal to achieve the breakdown voltage of the terminal. This method needs to be realized by multiple masks and multiple ion implantations, which is complex and has high manufacturing cost. SUMMARY

[0005] The present application aims to at least solve the technical problems in the prior art. To this end, the present application proposes, in a first aspect, a manufacturing method of a terminal structure of a shield gate trench MOSFET device, which comprises: forming a hard polishing layer and a peripheral trench array on an epitaxial layer of a semiconductor substrate; wherein the peripheral trench array comprises one active region trench and seven breakdown voltage rings, the interval between each trench of the peripheral trench array is not greater than 3.1um, and the value of the interval between the first four trenches is less than the value of the interval between the last three trenches; after P-type ion implantation is performed on the bottom of the peripheral trench array by using one mask, the hard polishing layer is removed; forming an inner pad oxide layer on the sidewall of the active region trench and the breakdown voltage ring, and forming a shield polysilicon inside, and etching the shield polysilicon and the inner pad oxide layer; forming a gate oxide layer on the sidewall of the active region trench, and processing a gate polysilicon; After the channel ion implantation and the source ion implantation are sequentially performed using the photo mask, a target terminal structure of the shield gate trench MOSFET device is obtained.

[0006] In a possible implementation, the implantation dose and the implantation energy of the P-type ion implantation are determined by the doping concentration of the epitaxial layer, the thickness of the epitaxial layer, and the current process thermal process condition of the shield gate trench MOSFET device.

[0007] In a possible implementation, the implantation dose of the P-type ion implantation is 1e12 cm -2 ~1e13 cm -2 , and the implantation energy is 100 kev ~ 500 kev.

[0008] In a possible implementation, the trench spacing of the peripheral trench array is 2.5 um, 2.3 um, 2.5 um, 2.9 um, 3.1 um, 3.1 um, and 3.1 um, respectively.

[0009] In a possible implementation, the trench bottoms of the active region trench and the first three adjacent trench voltage rings are connected together after the P-type ion implantation, and the trench bottoms of the last four trench voltage rings are separated after the P-type ion implantation.

[0010] In a possible implementation, the silicon mesa of the terminal region of the shield gate trench MOSFET device is connected to the doped polysilicon in the adjacent trench through the metal layer, so that the silicon mesa region has the same potential as the doped polysilicon in the trench.

[0011] In a possible implementation, the method further includes: The low-temperature oxide layer and the boron phosphorus silicon glass layer are sequentially deposited on the surface of the epitaxial layer, and a contact hole is formed by etching using a contact hole photo mask.

[0012] In a possible implementation, the method further includes: The metal layer is deposited on the entire device surface, and a metal layer structure is formed by metal layer photolithography.

[0013] In a possible implementation, the method further includes: The metal layer is formed into different regions by photolithography, including a plurality of floating electrodes formed by a source metal and a floating metal; and each floating electrode is used to make the potential of each trench independent of each other.

[0014] The second aspect of the present application provides a terminal structure of a shield gate trench MOSFET device, which is prepared according to the manufacturing method of the terminal structure of the shield gate trench MOSFET device described in the first aspect.

[0015] The embodiments of this application have the following beneficial effects: This application provides a terminal structure and manufacturing method for a shielded gate trench MOSFET device. The method includes: forming a hard polished layer and a peripheral trench array on an epitaxial layer located on a semiconductor substrate, wherein the peripheral trench array includes an active region trench and seven trench withstand rings, the spacing between each trench in the peripheral trench array is not greater than 3.1 μm, and the spacing between the first four trenches is less than the spacing between the last three trenches; performing P-type ion implantation at the bottom of the peripheral trench array using a photomask, removing the hard polished layer, forming an inner pad oxide layer on the sidewalls of the active region trench and the trench withstand rings, forming a shielded polysilicon layer inside, etching the shielded polysilicon layer and the inner pad oxide layer, forming a gate oxide layer on the sidewalls of the active region trench, and processing to form a gate polysilicon layer; finally, performing channel ion implantation and source ion implantation sequentially using a photomask to obtain the target terminal structure of the shielded gate trench MOSFET device. This solution employs a special peripheral trench array in the termination region. A single P-type ion implantation is performed at the bottom of this array, and the implanted ions are driven under the conditions of subsequent device fabrication thermal processes to achieve the desired uniform junction depth. This alleviates the lateral electric field in the device termination region and achieves the expected breakdown voltage. Furthermore, by ensuring that the spacing between the trenches in the peripheral trench array is no greater than 3.1µm, the final target termination structure has a smaller termination size, saving chip area. In addition, this manufacturing process is compatible with existing shielded gate trench MOSFET devices and is simple and cost-effective. Attached Figure Description

[0016] Figure 1 A flowchart illustrating the steps of a method for manufacturing a termination structure of a shielded gate trench MOSFET device according to an embodiment of this application; Figure 2 A schematic diagram of a substrate and an epitaxial layer provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the formation of a hard polished layer and a peripheral trench array, provided for an embodiment of this application; Figure 4 This is a schematic diagram of a P-type ion implantation procedure provided in an embodiment of this application; Figure 5 This is a schematic diagram of removing a hard abrasive layer provided in an embodiment of this application; Figure 6 This is a schematic diagram of the formation of an inner liner oxide layer provided in an embodiment of this application; Figure 7 This is a schematic diagram of a shielded polysilicon after being formed and polished, as provided in an embodiment of this application. Figure 8A schematic diagram of an etched shielding polysilicon and an inner oxide layer provided in an embodiment of this application. Figure 9 A schematic diagram illustrating the formation of a gate oxide layer and gate polysilicon, provided for an embodiment of this application; Figure 10 A schematic diagram of channel ion implantation provided for an embodiment of this application; Figure 11 A schematic diagram of a low-temperature oxide layer and a borosilicate glass layer provided in an embodiment of this application; Figure 12 This is a schematic diagram of forming a contact hole according to an embodiment of the present application; Figure 13 This is a schematic diagram of a metal layer structure provided in an embodiment of this application; Figure 14 A schematic diagram of the target termination structure of a shielded gate trench MOSFET device provided in an embodiment of this application; Figure 15 A schematic diagram of device simulation results provided in an embodiment of this application; Figure 16 A schematic diagram of the potential distribution on a terminal silicon surface provided in an embodiment of this application; Figure 17 This is a schematic diagram of the current distribution when a device breakdown occurs, provided as an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0019] like Figure 1 As shown, Figure 1A flowchart illustrating the steps of a method for manufacturing a termination structure for a shielded gate trench MOSFET device according to an embodiment of this application includes: Step 102: A hard polishing layer and a peripheral trench array are formed on the epitaxial layer located on the semiconductor substrate.

[0020] The shielded gate trench MOSFET device described in this application includes N-type MOSFETs and P-type MOSFETs. If it is an N-type MOSFET, its substrate and epitaxial layer are both N-type doped, for example, doped with arsenic or phosphorus. The source region is heavily N-type doped, and the body region is P-type doped. Furthermore, the gate polysilicon is heavily N-type doped polysilicon. Interchanging these doping types—that is, converting N-type to P-type and vice versa—results in a P-type MOSFET.

[0021] This application uses an N-type MOSFET as an example for illustration. Figure 2 As shown, Figure 2 This is a schematic diagram of a substrate and an epitaxial layer provided in an embodiment of this application, wherein, Figure 2 In the middle, an N-type lightly doped epitaxial layer 2 is grown on an N-type heavily doped semiconductor substrate 1.

[0022] Next, a hard polished layer 3 and a peripheral trench array 4 can be formed in the N-type lightly doped epitaxial layer 2 through photolithography and etching processes. The peripheral trench array 4 includes one active region trench and seven trench withstand rings. The spacing between each trench in the peripheral trench array is no greater than 3.1 μm, and the spacing values ​​of the first four trenches are smaller than the spacing values ​​of the last three trenches. Figure 3 As shown, Figure 3 This is a schematic diagram of forming a hard polished layer and an outer trench array provided in an embodiment of this application. One of the active area trenches is the leftmost half-U-shaped structure, and the seven trench pressure-resistant rings are the seven U-shaped structures.

[0023] In some alternative embodiments, the trench spacing of the peripheral trench array is 2.5um, 2.3um, 2.5um, 2.9um, 3.1um, 3.1um, and 3.1um, respectively.

[0024] Step 104: After performing P-type ion implantation at the bottom of the peripheral trench array using a photomask, remove the hard abrasive layer.

[0025] Among them, such as Figure 4 As shown, Figure 4 This is a schematic diagram of a P-type ion implantation process provided in an embodiment of this application. Optionally, the active region trench and the adjacent first three trench pressure rings are connected together at the bottom of the trench after P-type ion implantation, and the latter four trench pressure rings are separated at the bottom of the trench after P-type ion implantation.

[0026] Next, after performing P-type ion implantation 5 at the bottom of the peripheral trench array using a photomask, the hard abrasive layer 3 can be removed, such as... Figure 5 As shown, Figure 5 This is a schematic diagram of removing a hard abrasive layer, provided as an embodiment of this application.

[0027] In some alternative embodiments, the implantation dose and implantation energy of P-type ion implantation are determined by the doping concentration of the epitaxial layer, the thickness of the epitaxial layer, and the current process thermal conditions of the shielded gate trench MOSFET device.

[0028] In some alternative embodiments, the implantation dose of P-type ion implantation is 1e12cm. -2 ~1e13cm -2 The implantation energy is 100keV~500keV, thereby driving the P-type implanted ions under the conditions of the subsequent device fabrication thermal process to achieve the desired uniform junction depth.

[0029] Step 106: After forming an inner oxide layer on the sidewall of the active region trench and the trench withstand ring, and forming a shielding polysilicon inside, the shielding polysilicon and the inner oxide layer are etched.

[0030] Among them, such as Figure 6 As shown, Figure 6 This is a schematic diagram of forming an inner oxide layer according to an embodiment of the present application. An inner oxide layer 6 can be grown on the sidewall of the active region trench and the trench withstand ring by thermal oxidation process or a combination of thermal oxidation and chemical vapor deposition. The thickness of the inner oxide layer 6 can be set to different thickness values ​​according to different device withstand voltages.

[0031] Next, a shielding polysilicon 7 can be formed inside the active region trench and the trench withstand ring by polysilicon deposition, and then the shielding polysilicon 7 can be ground down to the surface of the inner pad oxide layer 6 using chemical mechanical polishing. Figure 7 As shown, Figure 7 This is a schematic diagram of a shielded polysilicon after being formed and polished, as provided in an embodiment of this application.

[0032] Therefore, a shielded polysilicon photomask can be used to etch the shielded polysilicon 7 within the active region trench to a certain depth, remove the photoresist, and then etch the inner oxide layer 6, making its surface lower than the surface of the shielded polysilicon 7. For example... Figure 8 As shown, Figure 8 This is a schematic diagram of an etched shielding polysilicon and an inner oxide layer provided in an embodiment of this application.

[0033] Step 108: Form a gate oxide layer on the sidewall of the active region trench and process it to form gate polysilicon.

[0034] In this process, a gate oxide layer 8 is formed on the sidewall of the active region trench through thermal oxidation. Subsequently, gate polysilicon is deposited, and then chemical mechanical polishing and etching are used to etch the gate polysilicon below the surface of the silicon epitaxial layer, typically to 0.1 micrometers below the silicon surface, ultimately forming the gate polysilicon 9. Figure 9 As shown, Figure 9 This is a schematic diagram illustrating the formation of a gate oxide layer and a gate polysilicon according to an embodiment of this application.

[0035] Step 110: After performing channel ion implantation and source ion implantation sequentially using a photomask, the target termination structure of the shielded gate trench MOSFET device is obtained.

[0036] Among them, such as Figure 10 As shown, Figure 10 This is a schematic diagram of a channel ion implantation process provided in an embodiment of this application. Specifically, a channel ion implantation mask 10 can be used to perform channel ion implantation 11. Then, a source ion implantation mask is used to perform source ion implantation. Since source ion implantation is not performed in the terminal region, this process is not shown in the figure.

[0037] Next, a low-temperature oxide layer 11 and a borosilicate glass layer 12 can be sequentially deposited on the surface of the epitaxial layer, and a contact hole 13 can be formed by etching using a contact hole photomask. For example... Figure 11 and Figure 12 As shown, Figure 11 This is a schematic diagram of a low-temperature oxide layer and a borosilicate glass layer deposited according to an embodiment of this application. Figure 12 This is a schematic diagram of forming a contact hole according to an embodiment of this application.

[0038] Finally, a metal layer can be deposited on the entire surface of the device, and a metal layer structure 14 can be formed by metal layer photolithography, such as... Figure 13 As shown, Figure 13 This is a schematic diagram of a metal layer structure provided in an embodiment of this application.

[0039] In some alternative embodiments, the metal layer can be formed into different regions by photolithography, including multiple floating electrodes formed by source metal and floating metal, wherein each floating electrode is used to make the potential of each trench independent of each other.

[0040] Specifically, the metal layer structure is formed into different regions through photolithography, including source metal (SM) and floating electrodes FM1-FM5 formed by floating metal. The floating electrodes make the subsequent trench potentials independent of each other. For example... Figure 14 As shown, Figure 14This is a schematic diagram of the target terminal structure of a shielded gate trench MOSFET device provided in an embodiment of this application. The trench spacing of the peripheral trench array is represented by L1-L7. Optionally, L1=2.5um, L2=2.3um, L3=2.5um, L4=2.9um, L5=3.1um, L6=3.1um, and L7=3.1um.

[0041] In this design, the first four trenches are spaced very close together, close enough that the ions implanted at the bottom of the trenches can diffuse and connect together, but not so close as to ensure a smooth potential distribution near the active region. The latter four trenches are spaced further apart, separating the ion-implanted regions at the bottom of the trenches. Under the combined action of the source metal and the floating electrode, the potential at the device termination gradually increases horizontally, thereby mitigating the lateral electric field in the termination region and achieving the desired breakdown voltage. Furthermore, in the shielded gate trench MOSFET device, the silicon mesa in the termination region is connected to the doped polysilicon in the adjacent trenches via a metal layer, ensuring that the potential of the silicon mesa region is the same as that of the doped polysilicon in the trenches.

[0042] like Figures 15-17 As shown, Figure 15 This is a schematic diagram of device simulation results provided in an embodiment of this application. For a 200V shielded gate trench MOSFET device, the schematic diagram shows the deep well injection and potential distribution results at the bottom of the trench array in the peripheral withstand voltage region. The simulated terminal withstand voltage reaches 223.5V. Figure 16 This is a schematic diagram of the potential distribution on a terminal silicon surface provided in an embodiment of this application. Figure 17 This is a schematic diagram of the current distribution when a device breakdown occurs, provided in an embodiment of this application. It shows that the breakdown occurs in the active region, indicating that the breakdown voltage of the deep well terminal region is higher than the breakdown voltage of the active region.

[0043] This application provides a termination structure and manufacturing method for a shielded gate trench MOSFET device. The method includes: forming a hard polished layer and a peripheral trench array on an epitaxial layer located on a semiconductor substrate, wherein the peripheral trench array includes an active region trench and seven trench withstand rings, the spacing between each trench in the peripheral trench array is not greater than 3.1 μm, and the spacing of the first four trenches is less than the spacing of the last three trenches; performing P-type ion implantation at the bottom of the peripheral trench array using a photomask, removing the hard polished layer, forming an inner pad oxide layer on the sidewalls of the active region trench and the trench withstand rings, forming a shielded polysilicon layer inside, etching the shielded polysilicon layer and the inner pad oxide layer, forming a gate oxide layer on the sidewalls of the active region trench, and forming a gate polysilicon layer; finally, performing channel ion implantation and source ion implantation sequentially using a photomask to obtain the target termination structure of the shielded gate trench MOSFET device. This solution employs a special peripheral trench array in the termination region. A single P-type ion implantation is performed at the bottom of this array, and the implanted ions are driven under the conditions of subsequent device fabrication thermal processes to achieve the desired uniform junction depth. This alleviates the lateral electric field in the device termination region and achieves the expected breakdown voltage. Furthermore, by ensuring that the spacing between the trenches in the peripheral trench array is no greater than 3.1µm, the final target termination structure has a smaller termination size, saving chip area. In addition, this manufacturing process is compatible with existing shielded gate trench MOSFET devices and is simple and cost-effective.

[0044] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0045] This application also provides a termination structure for a shielded gate trench MOSFET device, which is prepared according to the manufacturing method of the aforementioned shielded gate trench MOSFET device termination structure. Specific implementation processes and beneficial effects can be found in the above-described method embodiments, and will not be repeated here.

[0046] It is readily understood that, based on the several embodiments provided in this application, those skilled in the art can combine, split, or reorganize the embodiments of this application to obtain other embodiments, none of which exceed the protection scope of this application.

[0047] The above detailed embodiments further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a termination structure of a shielded gate trench MOSFET device, characterized in that, The method includes: A hard polished layer and a peripheral trench array are formed on an epitaxial layer located on a semiconductor substrate; wherein the peripheral trench array includes an active region trench and seven trench withstand rings, the trench spacing of each trench in the peripheral trench array is not greater than 3.1 μm, and the value of the first four trench spacings is less than the value of the last three trench spacings. After P-type ion implantation through a photomask at the bottom of the peripheral trench array, the hard abrasive layer is removed. An inner pad oxide layer is formed on the sidewall of the active region trench and the trench withstand ring, and a shielding polysilicon is formed inside, and then the shielding polysilicon and the inner pad oxide layer are etched. A gate oxide layer is formed on the sidewall of the active region trench, and gate polysilicon is formed therefrom. After performing channel ion implantation and source ion implantation sequentially using a photomask, the target termination structure of the shielded gate trench MOSFET device is obtained.

2. The method according to claim 1, characterized in that, The implantation dose and implantation energy of the P-type ion implantation are determined by the doping concentration of the epitaxial layer, the thickness of the epitaxial layer, and the current process thermal conditions of the shielded gate trench MOSFET device.

3. The method according to claim 2, characterized in that, The implantation dose of the P-type ion implantation was 1e12cm. -2 ~1e13cm -2 The injected energy is 100keV~500keV.

4. The method according to any one of claims 1-3, characterized in that, The trench spacing of the peripheral trench array is 2.5um, 2.3um, 2.5um, 2.9um, 3.1um, 3.1um, and 3.1um, respectively.

5. The method according to any one of claims 1-3, characterized in that, The active region trench and the adjacent first three trench pressure rings are connected together at the bottom of the trench after P-type ion implantation, and the last four trench pressure rings are separated at the bottom of the trench after P-type ion implantation.

6. The method according to any one of claims 1-3, characterized in that, The silicon mesa in the terminal region of the shielded gate trench MOSFET device is connected to the doped polysilicon in the adjacent trench through a metal layer, so that the potential of the silicon mesa region is the same as that of the doped polysilicon in the trench.

7. The method according to any one of claims 1-3, characterized in that, The method further includes: A low-temperature oxide layer and a borosilicate glass layer are sequentially deposited on the surface of the epitaxial layer, and contact holes are formed by etching using a contact hole photomask.

8. The method according to any one of claims 1-3, characterized in that, The method further includes: A metal layer is deposited on the entire surface of the device, and the metal layer structure is formed by metal layer photolithography.

9. The method according to claim 8, characterized in that, The method further includes: The metal layer is formed into different regions by photolithography, including multiple floating electrodes formed by source metal and floating metal; wherein each of the floating electrodes is used to make the potential of each trench independent of each other.

10. A termination structure for a shielded gate trench MOSFET device, characterized in that, The structure is prepared by the manufacturing method of the terminal structure of the shielded gate trench MOSFET device according to any one of claims 1-9.

Images