Semiconductor assembly

Abstract

The invention provides a semiconductor component which comprises a substrate, a protection structure and a conductive structure. The substrate includes an active region having an edge. The active region includes a control circuit. The protection structure is disposed on the substrate and surrounds at least a portion of the active region. The conductive structure is disposed on the substrate and at least partially between an edge of the active region and the protection structure. The first end and the second end of the conductive structure are electrically connected to the control circuit. The control circuit is configured to transmit a detection signal to a first end of the conductive structure and receive a return signal from a second end of the conductive structure, where the control circuit does not actively transmit the signal to the protection structure. Therefore, whether crystal grain cracks exist or not can be conveniently tested.

Description

Technical Field

[0001] This disclosure relates to a semiconductor component, and more particularly to a semiconductor component capable of detecting grain cracks. Background Technology

[0002] During the manufacturing and packaging of integrated circuits, the chip itself may develop die cracks due to stress, thermal effects, or process defects. Currently, there is no intuitive and non-destructive method to effectively confirm the presence of die cracks in a chip. After packaging, if die cracks occur internally, external failure analysis (FA) methods are typically required for confirmation. However, these traditional failure analysis methods are often time-consuming, labor-intensive, and costly. For example, while basic optical microscopy (OM) or X-ray inspection can be used to examine surface structures, it is difficult to detect problems if the die cracks occur in deeper layers. In such cases, further examination using an electron microscope for cross-section observation is necessary to confirm the anomaly. This method is not only destructive but also complex, requiring significant additional resources and negatively impacting actual production efficiency and yield control. Summary of the Invention

[0003] This disclosure discloses a semiconductor component comprising a substrate, a protective structure, and a first conductive structure. The substrate includes an active region having an edge. The active region includes a first control circuit. The protective structure is disposed on the substrate and surrounds at least a portion of the active region. The first conductive structure is disposed on the substrate and at least partially between the edge of the active region and the protective structure. A first end and a second end of the first conductive structure are both electrically connected to the first control circuit. The first control circuit is configured to transmit a first detection signal to the first end of the first conductive structure and receive a first feedback signal from the second end of the first conductive structure, wherein the first control circuit does not actively transmit signals to the protective structure.

[0004] In one embodiment of this disclosure, the edge of the active region is a grain edge, which is composed of multiple electronic components or multiple redundant components.

[0005] In one embodiment of this disclosure, the first control circuit is used to determine whether the first feedback signal matches the first detection signal. If the first feedback signal does not match the first detection signal, the first control circuit determines that a grain crack has occurred at the location of the first conductive structure.

[0006] In one embodiment of this disclosure, the first conductive structure described above includes an inner ring and an outer ring, the inner ring being electrically connected to the outer ring, the inner ring surrounding the active region, and the outer ring surrounding the inner ring.

[0007] In one embodiment of this disclosure, the first conductive structure described above includes at least one buffer and multiple wires. The input terminal of the buffer is electrically connected to one of the wires, and the output terminal of the buffer is electrically connected to another wire.

[0008] In one embodiment of this disclosure, the first conductive structure includes multiple wires and multiple through-holes. The multiple wires are respectively disposed in multiple layers, and each through-hole is disposed between two layers to electrically connect corresponding wires.

[0009] In one embodiment of this disclosure, the aforementioned through-hole is disposed between the first layer and the second layer, with at least one layer separating the first layer and the second layer.

[0010] In one embodiment of this disclosure, the first conductive structure described above comprises a metal, polycrystalline silicon, or a diffusion layer.

[0011] In one embodiment of this disclosure, the active region further includes a second control circuit. The semiconductor component also includes a second conductive structure, at least partially disposed between the edge of the active region and the protective structure. A first end and a second end of the second conductive structure are both electrically connected to the second control circuit. The second control circuit is used to transmit a second detection signal to the first end of the second conductive structure and receive a second feedback signal from the second end of the second conductive structure.

[0012] In one embodiment of this disclosure, the second control circuit is used to determine whether the second feedback signal matches the second detection signal. If the second feedback signal does not match the second detection signal, the second control circuit determines that a grain crack has occurred at the location of the second conductive structure.

[0013] In one embodiment of this disclosure, the first conductive structure forms an inner ring, the second conductive structure forms an outer ring, the inner ring is not electrically connected to the outer ring, the inner ring surrounds at least a portion of the active region, and the outer ring surrounds at least a portion of the inner ring.

[0014] In the aforementioned semiconductor components, the presence of grain cracks can be detected by transmitting signals.

[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0021] Figure 6 This is a top view of a semiconductor assembly according to a first embodiment;

[0022] Figure 7 It is along Figure 6 Side view of the center section AA';

[0023] Figure 8 This is a top view of a semiconductor assembly according to a second embodiment;

[0024] Figure 9 This is a top view of a semiconductor assembly according to a third embodiment;

[0025] Figure 10 This is a top view of a semiconductor assembly according to the fourth embodiment;

[0026] Figure 11 This is a top view of a semiconductor assembly according to a fifth embodiment;

[0027] Figure 12 This is a side view showing the conductive structure according to the sixth embodiment;

[0028] Figure 13 This is a side view showing the conductive structure according to the seventh embodiment;

[0029] Figure 14 This is a side view of the conductive structure according to the eighth embodiment. Detailed Implementation

[0030] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples of the systems and methods described in the claims of the present invention.

[0031] The terms "first," "second," etc., used in this article do not specifically refer to order or sequence; they are merely used to distinguish elements or operations described using the same technical terms.

[0032] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as control circuitry). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0033] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0034] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be coupled to a system bus 110.

[0035] In one exemplary embodiment, the host system 11 can be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 can be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0036] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0037] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0038] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0039] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 3 The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0040] Figure 4This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0041] The interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the interface unit 41. In one exemplary embodiment, the interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0042] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0043] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one cell), other flash memory modules, or other memory modules with the same characteristics.

[0044] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, and thus the one or more bits stored in that memory cell can be retrieved.

[0045] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0046] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of storage units that are erased. For example, a physical erase unit is a physical block.

[0047] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0048] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to describing the operation of the memory control circuit unit 42 and the memory storage device 10.

[0049] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0050] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0051] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuitry is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuitry 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0052] The host interface 52 is coupled to the memory management circuitry 51. The memory management circuitry 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuitry 51 through the host interface 52. Furthermore, the memory management circuitry 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the invention is not limited thereto, and the host interface 52 can also be compatible with SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0053] Memory interface 53 is coupled to memory management circuitry 51 and used to access rewritable non-volatile memory module 43. For example, memory management circuitry 51 can access rewritable non-volatile memory module 43 through memory interface 53. That is, data to be written to rewritable non-volatile memory module 43 is converted by memory interface 53 into a format acceptable to rewritable non-volatile memory module 43. Specifically, if memory management circuitry 51 needs to access rewritable non-volatile memory module 43, memory interface 53 transmits a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated by memory management circuitry 51 and transmitted to rewritable non-volatile memory module 43 through memory interface 53. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0054] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0055] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 obtains a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the error correcting code and / or error detecting code corresponding to the data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code. For example, the error checking and correction circuit 54 can use various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code to encode and decode data.

[0056] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0057] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0058] This embodiment presents a semiconductor component capable of detecting grain cracks. Figure 6 This is a top view of a semiconductor component according to a first embodiment. Figure 7 It is along Figure 6Side view with section line AA'. The semiconductor assembly 600 includes a substrate 610, which contains an active region 620. A component layer 660, containing control circuitry 640, is disposed on the substrate 610 and within the active region 620. From one perspective, the components performing functions in the semiconductor assembly 600 are all located within the active region 620. From another perspective, the active region 620 is the energy-consuming area in the semiconductor assembly 600. The active region 620 has an edge 620a, also called a die edge, which is composed of multiple electronic components or multiple dummy components. In other words, edge 620a refers to the boundary formed by the outermost electronic components or dummy components in the active region 620.

[0059] In addition, the semiconductor component 600 also includes a protective structure 630 and a conductive structure 650. The protective structure 630 is disposed on the substrate 610 and surrounds at least a portion of the active region 620. In this embodiment, the protective structure 630 completely surrounds the active region 620, but in other embodiments, the protective structure 630 may also have a notch, thus surrounding a portion of the active region 620. The conductive structure 650 is disposed on the substrate 610 and at least partially between the edge 620a of the active region 620 and the protective structure 630. The conductive structure 650 has a first end 650a and a second end 650b, both of which are electrically connected to the control circuit 640. The conductive structure 650 extends outside the active region 620 to surround the active region 620 and then extends into the active region 620 to be electrically connected to the control circuit 640. In some embodiments, the conductive structure 650 includes a metal, polysilicon, a diffusion layer, other conductive materials, or a combination thereof. In some embodiments, the conductive structure 650 may also be disposed outside the edge 620a of the active region 620. Figure 7 In one embodiment, the conductive structure 650 is disposed on and in direct contact with the substrate 610. However, in other embodiments, the conductive structure 650 may be disposed on other layers without directly contacting the substrate 610. For example, one or more insulating layers may be disposed between the conductive structure 650 and the substrate 610. In some embodiments, only the first end 650a and the second end 650b of the conductive structure 650 extend into the active region 620 and are electrically connected to the control circuit 640, while the rest is located outside the active region 620.

[0060] Control circuit 640 transmits a detection signal to a first terminal 650a of conductive structure 650 and receives a feedback signal from a second terminal 650b of conductive structure 650. When a grain crack occurs, it may cause an open circuit in conductive structure 650, in which case the feedback signal will not match the detection signal. Based on this detection signal and the feedback signal, control circuit 640 can determine whether a grain crack has occurred at the location of conductive structure 650. For example, control circuit 640 can determine whether the feedback signal matches the detection signal. When the feedback signal does not match the detection signal, control circuit 640 determines that a grain crack has occurred at the location of conductive structure 650. The detection signal can be a fixed voltage, a triangular signal, a sine wave, etc., and this invention is not limited thereto. In some embodiments, control circuit 640 may include a comparator to determine whether the feedback signal matches the detection signal.

[0061] The protective structure 630 is also called a seal ring. The protective structure 630 does not overlap with the active region 620, and the control circuit 640 does not actively transmit signals to the protective structure 630. This approach does not increase the area of ​​the active region 620, and eliminates the need for invasive inspection to determine if grain cracks have occurred. In some embodiments, the control circuit 640 has a pin (not shown) to which a tester can transmit a signal, thus triggering the control circuit 640 to issue a detection signal. After determining whether a grain crack has occurred, the control circuit 640 can return a signal through the same pin or another pin, allowing the tester to determine the result.

[0062] In some embodiments, semiconductor component 600 is a chip formed by dicing and packaging multiple dies. In other embodiments, semiconductor component 600 may also be an intermediate product in the chip manufacturing process. For example, in some embodiments, the protective structure 630 is also removed during die dicing, so the packaged chip contains no protective structure 630 or only a portion of the protective structure 630. However, the conductive structure 650 is not removed and is retained for detecting die cracks during testing. In some embodiments, semiconductor component 600 may be any of the aforementioned memory control circuit unit 42 or memory device 10 chips.

[0063] Figure 8 This is a top view of a semiconductor assembly according to a second embodiment. Please refer to... Figure 8 ,exist Figure 8In this embodiment, the conductive structure 650 includes multiple wires 701-704 and multiple buffers 711-713. Wire 702 is electrically connected to the control circuit 640 and the input terminal of buffer 711. Wire 703 is electrically connected to the output terminal of buffer 711 and the input terminal of buffer 712. Wire 704 is electrically connected to the output terminal of buffer 712 and the input terminal of buffer 713. Wire 701 is electrically connected to the output terminal of buffer 713 and the control circuit 640. In some embodiments, if the wires are too long, the detection signal may attenuate; therefore, one or more buffers can be provided to amplify the detection signal. Each buffer 711-713 may contain a complementary metal-oxide-semiconductor, but this invention is not limited thereto.

[0064] In the above embodiment, a control circuit and a conductive structure are provided, but in other embodiments, multiple control circuits and multiple conductive structures may be provided to detect grain cracks at different locations. Figure 9 This is a top view of a semiconductor assembly according to a third embodiment. Figure 9In this embodiment, the semiconductor component 800 includes multiple control circuits 801-804 and multiple conductive structures 811-814. Each conductive structure 811-814 surrounds a portion of the active region 620. Specifically, conductive structure 811 surrounds the upper left corner of the active region 620. A portion of conductive structure 811 lies between the edge of the protective structure 630 and the active region 620. Both ends of conductive structure 811 are electrically connected to control circuit 801. Control circuit 801 transmits a detection signal to one end of conductive structure 811 and receives a feedback signal from the other end. If the detection signal does not match the feedback signal, control circuit 801 determines that a grain crack has occurred at the location of conductive structure 811. Similarly, conductive structure 812 surrounds the upper right corner of the active region 620. A portion of conductive structure 812 lies between the edge of the protective structure 630 and the active region 620. Both ends of conductive structure 812 are electrically connected to control circuit 802. Control circuit 802 transmits a detection signal to one end of conductive structure 812 and then receives a feedback signal from the other end. If the detection signal does not match the feedback signal, control circuit 802 determines that a grain crack has occurred at the location of conductive structure 812. Conductive structure 813 surrounds the lower left corner of active region 620. A portion of conductive structure 813 lies between the edge of protective structure 630 and active region 620. Both ends of conductive structure 813 are electrically connected to control circuit 803. Control circuit 803 transmits a detection signal to one end of conductive structure 813 and then receives a feedback signal from the other end. If the detection signal does not match the feedback signal, control circuit 803 determines that a grain crack has occurred at the location of conductive structure 813. Conductive structure 814 surrounds the lower right corner of active region 620. A portion of conductive structure 814 lies between the edge of protective structure 630 and active region 620. Both ends of conductive structure 814 are electrically connected to control circuit 804. The control circuit 804 transmits a detection signal to one end of the conductive structure 814 and then receives a feedback signal from the other end. If the detection signal does not match the feedback signal, the control circuit 804 determines that a grain crack has occurred at the location of the conductive structure 814.

[0065] exist Figure 9 In one embodiment, there are gaps between these conductive structures 811-814, so that if grain cracks occur in these gaps, they will not be detected. Alternatively, in... Figure 8 In the embodiments described, grain cracks near buffers 711-713 could not be detected either. Figure 7 In some embodiments, grain cracks occurring between the first end 650a and the second end 650b are not easily detected. Therefore, in some embodiments, the conductive structure can be arranged to wrap around the active region twice. Figure 10 This is a top view of a semiconductor assembly according to a fourth embodiment. Figure 10In this embodiment, the conductive structure 900 includes an inner ring 901 and an outer ring 902. The inner ring 901 is electrically connected to the outer ring 902. The inner ring 901 surrounds the active region 620, while the outer ring 902 surrounds the inner ring 901. In this way, regardless of where the grain crack occurs, it will cause an open circuit in the conductive structure 900, and the control circuit 640 can detect the grain crack.

[0066] Figure 11 This is a top view of a semiconductor assembly according to the fifth embodiment. Please refer to... Figure 11 The two ends of conductive structure 1021 are electrically connected to control circuit 1011, and the two ends of conductive structure 1022 are also electrically connected to control circuit 1012. Both conductive structures 1021 and 1022 are at least partially located between active region 620 and protective structure 630. However, conductive structure 1021 forms an inner ring, while conductive structure 1022 forms an outer ring, and the inner ring is not electrically connected to the outer ring. The inner ring surrounds at least a portion of active region 620, and the outer ring surrounds at least a portion of the inner ring. In this way, regardless of the location of the grain crack, one or both of control circuits 1011 and 1012 will detect the grain crack.

[0067] Grain cracks can also occur between two semiconductor layers, meaning that the grain crack appears horizontal when viewed from the side. To detect such grain cracks, the conductive structure can be allowed to extend between multiple layers. Figure 12 This is a side view showing the conductive structure according to the sixth embodiment. Please refer to... Figure 12 The conductive structure comprises multiple conductors and multiple vias (VIAs), with each conductor positioned within one layer. For example, in... Figure 12 In this embodiment, there are seven layers L1 to L7, with wire 1110 located in the sixth layer L6 and wire 1120 located in the fifth layer L5. Furthermore, each via is positioned between two layers to electrically connect the corresponding two wires. For example, via 1130 is located between the sixth layer L5 and the fifth layer L5 to electrically connect wires 1110 and 1120. When a grain crack occurs between the sixth layer L5 and the fifth layer L5, causing via 1130 to become an open circuit, the detection signal will not match the returned signal, thus allowing the control circuit to detect such a grain crack.

[0068] Since vias typically have high resistance, in some embodiments the wires can be extended a longer distance before connecting to the via, thus reducing the number of vias. Figure 13 This is a side view illustrating the conductive structure according to the seventh embodiment. Figure 13 In one embodiment, wires 1210 and 1220 are located on different layers, and through-hole 1230 is used to electrically connect wires 1210 and 1220.

[0069] Figure 14 This is a side view of the conductive structure according to the eighth embodiment. Figure 14 In some embodiments, the via spans two or more layers, such that two connected wires are separated by at least one layer. For example, wire 1310 is located in the sixth layer L6, wire 1320 is located in the fourth layer L4, and via 1330 is disposed between the fourth layer L4 and the sixth layer L6 to electrically connect wires 1310 and 1320, wherein there is a layer between the fourth layer L4 and the sixth layer L6.

[0070] In some embodiments, there may be multiple conductive structures such as […]. Figure 12 , Figure 13 Or Figure 14 The structure allows for the detection of grain cracks occurring in the horizontal direction at different locations.

[0071] In the aforementioned semiconductor components, it is possible to detect whether grain cracks have occurred, or to detect the location of any grain cracks. This approach eliminates the need for optical inspection and chip slicing. Since the conductive structures are primarily located outside the active region, the area of ​​the active region is not increased.

[0072] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Include: A substrate comprising an active region having an edge, wherein the active region includes a first control circuit; A protective structure is disposed on the substrate and surrounds at least a portion of the active region; as well as A first conductive structure is disposed on the substrate and at least partially between the edge of the active region and the protective structure, wherein both a first end and a second end of the first conductive structure are electrically connected to the first control circuit. The first control circuit is used to transmit a first detection signal to the first end of the first conductive structure and receive a first feedback signal from the second end of the first conductive structure. The first control circuit will not actively transmit signals to the protection structure.

2. The semiconductor device according to claim 1, characterized in that, The edge of the active region is a grain edge, which is composed of multiple electronic components or multiple redundant components.

3. The semiconductor device according to claim 1, characterized in that, The first control circuit is used to determine whether the first feedback signal matches the first detection signal. If the first feedback signal does not match the first detection signal, the first control circuit determines that a grain crack has occurred at the location of the first conductive structure.

4. The semiconductor device according to claim 1, characterized in that, The first conductive structure includes an inner ring and an outer ring, the inner ring being electrically connected to the outer ring, the inner ring surrounding the active region, and the outer ring surrounding the inner ring.

5. The semiconductor device according to claim 1, characterized in that, The first conductive structure includes at least a buffer and a plurality of wires, wherein the input terminal of the buffer is electrically connected to one of the plurality of wires, and the output terminal of the buffer is electrically connected to another of the plurality of wires.

6. The semiconductor device according to claim 1, characterized in that, The first conductive structure includes multiple wires and multiple through holes, wherein the multiple wires are respectively disposed in multiple layers, and each of the multiple through holes is disposed between two of the multiple layers to electrically connect corresponding two of the multiple wires.

7. The semiconductor device according to claim 6, characterized in that, One of the plurality of through holes is disposed between the first layer and the second layer of the plurality of layers, wherein the first layer and the second layer are separated by at least one layer.

8. The semiconductor device according to claim 1, characterized in that, The first conductive structure comprises a metal, polycrystalline silicon, or a diffusion layer.

9. The semiconductor device according to claim 1, characterized in that, The active region further includes a second control circuit, and the semiconductor device further includes: A second conductive structure is at least partially disposed between the edge of the active region and the protective structure, wherein both the first and second ends of the second conductive structure are electrically connected to the second control circuit. The second control circuit is used to transmit a second detection signal to the first end of the second conductive structure and to receive a second feedback signal from the second end of the second conductive structure.

10. The semiconductor device according to claim 9, characterized in that, The second control circuit is used to determine whether the second feedback signal matches the second detection signal. If the second feedback signal does not match the second detection signal, the second control circuit determines that a grain crack has occurred at the location of the second conductive structure.

11. The semiconductor device according to claim 10, characterized in that, The first conductive structure forms an inner ring, and the second conductive structure forms an outer ring. The inner ring is not electrically connected to the outer ring. The inner ring surrounds at least a portion of the active region, and the outer ring surrounds at least a portion of the inner ring.

Images