Straight-through power delivery for top logic semiconductor systems

Abstract

The invention relates to pass-through power delivery for top logic semiconductor systems. A semiconductor system may be configured with a two-dimensional pattern of power transfer conductors through stacked semiconductor components (e.g., through one or more memory stacks) to provide more distributed power transfer to logic components bonded to the stacks. The power delivery conductor may include a through-substrate via that bypasses the stacked circuitry, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposed to the logic component in a heterogeneous stack), which may include a semiconductor device from relatively fewer interconnects at a surface of the semiconductor system (e.g., a semiconductor device). Redistributed conductors (e.g., for solder interconnects) converted to relatively more interconnects (e.g., for hybrid bond interconnects) at a surface bonded with the stack.

Description

[0001] Cross reference

[0002] This patent application claims priority to U.S. Patent Application No. 19 / 248,133, filed June 24, 2025, titled “PASS-THROUGH POWER DELIVERY FOR LOGIC-ON-TOP SEMICONDUCTOR SYSTEMS” by Johnson et al., and claims priority to U.S. Provisional Patent Application No. 63 / 668,679, filed July 8, 2024, titled “PASS-THROUGH POWER DELIVERY FOR LOGIC-ON-TOP SEMICONDUCTOR SYSTEMS” by Johnson et al., each of which is assigned to the assignee hereof and is expressly incorporated herein in its entirety by this reference. TECHNICAL FIELD

[0003] The following relates to one or more semiconductor systems, including pass-through power delivery for logic-on-top semiconductor systems. BACKGROUND

[0004] Memory devices are used in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like to store information. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, an individual memory cell can support more than two states, any of which can be stored by the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. SUMMARY

[0005] A semiconductor system is described. The semiconductor system can include a first semiconductor component comprising one or more processors of a processing system, and one or more second semiconductor components engaged with the first semiconductor component along a first side of the one or more second semiconductor components, the one or more second semiconductor components comprising: one or more memory arrays accessible by the one or more processors; and an array of two-dimensional contacts along a second side of the one or more second semiconductor components, the contacts coupled with the one or more processors and configured to provide power for operation of the one or more processors.

[0006] A semiconductor system is described. The semiconductor system can include a plurality of semiconductor dies bonded together in a stack, each of the plurality of semiconductor dies comprising: a plurality of memory banks each comprising a plurality of respective memory arrays; and a plurality of through-substrate vias arranged between the plurality of memory banks. The semiconductor system can also include: a two-dimensional first contact array arranged on a first surface of the stack; and a two-dimensional second contact array arranged on a second surface of the stack opposite the first surface, at least a subset of the two-dimensional second contact array coupled with the two-dimensional first contact array through the plurality of through-substrate vias of each of the plurality of semiconductor dies.

[0007] A method of forming a semiconductor system is described. The method can include bonding a first semiconductor component along a first side of a set of one or more second semiconductor components, the first semiconductor component comprising one or more processors of a processing system, and the set of one or more second semiconductor components comprising: one or more memory arrays accessible by the one or more processors; and a two-dimensional contact array along a second side of the set of one or more second semiconductor components, the contacts coupled with the one or more processors and configured to provide power for operation of the one or more processors.

[0008] A method of forming a semiconductor system is described. The method can include bonding a plurality of semiconductor dies together in a stack, each of the plurality of semiconductor dies comprising: a plurality of memory banks each comprising a plurality of respective memory arrays; and a plurality of through-substrate vias arranged between the plurality of memory banks, wherein a two-dimensional first contact array is arranged on a first surface of the stack, and a two-dimensional second contact array is arranged on a second surface of the stack opposite the first surface, at least a subset of the two-dimensional second contact array coupled with the two-dimensional first contact array through the plurality of through-substrate vias of each of the plurality of semiconductor dies. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system supporting pass-through power delivery for a top logic semiconductor system is shown in accordance with examples as disclosed herein.

[0010] Figure 2 An example of a system supporting pass-through power delivery for a top logic semiconductor system is shown in accordance with examples as disclosed herein.

[0011] Figures 3 to 5 An example of a system supporting pass-through power delivery for a top logic semiconductor system is shown in accordance with examples as disclosed herein.

[0012] Figure 6 and 7 A flow diagram illustrating a method of supporting pass-through power delivery for a top logic semiconductor system is shown in accordance with examples as disclosed herein. DETAILED DESCRIPTION

[0013] Some semiconductor systems (e.g., memory systems, processor systems) can include a stack of semiconductor components (e.g., semiconductor dies) that can include one or more memory dies (e.g., array dies) or one or more stacks of memory dies stacked with logic dies that are operable to access a set of memory arrays distributed across the one or more memory dies. This stacked architecture can be implemented as part of a high bandwidth memory (HBM) system or a coupled dynamic random access memory (DRAM) system, among other examples, and can support solutions for memory-centric logic, such as graphics processing units (GPUs) and other implementations. In some examples, an HBM system can include one or more memory dies coupled (e.g., bonded, stacked together) with logic dies. In some examples, a 3D stacked memory system can be tightly coupled (e.g., physically coupled, electrically coupled, directly coupled) with a processor (e.g., GPU or other host device) as part of a physical memory map accessible by the processor. The logic dies can include various components, such as interface blocks (e.g., memory interface blocks, interface circuitry), logic blocks, controllers, processors, and other components. The semiconductor components (e.g., semiconductor units, semiconductor subsystems) (e.g., logic dies) can be formed as a single die with associated circuitry, or can be formed with multiple die portions (e.g., relatively smaller dies, each including a respective subset of components of a logic unit), which can be referred to as “chiplets” (e.g., logic chiplets), among other examples.

[0014] In some semiconductor systems, memory die stacks (e.g., memory chips, memory stacks of HBM or 3D stacked memory systems) can be bonded on top of a logic component (e.g., a logic device, a logic die, a processing chip) in a heterogeneous stack (e.g., a 3D stack containing different die types). However, placing a relatively high power logic component at or near the bottom of a heterogeneous stack can result in thermal challenges, as the thermal impedance of the memory dies can trap heat generated by the logic component. For example, heat generated by the logic component can be dissipated (e.g., transferred) through the memory dies to a heat sink (e.g., a cold plate) at the other end of the stack, resulting in a relatively high temperature gradient and peak temperatures (e.g., at or near the logic component). In some cases, the thermal effects of a heterogeneous stack can be mitigated by placing a component (e.g., a logic component) with a relatively high thermal output (e.g., a relatively large heat source) as an upper device (e.g., opposite a system substrate or mounting surface) so as to be more closely integrated with a heat sink. In some cases, placing a logic component on a memory die stack can be referred to as a logic on top (LoT) configuration. However, a LoT configuration can be associated with challenges in providing power to the logic component, particularly in cases where integration with memory dies increases the lateral distance of distributed circuitry within which power is delivered to the logic component (e.g., using one or more redistribution layers around functional circuitry of the memory dies).

[0015] According to examples as disclosed herein, a semiconductor system (e.g., in a LoT configuration) can be configured with a two-dimensional pattern of power delivery conductors of a through- stack semiconductor assembly (e.g., through one or more memory stacks, between stacked functional circuitry) to provide more distributed power delivery to a logic assembly (e.g., one or more processors of a processing system, such as one or more GPUs) engaged with the stack. The power delivery conductors can include through-substrate vias (TSVs) that bypass circuitry of the stack (e.g., transistors or other circuitry of a memory stack), and thus can be allocated to provide power to the logic assembly (e.g., dedicated to the logic assembly). Such techniques can be combined with a redistribution assembly (e.g., a package substrate or interposer (e.g., opposite the logic assembly in a heterogeneous stack)) that can include conductors (e.g., redistribution conductors, conductors of a redistribution layer) that convert from relatively fewer interconnects (e.g., relatively coarser pitch solder balls) at a surface of the semiconductor system to relatively more interconnects (e.g., relatively finer pitch fusion contacts, hybrid bond contacts) at a surface engaged with the stack, the conductors supporting the two-dimensional pattern of power delivery conductors. In some examples, at least some dies of the stack (e.g., a memory stack) can each include one or more memory banks, each of the memory banks can include a memory array and bank logic operable to access the memory array. In various implementations, the two-dimensional pattern of power delivery conductors (e.g., TSVs) can include conductors formed between memory banks or between a memory array and bank logic of one or more memory banks or various combinations thereof. Thus, according to these and other examples, power delivery can be distributed through dies of a stack, thereby improving power distribution to a logic assembly in a LoT configuration by reducing a lateral distance of a distributed assembly to deliver power to the logic assembly and reducing attendant losses and distribution complexity.

[0016] In addition to applicability in memory systems as described herein, techniques for pass-through power delivery for a top logic semiconductor system can generally be implemented to improve performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and gaming. Some electronic device applications, including high performance applications such as AI, AR, VR, and gaming, can be associated with relatively high processing requirements to meet user expectations. As such, improving the processing capabilities of electronic devices by reducing response times, improving power consumption, reducing complexity, increasing data throughput or access speeds, reducing communication times, or increasing memory capacity or density, among other performance metrics, can improve user experience or appeal. Implementing techniques described herein can improve performance of electronic devices by distributing power delivery paths across a stack of semiconductor components (e.g., memory dies), reducing lateral dimensions of conductors to provide power to distributed circuit elements of a logic die (e.g., including one or more processors, such as one or more processing cores). Such techniques can support relatively high power consumption for operations of a logic die, while providing a more direct heat dissipation path to the logic die (e.g., as opposed to a stack of semiconductor components), which can support improved temperature uniformity, higher power density, higher processing density, improved processing speed, and overall improvements to user experience, among other benefits.

[0017] Features of the disclosure are illustrated and described in the context of systems (e.g., semiconductor systems) and architectures. Features of the disclosure are further illustrated and described in the context of flow diagrams (e.g., illustrating one or more methods of forming a semiconductor system).

[0018] Figure 1 An example of a system 100 that supports pass-through power delivery for a top logic semiconductor system in accordance with examples as disclosed herein is shown. The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or other fixed or portable electronic system, among other examples. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 coupling (e.g., to support communicatively coupling) the host system 105 with the memory system 110. The system 100 can include any number of memory system(s) 110 coupled with the host system 105.

[0019] Host system 105 may include one or more components (e.g., circuitry, processing circuitry, application processing circuitry, one or more processing components) that use memory to perform processes (e.g., applications, functions, calculations), any one or more of which may be referred to as processor 125 (e.g., application processor) or included in processor 125. Processor 125 may include at least one of one or more processing elements that may be co-located or distributed, including general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, controllers, discrete gate or transistor logic, one or more discrete hardware components, or combinations thereof. Processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC or a component thereof, and other instances.

[0020] In some instances, system 100 or host system 105 may include input components, output components, or combinations thereof. Input components may include sensors, microphones, keyboards, another processor (e.g., on a printed circuit board), interfaces (e.g., user interfaces, interfaces between other devices), or peripheral devices that interface with system 100 via one or more peripheral components, and other examples. Output components may include displays, audio speakers, printing devices, another processor on a printed circuit board, or peripheral devices that interface with system 100 via one or more peripheral components, and other examples.

[0021] Host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functionality of an external memory controller (e.g., a host system memory controller), which may be referred to as host system controller 120 or included within host system controller 120. For example, host system controller 120 may issue commands or other signaling for operating memory system 110, such as write commands, read commands, configuration signaling, or other operational signaling. In some instances, host system controller 120 or associated functionality described herein may be implemented by processor 125 or may be part of processor 125. For example, host system controller 120 may be hardware, instructions (e.g., software, firmware), or a combination thereof implemented by processor 125 or other components of host system 105. In various instances, host system 105 or host system controller 120 may be referred to as a host.

[0022] Memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by system 100. Memory system 110 may include memory system controller 140 and one or more memory devices 145 operable to store data (e.g., memory packages, memory dies, portions of memory dies). Memory system 110 may be configurable to operate with different types of host systems 105 and may respond to commands from host system 105 (e.g., from host system controller 120). For example, memory system 110 (e.g., memory system controller 140) may receive write commands instructing memory system 110 to store data received from host system 105, or read commands instructing memory system 110 to provide data stored in memory device 145 to host system 105, or refresh commands instructing memory system 110 to refresh data stored in memory device 145, and other types of commands and operations.

[0023] Memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of memory system 110. Memory system controller 140 may include hardware or instructions supporting various operations performed by memory system 110, and may be operable to receive, transmit, or respond to commands, data, or control information related to the operation of memory system 110. Memory system controller 140 may be operable to communicate with host system controller 120, one or more memory devices 145, or one or more processors 125. In some instances, memory system controller 140 may cooperate with host system controller 120, local controller 150 of memory device 145, or any combination thereof to control the operation of memory system 110. Although instances of memory system controller 140 are described as a separate component of memory system 110, in some instances, functional aspects of memory system 110 may be implemented by at least one or any combination of processor 125, host system controller 120, one or more local controllers 150, or thereof.

[0024] Each memory device 145 may include a local controller 150 (e.g., a logic controller, an interface controller, one or more processors) and one or more memory arrays 155. The memory array 155 may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array, an array of one or more semiconductor components), wherein each memory cell is operable to store data (e.g., as one or more stored bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase-change memory (PCM) cells, chalcogenide memory cells, NOR memory cells, NAND memory cells, or any combination thereof.

[0025] Local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of memory device 145. In some instances, local controller 150 may be operable to communicate with memory system controller 140 (e.g., receive or transmit data or commands, or both). In some instances, memory system 110 may not include memory system controller 140, and local controller 150 or host system controller 120 may perform the functions of memory system controller 140 as described herein. In some instances, local controller 150 or memory system controller 140, or both, may include decoding components operable to access addresses of memory array 155, sensing components for sensing the state of memory cells in memory array 155, writing components for writing state to memory cells in memory array 155, or various other components operable to support the described operations of memory system 110.

[0026] The host system 105 (e.g., host system controller 120) and memory system 110 (e.g., memory system controller 140) may use one or more channels 115 to convey information (e.g., data, commands, control information, configuration information, timing information). Each channel 115 may be an instance of a transmission medium carrying information, and each channel 115 may include one or more signal paths (e.g., transmission medium, electrical conductor, conductive path) between terminals (e.g., nodes, pins, contacts) associated with components of system 100. Terminals may be instances of conductive input or output points of devices of system 100, and terminals may operate as part of channel 115. In some embodiments, at least the channel 115 between host system 105 and memory system 110 may include or be referred to as a host interface (e.g., physical host interface). To support communication on channel 115, host system 105 (e.g., host system controller 120) and memory system 110 (e.g., memory system controller 140) may include receivers (e.g., latches) for receiving signals, transmitters (e.g., drivers) for transmitting signals, decoders for decoding or demodulating received signals or encoders for encoding or modulating signals to be transmitted, and other components that support signaling on channel 115, which may be included in the respective interface portions of the respective systems.

[0027] Channel 115 may be dedicated to conveying one or more types of information, and channel 115 may include unidirectional channels, bidirectional channels, or both. For example, channel 115 may include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some instances, channel 115 may be configured to provide power from one system to another (e.g., from host system 105 to memory system 110 according to regulated voltage). In some instances, at least a subset of channel 115 may be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operational protocol, an industry standard) that supports configured operation of host system 105 and memory system 110 and interaction between host system 105 and memory system 110.

[0028] In some instances, at least a portion of system 100 may implement a stacked semiconductor architecture in which multiple semiconductor dies are physically and communicatively coupled (e.g., directly coupled, bonded). For example, at least one of the memory arrays 155 of memory device 145 may be formed using one or more semiconductor dies (e.g., a single memory die, a stack of multiple memory dies), which may be stacked on another semiconductor die (e.g., a logic die) that includes at least a portion of local controller 150. In some instances, a semiconductor die or die assembly may include at least a portion or all of local controller 150 and at least a portion or all of memory system controller 140, and this semiconductor die or die assembly may be coupled to one or more memory dies or a stack of one or more memory dies (e.g., one or more memory stacks). According to these and other instances, circuitry for accessing one or more memory arrays 155 (e.g., circuitry for memory system 110) may be distributed among multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a set of multiple first interface blocks (e.g., memory interface blocks, examples of first interface circuitry), and one or more second dies may include corresponding second interface blocks, each coupled to a first interface block of the first die, each second interface block configured to access one or more memory arrays 155 of the second die. In some instances, the system may include a controller (e.g., at least a portion of a memory controller, interface controller, host interface controller, or memory system controller 140) for each set of one or more first interface blocks to support access operations via the set of first interface blocks (e.g., to access one or more memory arrays 155). In some instances, this controller may be located on the same first die as the first interface block. In some instances, multiple semiconductor dies of memory system 110 or system 100 (e.g., an HBM system including an aspect of memory system 110, a stacked semiconductor system including an aspect of memory system 110 and host system 105) may include one or more array dies stacked together with logic dies (e.g., an aspect including host system 105 coupled to another die including host system 105), the logic dies including interface blocks operable to access a set of memory arrays 155 distributed across one or more second dies.

[0029] In some instances of system 100 or a portion thereof, memory die stacks (e.g., memory chips, memory stacks of memory system 110, HBM, or 3D stacked memory systems) may be bonded on top of logic components (e.g., logic devices, logic dies, processing chips of memory system 110 (including at least a portion of memory system controller 140), host system 105 (including processor 125), etc.) in heterogeneous stacks (e.g., 3D stacks containing different die types). However, placing relatively high-power logic components at or near the bottom of a heterogeneous stack can present heat dissipation challenges, as the thermal resistance of the memory dies may trap heat generated by the logic components. In some cases, the thermal effects of heterogeneous stacks can be mitigated by placing components with relatively high thermal output (e.g., relatively large heat sources) (e.g., logic components) as upper devices (e.g., opposite the system substrate or mounting surface) for closer integration with heat sinks. In some cases, placing logic components on a memory die stack may be referred to as a top logic (LoT) configuration. However, LoT configurations can be associated with challenges in supplying power to logic components, particularly when integration with memory dies increases the lateral distance of the distributed circuitry within which power is delivered to the logic components (e.g., using one or more redistribution layers). According to examples disclosed herein, a semiconductor system (e.g., at least a portion of system 100 in a LoT configuration) can provide more distributed power delivery to logic components (e.g., one or more processors, such as one or more GPUs, of a processing system) coupled to the stack via a two-dimensional pattern of power delivery conductors configured to pass through stacked semiconductor components (e.g., via one or more memory stacks).

[0030] Figure 2Examples of system 200 supporting through-power delivery to a top-level logic semiconductor system are illustrated, based on examples disclosed herein (e.g., semiconductor system, coupled semiconductor die system, HBM system, 3D stacked memory system). System 200 illustrates examples of dies 205 (e.g., die 205-a, semiconductor die, logic die, processor die, host die, logic cell) coupled to one or more dies 240 (e.g., dies 240-a-1 and 240-a-2 of a memory stack, semiconductor die, memory die, array die, memory cell). Dies 205 or dies 240 may be formed using a corresponding semiconductor substrate (e.g., a substrate of a crystalline semiconductor material (e.g., silicon, germanium, silicon-germanium, gallium arsenide, or gallium nitride)) or a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG), silicon-on-sapphire (SOS)) or an epitaxial semiconductor material formed on another substrate, and other examples. Although the illustrated example of system 200 includes two dies 240, system 200 may, according to the described technology, include any number of one or more dies 240 coupled to die 205 (e.g., 8, 12, 16 or more dies 240), as well as other dies in a stacked or other coupled layout. Furthermore, while the non-limiting examples of system 200 herein are described generally in accordance with their suitability for memory systems, memory subsystems, memory devices or combinations thereof, examples of system 200 are not limited thereto. For example, aspects of this disclosure may also be applied to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem for applications such as data collection, data processing, data storage, networking, communication, power, artificial intelligence, system-on-a-chip, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0031] System 200 illustrates an example of an interface circuitry system between a host and memory (e.g., via a host interface, via a physical host interface), said interface circuitry system being implemented (e.g., partitioned between multiple semiconductor dies) in a plurality of semiconductor dies (e.g., a stack of directly coupled dies). For example, die 205-a may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 (e.g., access interface blocks) and one or more memory arrays 250 (e.g., die 240-a-1 includes an interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, die 240-a-2 includes an interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an instance of memory array 155 and may contain memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR or NAND memory cells, or any combination thereof.

[0032] Although an example of system 200 is described as including one interface block 245 in each die 240, the die 240 according to the described technology may include any number of one or more interface blocks 245, each interface block 245 coupled to a corresponding set of one or more memory arrays 250, and each interface block coupled to interface block 220 of die 205. Therefore, the interface circuitry of system 200 may include one or more interface blocks 220 of die 205, wherein each interface block 220 is coupled (e.g., for communication) to one or more interface blocks 245 of die 240 (e.g., external to die 205). In some instances, a coupled combination of interface blocks 220 and interface blocks 245 (e.g., coupled via a bus associated with one or more channels (e.g., one or more data channels, one or more control channels, one or more clock channels, one or more pseudo channels, or combinations thereof)) may include or be referred to as a data path associated with a corresponding set of one or more memory arrays 250.

[0033] In some implementations (e.g., a 3D stacked memory implementation), die 205 may include a host processor 210. The host processor 210 may be an instance of host system 105 or a portion thereof (e.g., processor 125, an aspect of host system controller 120, or both). The host processor 210 may include one or more processor cores configured to perform storage operations implementing memory array 250 (e.g., to support applications or other functions of host system 105 that may request access to memory array 250). For example, the host processor 210 may receive data read from memory array 250 or transfer data to be written to memory array 250, or both (e.g., depending on the application or other operation of host processor 210). Additionally or alternatively, the host processor 210 may be located outside the die 205 (e.g., in the HBM implementation), such as in another semiconductor die or other component coupled to the die 205 via one or more contacts 212 (e.g., externally accessible terminals of the die 205) (e.g., communicatively coupled, directly coupled, bonded, coupled via another intermediary component).

[0034] Host processor 210 may be configured to communicate signaling (e.g., transmit, receive) with interface block 220 via host interface 216 (e.g., physical host interface), which may implement aspects of channel 115. For example, host interface 216 may be configured according to industry standards that define channels, commands, clock control, deterministic response timing, and other characteristics of host interface 216. In some instances, host interface 216 may provide communication coupling between the physical or functional boundaries of host system 105 and memory system 110. For example, host processor 210 may be configured to communicate access signaling (e.g., control signaling, access command signaling, data signaling, configuration signaling, clock signaling) via host interface 216 to support access operations (e.g., read operations, write operations) and other operations to memory array 250. Although instances of system 200 include a single host interface 216, systems according to the described technology may include any number of one or more host interfaces 216 for accessing the memory array 250 of the system.

[0035] In some instances, a corresponding host interface 216 may be coupled between a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2) and a corresponding controller 215. The controller 215 may be an example of a control circuitry system (e.g., a memory controller circuitry system, a host interface control circuitry system) associated with the host system 105, and may be associated with a corresponding example implementing one or more aspects of the host system controller 120 or the memory system controller 140 or a combination thereof. For example, the controller 215 may be operable to respond to indications (e.g., requests, commands) from the host processor 210 for accessing one or more memory arrays 250 to support the functions or applications of the host processor 210, to transmit associated commands (e.g., for one or more interface blocks 220) to access one or more memory arrays 250, and to communicate data with the host processor 210 (e.g., write data, read data), and other functions.

[0036] In some instances, one or more controllers 215 may be implemented in die 205 (e.g., the same die containing one or more interface blocks 220 in a 3D stacked memory implementation, depending on the command and address protocol), regardless of whether the host processor 210 is contained within or outside die 205. In some other instances, controller 215 or associated circuitry or functionality may be implemented outside die 205 (e.g., in another die (not shown) coupled to a corresponding interface block 220 via a corresponding terminal of each of the corresponding host interfaces 216 in an HBM implementation), which may be in the same die as or a different die from the die containing the host processor 210. Interface block 220 may be operated via a single controller 215 or by one or more of a group of controllers 215 (e.g., depending on a controller multiplexing scheme). In some other instances, aspects of one or more controllers 215 may be contained within the host processor 210 (e.g., as a memory interface of the host processor 210, as a memory interface of the host system 105).

[0037] While in some instances the controller 215 may be directly coupled to one or more interface blocks 220 (not shown), in other instances the controller 215 (e.g., host interface 216) may be coupled to a group of interface blocks 220 via logic block 225 (e.g., logic circuitry for channel groups, logic circuitry for host interface 216, multiplexing circuitry). For example, logic block 225 may be coupled to interface block 220-a-1 via bus 223-a-1 and to interface block 220-a-2 via bus 223-a-2. The controller 215 and one or more corresponding interface blocks 220 may communicate (e.g., cooperate) via logic block 225 using host interface 216 to perform one or more operations (e.g., scheduling operations, access operations, operations initiated by host processor 210) associated with accessing a group of corresponding memory arrays 250.

[0038] In some instances, logic block 225, controller 215, or host interface 216, or combinations thereof, may be associated with a “channel group” corresponding to multiple memory arrays 250 (e.g., for parallel or otherwise coordinated access to multiple memory arrays 250). For example, this channel group may be associated with multiple memory arrays 250 accessed via a single interface block 245, or multiple memory arrays 250 each accessed via a corresponding entity in interface block 245, or multiple memory arrays 250 each accessed via a corresponding entity in interface block 220, wherein any of the memory arrays 250 may be associated with signaling via a single logic block 225, via a single host interface 216, or via a single controller 215. These and other configurations for implementing one or more channel groups in the system can support various techniques for parallel and high-bandwidth data transfer, memory management operations, repair and replacement techniques, or power and heat distribution, as well as other techniques utilizing the described coupling of components and interfaces in multiple semiconductor dies (e.g., according to the high-bandwidth configuration of system 200, according to the tightly coupled configuration of system 200). In some instances, such techniques can be implemented in a way that is transparent to host interface 216 or other aspects of host system 105 (e.g., at or using logic block 225).

[0039] In some instances, host interface 216 may include a set of one or more corresponding signal paths for each logic block 225 or interface block 220, such that host processor 210 can communicate with each logic block 225 or interface block 220 via its corresponding set of signal paths (e.g., to perform access operations via the logic block 225 or interface block 220 selected by host processor 210 based on the selection of the corresponding set). Additionally or alternatively, host interface 216 may include one or more signal paths shared among multiple logic blocks 225 (not shown) or interface blocks 220, and logic block 225, interface block 220, or host processor 210, or any of these, may interpret, ignore, respond to, or disable signaling in response to the shared signal paths via host interface 216 based on logical indications (e.g., addressing indications, interface enable signals, or interface select signals associated with logic block 225 or interface block 220, which may be provided by host processor 210, the corresponding logic block 225, or the corresponding interface block 220 depending on the signaling direction).

[0040] In some instances, host processor 210 may determine an access address (e.g., in response to an application of host processor 210 or with the support of host processor 210, the logical address of memory array 250, the physical address of memory array 250, the address of logical block 225, the address of interface block 220, or the address of host interface 216), and determine which controller 215 (e.g., the controller 215, logical block 225, or interface block 220 corresponding to the address) will transmit access signaling for accessing the address to. In some instances, the address may be associated with a row of memory cells, a column of memory cells, or both of memory array 250. Host processor 210 may transmit access signaling (e.g., one or more access signals, one or more access commands) to the determined controller 215, and the determined controller 215 may (e.g., according to a command and address protocol) transmit the access signaling to the corresponding logical block 225 or interface block 220. The corresponding interface block 220 can then transmit access signaling to the coupled interface block 245 to access (e.g., the determined address of the corresponding memory array 250).

[0041] The die 205 may also include logic blocks 230 (e.g., shared logic blocks, central logic blocks, common logic circuitry, evaluation circuitry, memory system configuration circuitry, memory system management circuitry), which may be configured to communicate signalingly (e.g., transmit, receive) with logic blocks 225, interface blocks 220, or both of the die 205. In some cases, logic blocks 230 may be configured to communicate information (e.g., commands, instructions, indications, data) with one or more logic blocks 225 or interface blocks 220 to facilitate the operation of system 200. For example, logic blocks 230 may be configured to transmit configuration signaling (e.g., initialization signaling, evaluation signaling, mapping signaling), which may be received by logic blocks 225 or interface blocks 220 to support the configuration of logic blocks 225 or interface blocks 220 or other aspects of operating the die 240 (e.g., via corresponding interface blocks 245). Logic block 230 may be coupled to each logic block 225 and each interface block 220 via a corresponding bus 231. In some instances, such buses may each contain a corresponding set of one or more signal paths, enabling logic block 230 to communicate with each logic block 225 or each interface block 220 via said set of corresponding signal paths. Additionally or alternatively, such buses may contain one or more signal paths shared among multiple logic blocks 225 or interface blocks 220 (not shown).

[0042] In some implementations, logic block 230 may be configured to (e.g., via bus 232, via contacts 212 of host processor 210 or controller 215 outside die 205) communicate signalingly (e.g., transmit, receive) with host processor 210 or one or more controllers 215, such that logic block 230 can support an interface between host processor 210 or one or more controllers 215 and logic block 225 or interface block 220. For example, host processor 210 or controller 215 may be configured to transmit initialization signaling (e.g., boot commands) or other configuration or operation signaling, which may be received by logic block 230 to support the initialization, configuration, evaluation, or other operations of logic block 225 or interface block 220. Additionally or alternatively, in some embodiments, logic block 230 may be configured to (e.g., via contact 234, which may be an externally accessible terminal of die 205) signal to components outside system 200 (e.g., transmit, receive), such that logic block 230 may support an interface bypassing host processor 210 or controller 215. Additionally or alternatively, logic block 230 may communicate with host processor 210 or controller 215 and with one or more memory arrays 250 of one or more dies 240 (e.g., to perform a self-test operation for access to memory array 250). In some instances, during manufacturing, assembly, verification, or other operations associated with system 200 (e.g., prior to coupling with host processor 210, where host processor 210 is not required for operations independent of host processor 210), such embodiments may support the evaluation, configuration, or other operations of the system via one or more contacts 234 accessible at the physical interface of system 200. Additionally or alternatively, logic block 230 may implement one or more aspects of controller 215. For example, logic block 230 may contain one or more controllers 215 or operate as one or more controllers 215 and perform operations attributable to controller 215.

[0043] In some instances, corresponding signals may be routed between die 205 and one or more dies 240. For example, each interface block 220 may be coupled at least to a corresponding bus 221 of die 205 and a corresponding bus 246 of die 240, said buses being configured to signal to the corresponding interface block 245 (e.g., via one or more associated signal paths). For example, interface block 220-a-1 may be coupled to interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 may be coupled to interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some instances, die 240 may include a bus, such as bus 255, that bypasses the operating circuitry of die 240 (e.g., bypasses the interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-1 via bus 255-a-1, which may bypass interface block 245 of die 240-a-1. This technique can be extended to interconnections among more than two dies 240 (e.g., interconnections via corresponding buses 255 of multiple dies 240). In some embodiments, at least a portion of bus 221, bus 246, or bus 255, or any combination thereof, may include one or more conductors in the redistribution layer (RDL) of the respective die (e.g., above or below the semiconductor substrate of the die). Additionally or alternatively, in some embodiments, at least a portion of bus 221, bus 246, or bus 255, or any combination thereof, may include one or more pathways formed through the semiconductor substrate of the respective die (e.g., as one or more TSVs).

[0044] The corresponding signal paths of buses 221, 246, and 255 can be coupled from one die to another via various arrangements of contacts (e.g., exposed contacts or metal surfaces of the respective dies) on the surfaces of mating dies. For example, bus 221-a-1 can be coupled to bus 246-a-1 via contact 222-a-1 of die 205-a (e.g., on its surface) and contact 247-a-1 of die 240-a-1; bus 221-a-2 can be coupled to bus 255-a-1 via contact 222-a-2 of die 205 and contact 256-a-1 of die 240-a-1; bus 255-a-1 can be coupled to bus 246-a-2 via contact 257-a-1 of die 240-a-1 and contact 247-a-2 of die 240-a-2, and so on. Although each corresponding bus is described as having a single line coupled via a single contact, it should be understood that each signal path of a given bus may be associated with a corresponding contact to support individual communication coupling via each signal path of the given bus. In some instances, bus 255 may traverse a portion of die 240 (e.g., in a plane direction, along a direction different from the thickness direction, in a waterfall arrangement, or in a stepped arrangement), which may support the arrangement of contacts 222 along the surface of die 205 and other contacts coupled along the stacking direction to interface blocks 245 of different dies 240 (e.g., via corresponding contacts 256 and 257 that do not overlap when viewed along the thickness direction).

[0045] Interconnection of mating contacts can be supported by various technologies. For example, in hybrid bonding embodiments, mating contacts can be coupled by the fusion of the conductive materials (e.g., electrically conductive materials) of the mating contacts (e.g., without solder or other intermediary materials between the contacts). For example, under assembly conditions, coupling of die 205-a to die 240-a-1 may involve the fusion of the conductive materials of contact 222-a-2 to the conductive materials of contact 256-a-1, and coupling of die 240-a-1 to die 240-a-2 may involve the fusion of the conductive materials of contact 257-a-1 to the conductive materials of contact 247-a-2, and so on. In some instances, this coupling may involve the non-operable fusion of contacts (e.g., non-communication coupling, physical coupling), such as the fusion of contacts 260-a-1 and 256-a-2, neither of which is coupled to the operable circuitry of die 240-a-1 or 240-a-2. In some instances, such techniques may be implemented to improve coupling strength or uniformity (e.g., implementing contacts 260 that may not be operablely coupled to interface block 245 or interface block 220), or this coupling may be a byproduct of repeating components that may be operable or non-operable in various configurations. (For example, for a bare die 240 with contacts 256 and 257 arranged together, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0046] In some instances, the fusion of conductive materials between dies (e.g., between contacts) may be accompanied by the fusion of other materials at one or more surfaces of the mating dies. For example, under assembly conditions, coupling of die 205-a to die 240-a-1 may involve the fusion of dielectric material 207 (e.g., a non-conductive material) of die 205-a to dielectric material 242 of die 240-a-1, and coupling of die 240-a-1 to die 240-a-2 may involve the fusion of dielectric material 242 of die 240-a-1 to dielectric material 242 of die 240-a-2. In some instances, such dielectric materials may comprise oxides, nitrides, carbides, oxide-nitride, oxide-carbide, or other conversions or doping of the substrate material of die 205 or die 240 (e.g., a semiconductor substrate material) or other materials, as well as other materials that may support this fusion. However, the coupling in die 205 and die 240 can be implemented using other techniques, such as solder, adhesive, thermal interface material and other intermediate materials or combinations thereof.

[0047] In some instances, dies 240 may be stacked and coupled (e.g., forming a “cube” of dies 240, a memory stack, or other arrangement), and one or more of such stacks may subsequently be coupled to die 205 (e.g., in a stack-to-die bonding arrangement). In some instances, (a plurality of) corresponding groups of one or more dies 240 may be coupled to each of a plurality of dies 205 formed in a wafer (e.g., in a chip-to-wafer bonding arrangement before wafers are diced from the dies 205, in a stack-to-wafer bonding arrangement), and the dies 205 of the wafers may be separated from each other (e.g., by dicing at least the wafers of the dies 205, by single-dicing), each die 205 being coupled to (a plurality of) their corresponding groups of dies 240. In some other instances, (a plurality of) corresponding groups of one or more dies 240 may be coupled to their respective dies 205 after the dies 205 have been separated from their wafers (e.g., in a chip-to-wafer bonding arrangement). In some other instances, a group of one or more corresponding wafers, each comprising a plurality of dies 240, may be stacked and coupled (e.g., in a wafer-to-wafer bonding arrangement). In various instances, such techniques may then be used to separate the stack of dies 240 from the coupled wafers, or to couple the wafer stack having dies 240 to another wafer comprising a plurality of dies 205 (e.g., in a second wafer-to-wafer bonding arrangement), after which the system 200 may be separated from the coupled wafers. In some other instances, wafer-to-wafer coupling techniques may be implemented by stacking one or more wafers of dies 240 on the wafers of dies 205 (e.g., sequentially) prior to separation into the system 200 and other instances for forming the system 200.

[0048] Buses 221, 246, and 255 may be implemented to provide configured signaling (e.g., coordination signaling, logic signaling, modulated signaling, digital signaling) between interface block 220 and corresponding interface block 245. This configured signaling may involve various modulation or encoding techniques performed by the transport interface blocks (e.g., via driver components of the transport interface blocks). In some instances, this signaling may be supported by clock signaling transmitted via the respective bus (e.g., accompanying clock signaling) (e.g., coordinated with signal transmission). For example, the bus may be configured to deliver one or more clock signals transmitted by interface block 220 for reception by interface block 245 (e.g., to trigger signal reception by latches or other receiving components of interface block 245 to support clock operation of interface block 245). Alternatively or concurrently, the bus may be configured to deliver one or more clock signals transmitted by interface block 245 for reception by interface block 220 (e.g., to trigger signal reception by latches or other receiving components of interface block 220 to support clock operation of interface block 220). Such clock signals can be associated with communication of various signaling types (e.g., control signaling, command signaling, data signaling, or any combination thereof) (e.g., one-way communication, two-way communication, deterministic communication). For example, the bus may include one or more signal paths for data bus communication (e.g., one or more data channels, DQ bus, via the data interface of the interface block) based on one or more corresponding clock signals (e.g., data clock signals), or one or more signal paths for control bus communication (e.g., command / address (C / A) bus, via the command interface of the interface block) based on one or more clock signals (e.g., control clock signals), or any combination thereof.

[0049] Interface block 220, interface block 245, logic block 225, and logic block 230 may each contain circuitry (signaling circuitry, multiplexing circuitry, processing circuitry, controller circuitry, logic circuitry, physical components, hardware) in various configurations (e.g., hardware configuration, logic configuration, software configuration, or instruction configuration), said circuitry supporting functionality allocated to the respective blocks for accessing or otherwise operating a set of corresponding memory arrays 250. For example, interface block 220 may contain circuitry configured to perform a first subset of operations supporting access to memory array 250, and interface block 245 may contain circuitry configured to perform a second subset of operations supporting access to memory array 250. In some instances, interface block 220, interface block 245, and logic block 225 may support the functional partitioning or distribution of functionality associated with memory system controller 140, local controller 150, or both across multiple dies (e.g., die 205 and at least one die 240). In some implementations, logic block 230 may be configured to coordinate or configure aspects of the operation of interface block 220, interface block 245, logic block 225, or combinations thereof, and may support one or more aspects of implementing memory system controller 140. Such operations or subsets of operations may include operations performed in response to commands from host processor 210 or controller 215, or operations performed without commands from host processor 210 or controller 215 (e.g., operations determined or initiated by logic block 225, operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logic block 230), or various combinations thereof.

[0050] In some implementations, system 200 may include one or more examples of non-volatile memory devices (e.g., non-volatile memory device 235 of die 205, one or more non-volatile memory devices 270 of die 240, or combinations thereof). In some instances, logic block 230, logic block 225, interface block 220, interface block 245, or combinations thereof may be configured to communicate signalingly with one or more examples of non-volatile memory devices. For example, logic block 230, logic block 225, interface block 220, or interface block 245 may be coupled to one or more examples of non-volatile memory devices via one or more buses (not shown) or corresponding contacts (not shown), wherein, where applicable, the buses or contacts may each include one or more signal paths operable to convey signaling (e.g., command signaling, data signaling). In some instances, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof, may configure one or more operations based on information (e.g., instructions, configurations, parameters) stored in one or more instances of the non-volatile memory device. Additionally or alternatively, in some instances, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof, may be written with information (e.g., configuration information, evaluation information) to be stored in one or more instances of the non-volatile memory device. In some instances, this non-volatile memory device may contain fuses, antifuses, or other types of one-time programmable memory elements, or any combination thereof.

[0051] In some implementations, system 200 may include one or more sensors (e.g., one or more sensors 237 on die 205, one or more sensors 275 on die 240, or a combination thereof). In some implementations, logic block 230, logic block 225, interface block 220, interface block 245, or a combination thereof may be configured to receive one or more indications based on measurements from one or more sensors of system 200. For example, logic block 230, logic block 225, interface block 220, or interface block 245 may be coupled to one or more sensors via one or more buses (not shown) or corresponding contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, and other types of sensors. In some instances, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may be configured with one or more operations based on the output of one or more sensors. For example, logic block 230 may configure one or more operations of logic block 225 or interface block 220 based on signaling (e.g., indications, data) received from one or more sensors. Additionally or alternatively, logic block 225 or interface block 220 may generate access signaling for transmission to the corresponding interface block 245 based on one or more sensors.

[0052] In some instances, a circuit system comprising logic block 225, interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least partially from a doped portion of the substrate of the respective die. In some instances, the substrate of die 205 may have characteristics (e.g., material, material properties, physical shape, or size) different from those of the substrate of die 240. Additionally or alternatively, in some instances, transistors formed from the substrate of die 205 may have characteristics (e.g., fabrication characteristics, performance characteristics, physical shape, or size) different from those formed from the substrate of die 240 (e.g., according to a different transistor architecture, according to a different transistor design).

[0053] In some instances, interface block 220 may support the layout of one or more components within interface block 220. For example, the layout may include pairing components to share access ports (e.g., command ports, data ports). Furthermore, in some instances, the layout may support an interface for controller 215 (e.g., host interface 216) that differs from the interface for interface block 245 (e.g., via bus 221). For example, host interface 216 may be synchronous and have separate channels for read and write operations, while the interface between interface block 220 and one or more interface blocks 245 may be asynchronous and utilize the same channels to support both read and write operations. In some instances, signaling for host interface 216 may be implemented using deterministic timing (e.g., deterministic timing between controller 215 and logic block 225 or one or more interface blocks 220), which may be associated with a configured timing between a first signal and a responsive second signal. In some instances, signaling between interface block 220 and one or more interface blocks 245 may be implemented using timing different from that of host interface 216 (e.g., based on different clock frequencies, based on timing offsets, such as phase offsets), which may be deterministic or nondeterministic.

[0054] Die 240 may contain one or more cells 265 (e.g., modules) separate from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of cells 265. Although each die 240 of system 200 is described as having a single cell 265 (e.g., cell 265-a-1 of die 240-a-1, cell 265-a-2 of die 240-a-2), according to the described technology, die 240 may contain any number of cells 265, and the cells 265 may be arranged in various patterns (e.g., groups of one or more cells 265 along a row direction, groups of one or more cells 265 along a column direction, and other patterns). Each cell 265 may at least include the circuitry of a corresponding interface block 245, together with one or more memory arrays 250, buses 251, buses 246, and one or more contacts 247 corresponding to the corresponding interface block 245. In some instances, where applicable, each cell 265 may also include one or more buses 255, contacts 256, contacts 257, or contacts 260 (e.g., associated with a corresponding interface block 245 of cell 265 of a different die 240), which may support various degrees of stackability or modularity in or via cell 265 of other dies 240. Although instances of nonvolatile memory 270 and sensor 275 are illustrated as being outside cell 265, in some other instances, nonvolatile memory 270, sensor 275, or both may be additionally or alternatively included in cell 265.

[0055] In some instances, interface block 220 may include circuitry configured to (e.g., based on a request from a host application, via host interface 216, via one or more contacts 212 outside the die 205 from host processor 210 or controller 215, from logic block 225) receive a first access command signaling, and to transmit a second access command signaling to a corresponding (e.g., coupled) interface block 245 based on (e.g., in response to) receiving the first access command signaling. Interface block 245 may correspondingly include circuitry configured to receive a second access command signaling from the corresponding interface block 220 and, in some instances, to access a corresponding set of one or more memory arrays 250 based on (e.g., in response to) receiving the second access command signaling. In various instances, the first access command signaling may include an access command associated with an operation type (e.g., read operation, write operation, refresh operation, memory management operation), which may be associated with an indication of an address (e.g., logical address, physical address) of one or more memory arrays 250. In some instances, the first access command signaling may include an indication of a logical address associated with memory array 250, and the circuitry of interface block 220 may be configured to generate a second access command signaling to indicate a physical address associated with memory array 250 (e.g., row address, column address, using the logic-to-physical (L2P) table or other mapping or computational functionality of interface block 220).

[0056] In some instances, to support write operations of system 200, the circuitry of interface block 220 may be configured (e.g., from host processor 210, from controller 215, from logic block 225) to receive first data signaling associated with a first access command signaling, and to transmit second data signaling (e.g., associated with a second access command signaling) based on the receipt of the first access command signaling and the first data signaling. Interface block 245 may be accordingly configured to receive the second data signaling, and to write data to one or more memory arrays 250 (e.g., according to an indicated address associated with the first access command signaling) based on the receipt of the second access command signaling and the second data signaling. In some instances, interface block 220 may include error control functionality (e.g., error detection circuitry, error correction circuitry, error correction code (ECC) logic, ECC engine) that enables interface block 220 to generate second data signaling based on receiving first data signaling and performing error control operations (e.g., detecting or correcting errors in the first data signaling, determining one or more parity bits to be delivered in the second data signaling and written with the data).

[0057] In some instances, to support read operations of system 200, the circuitry of interface block 245 may be configured to read data from memory array 250 based on received second access command signaling and based on read data transmission of first data signaling. Interface block 220 may be correspondingly configured to receive the first data signaling and transmit second data signaling (e.g., to host processor 210, to controller 215, to logic block 225) based on received first data signaling. In some instances, interface block 220 may include error control functionality that enables interface block 220 to generate second data signaling based on received first data signaling and the execution of error control operations (e.g., detecting or correcting errors in the first data signaling, which may involve calculations involving one or more parity bits received with the first data signaling).

[0058] In some instances, based on various determining or generating techniques configured at interface block 220 or logic block 225 (e.g., based on a configuration modified at interface block 220 or logic block 225 for accessing memory array 250), access command signaling and other signaling (e.g., based on access command signaling received from host processor 210, based on start signaling received from host processor 210, or in the absence of or otherwise independently of signaling from host processor 210) can be generated and transmitted to interface block 245. In some instances, such techniques may involve signaling or other coordination with logic block 230, logic block 225, host processor 210, one or more controllers 215, one or more examples of non-volatile memory devices, one or more sensors, or any combination thereof. Such techniques can support aspects of configuring interface block 220 or logic block 225 for access operations and other operations performed on memory array 250 by the corresponding interface block 245. For example, interface block 220 or logic block 225 may include evaluation circuitry, access configuration circuitry, signaling circuitry, scheduling circuitry, repair circuitry, refresh circuitry, error control circuitry, adverse access (e.g., row hammer) mitigation circuitry, and other circuitry operable to configure operations associated with one or more dies (e.g., operations associated with memory array 250 accessing die 240).

[0059] In some instances, the functionality of die 205 may be implemented as a semiconductor unit (e.g., a semiconductor system) having multiple semiconductor die portions (e.g., semiconductor chiplets, relatively small semiconductor dies), and each die portion may contain a corresponding portion of a circuit system associated with die 205. For example, unit 280 may represent a portion of a circuit system component contained in a die portion (e.g., in a chiplet), and the die portion may contain an integer multiple of units 280. In some instances, each semiconductor die portion of the semiconductor unit may contain a different corresponding portion of the circuit system. As a non-limiting example, the semiconductor unit (e.g., having the functionality of die 205) may be formed from one or more first die portions having one or more units 280-a-1 and one or more second die portions having one or more units 280-a-2. One or more units 280-a-1 may contain one or more interface blocks 220, logic blocks 225 or any combination thereof, and one or more units 280-a-2 may contain a host processor 210, one or more controllers 215, logic blocks 230 or any combination thereof.

[0060] In some embodiments of system 200, a stack of dies 240 may be bonded on top of die 205. However, the logic circuitry of die 205 (e.g., interface block 220, logic block 225, logic block 230, controller 215, host processor 210) may be associated with relatively high-power operation and the associated heat generation, and positioning die 205 at or near the bottom of the stack (e.g., relatively close to the system substrate or assembly surface) may present heat dissipation challenges because the thermal resistance of die 240 may trap the heat generated by die 205. For example, the heat generated by die 205 in the assembly can be transferred through die 240 to a heat sink (e.g., on top of die 240), resulting in a relatively high temperature gradient and peak temperature (e.g., at or near die 205). In some cases, the thermal effects of heterogeneous stacking can be mitigated by placing die 205 as a top device for closer integration with the heatsink. This may involve placing die 205 on top of die 240 according to a top logic (LoT) configuration. However, this configuration may be associated with challenges in powering the circuitry of die 205, particularly when integration with die 240 increases the lateral distance of power delivery to the distributed circuitry of die 205 (e.g., using one or more redistribution layers around the circuitry of die 240).

[0061] According to examples disclosed herein, a semiconductor system (e.g., system 200 in a LoT configuration) can provide more distributed power delivery to logic components (e.g., die 205) bonded to the stack via a two-dimensional pattern of power delivery conductors configured with through-stacked semiconductor components (e.g., through one or more stacks of die 240). The power delivery conductors may include TSVs that bypass stacked circuitry (e.g., bypass interface block 245 and memory array 250) and can therefore be allocated (e.g., dedicated to) providing power to the logic components. Such techniques can be combined with redistribution components, such as a package substrate or interposer (e.g., opposite die 205, below die 240), which may include redistribution conductors that transition from relatively fewer interconnects (e.g., relatively coarse-pitch solder balls) at the surface of the semiconductor system to relatively more interconnects (e.g., relatively fine-pitch fused contacts, hybrid bonding contacts) at the surface bonded to the stack, the redistribution conductors supporting the two-dimensional pattern of the power delivery conductors. In some instances, die 240 may be arranged according to memory banks, each of which may include a corresponding memory array 250 and memory bank logic operable for accessing the corresponding memory array 250 (e.g., associated with interface block 245). In various embodiments, the two-dimensional pattern of power delivery conductors (e.g., TSVs) may include conductors formed between memory banks or between memory arrays and memory bank logic of one or more memory banks, or various combinations thereof. Thus, according to these and other instances, power delivery can be distributed via die 240, thereby improving power distribution to die 205 or other logic components in the LoT configuration by reducing the lateral distance of distributed components for delivering power to logic components and reducing associated losses and power distribution complexity.

[0062] Figure 3 Examples of system 300 (e.g., semiconductor system, semiconductor die system) supporting through-power delivery to a top logic semiconductor system are shown, based on examples disclosed herein. Aspects of system 300 may be described with reference to the x, y, and z directions of the illustrated coordinate system, where the z direction may describe a direction orthogonal to or otherwise relative to a surface in the xy plane of system 300 (e.g., vertical, thickness, stacking direction). Although Figure 3 Examples of the relative dimensions and quantities of various features are provided, but based on the examples disclosed herein, aspects of system 300 may be implemented using other relative dimensions or quantities of such features.

[0063] System 300 may include semiconductor component 305 (e.g., semiconductor component 305-a), which may be an example of an aspect of die 205. Semiconductor component 305 may include processing system 310, which may include various embodiments of processing circuitry systems (e.g., logic circuitry systems, processing units). In some instances, processing system 310 may include one or more processors and may be an example of an aspect of processor 125, host processor 210, one or more controllers 215, or combinations thereof (e.g., in a 3D stacked memory embodiment). For example, one or more processors of processing system 310 may be associated with one or more processing cores, one or more GPUs, one or more CPUs, or other processing units. Additionally or alternatively, processing system 310 may include one or more interface blocks 220, logic blocks 225, logic blocks 230, or combinations thereof (e.g., in an HBM embodiment). Although in some instances the semiconductor component 305 may be implemented as a single semiconductor die, in other instances the semiconductor component 305 may be implemented as multiple semiconductor dies (e.g., in a stacked arrangement, in a chiplet arrangement, or both).

[0064] Semiconductor component 305 may include a plurality of contacts 315 configured to receive power (e.g., power based on one or more regulated voltages relative to ground) for operating the circuitry of processing system 310. In some instances (e.g., as shown), contacts 315 may be implemented on the front side of semiconductor component 305, wherein the front side may refer to the same side from which the semiconductor substrate of semiconductor component 305 is doped to form circuitry (e.g., transistor circuitry, transistor channels, circuitry of processing system 310). For example, as illustrated, side 306 (e.g., face, surface, interface) of semiconductor component 305-a may correspond to the front side and side 307 of semiconductor component 305-a may correspond to the rear side. In some instances, the contacts 315 may be formed on the front side with a smaller size, smaller pitch, or both (e.g., as TSV contacts, as contacts coupled to a conductor formed through the semiconductor substrate of the semiconductor assembly 305) compared to when the contacts are formed on the rear side. This may support a relatively higher number or higher density (e.g., in the xy plane) of contacts 315 or a relatively higher density of components (e.g., substrate assemblies, transistors) or combinations thereof in the processing system 310.

[0065] System 300 may also include a group 345 of one or more semiconductor components 340 (e.g., semiconductor dies, memory dies), each of the one or more semiconductor components 340 being an example of an aspect of die 240. The group 345 may be bonded to semiconductor component 305-a along a side 346 of the group 345 (e.g., a side of semiconductor component 340-a-2), which may include the fusion of conductive material of the contact 372 of the via 370 (e.g., TSV) and conductive material of the contact 315 of semiconductor component 305-a. In some instances, this fusion of conductive material may be accompanied by the fusion of dielectric material (e.g., dielectric material 207, dielectric material 242) at the mating surfaces (e.g., according to a hybrid bonding embodiment). Although Figure 3 The description describes a system 300 comprising two semiconductor components 340 in a stack, but a system 300 according to the described technology may comprise a single semiconductor component 340 or any number of semiconductor components 340 that can be stacked (e.g., memory stacks) together (e.g., two, four, eight, twelve, sixteen or more). A group 345 (e.g., one or more of the semiconductor components 340) may comprise one or more arrays 355 (e.g., memory arrays), each of the one or more arrays 355 may be an instance of memory array 155 or memory array 250, and each of the one or more arrays 355 may be accessible by at least a portion of the processing system 310 (e.g., via interface block 245, via interface block 220). In some instances, one or more of the semiconductor components 340 may include a plurality of memory banks 350 (e.g., memory banks), each memory bank including a corresponding array 355 (e.g., a pair of arrays 355) and corresponding memory bank logic 360 operable for accessing the corresponding array 355 (e.g., including at least a portion of an interface block 245 between the corresponding arrays 355, along the x-direction, along the y-direction, or both).

[0066] Group 345 (e.g., at least the bottom semiconductor component 340 of group 345) may also include a two-dimensional array (e.g., two-dimensional in the xy plane) of contacts 371 along (e.g., semiconductor component 340-a-1) the side 347 of group 345. Contacts 371 may be coupled to processing system 310 (e.g., via contacts 315, along one or more pathways 370 in the z-direction) and may be configured to provide power for operation of processing system 310. Contacts 371 may be coupled to processing system 310 via corresponding conductive paths (e.g., pathways 370) through semiconductor component 340, said conductive paths bypassing circuitry for accessing array 355 (e.g., bypassing array 355 itself, bypassing memory logic 360). For example, at least some pathways 370 and corresponding contacts 371 and 372 may be arranged between memory cells 350 (e.g., along the x-direction, along the y-direction, or both), such as pathway 370-a. Additionally or alternatively, at least some of the pathways 370 and corresponding contacts 371 and 372 may be arranged between the memory logic 360 and the array 355 of a given memory bank 350 (e.g., along the x-direction, along the y-direction, or both), such as pathway 370-b. Additionally or alternatively, at least some of the pathways 370 may be arranged along the periphery of one or more semiconductor components 340 (e.g., outside the memory bank 350), such as pathway 370-c.

[0067] In some instances, each of the stacked semiconductor components 340 may include a corresponding contact 371, which may be aligned with each other (e.g., at least partially overlapping in the xy plane with the same or similar pattern when viewed along the z-direction). Additionally or alternatively, at least some (if not all) of the contacts 371 may be aligned with contacts 372 (e.g., those of a given semiconductor component 340 through a path 370 passing directly between the front and rear sides of the given semiconductor component 340). In other words, each or one or more of the semiconductor components 340 in group 345 or a group may include a two-dimensional array of contacts 372 on a first surface (e.g., side 346) and a two-dimensional array of contacts 371 arranged on a second surface (e.g., side 347), wherein at least a subset of the contacts 371 are coupled to the contacts 372 via the path 370. Although the passage 370 is described as having different sizes (e.g., width, diameter, in the xy plane, along the x direction, along the y direction, at different locations along the z direction) between contacts 371 and 372, in some instances, the passage 370 may be formed from the front, rear, or both sides of a given semiconductor assembly 340 with a common dimension (e.g., conductor dimension) (e.g., formed in a cavity with continuous sidewalls), in which case contacts 371, 372, or both may refer to the mating surface (e.g., contact surface) of the passage 370 at the front or rear side of the given semiconductor assembly 340.

[0068] In some instances, a first set of contacts 371 (e.g., a first set of TSVs, a first set of contacts 372, a first set of contacts 315, including at least the contacts 371 associated with path 370-a) may be associated with a power supply voltage (e.g., a positive power supply voltage, drain voltage (Vdd)), and a second set of contacts 371 (e.g., including at least the contacts 371 associated with path 370-b) may be associated with a ground voltage (e.g., GND, source voltage (Vss)). In some instances, one or more other sets of TSVs (e.g., including at least the contacts 371 associated with path 370-c) may be associated with another power supply voltage (e.g., another positive power supply voltage, a negative power supply voltage, emitter voltage (Vee), collector voltage (Vcc)), which may be associated with a different voltage level or different voltage regulation characteristics (e.g., different filtering characteristics, different jitter characteristics, different regulation stability, different switching characteristics) or a combination thereof for supplying power to the processing system 310 than the first set of contacts 371. although Figure 3The description provides an example of such technology for two different voltages, but the different contacts 371 associated with different voltages may be distributed in different ways, or may be implemented using different numbers or ratios of contacts 371, or may be implemented using any number of one or more power supply voltages, and other configurations.

[0069] In some instances, power can be distributed from a relatively small number of contacts at the package interface to a relatively large number of contacts at the interface having group 345 (e.g., through group 345). Such techniques can support finer-grained power distribution through group 345 and regions of semiconductor component 305, and can utilize semiconductor component bonding techniques (e.g., hybrid bonding) that are relatively finer-grained than package assembly techniques (e.g., solder bonding). For example, as shown, system 300 may also include semiconductor component 380 (e.g., semiconductor component 380-a, interposer, system substrate) bonded to group 345 along side 347 of group 345. Semiconductor component 380-a may include a two-dimensional array of contacts 382 along side 385 of semiconductor component 380, the contacts 382 being coupled to contacts 371 along side 347 of group 345. Semiconductor component 380-a also includes a plurality of contacts 381 along side 386 of semiconductor component 380-a, the plurality of contacts 381 being coupled to contacts 382 (e.g., via one or more redistribution layers, via one or more power layers, via a relatively thick conductor configuration for reducing distributed losses), for which there are fewer contacts 381 than contacts 382. For example, contact 381-a may be associated with a first power supply voltage, contact 381-b may be associated with a ground voltage, and contact 381-c may be associated with a second power supply voltage having characteristics different from the first power supply voltage. In some such instances, a single contact 381 may be coupled to multiple contacts 382 (e.g., contact 381-a coupled to contact 382-a, contact 381-b coupled to contact 382-b, contact 381-c coupled to contact 382-c), such as dozens, hundreds, thousands, or tens of thousands of contacts 382, ​​etc. Thus, contacts 382 may be associated with a first pitch dimension (e.g., along the x-direction, along the y-direction, or both), and contacts 381 may be associated with a second pitch dimension larger than the first pitch dimension. This facilitates relatively large interconnects, such as solder ball connections (e.g., compared to the fusion bonding of contacts 382 and 371), at the interface of system 300 (e.g., on side 386 of semiconductor component 380). Although the description shows a single contact 381 being assigned to a corresponding power supply voltage, the described technology can support any number of one or more contacts 381 being assigned to a given power supply voltage, which can be implemented for any number of one or more power supply voltages.

[0070] In some instances, bonding of group 345 to semiconductor component 305-a can be performed based on front-to-front bonding (e.g., bonding the front side of semiconductor component 340-a-2 to the front side of semiconductor component 305-a). For example, semiconductor component 340 may be formed with a via 370 having a relatively fine pitch, but the manufacturing process or design of semiconductor component 305 may not support such a fine-pitch TSV. Therefore, by bonding to the front side of semiconductor component 305-a and, in some instances, the front side of semiconductor component 340-a-2, interconnects can be supported using a relatively fine pitch without implementing a fine-pitch TSV (e.g., a via through the semiconductor substrate of semiconductor component 305-a) at semiconductor component 305-a. Additionally or alternatively, bonding to the front side of semiconductor component 340-a-2 can support various redistribution techniques in the metallization layer of semiconductor component 340-a-2, such as techniques in which the number, size, or distribution of contacts 372 along side 346 may differ from the number, size, or distribution of contacts 371 (e.g., on side 347, on group 345, or on the side of semiconductor component 340 opposite to side 346).

[0071] System 300 may also include a heat dissipation assembly 390 coupled to semiconductor component 305-a, such that semiconductor component 305-a is located between heat dissipation assembly 390 and assembly 345. Heat dissipation assembly 390 may include various embodiments, such as a cold plate, radiator, liquid-cooled heat exchanger, thermoelectric cooler, or other components that absorb heat from system 300. By positioning heat dissipation assembly 390 relatively close to processing system 310, heat from the operation of processing system 310 can be dissipated relatively efficiently compared to configurations where this heat is dissipated via semiconductor component 340 and other embodiments.

[0072] Figure 4 An example of a layout 400 supporting through-power delivery to a top logic semiconductor system is shown, based on examples disclosed herein. Layout 400 may represent a top view (e.g., a cross-section in the xy plane) of one or more semiconductor components 340 (e.g., semiconductor component 340-b). Layout 400 may include multiple memory banks 350-a, each memory bank 350-a including a corresponding array 355 and memory bank logic 360. In examples of layout 400, memory banks 350-a may be arranged according to channels 410 (e.g., channel 410-a includes a first group of memory banks 350-a, and channel 410-b includes a second group of memory banks 350-a). In some examples, each channel 410 may correspond to an independently accessible portion of the memory supporting parallel processing of data delivered using processing system 310, and may correspond to a corresponding logic block 225, a corresponding host interface 216, or a corresponding controller 215, and other embodiments.

[0073] Layout 400 illustrates an example of a two-dimensional array of pathways 370-a that can support power delivery to a processing system 310 coupled to a semiconductor component 305 coupled to a semiconductor component 340-b. For example, pathways 370-a can be arranged between memory banks 350-a, between channels 410, between memory bank logic 360 and adjacent (e.g., associated, coupled) arrays 355 (e.g., along TSV channels), and other examples. Each of the pathways 370-a can be associated with corresponding contacts 371 and 372, which can support coupling to contacts of semiconductor components 305 or 340 adjacent to semiconductor components 340-b. In some examples (e.g., as illustrated), pathways 370-a can be associated with a circular cross-section (e.g., in the xy plane), which can promote component or processing uniformity. However, in some other examples, pathways 370 can be formed with other cross-sectional shapes, such as squares, rectangles, polygons, ellipses, or other shapes.

[0074] Layout 400 also illustrates an embodiment of signal conductor 440, which may represent a path (e.g., TSV) through semiconductor component 340-b (e.g., through one or more bypass regions, through one or more semiconductor extensions not occupied by the operating circuitry of semiconductor component 340-b). For example, signal conductor 440 in one or more regions 441 may be associated with signaling between one or more semiconductor components 340 and semiconductor component 305 (e.g., processing system 310), and signal conductor 440 may include conductive paths of bus 246 or bus 255. In another example, signal conductor 440 in one or more regions 442 may be associated with signaling between semiconductor component 305 (e.g., processing system 310) and semiconductor component 380 (e.g., packaging substrate, interposer). In some instances, zone 441 may contain a larger number of signal conductors 440 than zone 442 (e.g., for greater throughput), or have signal conductors 440 with finer pitch than zone 442 (e.g., for looser bonding requirements between group 345 and semiconductor component 380), or both. However, signal conductors 440 may be implemented according to other arrangements, distributions, or for carrying signals among other components of system 300. In some instances, signal conductors 440 may be implemented for carrying signals to or from the circuitry of semiconductor component 340-b. Additionally or alternatively, signal conductors 440 may be implemented for carrying signals through semiconductor component 340-b (e.g., bypassing the circuitry of semiconductor component 340-b). In some instances, path 370-a may also be implemented in zones 441 or 442 and other locations of layout 400.

[0075] Figure 5Examples of system 500 (e.g., semiconductor system, semiconductor die system) supporting through-power delivery to a top logic semiconductor system are shown, based on examples disclosed herein. Aspects of system 500 may be described with reference to the x, y, and z directions of the illustrated coordinate system, where the z direction may describe a direction orthogonal to or otherwise relative to a surface in the xy plane of system 500 (e.g., vertical, thickness, stacking direction). Although Figure 5 Examples of the relative dimensions and quantities of various features are provided, but based on the examples disclosed herein, aspects of system 500 may be implemented using other relative dimensions or quantities of such features.

[0076] System 500 may include semiconductor component 305-c, which may include processing system 310-a. Processing system 310 may include one or more processors and may be an example of processor 125, host processor 210, one or more controllers 215, or a combination thereof. Semiconductor component 305-c may include a plurality of contacts 315-a configured to receive power for operating the circuitry of processing system 310-a. System 300 may also include heat dissipation assembly 390-a, which may be coupled to semiconductor component 305-c.

[0077] System 300 may also include multiple groups 345-a (e.g., groups 345-a-1 and 345-a-2) of semiconductor components 340. For example, each group 345-a may include a corresponding group of one or more semiconductor components 340-c, each of the one or more semiconductor components 340-c being an instance of an aspect of die 240. Each semiconductor component 340-c may include a corresponding group of one or more memory cells 350-b and other components. Although Figure 5 The description refers to group 345-a, which includes two semiconductor components 340-c in a stack, but group 345-a according to the described technology may include a single semiconductor component 340-c, or any number of semiconductor components 340-c (e.g., two, four, eight, twelve, sixteen or more) that can be stacked (e.g., memory stack) together.

[0078] Each group 345-a may also include a corresponding semiconductor component 340-d, which may be an example of an aspect of die 205. For example, each of the semiconductor components 340-d may include logic 540, which may refer to interface block 220, one or more logic blocks 225, one or more controllers 215 (e.g., when not included in semiconductor component 305-c), various implementations of data sensing amplification (e.g., to support relatively low-level signaling between logic 540 and memory bank 350-b, such as signaling based on amplified voltage sensed from memory cells), or combinations thereof. In some instances, semiconductor component 340-d may be referred to as a data proximity layer (DPL), and the logic 540 of this semiconductor component 340-d may facilitate operation between processing system 310-a and memory bank 350-b using a circuit system separate from semiconductor components 340-c and 305-c.

[0079] Each group 345-a may be coupled to a semiconductor component 305-c along a first side (e.g., side 346) of group 345-a, which may include the fusion of conductive material of passages 370-d (e.g., contacts 372, 212) and conductive material of contacts 315-a. In some instances, this fusion of conductive material may be accompanied by the fusion of dielectric material at the mating interface (e.g., according to a hybrid bonding embodiment). Each group 345-a (e.g., at least the bottom semiconductor component 340-c of group 345-c) may also include a two-dimensional array of passages 370-b and associated contacts 371 along a second side (e.g., side 347) of group 345-a (e.g., semiconductor component 340-c). System 500 may also include one or more semiconductor components 380-c coupled to one or more of groups 345-a (e.g., both groups 345-a-1 and 345-a-2, as illustrated). Semiconductor component 380-c may include a two-dimensional array of contacts 382-d that engage with contacts 371 of pathways 370-b (e.g., semiconductor components 340-c-1 and 340-c-3). Semiconductor component 380-c may also include contacts 381-d coupled to contacts 382-d via redistribution layers 520. The redistribution layers 520 may support coupling of contacts 382-d to a relatively small number of contacts 381-d, which may facilitate relatively large interconnects at interfaces of system 500 (e.g., package interfaces according to package pitch). In some embodiments, the redistribution layers 520 may include or be connected to decoupling capacitors, which may improve the uniformity of power supplied through contacts 382-d (e.g., reduce noise, reduce jitter).

[0080] In some embodiments, semiconductor component 340-d may further include (a plurality of) redistribution layers 550, which may switch between a first number of vias 370-c (e.g., a first number of vias 370-b, a first number of contacts 371) and a second number of vias 370-d (e.g., a second number of contacts 372). For example, vias 370-b and 370-c may be formed and bonded according to a first manufacturing technique that supports relatively fine pitch TSVs and hybrid bonding techniques. By implementing a relatively low number of vias 370-d (e.g., lower than vias 370-b and 370-c), the interface between group 345-a and semiconductor component 305-c may have relatively loose tolerances or relatively large interconnects or both, which may facilitate integration of group 345-a and semiconductor component 305-c. In some instances, the redistribution layers 550 can be configured for (e.g., modified for) semiconductor components 305-c of different designs, which provides flexibility for implementing standardized semiconductor components 340-c using different designs of semiconductor components 305-c.

[0081] In some instances, the bonding of group 345-a to semiconductor component 305-c can also be performed according to front-to-front bonding (e.g., bonding the front sides of semiconductor components 340-d-1 and 340-d-2 to the front side of semiconductor component 305-c). By bonding to the front side of semiconductor component 305-c and, in some instances, the front side of semiconductor component 340-d, interconnects can be supported using relatively fine pitches without implementing fine pitch TSVs (e.g., through-paths to the semiconductor substrate of semiconductor component 305-c) at semiconductor component 305-c.

[0082] Therefore, according to these and other examples, semiconductor systems (e.g., system 300, system 500, and other configurations) may have a two-dimensional pattern of power delivery conductors (e.g., pathways 370) through semiconductor components 340 of group 345, thereby providing a more distributed power delivery to logic components (e.g., semiconductor component 305, processing system 310) associated with group 345. Paths 370 may bypass stacked circuit systems (e.g., memory bank 350 and other circuit systems) and can therefore be allocated for providing power to logic components. Such techniques can be combined with redistribution components (e.g., semiconductor component 380, redistribution layers 520, redistribution layers 550) to switch between relatively few interconnects and relatively many interconnects at various layers or interfaces of the semiconductor system. Therefore, according to these and other examples, power delivery can be distributed through semiconductor component 340, thereby improving power distribution in the LoT configuration by reducing the lateral distance of the distributed components used to deliver power to logic components and reducing associated losses and distribution complexity.

[0083] Figure 6 The illustration describes a flowchart of a method 600 supporting through-power delivery to a top-level logic semiconductor system, based on examples disclosed herein. Operation of method 600 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0084] At 605, the method may include joining a first semiconductor component (e.g., semiconductor component 305) to the set of one or more second semiconductor components (e.g., set 345) along a first side of one or more second semiconductor components (e.g., several semiconductor components 340). The first semiconductor component may include one or more processors of a processing system (e.g., processing system 310), and the set of one or more second semiconductor components may include one or more memory arrays (e.g., array 355) accessible by one or more processors and an array of two-dimensional contacts (e.g., contacts 371) along a second side of the set of one or more second semiconductor components, the contacts being coupled to and configured to provide power for the operation of one or more processors.

[0085] In some instances, the apparatus (e.g., a manufacturing system) described herein may perform one or more methods, such as method 600. The apparatus may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of a manufacturing system) or any combination thereof for performing aspects of this disclosure:

[0086] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operation, features, circuitry, logic, components, or instructions, or any combination thereof, for engaging a first semiconductor component (e.g., semiconductor component 305) with the group of one or more second semiconductor components (e.g., group 345) along a first side (e.g., side 346) of a group (e.g., group 345) of one or more second semiconductor components (e.g., several semiconductor components 340). In some instances, the first semiconductor component may include one or more processors of a processing system (e.g., processing system 310), and the group of one or more second semiconductor components may include: one or more memory arrays (e.g., array 355) accessible by the one or more processors; and an array of two-dimensional contacts (e.g., contacts 371) along a second side (e.g., side 347) of the group of one or more second semiconductor components, the contacts being coupled to the one or more processors and configured to provide power for operation of the one or more processors.

[0087] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, wherein the two-dimensional contact array is coupled to the one or more processors via a respective conductive path through the group of one or more second semiconductor components, the respective conductive path bypassing a circuit system for accessing the one or more memory arrays.

[0088] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 2, wherein the group of one or more second semiconductor components comprises a plurality of semiconductor dies stacked together, each of the plurality of semiconductor dies comprising: a plurality of memory cells containing a respective memory array of the one or more memory arrays; and a plurality of through-substrate pathways disposed between the plurality of memory cells, wherein at least a subset of the two-dimensional contact array is coupled to the one or more processors using the plurality of through-substrate pathways of the plurality of semiconductor dies stacked together.

[0089] Aspect 4: According to the method, apparatus, or non-transitory computer-readable medium of aspect 3, each of the plurality of semiconductor dies further comprises: a plurality of second through-substrate pathways disposed between a respective memory bank logic of the plurality of memory banks and a respective memory array of the plurality of memory banks, wherein at least a second subset of the two-dimensional contact array is coupled to the one or more processors using the plurality of second through-substrate pathways of the plurality of semiconductor dies in the stack.

[0090] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4, wherein the two-dimensional contact array comprises: a first plurality of contacts associated with a power supply voltage; and a second plurality of contacts associated with a ground voltage.

[0091] Aspect 6: The method, device, or non-transitory computer-readable medium according to aspect 5, wherein the two-dimensional contact array comprises: a third plurality of contacts associated with a second power supply voltage.

[0092] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to aspect 6, wherein the power supply voltage is associated with a first voltage level and the second power supply voltage is associated with a second voltage level different from the first voltage level.

[0093] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 6 to 7, wherein the power supply voltage is associated with a first voltage regulation characteristic and the second power supply voltage is associated with a second voltage regulation characteristic different from the first voltage regulation characteristic.

[0094] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 8 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for engaging a third semiconductor component with the group of one or more second semiconductor components along a second side of the group of one or more second semiconductor components, the third semiconductor component comprising: a two-dimensional array of second contacts along a first side of the third semiconductor component coupled to the two-dimensional array of contacts along the second side of the group of one or more second semiconductor components; and a plurality of third contacts along a second side of the third semiconductor component coupled to the two-dimensional array of contacts, the number of the plurality of third contacts being less than the number of the two-dimensional array of contacts.

[0095] Aspect 10: The method, device, or non-transitory computer-readable medium according to aspect 9, wherein the two-dimensional second contact array is associated with a first pitch dimension and the plurality of third contacts are associated with a second pitch dimension greater than the first pitch dimension.

[0096] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 9 to 10, wherein engaging the first semiconductor component with the group of one or more second semiconductor components includes engaging the front side of one of the group of one or more second semiconductor components with the front side of the first semiconductor component.

[0097] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein joining the first semiconductor component with the group of one or more second semiconductor components comprises a fused dielectric material portion and a fused conductive material portion.

[0098] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 12 further includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for engaging a heat dissipation assembly with the first semiconductor assembly such that the first semiconductor assembly is between the heat dissipation assembly and the group of one or more second semiconductor assemblies.

[0099] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 13, wherein the one or more processors are associated with one or more graphics processing units (GPUs).

[0100] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 14 further comprises, for operation, features, circuitry, logic, components, or instructions, or any combination thereof, for engaging the group of one or more fourth semiconductor components with the first semiconductor component along a first side of the group of one or more fourth semiconductor components, the group of one or more fourth semiconductor components comprising: one or more second memory arrays accessible by the one or more processors; and a two-dimensional array of second contacts along a second side of the group of one or more fourth semiconductor components, the second contacts being coupled to the one or more processors and configured to provide power for operation of the one or more processors.

[0101] Figure 7 The illustration describes a flowchart of a method 700 supporting through-power delivery to a top-level logic semiconductor system, based on examples disclosed herein. Operation of method 700 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some instances, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0102] At 705, the method may include bonding a plurality of semiconductor dies (e.g., semiconductor assembly 340) together in a stack (e.g., group 345), each of the plurality of semiconductor dies including a plurality of memory cells (e.g., memory cell 350) each including a plurality of respective memory arrays (e.g., array 355) and a plurality of through-substrate pathways (e.g., pathways 370) disposed between the plurality of memory cells. In some instances, an array of two-dimensional first contacts (e.g., contact 372) is disposed on a first surface of the stack (e.g., side 346), and an array of two-dimensional second contacts (e.g., contact 371) is disposed on a second surface of the stack opposite to the first surface (e.g., side 347), at least a subset of the two-dimensional second contact array being coupled to the two-dimensional first contact array through the plurality of through-substrate pathways of each of the plurality of semiconductor dies.

[0103] In some instances, the apparatus (e.g., a manufacturing system) described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more processors to control one or more functional elements of a manufacturing system) or any combination thereof for performing aspects of this disclosure:

[0104] Aspect 16: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: bonding a plurality of semiconductor dies (e.g., semiconductor assembly 340) together in a stacked (e.g., group 345) configuration, each of the plurality of semiconductor dies comprising a plurality of memory cells (e.g., memory cells 350) each comprising a plurality of respective memory arrays (e.g., array 355) and a plurality of through-substrate pathways (e.g., pathways 370) disposed between the plurality of memory cells. In some instances, an array of two-dimensional first contacts (e.g., contacts 372) is disposed on a first surface (e.g., side 346) of the stack, and an array of two-dimensional second contacts (e.g., contacts 371) is disposed on a second surface (e.g., side 347) of the stack opposite the first surface, at least a subset of the two-dimensional second contact array being coupled to the two-dimensional first contact array via the plurality of through-substrate pathways of each of the plurality of semiconductor dies.

[0105] Aspect 17: The method, apparatus, or non-transitory computer-readable medium according to aspect 16, wherein the number of the two-dimensional first contact arrays is different from the number of the two-dimensional second contact arrays.

[0106] Aspect 18: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 16 to 17, wherein each of the plurality of semiconductor dies further comprises: a plurality of second through-substrate pathways disposed between respective memory logic of the plurality of memory banks and the plurality of respective memory arrays of the plurality of memory banks, wherein at least a second subset of the two-dimensional second contact array is coupled to the two-dimensional first contact array through the plurality of second through-substrate pathways of each of the plurality of semiconductor dies.

[0107] Aspect 19: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 16 to 18, wherein the two-dimensional first contact array is aligned with the two-dimensional second contact array via the stack.

[0108] Aspect 20: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 16 to 19 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for engaging a third semiconductor component with the stack, the third semiconductor component comprising: a two-dimensional array of third contacts along a first side of the third semiconductor component coupled to the two-dimensional array of second contacts; and a plurality of fourth contacts along a second side of the third semiconductor component coupled to the two-dimensional array of second contacts, the number of the plurality of fourth contacts being less than the number of the two-dimensional array of second contacts.

[0109] Aspect 21: The method, device, or non-transitory computer-readable medium according to aspect 20, wherein the two-dimensional second contact array is associated with a first pitch dimension and the plurality of fourth contacts are associated with a second pitch dimension greater than the first pitch dimension.

[0110] Aspect 22: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 16 to 21, wherein the plurality of semiconductor dies stacked together comprise fused dielectric material portions and fused conductive material portions.

[0111] It should be noted that the aspects described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods can be combined.

[0112] Describe a device. An overview of aspects of the device as described herein is provided below:

[0113] Aspect 23: A semiconductor system (e.g., system 300, system 500, or a portion thereof) comprising: a first semiconductor component (e.g., semiconductor component 305) including one or more processors of a processing system (e.g., processing system 310); and one or more second semiconductor components (e.g., several semiconductor components 340) coupled to the first semiconductor component along a first side (e.g., side 346) of the one or more second semiconductor components, the one or more second semiconductor components including: one or more memory arrays (e.g., several arrays 355) accessible by the one or more processors; and an array of two-dimensional contacts (e.g., contacts 371) along a second side (e.g., side 347) of the one or more second semiconductor components, the contacts being coupled to the one or more processors and configured to provide power for the operation of the one or more processors.

[0114] Aspect 24: The semiconductor system according to aspect 23, wherein the two-dimensional contact array is coupled to the one or more processors via respective conductive paths through the one or more second semiconductor components, the respective conductive paths bypassing circuitry for accessing the one or more memory arrays.

[0115] Aspect 25: A semiconductor system according to any one of aspects 23 to 24, wherein the one or more second semiconductor components comprise a plurality of semiconductor dies stacked together, each of the plurality of semiconductor dies comprising: a plurality of memory cells including a respective memory array in the one or more memory arrays; and a plurality of through-substrate pathways disposed between the plurality of memory cells, wherein at least a subset of the two-dimensional contact array is coupled to the one or more processors using the plurality of through-substrate pathways of the stacked plurality of semiconductor dies.

[0116] Aspect 26: The semiconductor system according to aspect 25, wherein each of the plurality of semiconductor dies further comprises: a plurality of second through-substrate pathways disposed between a respective memory logic of the plurality of memory banks and a respective memory array of the plurality of memory banks, wherein at least a second subset of the two-dimensional contact array is coupled to the one or more processors using the plurality of second through-substrate pathways of the stacked plurality of semiconductor dies.

[0117] Aspect 27: A semiconductor system according to any one of aspects 23 to 26, wherein the two-dimensional contact array comprises: a first plurality of contacts associated with a power supply voltage; and a second plurality of contacts associated with a ground voltage.

[0118] Aspect 28: The semiconductor system according to aspect 27, wherein the two-dimensional contact array includes: a third plurality of contacts associated with a second power supply voltage.

[0119] Aspect 29: The semiconductor system according to aspect 28, wherein: the power supply voltage is associated with a first voltage level; and the second power supply voltage is associated with a second voltage level different from the first voltage level.

[0120] Aspect 30: A semiconductor system according to any one of aspects 28 to 29, wherein: the power supply voltage is associated with a first voltage regulation characteristic; and the second power supply voltage is associated with a second voltage regulation characteristic different from the first voltage regulation characteristic.

[0121] Aspect 31: A semiconductor system according to any one of aspects 23 to 30, further comprising: a third semiconductor component coupled to the one or more second semiconductor components along a second side of the one or more second semiconductor components, the third semiconductor component comprising: a two-dimensional second contact array coupled to the two-dimensional contact array along a first side of the third semiconductor component along the second side of the one or more second semiconductor components; and a plurality of third contacts coupled to the two-dimensional second contact array along a second side of the third semiconductor component, the number of the plurality of third contacts being less than the number of the two-dimensional second contact array.

[0122] Aspect 32: The semiconductor system according to aspect 31, wherein: the two-dimensional second contact array is associated with a first pitch dimension; and the plurality of third contacts are associated with a second pitch dimension greater than the first pitch dimension.

[0123] Aspect 33: A semiconductor system according to any one of aspects 23 to 32, wherein the junction of the one or more second semiconductor components with the first semiconductor component is associated with the junction of the front side of one or more second semiconductor components with the front side of the first semiconductor component.

[0124] Aspect 34: A semiconductor system according to any one of aspects 23 to 33, wherein the one or more processors are associated with one or more graphics processing units (GPUs).

[0125] Aspect 35: A semiconductor system according to any one of aspects 23 to 34, further comprising: one or more fourth semiconductor components coupled to the first semiconductor component along a first side of the one or more fourth semiconductor components, the one or more fourth semiconductor components comprising: one or more second memory arrays accessible by the one or more processors; and a two-dimensional array of second contacts along a second side of the one or more fourth semiconductor components, the second contacts being coupled to the one or more processors and configured to provide power for the operation of the one or more processors.

[0126] Aspect 36: A semiconductor system according to any one of aspects 23 to 35, wherein the bonding of the one or more second semiconductor components with the first semiconductor component comprises the fusion of dielectric material portions and the fusion of conductive material portions.

[0127] Aspect 37: A semiconductor system according to any one of aspects 23 to 36, further comprising: a heat dissipation component, which is coupled to the first semiconductor component such that the first semiconductor component is between the heat dissipation component and the one or more second semiconductor components.

[0128] Describe a device. An overview of aspects of the device as described herein is provided below:

[0129] Aspect 38: A semiconductor system (e.g., system 300, system 500, or a portion thereof) comprising: a plurality of semiconductor dies (e.g., semiconductor components 340) stacked together (e.g., group 345), each of the plurality of semiconductor dies comprising: a plurality of memory cells (e.g., memory cells 350), each comprising a plurality of respective memory arrays (e.g., array 355); and a plurality of through-substrate pathways (e.g., pathways 370) disposed between the plurality of memory cells; a two-dimensional array of first contacts (e.g., contacts 372) disposed on a first surface (e.g., side 346) of the stack; and a two-dimensional array of second contacts (e.g., contacts 371) disposed on a second surface (e.g., side 347) of the stack opposite the first surface, at least a subset of the two-dimensional second contact array being coupled to the two-dimensional first contact array through the plurality of through-substrate pathways of each of the plurality of semiconductor dies.

[0130] Aspect 39: The semiconductor system according to aspect 38, wherein the number of the two-dimensional first contact arrays is different from the number of the two-dimensional second contact arrays.

[0131] Aspect 40: A semiconductor system according to any one of aspects 38 to 39, wherein each of the plurality of semiconductor dies further comprises: a plurality of second through-substrate pathways disposed between respective memory logic of the plurality of memory banks and the plurality of respective memory arrays of the plurality of memory banks, wherein at least a second subset of the two-dimensional second contact array is coupled to the two-dimensional first contact array through the plurality of second through-substrate pathways of each of the plurality of semiconductor dies.

[0132] Aspect 41: A semiconductor system according to any one of aspects 38 to 40, wherein the two-dimensional first contact array is aligned with the two-dimensional second contact array via the stack.

[0133] Aspect 42: A semiconductor system according to any one of aspects 38 to 41, further comprising: a third semiconductor component coupled to the stack, the third semiconductor component comprising: a two-dimensional third contact array coupled to the two-dimensional second contact array along a first side of the third semiconductor component; and a plurality of fourth contacts coupled to the two-dimensional second contact array along a second side of the third semiconductor component, the number of the plurality of fourth contacts being less than the number of the two-dimensional second contact array.

[0134] Aspect 43: The semiconductor system according to aspect 42, wherein: the two-dimensional second contact array is associated with a first pitch dimension; and the plurality of fourth contacts are associated with a second pitch dimension greater than the first pitch dimension.

[0135] Aspect 44: A semiconductor system according to any one of aspects 38 to 43, wherein the bonding between the plurality of semiconductor dies comprises the fusion of dielectric material portions and the fusion of conductive material portions.

[0136] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some figures may illustrate signals as single signals; however, the signals may represent signal buses, which may have various bit widths.

[0137] The terms "electronic connection," "conductive contact," "connection," and "coupling" refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (e.g., conductive contact, connection, coupling) if any electrical path (e.g., conductive path) exists between them that can readily support the flow of signals (e.g., charge, current, voltage) between them. The conductive path between components that are electronically connected (e.g., conductive contact, connection, coupling) can be open or closed based on the operation of the device containing the connected component. The conductive path between connected components can be a direct conductive path between components or an indirect conductive path that includes intermediate components (e.g., switches, transistors, or other components). In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0138] The term "isolation" can refer to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, when a switch positioned between components is open, the two components separated by the switch are isolated from each other. When one component isolates two components, that component can initiate a change that prevents signals from flowing between other components using previously permitted conductive paths.

[0139] The term "coupling" (e.g., "electrical coupling") can refer to a condition that shifts from an open-circuit relationship between components (where signals cannot currently be transmitted between components (e.g., via a conductive path)) to a closed-circuit relationship between components (where signals can be transmitted between components (e.g., via a conductive path)). When one component (e.g., a controller) couples other components together, that component can initiate a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0140] The terms "layer" and "level" can refer to an organization of geometry (e.g., relative to a substrate) (e.g., a layer, a sheet). Each layer or level can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or level can be a three-dimensional structure, where two dimensions are greater than the third dimension, such as a thin film. A layer or level can contain different elements, components, or materials. In some instances, a layer or level can consist of two or more sublayers or sublevels.

[0141] The switching components (e.g., transistors) discussed herein may be field-effect transistors (FETs) and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and drain, and a gate (e.g., a gate terminal). The conductivity of the channel can be controlled (e.g., modulated) by applying a voltage to the gate, which in some instances may cause the channel to become conductive. The switching components may be examples of n-type FETs or p-type FETs.

[0142] The descriptions set forth herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be practiced or that are within the scope of the claims. Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0143] In the accompanying drawings, similar components or features may have the same reference label. Similar components can be distinguished by adding one or more hyphens after the reference label and additional labels to differentiate them. When the first reference label is used only in the specification, the description applies to any of the similar components having the same first reference label, regardless of any additional reference labels.

[0144] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored as one or more instructions (e.g., code) on or transmitted via a computer-readable medium. Due to the nature of software, the functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0145] The illustrative blocks and modules described herein may be implemented or executed using one or more processors designed to perform the functions described herein, such as DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. The processor may be an instance of a microprocessor, controller, microcontroller, state machine, or other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0146] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0147] As used herein (included in the claims), the article “a” preceding a noun is open-ended and should be understood to refer to “at least one” or “one or more” of those nouns. Therefore, the terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. For example, if a claim refers to a “component” performing one or more functions, then each of the individual functions can be performed by a single component or any combination of components. Therefore, the term “component” having a characteristic or performing a function can refer to “at least one of one or more components” having a particular characteristic or performing a particular function. Subsequent references to a component introduced by the article “a” using the term “the” or “said” can refer to any or all of the one or more components. For example, a component introduced by the article “a” can be understood to mean “one or more components,” and subsequent references to “component” in the claims can be understood to be equivalent to references to “at least one of one or more components.” Similarly, subsequent references to a component introduced as "one or more components" using the term "the" or "said" may refer to any or all of the one or more components. For example, a subsequent reference to "one or more components" in a claim may be understood as equivalent to a reference to "at least one of the one or more components."

[0148] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media or combination of media that can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a computer or one or more processors.

[0149] Description and accompanying drawings are provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the techniques disclosed herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor system comprising: A first semiconductor component, which includes one or more processors of a processing system; and One or more second semiconductor components are coupled to the first semiconductor component along a first side of the one or more second semiconductor components, the one or more second semiconductor components comprising: One or more memory arrays that can be accessed by the one or more processors; and A two-dimensional array of contacts along a second side of the one or more second semiconductor components, the contacts being coupled to the one or more processors and configured to provide power for the operation of the one or more processors.

2. The semiconductor system of claim 1, wherein the two-dimensional contact array is coupled to the one or more processors via respective conductive paths through the one or more second semiconductor components, the respective conductive paths bypassing circuitry for accessing the one or more memory arrays.

3. The semiconductor system of claim 1, wherein the one or more second semiconductor components comprise a plurality of semiconductor dies stacked together, each of the plurality of semiconductor dies comprising: Multiple storage units, including a corresponding memory array in one or more memory arrays; and Multiple through-substrate pathways are arranged between the multiple memory cells. At least a subset of the two-dimensional contact array is coupled to the one or more processors using the plurality of through-substrate pathways of the plurality of semiconductor dies in the stack.

4. The semiconductor system of claim 3, wherein each of the plurality of semiconductor dies further comprises: Multiple second through-substrate pathways are arranged between the respective memory logic of the multiple memory banks and the respective memory arrays of the multiple memory banks. At least a second subset of the two-dimensional contact array is coupled to the one or more processors using the multiple second through-substrate pathways of the multiple semiconductor dies in the stack.

5. The semiconductor system of claim 1, wherein the two-dimensional contact array comprises: The first plurality of contacts are associated with the power supply voltage; and The second set of contacts is associated with the ground voltage.

6. The semiconductor system of claim 5, wherein the two-dimensional contact array comprises: The third set of contacts is associated with the second power supply voltage.

7. The semiconductor system according to claim 6, wherein: The power supply voltage is associated with a first voltage level; and The second power supply voltage is associated with a second voltage level that is different from the first voltage level.

8. The semiconductor system according to claim 6, wherein: The power supply voltage is associated with a first voltage regulation characteristic; and The second power supply voltage is associated with a second voltage regulation characteristic that is different from the first voltage regulation characteristic.

9. The semiconductor system of claim 1, further comprising: A third semiconductor component is coupled to the one or more second semiconductor components along the second side of the first or more second semiconductor components, the third semiconductor component comprising: A two-dimensional second contact array along a first side of the third semiconductor component, coupled to the two-dimensional contact array along the second side of the one or more second semiconductor components; and A plurality of third contacts along the second side of the third semiconductor component are coupled to the two-dimensional second contact array, the number of the plurality of third contacts being less than the number of the two-dimensional second contact array.

10. The semiconductor system according to claim 9, wherein: The two-dimensional second contact array is associated with the first pitch dimension; and The plurality of third contacts are associated with a second pitch dimension that is larger than the first pitch dimension.

11. The semiconductor system of claim 1, wherein the junction of the one or more second semiconductor components with the first semiconductor component is associated with a junction between the front side of one or more of the second semiconductor components and the front side of the first semiconductor component.

12. The semiconductor system of claim 1, wherein the one or more processors are associated with one or more graphics processing units (GPUs).

13. The semiconductor system of claim 1, further comprising: One or more fourth semiconductor components are coupled to the first semiconductor component along a first side of the one or more fourth semiconductor components, the one or more fourth semiconductor components comprising: One or more second memory arrays, which can be accessed by the one or more processors; and A two-dimensional array of second contacts along a second side of the one or more fourth semiconductor components, the second contacts being coupled to the one or more processors and configured to provide power for the operation of the one or more processors.

14. The semiconductor system of claim 1, wherein the bonding of the one or more second semiconductor components to the first semiconductor component comprises the fusion of dielectric material portions and the fusion of conductive material portions.

15. The semiconductor system of claim 1, further comprising: A heat dissipation component, which is coupled to the first semiconductor component such that the first semiconductor component is between the heat dissipation component and the one or more second semiconductor components.

16. A semiconductor system comprising: A plurality of semiconductor dies are stacked together, each of the plurality of semiconductor dies comprising: Multiple memory banks, each comprising multiple corresponding memory arrays; and Multiple through-substrate pathways are arranged between the multiple memory cells; A two-dimensional first contact array is arranged on the first surface of the stack; and A two-dimensional second contact array is disposed on the stacked second surface opposite to the first surface, and at least a subset of the two-dimensional second contact array is coupled to the two-dimensional first contact array through the plurality of through-substrate pathways of each of the plurality of semiconductor dies.

17. The semiconductor system of claim 16, wherein the number of the two-dimensional first contact arrays is different from the number of the two-dimensional second contact arrays.

18. The semiconductor system of claim 16, wherein each of the plurality of semiconductor dies further comprises: Multiple second through-substrate pathways are arranged between the respective memory logic of the multiple memory banks and the multiple respective memory arrays of the multiple memory banks. At least a second subset of the two-dimensional second contact array is coupled to the two-dimensional first contact array through the plurality of second through-substrate pathways of each of the plurality of semiconductor dies.

19. The semiconductor system of claim 16, wherein the two-dimensional first contact array is aligned with the two-dimensional second contact array via the stack.

20. The semiconductor system of claim 16, further comprising: A third semiconductor component, which is bonded to the stack, the third semiconductor component comprising: A two-dimensional third contact array along a first side of the third semiconductor component, coupled to the two-dimensional second contact array; and A plurality of fourth contacts along the second side of the third semiconductor component are coupled to the two-dimensional second contact array, the number of the plurality of fourth contacts being less than the number of the two-dimensional second contact array.

21. The semiconductor system of claim 20, wherein: The two-dimensional second contact array is associated with the first pitch dimension; and The plurality of fourth contacts are associated with a second pitch dimension that is larger than the first pitch dimension.

22. The semiconductor system of claim 16, wherein the bonding between the plurality of semiconductor dies comprises the fusion of dielectric material portions and the fusion of conductive material portions.

23. A method of forming a semiconductor system, comprising: A first semiconductor component is coupled to the group of one or more second semiconductor components along a first side of the group of one or more second semiconductor components, the first semiconductor component including one or more processors of a processing system, and the group of one or more second semiconductor components including: One or more memory arrays accessible by the one or more processors; and A two-dimensional array of contacts along the second side of the group of one or more second semiconductor components, the contacts being coupled to the one or more processors and configured to provide power for the operation of the one or more processors.

24. The method of claim 23, further comprising: A third semiconductor component is coupled to the group of one or more second semiconductor components along the second side of the group of one or more second semiconductor components, the third semiconductor component comprising: A two-dimensional second contact array along a first side of the third semiconductor component, coupled to the two-dimensional contact array along the second side of the group of one or more second semiconductor components; and A plurality of third contacts along the second side of the third semiconductor component are coupled to the two-dimensional second contact array, the number of the plurality of third contacts being less than the number of the two-dimensional second contact array.

25. The method of claim 24, wherein joining the first semiconductor component to the group of one or more second semiconductor components includes joining the front side of one of the group of one or more second semiconductor components to the front side of the first semiconductor component.

26. The method of claim 23, further comprising: The group of one or more fourth semiconductor components is coupled to the first semiconductor component along a first side of the group of one or more fourth semiconductor components, the group of one or more fourth semiconductor components comprising: One or more second memory arrays, which can be accessed by the one or more processors; and A two-dimensional array of second contacts along the second side of the group of one or more fourth semiconductor components, the second contacts being coupled to the one or more processors and configured to provide power for the operation of the one or more processors.

27. A method of forming a semiconductor system, comprising: Multiple semiconductor dies are stacked together, each of the multiple semiconductor dies comprising: Multiple memory banks, each comprising multiple corresponding memory arrays; and Multiple through-substrate pathways are arranged between the multiple memory cells. A two-dimensional first contact array is disposed on a first surface of the stack, and a two-dimensional second contact array is disposed on a second surface of the stack opposite to the first surface. At least a subset of the two-dimensional second contact array is coupled to the two-dimensional first contact array through the plurality of through-substrate pathways of each of the plurality of semiconductor dies.

28. The method of claim 27, wherein the number of the two-dimensional first contact arrays is different from the number of the two-dimensional second contact arrays.

29. The method of claim 27, wherein each of the plurality of semiconductor dies further comprises: Multiple second through-substrate pathways are arranged between the respective memory logic of the multiple memory banks and the multiple respective memory arrays of the multiple memory banks. At least a second subset of the two-dimensional second contact array is coupled to the two-dimensional first contact array through the plurality of second through-substrate pathways of each of the plurality of semiconductor dies.

30. The method of claim 27, further comprising: A third semiconductor component is coupled to the stack, the third semiconductor component comprising: A two-dimensional third contact array along a first side of the third semiconductor component, coupled to the two-dimensional second contact array; and A plurality of fourth contacts along the second side of the third semiconductor component are coupled to the two-dimensional second contact array, the number of the plurality of fourth contacts being less than the number of the two-dimensional second contact array.

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