Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the steps of providing a substrate; an interconnection line is formed on the substrate and used for being electrically connected with the interconnection structure; forming a growth layer covering the top surface of the interconnection line, wherein the material of the growth layer is the same as that of the interconnection structure; and forming an interconnection structure on the growth layer, wherein the interconnection structure is electrically connected with the interconnection line through the growth layer. The performance of the semiconductor structure can be guaranteed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the development of integrated circuit manufacturing to ultra large scale integration (ULSI), the circuit density inside is getting larger and larger, and the number of components contained is increasing, so that the surface of the wafer cannot provide enough area to manufacture the required interconnects. In order to meet the increased interconnect requirements after the shrinkage of components, the design of multi-layer metal interconnects realized by vias of two or more layers has become a necessary method for ULSI technology.

[0003] However, as the semiconductor process node continues to shrink, the critical dimension (CD) of the via in the semiconductor device also decreases accordingly, and when filling tungsten metal in the via, voids are easily generated, which seriously affects the electrical characteristics of the manufactured interconnect structure. In addition, before filling the tungsten metal material in the via, an adhesion layer is usually deposited on the bottom and sidewall of the via to improve the adhesion between the dielectric layer and the subsequently formed tungsten metal interconnect, and to act as a barrier layer between the dielectric layer and the subsequently formed tungsten metal interconnect to prevent tungsten metal from diffusing into the dielectric layer. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which is beneficial to guarantee the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate; an interconnect line on the substrate, configured to be electrically connected with an interconnect structure; a growth layer covering a top surface of the interconnect line, the material of the growth layer being the same as that of the interconnect structure; and the interconnect structure on the growth layer and in contact with the growth layer, the interconnect structure being electrically connected with the interconnect line through the growth layer.

[0006] Optionally, a channel structure and a gate structure crossing the channel structure are formed on the substrate, and source / drain doped layers in contact with the channel structure are formed on both sides of the gate structure; the interconnect line is on the source / drain doped layers and is electrically connected with the source / drain doped layers.

[0007] Optionally, the interconnect line is an interconnect plug extending along the extension direction of the gate structure and covering multiple source / drain doped layers; and the interconnect structure is an interconnect via plug.

[0008] Optionally, the semiconductor structure further comprises: a first dielectric layer covering sidewalls of the interconnection line and exposing a top surface of the interconnection line; and a second dielectric layer on the first dielectric layer, the second dielectric layer covering the growth layer and sidewalls of the interconnection structure, the interconnection structure penetrating through the second dielectric layer and contacting the second dielectric layer.

[0009] Optionally, the material of the interconnection line comprises one or more of Co, Ti, TiN, Ru and Mo.

[0010] Optionally, the material of the growth layer comprises W or Cu.

[0011] Optionally, the thickness of the growth layer is to

[0012] Correspondingly, the embodiment of the present application further provides a forming method of a semiconductor structure, comprising: providing a substrate; forming an interconnection line on the substrate for electrically connecting with an interconnection structure; forming a growth layer covering a top surface of the interconnection line, the material of the growth layer being the same as that of the interconnection structure; and forming the interconnection structure on the growth layer, the interconnection structure being electrically connected with the interconnection line through the growth layer.

[0013] Optionally, in the step of providing the substrate, a channel structure and a gate structure crossing the channel structure are formed on the substrate, and source-drain doped layers contacting the channel structure are formed on the substrate on both sides of the gate structure; and in the step of forming the interconnection line, the interconnection line is located on and electrically connected with a source-drain interconnection layer.

[0014] Optionally, in the step of forming the interconnection line, the interconnection line is an interconnection plug extending along an extension direction of the gate structure and covering a plurality of source-drain doped layers; and in the step of forming the interconnection structure on the growth layer, the interconnection structure is an interconnection via plug.

[0015] Optionally, the growth layer covering the top surface of the interconnection line is formed by using a selective growth process.

[0016] Optionally, the step of forming the interconnection line on the substrate comprises: forming a first dielectric layer on the substrate; patterning the first dielectric layer to form a recess; and forming the interconnection line in the recess.

[0017] Optionally, the step of forming the interconnection structure on the growth layer and electrically connecting the interconnection structure with the interconnection line through the growth layer comprises: forming a second dielectric layer covering the growth layer on the first dielectric layer; patterning the second dielectric layer to form a via exposing the growth layer; and forming the interconnection structure in the via, the interconnection structure contacting the second dielectric layer.

[0018] Optionally, the step of forming the interconnection structure in the via hole comprises: forming an interconnection material layer filling the via hole and covering the second dielectric layer; planarizing the interconnection material layer to remove the interconnection material layer higher than the second dielectric layer, and leaving the interconnection material layer in the via hole as the interconnection structure.

[0019] Optionally, the interconnection structure is formed on the growth layer by using a selective growth process.

[0020] Optionally, in the step of forming the interconnection line on the substrate, the material of the interconnection line comprises one or more of Co, Ti, TiN, Ru and Mo.

[0021] Optionally, in the step of forming the growth layer covering the top surface of the interconnection line, the material of the growth layer comprises W or Cu.

[0022] Optionally, in the step of forming the growth layer covering the top surface of the interconnection line, the thickness of the growth layer is to

[0023] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0024] In the semiconductor structure provided by the embodiment of the present application, the growth layer covers the top surface of the interconnection line, the material of the growth layer is the same as that of the interconnection structure, the interconnection structure is located on the growth layer and in contact with the growth layer, and the interconnection structure is electrically connected with the interconnection line through the growth layer; in the embodiment of the present application, the interconnection structure is electrically connected with the interconnection line through the growth layer, so that the interconnection structure can be formed based on the growth layer when the interconnection structure is formed, the material of the growth layer is the same as that of the interconnection structure, so that the interconnection structure has a good formation basis, and it is easy to form an interconnection structure with good film layer quality on the growth layer, which is conducive to guaranteeing the electrical connection performance of the interconnection structure and the interconnection line, thereby being conducive to guaranteeing the performance of the semiconductor structure.

[0025] In the forming method provided by the embodiment of the present application, the growth layer covering the top surface of the interconnection line is formed, the material of the growth layer is the same as that of the interconnection structure, the interconnection structure is formed on the growth layer, and the interconnection structure is electrically connected with the interconnection line through the growth layer; in the embodiment of the present application, the interconnection structure is electrically connected with the interconnection line through the growth layer, so that the interconnection structure can be formed based on the growth layer when the interconnection structure is formed, the material of the growth layer is the same as that of the interconnection structure, so that the interconnection structure has a good formation basis, and it is easy to form an interconnection structure with good film layer quality on the growth layer, which is conducive to guaranteeing the electrical connection performance of the interconnection structure and the interconnection line, thereby being conducive to guaranteeing the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1-2 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0027] Figures 3-4is a structure diagram of an embodiment of a semiconductor structure of the present application;

[0028] Figures 5-18 is a structure diagram of each step in an embodiment of a forming method of a semiconductor structure of the present application. DETAILED DESCRIPTION

[0029] At present, the performance of semiconductor structures is difficult to guarantee. The reasons why the performance of semiconductor structures is difficult to guarantee are analyzed.

[0030] Figures 1-2 is a structure diagram of an embodiment of a semiconductor structure of the present application.

[0031] REFERENCE Figure 1 The semiconductor structure comprises: an interconnection line 10; a dielectric layer 30 covering the interconnection line 10; an interconnection structure 20 located on the interconnection line 10 and penetrating the dielectric layer 30 to electrically connect the interconnection line 10; and an adhesion layer 40 located between the interconnection structure 20 and the dielectric layer 30 and between the interconnection structure 20 and the interconnection line 10.

[0032] The interconnection structure 20 is usually formed by a chemical vapor deposition (CVD) process. In order to avoid the interconnection structure 20 formed from the dielectric layer 30, the adhesion layer 40 needs to be formed between the interconnection structure 20 and the dielectric layer 30. Due to the existence of the adhesion layer 40, the contact resistance between the interconnection structure 20 and the interconnection line 10 is high, which affects the performance of the semiconductor structure.

[0033] REFERENCE Figure 2 If the adhesion layer 40 is not formed, a growth process needs to be used to form the interconnection structure 20. However, the growth conditions of the interconnection structure 20 formed by the growth process are harsh, the film quality of the interconnection structure 20 is difficult to guarantee, and the interconnection structure 20 is easy to form a cavity, which causes high resistance or open circuit, thereby affecting the performance of the semiconductor structure.

[0034] In order to solve the above technical problems, an embodiment of the present application provides a semiconductor structure, which comprises: a substrate; an interconnection line located on the substrate and used to electrically connect an interconnection structure; a growth layer covering a top surface of the interconnection line, the material of the growth layer being the same as that of the interconnection structure; and the interconnection structure located on the growth layer and in contact with the growth layer, the interconnection structure being electrically connected to the interconnection line through the growth layer.

[0035] In the embodiment of the present application, the interconnection structure is electrically connected to the interconnection line through the growth layer, so that the interconnection structure can be formed based on the growth layer when the interconnection structure is formed. The material of the growth layer is the same as that of the interconnection structure, so that the interconnection structure has a good formation basis and is easy to form a film layer with good quality on the growth layer, which is beneficial to guarantee the electrical connection performance of the interconnection structure and the interconnection line, thereby being beneficial to guarantee the performance of the semiconductor structure.

[0036] In order to make the above objectives, characteristics and advantages of the present application more apparent, specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0037] Figures 3-4 is a structural schematic diagram of an embodiment of the semiconductor structure of the present application, Figure 3 is a sectional view of the semiconductor structure along the extending direction of the gate structure, Figure 4 is a sectional view of the semiconductor structure along the direction perpendicular to the extending direction of the gate structure.

[0038] With reference to Figure 3 and Figure 4 , the semiconductor structure comprises: a substrate 100; an interconnection line 200 on the substrate 100, used for electrical connection with an interconnection structure; a growth layer 300 covering the top surface of the interconnection line 200, the material of the growth layer 300 being the same as that of the interconnection structure; and an interconnection structure 400 on the growth layer 300 and in contact with the growth layer 300, the interconnection structure 400 being electrically connected with the interconnection line 200 through the growth layer 300.

[0039] The substrate 100 provides a process operation basis for the forming process of the semiconductor structure.

[0040] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate can be a material suitable for the process requirement or easy for integration.

[0041] In this embodiment, the substrate 100 is formed with a channel structure 110 and a gate structure 130 across the channel structure 110, and the substrate 100 on both sides of the gate structure 130 is formed with source-drain doped layers 120 in contact with the channel structure 110.

[0042] The channel structure 110 is used as a channel of a transistor.

[0043] In this embodiment, the material of the channel structure 110 includes silicon, germanium, silicon germanium or a Ⅲ-Ⅴ semiconductor material. As an example, the material of the channel structure 110 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0044] The gate structure 130 is used to control the opening and closing of the channel of the transistor.

[0045] In this embodiment, the gate structure 130 comprises a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

[0046] The gate dielectric layer is used to isolate the gate electrode layer from the channel structure 110.

[0047] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0048] It should be noted that the gate dielectric layer can also include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 220. Specifically, the material of the gate oxide layer can be silicon oxide.

[0049] In this embodiment, the gate structure 130 is a metal gate structure, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0050] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical property of the metal gate structure.

[0051] In other embodiments, the gate electrode layer can also only include the work function layer.

[0052] In other embodiments, according to the process requirement, the gate structure can also be a polysilicon gate structure.

[0053] The source-drain doped layer 120 is used as a source region or a drain region of the transistor. Specifically, the doping type of the source-drain doped layer 120 is the same as the channel conduction type of the corresponding transistor.

[0054] The doping type of the source-drain doped layer 120 is the same as the channel conduction type of the corresponding transistor. Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source-drain doped layer 120 are N-type ions, and the N-type ions include P ions, As ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doping ions in the source-drain doped layer 120 are P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0055] The interconnection line 200 is used to be electrically connected with the interconnection structure 400.

[0056] In this embodiment, the interconnection line 200 is a metal material, which can play a good conductive role.

[0057] In the embodiment, the interconnection line 200 is located on the source-drain doped layer 120 and is electrically connected with the source-drain doped layer 120.

[0058] The interconnection line 200 is located on the source-drain doped layer 120 and is electrically connected with the source-drain doped layer 120, so as to realize the electrical connection between the source-drain doped layer 120 and the outside through the interconnection line 200.

[0059] In the embodiment, the material of the interconnection line 200 includes one or more of Co, Ti, TiN, Ru and Mo.

[0060] Generally, one or more of Co, Ti, TiN, Ru and Mo is used as the interconnection line 200 connected with the source-drain doped layer 120, which has good electrical connection performance.

[0061] Specifically, in the embodiment, the interconnection line 200 is an interconnection plug extending along the extension direction of the gate structure 130 and covering a plurality of source-drain doped layers 120.

[0062] As the interconnection plug, the interconnection line 200 not only electrically connects the source-drain doped layer 120 with the outside, but also electrically connects the source-drain doped layers 120 with each other.

[0063] The growth layer 300 is used to provide a good formation basis for the formation of the interconnection structure 400.

[0064] In the embodiment, the interconnection structure 400 is electrically connected with the interconnection line 200 through the growth layer 300, so that the interconnection structure 400 can be formed based on the growth layer 300. The material of the growth layer 300 is the same as that of the interconnection structure 400, so that the interconnection structure 400 has a good formation basis, and it is easy to form the interconnection structure 400 with good film layer quality on the growth layer 300, which is conducive to guaranteeing the electrical connection performance of the interconnection structure 400 and the interconnection line 200, thereby being conducive to guaranteeing the performance of the semiconductor structure.

[0065] In the embodiment, the material of the growth layer 300 includes W or Cu.

[0066] The W or Cu material can further provide a better formation basis for the formation of the interconnection structure 400.

[0067] Specifically, in the embodiment, in the semiconductor process, the selective growth process is used to form the interconnection structure 400 electrically connected with the interconnection line 200. It is difficult to grow directly on the interconnection line 200 (especially Co, Ti, TiN, Ru or Mo material), but it is easy to grow on the growth layer 300 (especially W or Cu material) with the same material as the interconnection structure 400, and the interconnection structure 400 with good film layer quality can be obtained.

[0068] It should be noted that in the embodiment, the thickness of the growth layer 300 should not be too large or too small. If the thickness of the growth layer 300 is too large, it is easy to cause unnecessary material waste, and also easy to cause the height of the semiconductor structure in the longitudinal direction to be too large, and it is difficult to obtain better integration requirements. If the thickness of the growth layer 300 is too small, the growth layer 300 is difficult to provide a good formation basis for the formation of the interconnection structure 400, so that it is difficult to obtain a better interconnection structure 400 film. Therefore, in the embodiment, the thickness of the growth layer 300 is to

[0069] The interconnection structure 400 is used to be electrically connected with the interconnection line 200 through the growth layer 300, so as to realize the electrical connection between the interconnection line 200 and the outside through the interconnection structure 400.

[0070] Specifically, in the embodiment, the interconnection structure 400 is an interconnection via plug, which realizes the electrical connection between the interconnection plug on the source-drain doped layer 120 and the outside.

[0071] In the embodiment, the semiconductor structure further includes a first dielectric layer 600 covering the sidewall of the interconnection line 200 and exposing the top surface of the interconnection line 200.

[0072] The first dielectric layer 600 is used as a process platform for forming the interconnection line 200, and the first dielectric layer 600 exposes the top surface of the interconnection line 200 to provide a spatial position for the formation of the growth layer 300.

[0073] In the embodiment, the material of the first dielectric layer 600 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0074] In the embodiment, the semiconductor structure further includes a second dielectric layer 500 located on the first dielectric layer 600, the second dielectric layer 500 covering the growth layer 300 and the sidewall of the interconnection structure 400, and the interconnection structure 400 penetrating through the second dielectric layer 500 and being in contact with the second dielectric layer 500.

[0075] The second dielectric layer 500 is used as a process platform for forming the interconnection structure 400.

[0076] Specifically, in the embodiment, the interconnection structure 400 penetrates through the second dielectric layer 500 and is in contact with the second dielectric layer 500, that is, there is no need to form an adhesion layer between the interconnection structure 400 and the second dielectric layer 500, that is, the interconnection structure 400 also does not have an adhesion layer at the bottom, so that the contact resistance between the interconnection structure 400 and the growth layer 300 is small, thereby facilitating the electrical connection performance between the interconnection structure 400 and the interconnection line 200.

[0077] In this embodiment, the material of the second dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0078] Figures 5-18 is a structural schematic diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present application.

[0079] In combination with reference to Figure 5 and Figure 6 , Figure 5 is a sectional view of the semiconductor structure along the extending direction of the gate structure, Figure 6 is a sectional view of the semiconductor structure along the direction perpendicular to the extending direction of the gate structure, providing a substrate 100.

[0080] The substrate 100 provides a process operation basis for the forming process of the semiconductor structure.

[0081] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate can be a material suitable for the process needs or easy to integrate.

[0082] In the step of providing the substrate 100, a channel structure 110 is formed on the substrate 100, and a gate structure 130 is formed across the channel structure 110, and source-drain doped layers 120 are formed on the substrate 100 on both sides of the gate structure 130 and in contact with the channel structure 110.

[0083] The channel structure 110 is used as the channel of the transistor.

[0084] In this embodiment, the material of the channel structure 110 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the channel structure 110 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0085] The gate structure 130 is used to control the opening and closing of the channel of the transistor.

[0086] In this embodiment, the gate structure 130 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

[0087] The gate dielectric layer is used to isolate the gate electrode layer from the channel structure 110.

[0088] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0089] It should be noted that the gate dielectric layer can also include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 220. Specifically, the material of the gate oxide layer can be silicon oxide.

[0090] In this embodiment, the gate structure 130 is a metal gate structure, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0091] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical property of the metal gate structure.

[0092] In other embodiments, the gate electrode layer can also only include the work function layer.

[0093] In other embodiments, the gate structure can also be a polysilicon gate structure according to process requirements.

[0094] The source-drain doped layer 120 is used as a source region or a drain region of the transistor. Specifically, the doping type of the source-drain doped layer 120 is the same as the channel conduction type of the corresponding transistor.

[0095] The doping type of the source-drain doped layer 120 is the same as the channel conduction type of the corresponding transistor. Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source-drain doped layer 120 are N-type ions, and the N-type ions include P ions, As ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doping ions in the source-drain doped layer 120 are P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0096] Reference is made to Figure 7 and Figure 8 , Figure 7 is a sectional view of the semiconductor structure along the extension direction of the gate structure, Figure 8is a sectional view of the semiconductor structure along a direction perpendicular to the extending direction of the gate structure, and the interconnection line 200 is formed on the substrate 100 and used for electrical connection with the interconnection structure.

[0097] Specifically, the interconnection structure electrically connected with the interconnection line 200 will be formed on the interconnection line 200 subsequently, and the material of the subsequently formed interconnection structure is preset in the semiconductor process.

[0098] The interconnection line 200 is used for electrical connection with the interconnection structure 400.

[0099] In the embodiment, the interconnection line 200 is of metal material in the step of forming the interconnection line 200, and can play a better conductive role.

[0100] In the embodiment, the interconnection line 200 is located on the source-drain doped layer 120 and electrically connected with the source-drain doped layer 120 in the step of forming the interconnection line 200.

[0101] The interconnection line 200 is located on the source-drain doped layer 120 and electrically connected with the source-drain doped layer 120, and is used for electrical connection between the source-drain doped layer 120 and the outside through the interconnection line 200.

[0102] In the embodiment, the material of the interconnection line 200 includes one or more of Co, Ti, TiN, Ru and Mo in the step of forming the interconnection line 200 on the substrate 100.

[0103] Generally, one or more of Co, Ti, TiN, Ru and Mo is used as the interconnection line 200 connected with the source-drain doped layer 120, and has a better electrical connection performance.

[0104] Specifically, in the embodiment, the interconnection line 200 is an interconnection plug extending along the extending direction of the gate structure 130 and covering multiple source-drain doped layers 120 in the step of forming the interconnection line 200.

[0105] As the interconnection plug, the interconnection line 200 not only electrically connects the source-drain doped layer 120 with the outside, but also electrically connects the source-drain doped layers 120 with each other.

[0106] Specifically, in the embodiment, the step of forming the interconnection line 200 on the substrate 100 includes forming a first dielectric layer 600 on the substrate 100.

[0107] The first dielectric layer 600 is used as a process platform for forming the interconnection line 200.

[0108] In the embodiment, the material of the first dielectric layer 600 is insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0109] In the embodiment, the first dielectric layer 600 is patterned to form the recess.

[0110] The recess provides a space position for forming the interconnection line 200.

[0111] Correspondingly, in the embodiment, the recess exposes the source-drain doped layer 120, so that the interconnection line 200 formed in the recess is electrically connected with the source-drain doped layer 120.

[0112] In the embodiment, the interconnection line 200 is formed in the recess.

[0113] Specifically, in the embodiment, the interconnection line 200 is formed in the recess, and then the first dielectric layer 600 exposes the top surface of the interconnection line 200, thereby providing a space position for forming the growth layer 300.

[0114] In combination with reference to Figure 9 and Figure 10 , Figure 9 is a sectional view of the semiconductor structure along the extending direction of the gate structure, Figure 10 is a sectional view of the semiconductor structure along the direction perpendicular to the extending direction of the gate structure, the growth layer 300 covering the top surface of the interconnection line 200 is formed, and the material of the growth layer 300 is the same as that of the interconnection structure.

[0115] That is, the material of the growth layer 300 is the same as the material of the interconnection structure to be subsequently formed.

[0116] The growth layer 300 is used to provide a better forming basis for the interconnection structure.

[0117] In the embodiment, the growth layer 300 is used as a basis for forming the interconnection structure subsequently, and the material of the growth layer 300 is the same as that of the interconnection structure, so that the interconnection structure has a better forming basis, and it is easy to form the interconnection structure with good film layer quality on the growth layer 300, which is beneficial to guarantee the electrical connection performance between the interconnection structure and the interconnection line 200, thereby being beneficial to guarantee the performance of the semiconductor structure.

[0118] In the embodiment, the growth layer 300 covering the top surface of the interconnection line 200 is formed by using a selective growth process.

[0119] The selective growth process can selectively grow a metal material only on a metal material, and the growth layer 300 covering the top surface of the interconnection line 200 is formed by using the selective growth process, so that the growth layer 300 can be selectively grown only on the top surface of the interconnection line 200, and has a better position selectivity, which is beneficial to make the position accuracy of the growth layer 300 higher, and is also beneficial to make the interface between the growth layer 300 and the interconnection line 200 better, thereby improving the reliability of the device, and the selective growth of the material in the target region is also beneficial to reduce the waste of the material and save the process cost.

[0120] Specifically, in this embodiment, the first dielectric layer 600 exposes the top surface of the interconnection line 200, so that the growth layer 300 can be selectively grown only on the top surface of the interconnection line 200.

[0121] In this embodiment, in the step of forming the growth layer 300 covering the top surface of the interconnection line 200, the material of the growth layer 300 includes W or Cu.

[0122] The W or Cu material can further provide a better formation basis for the formation of the interconnection structure.

[0123] Specifically, in this embodiment, the interconnection structure electrically connected to the interconnection line 200 is formed by a subsequent selective growth process, and it is more difficult to grow directly on the interconnection line 200 (especially Co, Ti, TiN, Ru or Mo material), and it is easier to grow on the growth layer 300 (especially W or Cu material) of the same material as the interconnection structure, and a better quality interconnection structure film can be obtained.

[0124] It should be noted that, in this embodiment, in the step of forming the growth layer 300 covering the top surface of the interconnection line 200, the thickness of the growth layer 300 should not be too large or too small. If the thickness of the growth layer 300 is too large, it is easy to cause unnecessary material waste, and it is also easy to cause the height of the semiconductor structure in the longitudinal direction to be too large, which is difficult to obtain better integration requirements; if the thickness of the growth layer 300 is too small, the growth layer 300 is difficult to provide a sufficient formation basis for the formation of the interconnection structure, so that a better interconnection structure film is difficult to obtain. Therefore, in this embodiment, in the step of forming the growth layer 300 covering the top surface of the interconnection line 200, the thickness of the growth layer 300 is to

[0125] In combination with reference Figures 11-18 The interconnection structure 400 is formed on the growth layer 300, and the interconnection structure 400 is electrically connected to the interconnection line 200 through the growth layer 300.

[0126] The interconnection structure 400 is used to be electrically connected to the interconnection line 200 through the growth layer 300, so as to realize the electrical connection between the interconnection line 200 and the outside through the interconnection structure 400.

[0127] Specifically, in this embodiment, in the step of forming the interconnection structure 400 on the growth layer 300, the interconnection structure 400 is an interconnection via plug, which realizes the electrical connection between the interconnection plug on the source / drain doped layer 120 and the outside.

[0128] In this embodiment, the selective growth process is used to form the interconnection structure 400 on the growth layer 300.

[0129] The selective growth process can selectively grow the metal material only on the metal material. The interconnection structure 400 is formed on the growth layer 300 by using the selective growth process, and the interconnection structure 400 can be selectively grown only on the growth layer 300. The selective growth process has good position selectivity, which is beneficial to improve the position accuracy of the interconnection structure 400 and improve the interface bonding between the interconnection structure 400 and the growth layer 300, thereby improving the reliability of the device. In addition, the selective growth of the material in the target region is also beneficial to reduce the waste of the material and save the process cost.

[0130] With reference to Figure 11 and Figure 12 , Figure 11 is a sectional view of the semiconductor structure along the extension direction of the gate structure, Figure 12 is a sectional view of the semiconductor structure along the direction perpendicular to the extension direction of the gate structure, the step of forming the interconnection structure 400 on the growth layer 300 and electrically connecting the interconnection structure 400 and the interconnection line 200 through the growth layer 300 includes: forming a second dielectric layer 500 covering the growth layer 300 on the first dielectric layer 600.

[0131] The second dielectric layer 500 is used as a process platform for forming the interconnection structure 400.

[0132] In the embodiment, the material of the second dielectric layer 500 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0133] With reference to Figure 13 and Figure 14 , Figure 13 is a sectional view of the semiconductor structure along the extension direction of the gate structure, Figure 14 is a sectional view of the semiconductor structure along the direction perpendicular to the extension direction of the gate structure, the step of forming the interconnection structure 400 on the growth layer 300 and electrically connecting the interconnection structure 400 and the interconnection line 200 through the growth layer 300 includes: forming a second dielectric layer 500 covering the growth layer 300 on the first dielectric layer 600.

[0134] The via hole 510 is used to provide a spatial position for the formation of the interconnection structure 400.

[0135] With reference to Figures 15-18 The interconnection structure 400 is formed in the via hole 510, and the interconnection structure 400 is in contact with the second dielectric layer 500.

[0136] In the embodiment, the interconnection structure 400 is in contact with the second dielectric layer 500, that is, no adhesion layer is formed between the interconnection structure 400 and the second dielectric layer 500, that is, the interconnection structure 400 also has no adhesion layer at the bottom, and the contact resistance between the interconnection structure 400 and the growth layer 300 is small, thereby being beneficial to improve the electrical connection performance between the interconnection structure 400 and the interconnection line 200.

[0137] Specifically, referring to Figure 15 and Figure 16 , Figure 15 is a sectional view of the semiconductor structure along the extending direction of the gate structure, Figure 16 is a sectional view of the semiconductor structure along the direction perpendicular to the extending direction of the gate structure, the step of forming the interconnection structure 400 in the via 510 includes: forming an interconnection material layer 410 filling the via 510 and covering the second dielectric layer 500.

[0138] The interconnection material layer 410 is used to directly form the interconnection structure 400.

[0139] It should be noted that in the embodiment, the interconnection structure 400 is formed by using the selective growth process, and correspondingly, the interconnection material layer 410 is formed by using the selective growth process. The selective growth process can grow a film layer with good film quality in the via 510. Compared with other deposition processes, there is no need to form a thicker interconnection material layer 410 for better filling of the via 510, that is, the film thickness of the interconnection material layer 410 in the embodiment will not be too large.

[0140] Referring to Figure 17 and Figure 18 , Figure 17 is a sectional view of the semiconductor structure along the extending direction of the gate structure, Figure 18 is a sectional view of the semiconductor structure along the direction perpendicular to the extending direction of the gate structure, the step of forming the interconnection structure 400 in the via 510 includes: forming an interconnection material layer 410 filling the via 510 and covering the second dielectric layer 500.

[0141] The interconnection material layer 410 is used to directly form the interconnection structure 400.

[0142] It should be noted that in the embodiment, the film thickness of the interconnection material layer 410 will not be too large, so the thickness of the interconnection material layer 410 to be removed in the planarization process of the interconnection material layer 410 is small, and the planarization process time is short. The influence on the interconnection material layer 410 in the via 510 is small, so the influence on the contact surface between the interconnection structure 400 and the second dielectric layer 500 is small. Therefore, in the embodiment, there is no need to form an adhesion layer between the interconnection structure 400 and the second dielectric layer 500, and the interconnection structure 400 and the second dielectric layer 500 can also be in good contact.

[0143] In summary, by using the forming method of the embodiment, the interconnection structure 400 with good film quality can be obtained while ensuring good contact between the interconnection structure 400 and the second dielectric layer 500, and the contact resistance between the interconnection structure 400 and the interconnection line 200 is small, which ensures the performance of the semiconductor structure.

[0144] Although the present application has been disclosed with reference to various implementations, it is understood that equivalents can be employed and substitutions made herein without departing from the spirit and scope of the application as defined in the following claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; an interconnect line on the substrate for electrically connecting with an interconnect structure; a growth layer covering a top surface of the interconnect line, the growth layer being of a same material as the interconnect structure; an interconnect structure on the growth layer and in contact with the growth layer, the interconnect structure being electrically connected with the interconnect line through the growth layer.

2. The semiconductor structure of claim 1, wherein, The substrate has a channel structure formed thereon, and a gate structure across the channel structure, the substrate on both sides of the gate structure has source / drain doped layers in contact with the channel structure; The interconnect line is on and electrically connected with the source / drain doped layers.

3. The semiconductor structure of claim 2, wherein, The interconnect line is an interconnect plug extending along an extension direction of the gate structure and covering a plurality of the source / drain doped layers. The interconnect structure is an interconnect via plug.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a first dielectric layer covering sidewalls of the interconnect line and exposing a top surface of the interconnect line; a second dielectric layer on the first dielectric layer, the second dielectric layer covering sidewalls of the growth layer and the interconnect structure, the interconnect structure penetrating through the second dielectric layer and in contact with the second dielectric layer.

5. The semiconductor structure of claim 1, wherein, The material of the interconnect line comprises one or more of Co, Ti, TiN, Ru and Mo.

6. The semiconductor structure of claim 1, wherein, The material of the growth layer comprises W or Cu.

7. The semiconductor structure of claim 1, wherein, The thickness of the growth layer is to 8. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: providing a substrate; forming an interconnect line on the substrate for electrically connecting with an interconnect structure; forming a growth layer covering a top surface of the interconnect line, the growth layer being of a same material as the interconnect structure; forming an interconnect structure on the growth layer, the interconnect structure being electrically connected with the interconnect line through the growth layer.

9. The method of forming a semiconductor structure of claim 8, wherein, In the step of providing the substrate, the substrate has a channel structure formed thereon, and a gate structure across the channel structure, the substrate on both sides of the gate structure has source / drain doped layers in contact with the channel structure; In the step of forming the interconnect line, the interconnect line is on and electrically connected with the source / drain doped layers.

10. The method of forming a semiconductor structure of claim 9, wherein, In the step of forming the interconnect line, the interconnect line is an interconnect plug extending along an extension direction of the gate structure and covering a plurality of the source / drain doped layers. In the step of forming the interconnect structure on the growth layer, the interconnect structure is an interconnect via plug.

11. The method of forming a semiconductor structure of claim 8, wherein, The growth layer covering the top surface of the interconnect line is formed by a selective growth process.

12. The method of forming a semiconductor structure of claim 8, wherein, The step of forming the interconnect line on the substrate comprises: forming a first dielectric layer on the substrate; patterning the first dielectric layer to form a recess; forming the interconnect line in the recess.

13. The method of forming a semiconductor structure of claim 12, wherein, The step of forming the interconnect structure on the growth layer and in contact with the growth layer through the growth layer comprises: forming a second dielectric layer covering the growth layer on the first dielectric layer; patterning the second dielectric layer to form a via exposing the growth layer; forming the interconnect structure in the via, the interconnect structure being in contact with the second dielectric layer.

14. The method of forming a semiconductor structure of claim 13, wherein, The step of forming the interconnect structure in the via comprises: forming an interconnect material layer filling the via and covering the second dielectric layer; planarizing the interconnect material layer, removing interconnect material layer above the second dielectric layer, leaving interconnect material layer in the via as the interconnect structure.

15. The method of forming a semiconductor structure of claim 8, wherein, forming the interconnect structure on the growth layer using a selective growth process.

16. The method of forming a semiconductor structure of claim 8, wherein, In the step of forming interconnect lines on the substrate, the material of the interconnect lines comprises one or more of Co, Ti, TiN, Ru, and Mo.

17. The method of forming a semiconductor structure of claim 8, wherein, In the step of forming a growth layer covering the top surface of the interconnect lines, the material of the growth layer comprises W or Cu.

18. The method of forming a semiconductor structure of claim 8, wherein, In the step of forming a growth layer covering the top surface of the interconnection line, the thickness of the growth layer is to

Images