Manufacturing method of wafer structure and contact structure

Abstract

The invention provides a manufacturing method of a wafer structure and a contact structure, and the manufacturing method of the contact structure comprises the following steps: providing a semiconductor structure which comprises a device region and an edge region, a plurality of device structures are formed in the device region, the upper surface of the device region is higher than the upper surface of the edge region, and an edge buffer layer is formed on the upper surface layer of the edge region; sequentially forming a middle layer covering the upper surface of the edge buffer layer and an interlayer dielectric structure; forming a patterned shielding layer covering the upper surface of the interlayer dielectric structure right above the device region, forming a contact hole based on the shielding layer, and removing the interlayer dielectric structure right above the edge region and at least part of the middle layer; and sequentially forming an electrode buffer layer which is located right above the edge region and covers the inner wall and the bottom surface of the contact hole, and an electrode layer which fills the contact hole. According to the invention, the intermediate layer right above the edge region is formed before the interlayer dielectric structure is formed, so that the peeling of the electrode buffer layer right above the edge region is reduced, and the performance of the contact structure is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a method for fabricating a wafer structure and contact structure. Background Technology

[0002] In semiconductor manufacturing processes, after contact hole etching is completed, Ti and TiN layers are deposited sequentially as adhesion layers (Ti / TiN layers) to enhance the adhesion between the metal electrode filling the contact hole and the second interlayer dielectric layer, and to improve electrical performance and mechanical stability. However, after the contact hole etching process (CT Etch), the Ti / TiN layer in the wafer edge region is easily peeled off, resulting in peeling defects. The peeled Ti / TiN layer can block part of the contact hole (CT), preventing the subsequent metal electrode W from being completely filled, thus affecting contact resistance and device reliability.

[0003] Currently, to avoid the detached Ti / TiN layer blocking contact holes, a wet etching process is typically used to remove the detached Ti / TiN layer after TiN deposition. However, this may damage the TiN that needs to be retained within the contact holes, affecting electrical performance. Alternatively, bevel etching is performed after TiN deposition to remove the detached Ti / TiN layer at the edges. However, this is only a remedial measure and cannot fundamentally reduce the detachment of the Ti / TiN layer in the bevel region. This is because Ti / TiN layer detachment also occurs during TiN deposition and between TiN deposition and bevel etching, still resulting in incomplete filling of the subsequent metal electrode W, affecting contact resistance and device reliability.

[0004] Therefore, there is an urgent need to find a method for fabricating contact structures that can reduce the peeling of the electrode buffer layer in the edge region. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating a wafer structure and a contact structure, which solves the problem in the prior art that the adhesion layer located on the upper surface of the edge region is prone to falling off and affects the filling of the contact hole.

[0006] To achieve the above and other related objectives, the present invention provides a method for manufacturing a contact structure, comprising the following steps:

[0007] A semiconductor structure is provided, including a device region and an edge region surrounding the device region. Multiple device structures are formed in the device region, and the upper surface of the device region is higher than the upper surface of the edge region. The upper surface layer of the edge region is provided with an edge buffer layer of a predetermined thickness.

[0008] An intermediate layer covering the upper surface of the edge buffer layer and an interlayer dielectric structure covering the exposed upper surface of the semiconductor structure and the upper surface of the intermediate layer are formed sequentially.

[0009] A patterned masking layer is formed covering the upper surface of the interlayer dielectric structure directly above the device region, and a contact hole is formed based on the masking layer to penetrate the interlayer dielectric structure. At the same time, the interlayer dielectric structure directly above the edge region and at least part of the intermediate layer are removed, and the bottom surface of the contact hole exposes the corresponding area of ​​the device structure.

[0010] An electrode buffer layer and an electrode layer filling the contact hole are sequentially formed, located directly above the edge area and covering the inner wall and bottom surface of the contact hole.

[0011] Optionally, the semiconductor structure includes a stacked structure, a first well region of a first conductivity type, a second well region of a second conductivity type, an isolation structure, a first source / drain region of a second conductivity type, a second source / drain region of a first conductivity type, a first gate structure, and a second gate structure. The stacked structure includes a substrate of a second conductivity type and an epitaxial layer of a first conductivity type stacked sequentially. The first well region and the second well region are located on the upper surface of the epitaxial layer. The isolation structure is embedded in the epitaxial layer surrounding the first well region and the second well region, respectively. The first gate structure is located on the upper surface of the first well region. The first source / drain region is located on the upper surface of the first well region on opposite sides of the first gate structure. The second gate structure is located on the upper surface of the second well region. The second source / drain region is located on the upper surface of the second well region on opposite sides of the second gate structure.

[0012] Optionally, the semiconductor structure further includes a stress layer that covers the exposed surfaces of the first well region, the second well region, the first gate structure, and the second gate structure.

[0013] Optionally, after forming the intermediate layer and before forming the interlayer dielectric structure, the method further includes a step of smoothing the upper surface of the intermediate layer.

[0014] Optionally, the method for planarizing the upper surface of the intermediate layer includes plasma etching.

[0015] Optionally, the material of the intermediate layer is the same as that of the edge buffer layer; or the crystal structure type of the edge buffer layer is the same as that of the intermediate layer, wherein the crystal structure type of the intermediate layer includes polycrystalline and amorphous.

[0016] Optionally, the upper surface of the intermediate layer is not higher than the upper surface of the epitaxial layer in the device region.

[0017] Optionally, the interlayer dielectric structure includes a first interlayer dielectric layer and a second interlayer dielectric layer stacked sequentially.

[0018] Optionally, the electrode buffer layer directly above the edge region covers the upper surface of the edge buffer layer.

[0019] The present invention also provides a wafer structure in which the contact structure of at least one semiconductor device is fabricated using the contact structure fabrication method described above.

[0020] As described above, the wafer structure and contact structure fabrication method of the present invention improves the contact structure fabrication process by forming an intermediate layer covering the upper surface of the edge buffer layer before forming the interlayer dielectric structure. This reduces the removal of the edge buffer layer during the over-etching process of forming the contact hole, providing a better adhesion surface for the electrode buffer layer subsequently formed directly above the edge region. This enhances the bonding strength between the electrode buffer layer and the semiconductor structure in the edge region, reduces the stress between the semiconductor structure in the edge region and the electrode buffer layer, and fundamentally reduces the peeling of the electrode buffer layer directly above the edge region. Consequently, it reduces the impact of the electrode buffer layer peeling on the filling of the electrode layer. Furthermore, it eliminates the need to directly remove the electrode buffer layer directly above the edge region after forming the electrode buffer layer, thus improving the performance of the contact structure and the reliability of the devices in the device region. This method has high industrial application value. Attached Figure Description

[0021] Figure 1 The diagram shows a process flow chart of the method for manufacturing the contact structure of the present invention.

[0022] Figure 2 Shown is a top view of a semiconductor structure used in the fabrication method of the contact structure of the present invention.

[0023] Figure 3 The diagram shows a cross-sectional view of a portion of a semiconductor structure used in the fabrication method of the contact structure of the present invention.

[0024] Figure 4 The diagram shows a cross-sectional view of a portion of the contact structure after the intermediate layer has been formed, as shown in the method for manufacturing the contact structure of the present invention.

[0025] Figure 5 The diagram shows a cross-sectional view of a portion of the upper surface of the flattened intermediate layer, which is a method for manufacturing the contact structure of the present invention.

[0026] Figure 6 The diagram shows a cross-sectional view of a portion of the contact structure fabrication method of the present invention after forming an interlayer dielectric structure.

[0027] Figure 7The diagram shows a cross-sectional view of a portion of the contact structure after the patterned masking layer is formed, as shown in the method for manufacturing the contact structure of the present invention.

[0028] Figure 8 The diagram shows a cross-sectional view of a portion of the contact structure after the contact hole is formed, illustrating the method for fabricating the contact structure of the present invention.

[0029] Figure 9 The diagram shows a cross-sectional view of a portion of the area after the electrode buffer layer is formed, which is a method for fabricating the contact structure of the present invention.

[0030] Figure 10 The diagram shows a cross-sectional view of a portion of the contact structure after the electrode layer has been formed, illustrating the fabrication method of the contact structure of the present invention.

[0031] Reference numerals: 1 Semiconductor structure, 11 Substrate, 12 Epitaxial layer, 13 First well region, 131 First source / drain region, 132 First lightly doped region, 14 Second well region, 141 Second source / drain region, 142 Second lightly doped region, 15 Isolation structure, 16 First gate structure, 161 First gate conductive layer, 17 Second gate structure, 171 Second gate conductive layer, 18 Metal silicide layer, 181 Edge buffer layer, 19 Stress layer, 2 Device region, 21 Edge region, 22 Masking layer, 23 Intermediate layer, 3 Interlayer dielectric structure, 31 First interlayer dielectric layer, 32 Second interlayer dielectric layer, 33 First contact hole, 34 Second contact hole, 35 First gate contact hole, 36 Third contact hole, 37 Fourth contact hole, 38 Second gate contact hole, 4 Electrode buffer layer, 41 First electrode, 42 Second electrode, 43 First gate, 44 Third electrode, 45 Fourth electrode, 46 Second gate. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please see Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] Example 1

[0035] This embodiment provides a method for fabricating a contact structure, such as... Figure 1 The diagram shown is a process flow chart of the method for manufacturing the contact structure, including the following steps:

[0036] S1: A semiconductor structure including a device region and an edge region surrounding the device region is provided. Multiple device structures are formed in the device region, and the upper surface of the device region is higher than the upper surface of the edge region. The upper surface layer of the edge region is provided with an edge buffer layer of a predetermined thickness.

[0037] S2: Sequentially form an intermediate layer covering the upper surface of the edge buffer layer and an interlayer dielectric structure covering the exposed upper surface of the semiconductor structure and the upper surface of the intermediate layer;

[0038] S3: A patterned masking layer is formed covering the upper surface of the interlayer dielectric structure directly above the device region, and a contact hole is formed based on the masking layer to penetrate the interlayer dielectric structure. At the same time, the interlayer dielectric structure directly above the edge region and at least part of the intermediate layer are removed, and the bottom surface of the contact hole exposes the corresponding area of ​​the device structure.

[0039] S4: Sequentially form an electrode buffer layer located directly above the edge area and covering the inner wall and bottom surface of the contact hole, and an electrode layer filling the contact hole.

[0040] Please see Figures 2 to 6 Steps S1 and S2 are performed as follows: A semiconductor structure 1 including a device region 2 and an edge region 21 surrounding the device region 2 is provided. Multiple device structures are formed in the device region 2, and the upper surface of the device region 2 is higher than the upper surface of the edge region 21. An edge buffer layer 181 of a preset thickness is provided on the upper surface of the edge region 21. An intermediate layer 23 covering the upper surface of the edge buffer layer 181 and an interlayer dielectric structure 3 covering the exposed upper surface of the semiconductor structure 1 and the upper surface of the intermediate layer 23 are formed in sequence.

[0041] It should be noted that semiconductor structure 1 is usually the wafer of the contact electrodes of each device in the semiconductor device to be fabricated, and its specific size, shape and thickness can be selected according to the actual situation.

[0042] As an example, such as Figure 2 and Figure 3The figures show a top view and a cross-sectional view of a portion of the semiconductor structure 1. The semiconductor structure 1 includes a stacked structure, a first well region 13 of a first conductivity type, a second well region 14 of a second conductivity type, an isolation structure 15, a first source / drain region 131 of a second conductivity type, a second source / drain region 141 of a first conductivity type, a first gate structure 16, and a second gate structure 17. The stacked structure includes a substrate 11 of a second conductivity type and an epitaxial layer 12 of a first conductivity type stacked sequentially. The first well region 13 and the second well region 14 are located on the upper surface of the epitaxial layer 12. The isolation structure 15 is embedded in the epitaxial layer 12 surrounding the first well region 13 and the second well region 14, respectively. The first gate structure 16 is located on the upper surface of the first well region 13. The first source / drain region 131 is located on the upper surface of the first well region 13 on opposite sides of the first gate structure 16. The second gate structure 17 is located on the upper surface of the second well region 14. The second source / drain region 141 is located on the upper surface of the second well region 14 on opposite sides of the second gate structure 17. In this embodiment, the device to be fabricated in the first well region 13 is an NMOS device, and the device to be fabricated in the second well region 14 is a PMOS device.

[0043] It should be noted that the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0044] Specifically, substrate 11 is usually the process platform used to fabricate epitaxial layer 12. While ensuring the performance of the fabricated device, the thickness and doping concentration of substrate 11 can be selected according to the actual situation.

[0045] Specifically, the epitaxial layer 12 is used to fabricate the well region of the device. The thickness of the epitaxial layer 12 can be selected according to the actual situation while ensuring the performance of the fabricated device.

[0046] It should be noted that the epitaxial layer 12 is usually formed on the upper surface of the substrate 11 by a concentration epitaxial process, and the first well region 13 and the second well region 14 in the epitaxial layer 12 are formed by ion implantation processes.

[0047] Specifically, the isolation structure 15 is used to isolate the devices formed in the device region 2 from each other. The isolation structure 15 includes an isolation trench, a filling buffer layer and an isolation filling layer. The isolation trench is embedded in the epitaxial layer 12 to define the area of ​​each device to be fabricated in the device region 2. The filling buffer layer covers the inner wall and bottom surface of the isolation trench. The isolation filling layer fills the remaining part of the isolation trench. That is, the isolation filling layer and the filling buffer layer together fill the isolation trench.

[0048] Specifically, the methods for forming isolation trenches include dry etching, wet etching, or other suitable methods; the methods for forming the filling buffer layer include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods; and the methods for forming the isolation filling layer include chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, a dry etching process is used to form isolation trenches surrounding the areas where each device to be fabricated is located in device region 2, then a thermal oxidation process is used to form a filling buffer layer covering the inner wall and bottom surface of the isolation trench, and finally a chemical vapor deposition process is used to form an isolation filling layer filling the isolation trench.

[0049] Specifically, the first source / drain region 131 on the upper surface of the first well region 13 and the second source / drain region 141 on the upper surface of the second well region 14 are formed by ion implantation processes.

[0050] Specifically, a first shallow doped region 132 of the second conductivity type is formed on the upper surface of the first well region 13 on both sides of the first gate structure 16. The bottom surface of the first shallow doped region 132 is higher than the bottom surface of the first source / drain region 131, and the sidewall of the first shallow doped region 132 away from the edge of the adjacent first well region 13 extends to the bottom of the first gate structure 16. The first shallow doped regions 132 on both sides of the first gate structure 16 are spaced apart by a predetermined distance.

[0051] Specifically, the first source / drain region 131 is typically a heavily doped region to form an ohmic contact with the subsequently formed electrode, and the doping concentration of the first shallowly doped region 132 is lower than that of the first source / drain region 131.

[0052] Specifically, a second shallow doped region 142 of the first conductivity type is formed on the upper surface of the second well region 14 on both sides of the second gate structure 17. The bottom surface of the second shallow doped region 142 is higher than the bottom surface of the second source / drain region 141, and the sidewall of the second shallow doped region 142 away from the edge of the adjacent second well region 14 extends to the bottom of the second gate structure 17. The second shallow doped regions 142 on both sides of the second gate structure 17 are spaced apart by a predetermined distance.

[0053] Specifically, the second source / drain region 141 is typically a heavily doped region to form an ohmic contact with the subsequently formed electrode, and the doping concentration of the second shallowly doped region 142 is lower than that of the second source / drain region 141.

[0054] Specifically, the first gate structure 16 includes a first isolation sidewall and a first gate dielectric layer and a first gate conductive layer 161 stacked sequentially. The first isolation sidewall covers the exposed sidewalls of the first gate dielectric layer and the first gate conductive layer 161. The second gate structure 17 includes a second isolation sidewall and a second gate dielectric layer and a second gate conductive layer 171 stacked sequentially. The second isolation sidewall covers the exposed sidewalls of the second gate dielectric layer and the second gate conductive layer 171.

[0055] Specifically, the method for forming the first gate dielectric layer includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the second gate dielectric layer includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the first gate conductive layer 161 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the second gate conductive layer 171 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the first isolation sidewall includes chemical vapor deposition, physical vapor deposition, or other suitable methods; and the method for forming the second isolation sidewall includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0056] It should be noted that the first gate structure 16 and the second gate structure 17 can be formed simultaneously or in stages. Preferably, the first gate structure 16 and the second gate structure 17 are formed simultaneously. In this embodiment, a stacked film layer for forming the gate structure is first deposited, and then the film layer is simultaneously etched to form the stacked structure consisting of the first gate dielectric layer and the first gate conductive layer 161, and the stacked structure consisting of the second gate dielectric layer and the second gate conductive layer 171. Then, the film layer structure for fabricating the isolation sidewall (stacked silicon oxide layer, silicon nitride layer, and silicon oxide layer) is deposited. Finally, the film layer structure is etched to simultaneously form the first isolation sidewall and the second isolation sidewall.

[0057] Specifically, the semiconductor structure 1 also includes a metal silicide layer 18, which is located on the upper surface of the first source / drain region 131, the second source / drain region 141, the first gate conductive layer 161 in the first gate structure 16, and the second gate conductive layer 171 in the second gate structure 17.

[0058] It should be noted that the metal silicide layer 18 is usually formed using the Polycide process to reduce the contact resistance between the first source / drain region 131, the second source / drain region 141, the first gate conductive layer 161 and the second gate conductive layer 171 and the corresponding electrodes, thereby forming an ohmic contact.

[0059] As an example, the semiconductor structure 1 also includes a stress layer 19, which covers the exposed surfaces of the first well region 13, the second well region 14, the first gate structure 16, and the second gate structure 17.

[0060] Specifically, the stress type of the stress layer 19 covering the first well region 13 and the first gate structure 16 is usually different from the stress type of the stress layer 19 covering the exposed surfaces of the second well region 14 and the second gate structure 17. That is, the stress type generated by the stress layer 19 covering the exposed surfaces of the first source / drain region 131 and the first gate structure 16 is different from the stress type generated by the stress layer 19 covering the exposed surfaces of the second source / drain region 141 and the second gate structure 17. For example, when the device formed in the first well region 13 is a PMOS device and the device formed in the second well region 14 is an NMOS device, the stress generated by the stress layer 19 covering the exposed surfaces of the first source / drain region 131 and the first gate structure 16 is compressive stress, and the stress generated by the stress layer 19 covering the exposed surfaces of the second source / drain region 141 and the second gate structure 17 is tensile stress.

[0061] It should be noted that the stress layer 19 usually does not cover the edge region 21 of the wafer. The edge buffer layer 181 of the edge region 21 is usually a residue of the previous process. Its specific thickness is related to the previous process and will not be limited here.

[0062] Specifically, the material of the intermediate layer 23 includes silicon oxide, a composite film of silicon oxide and silicon nitride, or other suitable films.

[0063] As an example, the material of the intermediate layer 23 is the same as that of the edge buffer layer 181, so that the intermediate layer 23 and the edge buffer layer 181 have a better bonding force and avoid the intermediate layer 23 from falling off due to stress mismatch.

[0064] Specifically, while ensuring the safety of subsequent processes, the material of the intermediate layer 23 can also be different from that of the edge buffer layer 181.

[0065] Specifically, such as Figure 4 The diagram shows a cross-sectional view of a portion of the area after the formation of the intermediate layer 23. The methods for forming the intermediate layer 23 include chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, the intermediate layer 23 covering the upper surface of the edge buffer layer 181 is formed using a PECVD process. In this embodiment, a silicon oxide thin film is generated by controlling plasma excitation of SiH4 / O2 in the edge region 21 as the intermediate layer 23.

[0066] As an example, such as Figure 5 The diagram shows a cross-sectional structure of a portion of the upper surface of the intermediate layer 23 after it has been leveled. After the intermediate layer 23 is formed and before the interlayer medium structure 3 is formed, the process of leveling the upper surface of the intermediate layer 23 is also included.

[0067] Specifically, by smoothing the upper surface of the intermediate layer 23, the undulations of the intermediate layer 23 surface are reduced, making the upper surface of the intermediate layer 23 smooth and facilitating subsequent processes. Simultaneously, the thickness of the intermediate layer 23 can be adjusted so that the thickness of the intermediate layer 23 and the edge buffer layer 181 is greater than the thickness loss of the intermediate layer 23 and the edge buffer layer 181 caused by subsequent processes (i.e., the thickness loss of the intermediate layer 23 and the edge buffer layer 181 caused by the formation of contact holes). Preferably, the thickness of the intermediate layer 23 is equal to the thickness loss of the intermediate layer 23 caused by subsequent processes.

[0068] As an example, the upper surface of the intermediate layer 23 is not higher than the upper surface of the epitaxial layer 12 in the device region 2.

[0069] Specifically, by making the upper surface of the intermediate layer 23 lower than the upper surface of the epitaxial layer 12 in the device region 2, the stress change on the wafer caused by the introduction of the intermediate layer 23 can be reduced, and the impact of the introduction of the intermediate layer 23 on the wafer can be reduced.

[0070] As an example, methods for planarizing the upper surface of the intermediate layer 23 include plasma etching or other suitable methods. Preferably, Ar is used. + / N + Ions bombard the upper surface of the intermediate layer 23 to achieve a smooth surface on the upper surface of the intermediate layer 23.

[0071] It should be noted that during the process of using plasma etching to flatten the intermediate layer 23, the raised areas on the surface of the intermediate layer 23 are exposed to a greater extent, and thus have a higher probability of being bombarded by ions. The excited atoms diffuse along the surface of the intermediate layer 23 and preferentially fill the recessed areas on the surface of the intermediate layer 23, thereby flattening the surface of the intermediate layer 23 and achieving a smooth surface.

[0072] As an example, the crystal structure type of the edge buffer layer 181 is the same as that of the intermediate layer 23, which includes polycrystalline and amorphous crystal structures.

[0073] Specifically, by making the crystal structure of the edge buffer layer 181 and the intermediate layer 23 polycrystalline or amorphous, the stress between the subsequently formed electrode buffer layer 4 and the edge buffer layer 181 or the intermediate layer 23 can be effectively alleviated, preventing the subsequent electrode buffer layer 4 from peeling off. Preferably, the crystal structure of the edge buffer layer 181 and the intermediate layer 23 is amorphous, so that the edge buffer layer 181 or the intermediate layer 23 can absorb some of the stress through deformation, reducing the accumulation of stress, thereby reducing the stress between it and the electrode buffer layer 4 attached to its upper surface, and reducing the probability of the electrode buffer layer 4 peeling off.

[0074] As an example, such as Figure 6The diagram shown is a cross-sectional view of a portion of the region after the formation of the interlayer dielectric structure 3. The interlayer dielectric structure 3 includes a first dielectric layer 31 and a second dielectric layer 32 stacked sequentially.

[0075] Specifically, the first interlayer dielectric layer 31 is typically used to ensure that the subsequent contact holes have a good aspect ratio; the method for forming the first interlayer dielectric layer 31 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, the first interlayer dielectric layer 31 is formed using the HARP process.

[0076] Specifically, the methods for forming the second interlayer dielectric layer 32 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0077] Please see Figures 7 to 10 Steps S3 and S4 are executed: a patterned masking layer 22 is formed on the upper surface of the interlayer dielectric structure 3 directly above the device region 2, and a contact hole penetrating the interlayer dielectric structure 3 is formed based on the masking layer 22. At the same time, the interlayer dielectric structure 3 directly above the edge region 21 and at least part of the intermediate layer 23 are removed, and the bottom surface of the contact hole exposes the corresponding area of ​​the device structure. An electrode buffer layer 4 located directly above the edge region 21 and covering the inner wall and bottom surface of the contact hole and an electrode layer filling the contact hole are formed in sequence.

[0078] Specifically, such as Figure 7 The diagram shows a cross-sectional view of a portion of the area after the patterned masking layer 22 is formed. The masking layer 22 is typically an etch protection layer for forming contact holes, preventing the etchant from etching non-patterned areas during the contact hole formation process. The method for patterning the masking layer 22 is a commonly used photolithography process, which will not be elaborated here.

[0079] It should be noted that the masking layer 22 can typically be a single photoresist layer or a composite film layer composed of an anti-reflective layer and a photoresist layer. Preferably, the masking layer 22 is a composite film layer composed of an anti-reflective film layer and a photoresist layer, with the top layer of the masking layer 22 being a photoresist layer. In this embodiment, the masking layer 22 is composed of a stacked etching mask layer (APF), a nitrogen-free dielectric anti-reflective layer (NFDARC), a bottom anti-reflective coating (BARC), and a photoresist layer (PR). In this embodiment, the masking layer 22 is composed of an APF layer with a thickness of 1900 Å, an NFDARC layer with a thickness of 350 Å, a BARC layer with a thickness of 260 Å, and a PR layer with a thickness of 1800 Å stacked sequentially.

[0080] Specifically, methods for forming contact holes include dry etching, wet etching, or other suitable methods.

[0081] Specifically, such as Figure 8The diagram shows a cross-sectional view of a portion of the area after the contact holes are formed. The contact holes include a first contact hole 33, a second contact hole 34, a third contact hole 36, a fourth contact hole 37, a first gate contact hole 35, and a second gate contact hole 38. The first contact hole 33 and the second contact hole 34 penetrate the interlayer dielectric structures 3 on opposite sides of the first gate structure 16, and their bottom surfaces expose the metal silicide layer 18 on the upper surface of the first source / drain region 131, respectively. The first gate contact hole 35 penetrates the interlayer dielectric structure 3 directly above the first gate conductive layer 161, and its bottom surface exposes the metal silicide layer 18 on the upper surface of the first gate conductive layer 161, respectively. The third contact hole 36 and the fourth contact hole 37 penetrate the interlayer dielectric structures 3 on opposite sides of the second gate structure 17, and their bottom surfaces expose the metal silicide layer 18 on the upper surface of the second source / drain region 141, respectively. The second gate contact hole 38 penetrates the interlayer dielectric structure 3 directly above the second gate conductive layer 171, and its bottom surface exposes the metal silicide layer 18 on the upper surface of the second gate conductive layer 171, respectively. In this embodiment, the first contact hole 33, the second contact hole 34, the third contact hole 36, and the fourth contact hole 37 are arranged along the arrangement direction of the first well region 13 and the second well region 14.

[0082] Specifically, the first contact hole 33, the second contact hole 34, the first gate contact hole 35, the third contact hole 36, the fourth contact hole 37, and the second gate contact hole 38 can be formed simultaneously or in stages. In this embodiment, the stress layer 19 is used as an etching stop layer. The first contact hole 33, the second contact hole 34, the first gate contact hole 35, the third contact hole 36, the fourth contact hole 37, and the second gate contact hole 38 located in the second interlayer dielectric layer 32 are etched simultaneously first, and then the stress layer 19 is etched simultaneously to form contact holes that penetrate the interlayer dielectric structure 3 and the stress layer 19.

[0083] Specifically, during the formation of the contact hole, since the shielding layer 22 does not cover the area directly above the edge region 21, the interlayer dielectric structure 3 directly above the edge region 21 will be etched simultaneously. Through the formation of the intermediate layer 23, over-etching can be avoided, which would cause the edge buffer layer 181 below the intermediate layer 23 to be completely removed, thus providing a good process adhesion surface for the electrode buffer layer 4 to be formed subsequently.

[0084] Specifically, such as Figure 9 The diagram shows a cross-sectional view of a portion of the area after the formation of electrode buffer layer 4. The electrode buffer layer 4 is made of materials including titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. In this embodiment, a Ti layer and a TiN layer stacked sequentially are used as the electrode buffer layer 4.

[0085] It should be noted that the electrode buffer layer 4 is used to enhance the bonding force between the electrode layer that fills the contact hole and the inner wall of the contact hole, and at the same time, it is used to prevent the atoms of the electrode layer from diffusing into the interlayer dielectric structure 3, thus ensuring the reliability of the device.

[0086] Specifically, the methods for forming the electrode buffer layer 4 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0087] It should be noted that the bond energy of the chemical bonds formed between the electrode buffer layer 4 and the edge buffer layer 181 or the intermediate layer 23 is usually greater than the bond energy of the chemical bonds formed between the electrode buffer layer 4 and the substrate 11 or the epitaxial layer 12 below the edge buffer layer 181. Furthermore, the lattice mismatch between the epitaxial layer 12 or the substrate 11 below the edge buffer layer 181 and the electrode buffer layer 4 is relatively large. For example, when the substrate 11 or the epitaxial layer 12 is made of silicon, the edge buffer layer 181 and the intermediate layer 23 are made of silicon oxide, and the electrode buffer layer 4 is a stacked titanium layer and a titanium nitride layer, the bond energy of the Si-Ti bond between the substrate 11 and the electrode buffer layer 4 is between 178 KJ / mol and 470 KJ / mol, and the bond energy of the Ti-O bond between the electrode buffer layer 4 and the intermediate layer 23 is approximately 672 KJ / mol.

[0088] Specifically, after forming the contact hole, by leaving an edge buffer layer 181 on the top layer of the edge region 21 or leaving an intermediate layer 23 directly above the edge region 21, the electrode buffer layer 4 is formed on the upper surface of the intermediate layer 23 or the edge buffer layer 181, so that the electrode buffer layer 4 of the edge region 21 has better bonding force with the semiconductor structure 1 and reduces the peeling of the electrode buffer layer 4.

[0089] Specifically, after forming the electrode buffer layer 4 and before forming the electrode layer, the process includes forming a filling contact hole (first contact hole 33, second contact hole 34, first gate contact hole 35, third contact hole 36, fourth contact hole 37, second gate contact hole 38) and covering the metal layer on the upper surface of the shielding layer 22.

[0090] Specifically, methods for forming metal layers include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0091] It should be noted that the shielding layer 22 can be removed after the contact hole is formed but before the electrode buffer is formed, or it can be removed after the metal layer filling the contact hole is formed. In this embodiment, the shielding layer 22 is removed after the metal layer filling the contact hole is formed.

[0092] Specifically, after the metal layer is formed and before the electrode layer is formed, the process also includes removing the metal layer and electrode buffer layer 4 and the shielding layer 22 directly above the shielding layer 22.

[0093] Specifically, the methods for removing the metal layer include dry etching, wet etching, chemical mechanical polishing, or other suitable methods; the methods for removing the electrode buffer layer 4 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods; and the methods for removing the masking layer 22 include dry etching, wet etching, or other suitable methods.

[0094] Specifically, such as Figure 10 The diagram shows a cross-sectional view of a portion of the region after the electrode layer is formed. After removing the shielding layer 22, the electrode buffer layer 4 and the metal layer filling the contact hole portion serve as the electrode layer. The electrode layer includes a first electrode 41, a second electrode 42, a third electrode 44, a fourth electrode 45, a first gate 43, and a second gate 46. The first electrode 41 fills the first contact hole 33 to form an ohmic contact with the first source / drain region 131 directly below it. The second electrode 42 fills the second contact hole 34 to form an ohmic contact with the first source / drain region 131 directly below it. The third electrode 44 fills the third contact hole 36 to form an ohmic contact with the second source / drain region 141 directly below it. The fourth electrode 45 fills the fourth contact hole 37 to form an ohmic contact with the second source / drain region 141 directly below it. The first gate 43 fills the first gate contact hole 35, and the second gate 46 fills the second gate contact hole 38.

[0095] Specifically, before forming the interlayer dielectric structure 3 of the device, an intermediate layer 23 is formed covering the upper surface of the edge buffer layer 181 covering the edge region 21. Then, the interlayer dielectric structure 3 is formed and the contact structure is fabricated. This ensures that after the contact hole is formed, the edge region 21 retains the edge buffer layer 181 and the intermediate layer 23 or the edge buffer layer 181. Subsequently, the electrode buffer layer 4 located directly above the edge region 21 is attached to the upper surface of the remaining intermediate layer 23 or the edge buffer layer 181. This enhances the bonding force between the electrode buffer layer 4 and the semiconductor structure 1 of the edge region 21, thereby reducing the probability of the electrode buffer layer 4 peeling off. This fundamentally reduces the impact of the electrode buffer layer 4 peeling off from the edge region 21 on the filling of the electrode layer due to blocking the contact hole, thus improving the performance of the device's contact structure and the device's reliability.

[0096] Specifically, by forming the intermediate layer 23 before forming the interlayer dielectric structure 3, the step of directly removing the electrode buffer layer 4 located directly above the edge region 21 after forming the electrode buffer layer 4 can be omitted.

[0097] The contact structure fabrication method of this embodiment forms an intermediate layer 23 covering the upper surface of the edge buffer layer 181 before forming the interlayer dielectric structure 3. This avoids completely removing the edge buffer layer 181 during the formation of the contact hole, thereby giving the electrode buffer layer 4 directly above the edge region 21 a better adhesion surface. This reduces the probability of the electrode buffer layer 4 peeling off, thereby reducing the impact of the electrode buffer layer 4 peeling off from the edge region 21 on the filling of the electrode layer and preventing it from blocking the contact hole. This eliminates the need to directly remove the electrode buffer layer 4 directly above the edge region 21 after forming the electrode buffer layer 4, thus improving the performance of the contact structure.

[0098] Example 2

[0099] This embodiment also provides a wafer structure, such as Figure 10 The diagram shown is a cross-sectional view of a wafer structure, wherein the contact structure of at least one semiconductor device in the wafer structure is fabricated using the contact structure fabrication method described above.

[0100] The wafer structure includes a semiconductor structure 1, an interlayer dielectric structure 3, contact holes, an electrode buffer layer 4, and an electrode layer. The semiconductor structure 1 includes a device region 2 and an edge region 21 surrounding the device region 2. Multiple device structures are formed in the device region 2, and the upper surface of the device region 2 is higher than the upper surface of the edge region 21. The upper surface of the edge region 21 is provided with an edge buffer layer 181 of at least a predetermined thickness. The interlayer dielectric structure 3 covers the exposed surface of the device structure. The contact holes penetrate the interlayer dielectric structure 3 and expose the corresponding area of ​​the device structure on their bottom surface. The electrode buffer layer 4 covers the inner wall and bottom surface of the contact holes. The electrode layer fills the contact holes.

[0101] Specifically, the semiconductor structure 1 also includes a second conductivity type substrate 11 (substrate wafer) and a first conductivity type epitaxial layer 12 stacked sequentially, and the upper surface of the epitaxial layer 12 in the edge region 21 is lower than the upper surface of the epitaxial layer 12 in the device region 2.

[0102] Specifically, the substrate 11 may be made of silicon, silicon germanium, silicon carbide, diamond, or other suitable semiconductor materials. Preferably, a silicon wafer is used as the substrate 11.

[0103] Specifically, the epitaxial layer 12 is usually a homogeneous epitaxial layer 12 of the substrate 11. While ensuring the device performance in the device region 2, the doping concentration of the epitaxial layer 12 can be selected according to the actual situation.

[0104] Specifically, the semiconductor structure 1 also includes a first well region 13 of a first conductivity type, a second well region 14 of a second conductivity type, an isolation structure 15, a first source / drain region 131 of a second conductivity type, a second source / drain region 141 of a first conductivity type, a first gate structure 16, and a second gate structure 17. The first well region 13 and the second well region 14 are located on the upper surface of the epitaxial layer 12. The isolation structure 15 is embedded in the epitaxial layer 12 surrounding the first well region 13 and the second well region 14, respectively. The first gate structure 16 is located on the upper surface of the first well region 13. The first source / drain region 131 is located on the upper surface of the first well region 13 on opposite sides of the first gate structure 16. The second gate structure 17 is located on the upper surface of the second well region 14. The second source / drain region 141 is located on the upper surface of the second well region 14 on opposite sides of the second gate structure 17.

[0105] Specifically, while ensuring the device performance in device region 2, the doping concentration, thickness, size, and shape of the first well region 13 can be selected according to the actual situation; the size, shape, thickness, and doping concentration of the second well region 14 can be selected according to the actual situation; the size, shape, thickness, and doping concentration of the first source / drain region 131 can be selected according to the actual situation; and the size, shape, thickness, and doping concentration of the second source / drain region 141 can be selected according to the actual situation.

[0106] Specifically, the isolation structure 15 includes an isolation trench, a filling buffer layer, and an isolation filling layer. The isolation trench is embedded in the epitaxial layer 12, the filling buffer layer covers the inner wall and bottom surface of the isolation trench, and the isolation filling layer fills the remaining part of the isolation trench.

[0107] Specifically, while ensuring the performance of the devices in device area 2, the depth, opening size, and opening shape of the isolation trench can be selected according to the actual situation; the thickness of the filling buffer layer can be selected according to the actual situation.

[0108] Specifically, the material of the filling buffer layer includes silicon oxide, silicon oxynitride, or other suitable dielectric materials; the material of the isolation filling layer includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0109] Specifically, the first gate structure 16 includes a first isolation sidewall and a first gate dielectric layer and a first gate conductive layer 161 stacked sequentially. The first isolation sidewall covers the sidewalls of the first gate dielectric layer and the first gate conductive layer 161. The second gate structure 17 includes a second isolation sidewall and a second gate dielectric layer and a second gate conductive layer 171 stacked sequentially. The second isolation sidewall covers the sidewalls of the second gate dielectric layer and the second gate conductive layer 171. While ensuring the device performance in device region 2, the thickness of the first gate dielectric layer can be selected according to the actual situation; the thickness of the second gate dielectric layer can be selected according to the actual situation; the thickness of the first isolation sidewall can be selected according to the actual situation; and the thickness of the second isolation sidewall can be selected according to the actual situation.

[0110] Specifically, the first gate dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the second gate dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the first gate conductive layer 161 is made of polysilicon or other suitable conductive materials; the second gate conductive layer 171 is made of polysilicon or other suitable conductive materials; the first isolation sidewall is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; and the second isolation sidewall is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. In this embodiment, both the first and second gate dielectric layers are made of silicon oxide, both the first and second gate conductive layers 161 and 171 are made of polysilicon, and both the first and second isolation sidewalls are composed of stacked silicon oxide, silicon nitride, and silicon oxide layers (i.e., ONO layers).

[0111] Specifically, the upper surface of the first source / drain region 131 is further provided with a second conductivity type first shallow doped region 132 located on opposite sides of the first gate structure 16, and the first shallow doped region 132 extends from the sidewall away from the outer edge of the first well region 13 to the upper surface of the first well region 13 directly below the first gate conductive layer 161. The first shallow doped regions 132 located on opposite sides of the first gate structure 16 are spaced apart by a predetermined distance. The upper surface of the second source / drain region 141 is further provided with a first conductivity type second shallow doped region 142 located on opposite sides of the second gate structure 17, and the second shallow doped region 142 extends from the sidewall away from the outer edge of the second well region 14 to the upper surface of the second well region 14 directly below the second gate conductive layer 171. The second shallow doped regions 142 located on opposite sides of the second gate structure 17 are spaced apart.

[0112] Specifically, the doping concentration of the first shallow doped region 132 is usually less than that of the first source / drain region 131, and the doping concentration of the second shallow doped region 142 is less than that of the second source / drain region 141. While ensuring the device performance in device region 2, the size, shape, thickness, and doping concentration of the first shallow doped region 132 can be selected according to the actual situation; the size, shape, thickness, and doping concentration of the second shallow doped region 142 can be selected according to the actual situation.

[0113] Specifically, the semiconductor structure 1 also includes a metal silicide layer 18 covering the upper surfaces of the first source / drain region 131, the second source / drain region 141, the first gate conductive layer 161, and the second gate conductive layer 171. The metal silicide layer 18 is used to reduce the contact resistance between the electrode layer and the corresponding region of the device structure.

[0114] Specifically, while ensuring the performance of the devices in device region 2, the thickness of the metal silicide layer 18 can be selected according to the actual situation.

[0115] Specifically, the material of the metal silicide layer 18 includes TiSi2, TaSi2, MoSi2, WSi2, ZrSi2, PdSi2, PtSi2, CoSi2, AlMgSi, or other suitable materials.

[0116] Specifically, the semiconductor structure 1 also includes a stress layer 19 covering the exposed upper surface of the device structure in the device region 2. The thickness of the stress layer 19 can be selected based on actual conditions while ensuring device performance. In this embodiment, the thickness of the stress layer 19 is 360 Å.

[0117] Specifically, the stress layer 19 is made of silicon nitride or other suitable cushioning materials. Preferably, a silicon nitride layer is used as the stress layer 19.

[0118] It should be noted that the stress type generated by the stress layer 19 directly above the first well region 13 is different from the stress type generated by the stress layer 19 directly above the second well region 14.

[0119] Specifically, the interlayer dielectric structure 3 includes a first interlayer dielectric layer 31 and a second interlayer dielectric layer 32 stacked sequentially, with the first interlayer dielectric layer 31 covering the upper surface of the stress layer 19.

[0120] Specifically, the material of the first interlayer dielectric layer 31 includes silicon oxide, silicon oxynitride, or other suitable materials; the material of the second interlayer dielectric layer 32 includes silicon oxide, silicon oxynitride, or other suitable dielectric materials. Preferably, a HARP silicon oxide layer is used as the first interlayer dielectric layer 31, and a silicon oxide layer is used as the second interlayer dielectric layer 32.

[0121] Specifically, while ensuring the performance of the devices in device region 2, the thickness of the first interlayer dielectric layer 31 can be selected according to actual conditions; the thickness of the second interlayer dielectric layer 32 can also be selected according to actual conditions. In this embodiment, the thickness of the interlayer dielectric structure 3 is 3200 Å.

[0122] Specifically, the contact holes include a first contact hole 33, a second contact hole 34, a third contact hole 36, a fourth contact hole 37, a first gate contact hole 35, and a second gate contact hole 38. The first contact hole 33 and the second contact hole 34 respectively penetrate the interlayer dielectric structure 3 on opposite sides of the first gate structure 16 and expose the metal silicide layer 18 on the upper surface of the first source / drain region 131 on their bottom surfaces. The first gate contact hole 35 penetrates the interlayer dielectric structure 3 directly above the first gate conductive layer 161 and exposes the metal silicide layer 18 on the upper surface of the first gate conductive layer 161 on its bottom surface. The third contact hole 36 and the fourth contact hole 37 respectively penetrate the interlayer dielectric structure 3 on opposite sides of the second gate structure 17 and expose the metal silicide layer 18 on the upper surface of the second source / drain region 141 on their bottom surfaces. The second gate contact hole 38 penetrates the interlayer dielectric structure 3 directly above the second gate conductive layer 171 and exposes the metal silicide layer 18 on the upper surface of the second gate conductive layer 171 on its bottom surface.

[0123] Specifically, while ensuring the performance of the devices in device area 2, the opening shape and opening size of the contact holes (first contact hole 33, second contact hole 34, third contact hole 36, fourth contact hole 37, first gate contact hole 35 and second gate contact hole 38) can be selected according to the actual situation.

[0124] Specifically, while ensuring the performance of the devices in device region 2, the thickness of the electrode buffer layer 4 can be selected according to the actual situation.

[0125] Specifically, the electrode layer includes a first electrode 41, a second electrode 42, a third electrode 44, a fourth electrode 45, a first gate 43, and a second gate 46. The first electrode 41 fills the first contact hole 33 to form an ohmic contact with the first source / drain region 131 directly below it. The second electrode 42 fills the second contact hole 34 to form an ohmic contact with the first source / drain region 131 directly below it. The third electrode 44 fills the third contact hole 36 to form an ohmic contact with the second source / drain region 141 directly below it. The fourth electrode 45 fills the fourth contact hole 37 to form an ohmic contact with the second source / drain region 141 directly below it. The first gate 43 fills the first gate contact hole 35, and the second gate 46 fills the second gate contact hole 38.

[0126] Specifically, by using the contact structure fabrication method described in Example 1 to fabricate the contact structure in the device region 2 of the wafer structure, the performance and yield of the contact structure are improved, thereby improving the fabrication yield of the wafer structure.

[0127] The wafer structure in this embodiment uses the contact structure fabrication method described in Embodiment 1 to fabricate the contact structure in the device region 2 of the wafer structure, thereby improving the performance and yield of the contact structure.

[0128] In summary, the wafer structure and contact structure fabrication method of the present invention improves the contact structure fabrication process by forming an intermediate layer covering the upper surface of the edge buffer layer before forming the interlayer dielectric structure. This avoids the complete removal of the edge buffer layer in the edge region during the contact hole fabrication process, providing a better adhesion surface for the subsequent electrode buffer layer formed directly above the edge region. This reduces the probability of the electrode buffer layer directly above the edge region peeling off, thereby reducing the impact of the electrode buffer layer peeling off from blocking the contact hole and affecting the filling of the electrode layer. Furthermore, it eliminates the step of directly removing the electrode buffer layer directly above the edge region after forming the electrode buffer layer, improving the performance of the contact structure. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0129] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a contact structure, characterized in that, Includes the following steps: A semiconductor structure is provided, including a device region and an edge region surrounding the device region. Multiple device structures are formed in the device region, and the upper surface of the device region is higher than the upper surface of the edge region. The upper surface layer of the edge region is provided with an edge buffer layer of a predetermined thickness. An intermediate layer covering the upper surface of the edge buffer layer and an interlayer dielectric structure covering the exposed upper surface of the semiconductor structure and the upper surface of the intermediate layer are formed sequentially. A patterned masking layer is formed covering the upper surface of the interlayer dielectric structure directly above the device region, and a contact hole is formed based on the masking layer to penetrate the interlayer dielectric structure. At the same time, the interlayer dielectric structure directly above the edge region and at least part of the intermediate layer are removed, and the bottom surface of the contact hole exposes the corresponding area of ​​the device structure. An electrode buffer layer and an electrode layer filling the contact hole are sequentially formed, located directly above the edge area and covering the inner wall and bottom surface of the contact hole.

2. The method for manufacturing the contact structure according to claim 1, characterized in that: The semiconductor structure includes a stacked structure, a first well region of a first conductivity type, a second well region of a second conductivity type, an isolation structure, a first source / drain region of a second conductivity type, a second source / drain region of a first conductivity type, a first gate structure, and a second gate structure. The stacked structure includes a substrate of a second conductivity type and an epitaxial layer of a first conductivity type stacked sequentially. The first well region and the second well region are located on the upper surface of the epitaxial layer. The isolation structure is embedded in the epitaxial layer surrounding the first well region and the second well region, respectively. The first gate structure is located on the upper surface of the first well region. The first source / drain region is located on the upper surface of the first well region on opposite sides of the first gate structure. The second gate structure is located on the upper surface of the second well region. The second source / drain region is located on the upper surface of the second well region on opposite sides of the second gate structure.

3. The method for manufacturing the contact structure according to claim 2, characterized in that: The semiconductor structure further includes a stress layer that covers the exposed surfaces of the first well region, the second well region, the first gate structure, and the second gate structure.

4. The method for manufacturing the contact structure according to claim 1, characterized in that: After the intermediate layer is formed but before the interlayer medium structure is formed, the method further includes a step of smoothing the upper surface of the intermediate layer.

5. The method for manufacturing the contact structure according to claim 4, characterized in that: Methods for planarizing the upper surface of the intermediate layer include plasma etching.

6. The method for manufacturing the contact structure according to claim 1, characterized in that: The intermediate layer is made of the same material as the edge buffer layer; or the crystal structure type of the edge buffer layer is the same as the crystal structure type of the intermediate layer, wherein the crystal structure type of the intermediate layer includes polycrystalline and amorphous.

7. The method for manufacturing the contact structure according to claim 1, characterized in that: The upper surface of the intermediate layer is not higher than the upper surface of the epitaxial layer in the device region.

8. The method for manufacturing the contact structure according to claim 1, characterized in that: The interlayer dielectric structure includes a first interlayer dielectric layer and a second interlayer dielectric layer stacked sequentially.

9. The method for manufacturing the contact structure according to claim 1, characterized in that: The electrode buffer layer directly above the edge region covers the upper surface of the edge buffer layer.

10. A wafer structure, characterized in that, The contact structure of at least one semiconductor device in the wafer structure is fabricated using the contact structure fabrication method described in any one of claims 1 to 9.

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