Test structure and test method of test structure

Abstract

The invention discloses a test structure and a test method of the test structure, and the test structure comprises at least two test array units, each test array unit is provided with a different number of transistors; grid electrodes and source electrodes of the transistors in all the test array units are electrically connected with the substrate; the drain electrodes of the transistors in each test array unit are electrically connected. A plurality of test array units are arranged, and grid electrodes and source electrodes of transistors in all the test array units are electrically connected with a substrate, so that when different test array units are measured, the introduced leakage current values of other paths are close, and in the subsequent calculation process, the introduced leakage current values of other paths can be counteracted mutually; therefore, the calculation precision of the leakage current of the single transistor is improved. In addition, due to the arrangement of more test array units, the influence caused by abnormal leakage current of part of the test array units can be eliminated, so that the calculation precision of the leakage current of a single transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a test structure and a test method of the test structure. BACKGROUND

[0002] In the field of semiconductor manufacturing, with the development of technology, the size of semiconductor devices is getting smaller and smaller, and the complexity is getting higher and higher. In order to monitor the manufacturing process of semiconductor devices and ensure the reliability of semiconductor devices, it is a common practice to form a test structure (test key) in the semiconductor device for testing and simulation of some key parameters of the semiconductor device to ensure the quality of the semiconductor device out of the factory.

[0003] The test structure is usually manufactured in the same semiconductor process as the semiconductor devices in the wafer, and the test structure and the semiconductor devices have a mutual correspondence relationship. Each layer of interconnection line in the semiconductor device corresponds to the test line in the same layer in the test structure, and each plug in the semiconductor device corresponds to the test plug in the same layer in the test structure. Since the test structure and the semiconductor device are prepared in the same process and have a mutual correspondence relationship, the performance of the wafer semiconductor device can be obtained by detecting the performance of the test structure. The performance of the semiconductor device in the wafer is reflected by the test structure, avoiding the damage to the semiconductor device in the wafer.

[0004] However, the test structure in the prior art still has many problems in the test process. SUMMARY

[0005] The technical problem solved by the present application is to provide a test structure and a test method of the test structure to improve the calculation accuracy of the single transistor leakage current.

[0006] To solve the above problems, the present application provides a test structure, comprising: at least 2 test array units, each of the test array units having a different number of transistors; the gate, source and substrate of the transistors in all the test array units are electrically connected; the drain of the transistors in each of the test array units is electrically connected.

[0007] Optionally, it further comprises: a first interconnection structure, which electrically connects the gate, source and substrate of the transistors in all the test array units.

[0008] Optionally, it further comprises: at least 2 second interconnection structures, which respectively electrically connect the drain of the transistors in each of the test array units.

[0009] Optionally, the first interconnection structure comprises: a plurality of first conductive plugs, the plurality of first conductive plugs being electrically connected with the gate, the source and the substrate of the transistor in all the test array units; and a first conductive layer, the first conductive layer being electrically connected with all the first conductive plugs.

[0010] Optionally, each of the second interconnection structures comprises: a plurality of second conductive plugs, the plurality of second conductive plugs being electrically connected with the drain of the transistor in the corresponding one of the test array units; and a second conductive layer, the second conductive layer being electrically connected with all the second conductive plugs corresponding to the one of the test array units.

[0011] Optionally, the first conductive layer and the second conductive layer are electrically isolated, and the first conductive layer and the second conductive layer are located in the same or different process layers.

[0012] Optionally, the test structure further comprises: a first test key, the first test key being electrically connected with the first interconnection structure.

[0013] Optionally, the test structure further comprises: at least two second test keys, the at least two second test keys being respectively electrically connected with the at least two second interconnection structures.

[0014] Correspondingly, the present application also provides a test method of the test structure, comprising: providing the test structure according to any one of the above technical solutions; applying a first voltage to the gate, the source and the substrate of the transistor in all the test array units; applying a second voltage to the drain of the transistor in each of the test array units; measuring the total drain current of the drain of the transistor in each of the test array units; and obtaining the drain current of a single transistor based on the number of the transistors in each of the test array units and the total drain current of each of the test array units.

[0015] Optionally, the test structure further comprises: a first interconnection structure, the first interconnection structure electrically connecting the gate, the source and the substrate of the transistor in all the test array units.

[0016] Optionally, the test structure further comprises: at least two second interconnection structures, the at least two second interconnection structures respectively electrically connecting the drain of the transistor in each of the test array units.

[0017] Optionally, the test structure further comprises: a first test key, the first test key being electrically connected with the first interconnection structure.

[0018] Optionally, the test structure further comprises: at least two second test keys, the at least two second test keys being respectively electrically connected with the at least two second interconnection structures.

[0019] Optionally, based on the first test key, a first voltage is applied to the gate, source and substrate of the transistor in all the test array units.

[0020] Optionally, based on the at least two second test keys, a second voltage is applied to the drain of the transistor in each of the test array units.

[0021] Optionally, based on the at least two second test keys, the total drain current of the drain of the transistor in each of the test array units is measured.

[0022] Optionally, the first voltage is 0 volt, and the second voltage is the working voltage of the transistor.

[0023] Optionally, when the number of the test array units is two, the method for obtaining the drain current of the single transistor comprises: obtaining the difference of the total drain current corresponding to the two test array units; obtaining the difference of the number of the transistors in the two test array units; and taking the ratio of the difference of the total drain current to the difference of the number of the transistors as the drain current of the single transistor.

[0024] Optionally, when the number of the test array units is greater than two, the method for obtaining the drain current of the single transistor comprises: establishing a rectangular coordinate system; forming coordinate points by the number of the transistors in each of the test array units and the total drain current corresponding to each of the test array units, and distributing the coordinate points in the coordinate system; and taking the slope value of a trend line fitted by all the coordinate points as the drain current of the single transistor.

[0025] Optionally, the total drain current corresponding to each of the test array units is greater than the minimum accuracy value of a measuring machine.

[0026] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0027] In the test structure of the technical scheme of the present application, a plurality of test array units are arranged, and the gate, source and substrate of the transistor in all the test array units are electrically connected, so that the introduced other path drain current values are close when the different test array units are measured, and the introduced other path drain current values can be offset in the subsequent calculation process, thereby improving the calculation accuracy of the drain current of the single transistor. In addition, the arrangement of more test array units is beneficial to eliminating the influence of abnormal drain current of part of the test array units, thereby improving the calculation accuracy of the drain current of the single transistor.

[0028] In the test method of the test structure of the technical solution, a plurality of test array units are arranged, and the gate, source and substrate of the transistor in all test array units are electrically connected, so that the introduced other path leakage current values are close when measuring different test array units, and in the subsequent calculation process, the introduced other path leakage current values can be offset to each other, thereby improving the calculation accuracy of the single transistor leakage current. In addition, the arrangement of more test array units is beneficial to exclude the influence of abnormal leakage current of part of the test array units, thereby improving the calculation accuracy of the single transistor leakage current.

[0029] Further, when the number of test array units is 2, the method for obtaining the leakage current of a single transistor includes: obtaining the difference value of the total leakage current corresponding to the two test array units; obtaining the difference value of the number of transistors in the two test array units; and taking the ratio of the difference value of the total leakage current to the difference value of the number of transistors as the leakage current of a single transistor. When the number of test array units is 2, the calculation process for obtaining the leakage current of a single transistor is simple and fast.

[0030] Further, when the number of test array units is greater than 2, the method for obtaining the leakage current of a single transistor includes: establishing a rectangular coordinate system; forming coordinate points of the number of transistors and the corresponding total leakage current in each test array unit and distributing them in the coordinate system; and taking the slope value of the trend line fitted by all coordinate points as the leakage current of a single transistor. The trend line fitted by all coordinate points can eliminate the total leakage current corresponding to part of the test array units with measurement deviation, thereby improving the calculation accuracy of the leakage current of a single transistor. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a structural schematic diagram of a test structure;

[0032] Figure 2 is a structural schematic diagram of a test structure of an embodiment of the present application;

[0033] Figure 3 is a scatter diagram established based on the number of transistors and the total leakage current in each test array unit in the test method of the test structure of an embodiment of the present application. DETAILED DESCRIPTION

[0034] As described in the background, the test structure in the prior art still has many problems in the test process. The following will be specifically described with reference to the drawings.

[0035] Figure 1 is a structural schematic diagram of a test structure.

[0036] In the field of semiconductor, with the iteration of technology, the size of the device and the distance between devices are getting smaller and smaller, and the leakage current of the device cannot be ignored. With the light weight and small screen of electronic products, the leakage current requirements of semiconductor devices are getting higher and higher. In the application of silicon-based Micro-OLED, silicon-based Micro-LED, LCoS, etc., the driving circuit of the device will use MOS transistor, and the leakage current needs to be lower than 10fA. The minimum current value that can be measured by the conventional measurement machine is about 0.1pA, and it is difficult to accurately characterize the leakage current level of the device.

[0037] Since the conventional measurement machine cannot accurately measure the leakage current of a single transistor, the gate 100a, the source 100b, the drain 100c and the substrate 100d of a plurality of transistors 100 are connected in parallel to form a test array unit, the leakage current of the whole is measured, and then divided by the number of transistors 100 in the test array unit to characterize the leakage current of a single transistor 100.

[0038] However, the problem of measuring the leakage current of a single transistor 100 by a test array unit is that:

[0039] Because the number of transistors 100 in the test array unit is large, the leakage current of a single transistor 100 is small and fluctuates greatly, and is easily disturbed, and the leakage current of some transistors 100 in the test array unit is abnormal, which leads to the overall test result being too high or too low, thereby affecting the calculation accuracy of the leakage current of a single transistor.

[0040] Compared with directly testing a single transistor 100, the way of testing a test array unit will introduce other path leakage current, and the size of the introduced leakage current is related to the number and structure of the transistors 100 in the test array unit, that is, the measured leakage current is the sum of the actual leakage current and the other path leakage current, thereby affecting the calculation accuracy of the leakage current of a single transistor 100.

[0041] On this basis, the present application provides a test structure and a test method of the test structure, by setting a plurality of test array units, and electrically connecting the gate, the source and the substrate of the transistors in all test array units, to ensure that when different test array units are measured, the introduced other path leakage current value is close, and then in the subsequent calculation process, the introduced other path leakage current value can be offset each other, thereby improving the calculation accuracy of the leakage current of a single transistor. In addition, more test array units are set, which is beneficial to exclude the influence of abnormal leakage current of some test array units, thereby improving the calculation accuracy of the leakage current of a single transistor.

[0042] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0043] Figure 2 is a structural diagram of a test structure of an embodiment of the present application.

[0044] Please refer to Figure 2 A test structure comprises: at least two test array units, each test array unit having a different number of transistors 101; the gate 1011, the source 1012 and the substrate 1013 of the transistors 101 in all test array units are electrically connected; the drain 1014 of the transistors 101 in each test array unit is electrically connected.

[0045] By setting multiple test array units and electrically connecting the gate 1011, the source 1012 and the substrate 1013 of the transistors 101 in all test array units, it is ensured that the introduced other-path leakage current values are close when measuring different test array units, and thus the introduced other-path leakage current values can be offset in the subsequent calculation process, thereby improving the calculation accuracy of the leakage current of a single transistor 101. In addition, more test array units are set, which is beneficial to exclude the influence of abnormal leakage current of part of the test array units, thereby improving the calculation accuracy of the leakage current of a single transistor 101.

[0046] Please continue to refer to Figure 2 In this embodiment, for the convenience of illustration, three test array units are taken as an example, i.e., the first test array unit 201, the second test array unit 202 and the third test array unit 203; wherein the number of transistors 101 in the first test array unit 201 is 1, the number of transistors 101 in the second test array unit 202 is 2, and the number of transistors 101 in the third test array unit 203 is 3. It should be noted that in the actual process, in order to ensure that the total leakage current of each test array unit reaches the minimum accuracy value of the measuring machine, the number of transistors 101 in each test array unit will reach hundreds or thousands of orders of magnitude.

[0047] In this embodiment, the transistor 101 is a MOS transistor.

[0048] The test structure further comprises: a first interconnection structure 301, which electrically connects the gate 1011, the source 1012 and the substrate 1013 of the transistors 101 in all test array units.

[0049] Please continue to refer to Figure 2 In this embodiment, the first interconnection structure 301 electrically connects the gate 1011, the source 1012 and the substrate 1013 of the transistors 101 in the first test array unit 201, the second test array unit 202 and the third test array unit 203.

[0050] The test structure further comprises: at least two second interconnection structures, each of the at least two second interconnection structures electrically connecting the drain 1014 of the transistor 101 in each test array unit.

[0051] Please continue to refer to Figure 2 In this embodiment, since the number of test array units is three, the number of corresponding second interconnection structures is also three, i.e., the first sub-interconnection structure 302, the second sub-interconnection structure 303 and the third sub-interconnection structure 304. The first sub-interconnection structure 302 electrically connects the drain 1014 of the transistor 101 in the first test array unit 201; the second sub-interconnection structure 303 electrically connects the drain 1014 of the transistor 101 in the second test array unit 202; and the third sub-interconnection structure 304 electrically connects the drain 1014 of the transistor 101 in the third test array unit 203.

[0052] The first interconnection structure 301 comprises: a plurality of first conductive plugs 3011, the plurality of first conductive plugs 3011 being electrically connected to the gate 1011, the source 1012 and the substrate 1013 of the transistor 101 in all test array units; and a first conductive layer 3012, the first conductive layer 3012 being electrically connected to all first conductive plugs 3011.

[0053] Please continue to refer to Figure 2 In this embodiment, the plurality of first conductive plugs 3011 are electrically connected to the gate 1011, the source 1012 and the substrate 1013 of the transistor 101 in the first test array unit 201, the second test array unit 202 and the third test array unit 203.

[0054] Each second interconnection structure comprises: a plurality of second conductive plugs 3021, the plurality of second conductive plugs 3021 being electrically connected to the drain 1014 of the transistor 101 in the corresponding one test array unit; and a second conductive layer 3022, the second conductive layer 3022 being electrically connected to all second conductive plugs 3021 corresponding to one test array unit.

[0055] Please continue to refer to Figure 2In the embodiment, the first sub-interconnection structure 302, the second sub-interconnection structure 303 or the third sub-interconnection structure 304 each comprises: a plurality of second conductive plugs 3021; the plurality of second conductive plugs 3021 in the first sub-interconnection structure 302 are electrically connected to the drain 1014 of the transistor 101 in the first test array unit 201; the plurality of second conductive plugs 3021 in the second sub-interconnection structure 303 are electrically connected to the drain 1014 of the transistor 101 in the second test array unit 202; the plurality of second conductive plugs 3021 in the third sub-interconnection structure 304 are electrically connected to the drain 1014 of the transistor 101 in the third test array unit 203; a second conductive layer 3022; the second conductive layer 3022 in the first sub-interconnection structure 302 is electrically connected to all the second conductive plugs 3021 corresponding to the first test array unit 201; the second conductive layer 3022 in the second sub-interconnection structure 303 is electrically connected to all the second conductive plugs 3021 corresponding to the second test array unit 202; the second conductive layer 3022 in the third sub-interconnection structure 304 is electrically connected to all the second conductive plugs 3021 corresponding to the third test array unit 203.

[0056] Please continue to refer to Figure 2 In the embodiment, the first conductive layer 3012 and the second conductive layer 3022 are electrically isolated, and the first conductive layer 3012 and the second conductive layer 3022 are located in different process layers.

[0057] Please continue to refer to Figure 2 It should be noted that, in the embodiment, since the first conductive layer 3012 and the second conductive layer 3022 are located in different process layers, and the second conductive layer 3022 is located on the first conductive layer 3012, the second conductive plug 3021 in the first sub-interconnection structure 302, the second sub-interconnection structure 303 and the third sub-interconnection structure 304 cannot directly contact the drain 1014 of the transistor 101. In order to ensure that the second conductive plug 3021 in the first sub-interconnection structure 302, the second sub-interconnection structure 303 and the third sub-interconnection structure 304 can be electrically connected to the drain 1014 of the corresponding transistor 101, during the formation of the first interconnection structure 301, the first conductive plug 3011 and the first conductive layer 3012 also need to be formed on the drain 1014 of each transistor 101 at the same time, the second conductive plug 3021 in the first sub-interconnection structure 302, the second sub-interconnection structure 303 and the third sub-interconnection structure 304 respectively electrically contact the first conductive layer 3012 on the drain 1014 of the corresponding transistor 101, thereby realizing the electrical connection between the second conductive plug 3021 in the first sub-interconnection structure 302, the second sub-interconnection structure 303 and the third sub-interconnection structure 304 and the drain 1014 of the corresponding transistor 101.

[0058] In other embodiments, the first conductive layer and the second conductive layer are electrically isolated, and through proper wiring, the first conductive layer and the second conductive layer can also be located in the same process layer.

[0059] In the embodiment, the test structure further comprises a first test key 401, which is electrically connected with the first interconnection structure 301.

[0060] The test structure further comprises at least two second test keys, which are respectively electrically connected with the at least two second interconnection structures.

[0061] Please continue to refer to Figure 2 In the embodiment, since the number of the second interconnection structures is three, the number of the corresponding second test keys is also three, i.e., a first sub-test key 402, a second sub-test key 403 and a third sub-test key 404. Among them, the first sub-test key 402 is electrically connected with the first sub-interconnection structure 302; the second sub-test key 403 is electrically connected with the second sub-interconnection structure 303; and the third sub-test key 404 is electrically connected with the third sub-interconnection structure 304.

[0062] The number of test array units is preferably set to five. By setting the number of test array units to five, the total leakage current corresponding to part of the test array units with measurement deviation can be discarded, thereby improving the calculation accuracy of the leakage current of a single transistor 101; in addition, by setting the number of test array units to five, more test area can be avoided, and the test cost can be controlled.

[0063] Figure 3 The scatter diagram is established based on the number of transistors in each test array unit and the total leakage current in the test method of the test structure of the embodiment.

[0064] Correspondingly, the embodiment of the present application also provides a test method of a test structure, please continue to refer to Figure 2 , comprising: providing a test structure, the test structure comprising: at least two test array units, each test array unit having different numbers of transistors 101; the gate 1011, the source 1012 and the substrate 1013 of the transistors 101 in all test array units are electrically connected; the drain 1014 of the transistors 101 in each test array unit is electrically connected; a first voltage is applied to the gate 1011, the source 1012 and the substrate 1013 of the transistors 101 in all test array units; a second voltage is applied to the drain 1014 of the transistors 101 in each test array unit; the total leakage current of the drain 1014 of the transistors 101 in each test array unit is measured; and the leakage current of a single transistor 101 is obtained based on the number of transistors 101 in each test array unit and the total leakage current of each test array unit.

[0065] By setting multiple test array units, and electrically connecting the gate 1011, the source 1012 and the substrate 1013 of the transistor 101 in all test array units, it is ensured that the introduced other path leakage current values are close when measuring different test array units, and then in the subsequent calculation process, the introduced other path leakage current values can be offset to each other, so as to improve the calculation accuracy of the leakage current of a single transistor 101. In addition, more test array units are set, which is beneficial to exclude the influence of abnormal leakage current of part of the test array units, so as to improve the calculation accuracy of the leakage current of a single transistor 101.

[0066] It should be noted that the purpose of having different numbers of transistors 101 in each test array unit is to ensure that the total leakage current of each test array unit obtained by measurement has difference, so as to realize difference calculation. The transistors 101 in each test array unit are formed synchronously by using a global process technology, and the structure and electrical parameters of each transistor 101 are the same.

[0067] In the embodiment, the transistor 101 is a MOS transistor.

[0068] It should be noted that in the embodiment, the total leakage current corresponding to each test array unit is greater than the minimum accuracy value of the measurement machine. In order to ensure the measurement accuracy of the total leakage current of each test array unit by the measurement machine.

[0069] In the embodiment, since the leakage current of the transistor 101 is tested, the first voltage can be set to 0 volt, that is, the gate 1011, the source 1012 and the substrate 1013 of all transistors 101 are grounded, so that the channel of each transistor 101 is in the off state, so as to realize the test of the leakage current of each transistor 101; the second voltage can be set to the working voltage of the transistor 101, that is, used for testing the leakage current of the transistor 101 when it is off.

[0070] Please continue to refer to Figure 2 In the embodiment, in order to facilitate illustration, three test array units are taken as an example, that is, the first test array unit 201, the second test array unit 202 and the third test array unit 203; wherein the number of transistors 101 in the first test array unit 201 is 1, the number of transistors 101 in the second test array unit 202 is 2, and the number of transistors 101 in the third test array unit 203 is 3. It should be noted that in the actual process technology, in order to ensure that the total leakage current of each test array unit reaches the minimum accuracy value of the measurement machine, the number of transistors 101 in each test array unit will reach hundreds or thousands of orders of magnitude.

[0071] The test structure further comprises: a first interconnection structure 301, which electrically connects the gate 1011, the source 1012 and the substrate 1013 of the transistor 101 in all test array units.

[0072] Please continue to refer to Figure 2 In this embodiment, the first interconnection structure 301 electrically connects the gate 1011, the source 1012 and the substrate 1013 of the transistor 101 in the first test array unit 201, the second test array unit 202 and the third test array unit 203.

[0073] The test structure further comprises: at least two second interconnection structures, which respectively electrically connect the drain 1014 of the transistor 101 in each test array unit.

[0074] Please continue to refer to Figure 2 In this embodiment, since the number of test array units is 3, the number of corresponding second interconnection structures is also 3, which are the first sub-interconnection structure 302, the second sub-interconnection structure 303 and the third sub-interconnection structure 304. Among them, the first sub-interconnection structure 302 electrically connects the drain 1014 of the transistor 101 in the first test array unit 201; the second sub-interconnection structure 303 electrically connects the drain 1014 of the transistor 101 in the second test array unit 202; and the third sub-interconnection structure 304 electrically connects the drain 1014 of the transistor 101 in the third test array unit 203.

[0075] The first interconnection structure 301 comprises: a plurality of first conductive plugs 3011, which are electrically connected with the gate 1011, the source 1012 and the substrate 1013 of the transistor 101 in all test array units; and a first conductive layer 3012, which is electrically connected with all first conductive plugs 3011.

[0076] Please continue to refer to Figure 2 In this embodiment, the plurality of first conductive plugs 3011 are electrically connected with the gate 1011, the source 1012 and the substrate 1013 of the transistor 101 in the first test array unit 201, the second test array unit 202 and the third test array unit 203.

[0077] Each second interconnection structure comprises: a plurality of second conductive plugs 3021, which are electrically connected with the drain 1014 of the transistor 101 in the corresponding one test array unit; and a second conductive layer 3022, which is electrically connected with all second conductive plugs 3021 corresponding to one test array unit.

[0078] Please continue to refer to Figure 2In the embodiment, the first, second or third sub-interconnection structure 302, 303 or 304 comprises: a plurality of second conductive plugs 3021; the plurality of second conductive plugs 3021 in the first sub-interconnection structure 302 are electrically connected with the drain 1014 of the transistor 101 in the first test array unit 201; the plurality of second conductive plugs 3021 in the second sub-interconnection structure 303 are electrically connected with the drain 1014 of the transistor 101 in the second test array unit 202; the plurality of second conductive plugs 3021 in the third sub-interconnection structure 304 are electrically connected with the drain 1014 of the transistor 101 in the third test array unit 203; a second conductive layer 3022; the second conductive layer 3022 in the first sub-interconnection structure 302 is electrically connected with all the second conductive plugs 3021 corresponding to the first test array unit 201; the second conductive layer 3022 in the second sub-interconnection structure 303 is electrically connected with all the second conductive plugs 3021 corresponding to the second test array unit 202; the second conductive layer 3022 in the third sub-interconnection structure 304 is electrically connected with all the second conductive plugs 3021 corresponding to the third test array unit 203.

[0079] Please continue to refer to Figure 2 In the embodiment, the first conductive layer 3012 and the second conductive layer 3022 are located in different process layers. By distributing the first conductive layer 3012 and the second conductive layer 3022 in different process layers, the wiring between the first conductive layer 3012 and the second conductive layer 3022 is facilitated, and short circuit between the first conductive layer 3012 and the second conductive layer 3022 is effectively avoided.

[0080] Please continue to refer to Figure 2It should be noted that, in the embodiment, the first conductive layer 3012 and the second conductive layer 3022 are located in different process layers, and the second conductive layer 3022 is located on the first conductive layer 3012. Therefore, the second conductive plug 3021 in the first sub-interconnection structure 302, the second sub-interconnection structure 303, and the third sub-interconnection structure 304 cannot directly contact the drain 1014 of the transistor 101. In order to ensure that the second conductive plug 3021 in the first sub-interconnection structure 302, the second sub-interconnection structure 303, and the third sub-interconnection structure 304 can be electrically connected to the drain 1014 of the corresponding transistor 101, the first conductive plug 3011 and the first conductive layer 3012 also need to be formed on the drain 1014 of each transistor 101 during the formation of the first interconnection structure 301. The second conductive plug 3021 in the first sub-interconnection structure 302, the second sub-interconnection structure 303, and the third sub-interconnection structure 304 is electrically connected to the first conductive layer 3012 on the drain 1014 of the corresponding transistor 101, thereby realizing the electrical connection between the second conductive plug 3021 in the first sub-interconnection structure 302, the second sub-interconnection structure 303, and the third sub-interconnection structure 304 and the drain 1014 of the corresponding transistor 101.

[0081] In the embodiment, the test structure further includes a first test key 401, which is electrically connected to the first interconnection structure 301.

[0082] The test structure further includes at least two second test keys, which are respectively electrically connected to the at least two second interconnection structures.

[0083] Please continue to refer to Figure 3 In the embodiment, the number of the second interconnection structures is three, and the number of the corresponding second test keys is also three, i.e., the first sub-test key 402, the second sub-test key 403, and the third sub-test key 404. The first sub-test key 402 is electrically connected to the first sub-interconnection structure 302; the second sub-test key 403 is electrically connected to the second sub-interconnection structure 303; and the third sub-test key 404 is electrically connected to the third sub-interconnection structure 304.

[0084] Based on the first test key 401, a first voltage V1 is applied to the gate 1011, the source 1012, and the substrate 1013 of the transistor 101 in all test array units.

[0085] In the embodiment, based on the first test key 401, the first voltage V1 is respectively applied to the gate 1011, the source 1012, and the substrate 1013 of the transistor 101 in the first test array unit 201, the second test array unit 202, and the third test array unit 203.

[0086] A second voltage V2 is applied to the drain 1014 of the transistor 101 in each test array unit based on at least two second test keys.

[0087] In this embodiment, the second voltage V2 is applied to the drain 1014 of the transistor 101 in the first test array unit 201 based on the first sub-test key 402; the second voltage V2 is applied to the drain 1014 of the transistor 101 in the second test array unit 202 based on the second sub-test key 403; and the second voltage V2 is applied to the drain 1014 of the transistor 101 in the third test array unit 203 based on the third sub-test key 404.

[0088] The total drain current of the drain 1014 of the transistor 101 in each test array unit is measured based on at least two second test keys.

[0089] In this embodiment, the total drain current of the drain 1014 of the transistor 101 in the first test array unit 201 is measured based on the first sub-test key 402; the total drain current of the drain 1014 of the transistor 101 in the second test array unit 202 is measured based on the second sub-test key 403; and the total drain current of the drain 1014 of the transistor 101 in the third test array unit 203 is measured based on the third sub-test key 404.

[0090] The number of test array units is preferably set to 5. By setting the number of test array units to 5, the total drain current corresponding to the test array unit with measurement deviation can be discarded, thereby improving the calculation accuracy of the drain current of the single transistor 101; in addition, by setting the number of test array units to 5, the test area occupied can be reduced, and the test cost can be controlled.

[0091] Please refer to Figure 3 In this embodiment, when the number of test array units is greater than 2, the method for obtaining the drain current of the single transistor 101 includes: establishing a rectangular coordinate system; forming coordinate points by the number of transistors 101 in each test array unit and the corresponding total drain current, and distributing the coordinate points in the coordinate system; and taking the slope value of the trend line fitted by all the coordinate points as the drain current of the single transistor 101. By fitting the trend line, the total drain current corresponding to the test array unit with measurement deviation can be discarded, thereby improving the calculation accuracy of the drain current of the single transistor 101.

[0092] ​ Six coordinate points are shown in the coordinate system, the horizontal coordinate of the coordinate system is the number of transistors 101 in each test array unit (n1-n6), and the vertical coordinate is the corresponding total drain current (Id1-Id6) of each test array unit. Among them, the total drain currents Id2 and Id4 have deviation and are discarded in linear fitting.

[0093] In other embodiments, the number of test array units can also be 2 or 3. When the number of test array units is 2, the method for obtaining the drain current of a single transistor includes: obtaining the difference |Id1-Id2| of the total drain current corresponding to the 2 test array units; obtaining the difference |n1-n2| of the number of transistors in the 2 test array units; and taking the ratio |Id1-Id2| / |n1-n2| of the difference of the total drain current and the difference of the number of transistors as the drain current of a single transistor. When the number of test array units is 2, the calculation process for obtaining the drain current of a single transistor is simple and fast.

[0094] Although the present application has been disclosed as above, it is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A test structure, characterized in that, include: At least two test array units, each of which contains a different number of transistors; The gate, source, and substrate of the transistors in all of the test array units are electrically connected; The drain electrical connection of the transistor in each of the test array units.

2. The test structure as described in claim 1, characterized in that, Also includes: A first interconnect structure electrically connects the gate, source, and substrate of all the transistors in the test array cells.

3. The test structure as described in claim 2, characterized in that, Also includes: At least two second interconnect structures, wherein the at least two second interconnect structures electrically connect the drain of the transistor in each of the test array units.

4. The test structure as described in claim 3, characterized in that, The first interconnect structure includes: a plurality of first conductive plugs, the plurality of first conductive plugs being electrically connected to the gate, source and substrate of the transistors in all the test array units; and a first conductive layer, the first conductive layer being electrically connected to all the first conductive plugs.

5. The test structure as described in claim 4, characterized in that, Each of the second interconnect structures includes: a plurality of second conductive plugs, the plurality of second conductive plugs being electrically connected to the drain of the transistor in a corresponding test array unit; and a second conductive layer, the second conductive layer being electrically connected to all the second conductive plugs corresponding to the test array unit.

6. The test structure as described in claim 5, characterized in that, The first conductive layer and the second conductive layer are electrically isolated, and the first conductive layer and the second conductive layer are located in the same or different process layers.

7. The test structure as described in claim 2, characterized in that, Also includes: A first test key is electrically connected to a first interconnect structure.

8. The test structure as described in claim 3, characterized in that, Also includes: At least two second test keys, each of which is electrically connected to one of the at least two second interconnect structures.

9. A test method for a test structure, characterized in that, include: Provide a test structure as described in any one of claims 1 to 8; A first voltage is applied to the gate, source, and substrate of the transistors in all of the test array cells; A second voltage is applied to the drain of the transistor in each of the test array units; Measure the total leakage current of the transistor drain in each of the test array units; The leakage current of a single transistor is obtained based on the number of transistors in each test array unit and the total leakage current of each test array unit.

10. The test method for the test structure as described in claim 9, characterized in that, The test structure further includes a first interconnect structure, which electrically connects the gate, source, and substrate of all the transistors in the test array units.

11. The test method for the test structure as described in claim 9, characterized in that, The test structure further includes at least two second interconnect structures, wherein the at least two second interconnect structures electrically connect the drain of the transistor in each of the test array units.

12. The test method for the test structure as described in claim 10, characterized in that, The test structure further includes a first test key, which is electrically connected to a first interconnect structure.

13. The test method for the test structure as described in claim 11, characterized in that, The test structure further includes at least two second test keys, which are electrically connected to the at least two second interconnection structures respectively.

14. The test method for the test structure as described in claim 12, characterized in that, Based on the first test key, a first voltage is applied to the gate, source, and substrate of the transistors in all the test array units.

15. The test method for the test structure as described in claim 13, characterized in that, A second voltage is applied to the drain of the transistor in each of the at least two second test keys.

16. The test method for the test structure as described in claim 13, characterized in that, Based on the at least two second test keys, the total leakage current of the transistor drain in each of the test array units is measured.

17. The test method for the test structure as described in claim 13, characterized in that, The first voltage is 0 volts; the second voltage is the operating voltage of the transistor.

18. The test method for the test structure as described in claim 9, characterized in that, When the number of test array units is 2, the method for obtaining the leakage current of a single transistor includes: obtaining the difference between the total leakage currents corresponding to the 2 test array units; obtaining the difference between the number of transistors in the 2 test array units; and taking the ratio of the difference between the total leakage currents and the difference between the number of transistors as the leakage current of a single transistor.

19. The test method for the test structure as described in claim 9, characterized in that, When the number of test array units is greater than 2, the method for obtaining the leakage current of a single transistor includes: establishing a Cartesian coordinate system; forming coordinate points by the number of transistors in each test array unit and the corresponding total leakage current, and distributing them in the coordinate system; and using the slope value of the trend line fitted by all the coordinate points as the leakage current of a single transistor.

20. The test method for the test structure as described in claim 9, characterized in that, The total leakage current corresponding to each of the test array units is greater than the minimum accuracy value of the measurement instrument.

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