Electronic device and manufacturing method and packaging structure thereof

Abstract

The invention provides an electronic device, a manufacturing method thereof and a packaging structure. The electronic device includes a first semiconductor device, a second semiconductor device, an encapsulation layer, and a circuit layer. The second semiconductor component is adjacent to the first semiconductor component. The encapsulation layer has a first side and surrounds the first semiconductor device and the second semiconductor device. The circuit layer is arranged on the first side of the packaging layer. The encapsulation layer has a first thickness, and the first semiconductor component has a second thickness. The first thickness is greater than the second thickness. The difference between the first thickness and the second thickness is larger than half of the first thickness and smaller than three times of the second thickness. In a plan view, the encapsulation layer has a first area, the first semiconductor component has a second area, the second semiconductor component has a third area, and the sum of the second area and the third area is greater than half of the first area.

Description

Technical Field

[0001] This disclosure relates to an electronic device, its manufacturing method, and its packaging structure, and more particularly to an electronic device with better structural reliability, its manufacturing method, and its packaging structure. Background Technology

[0002] Electronic or semiconductor devices can be formed using panel-level package (PLP) or wafer-level package (WLP) processes. During these processes, warping can occur due to the mismatch in the chemical shrinkage or thermal expansion coefficients of the package layer materials. When the package structure detaches from the carrier substrate, the lack of support from the carrier substrate causes a sharp amplification of the warping, leading to cracks in the package layer and affecting the structural reliability of the product. Summary of the Invention

[0003] This disclosure relates to an electronic device with superior structural reliability.

[0004] This disclosure relates to a method for manufacturing an electronic device, which can reduce process risks.

[0005] This disclosure relates to a packaging structure with superior structural reliability.

[0006] According to embodiments disclosed herein, an electronic device includes a first semiconductor component, a second semiconductor component, a packaging layer, and a circuit layer. The second semiconductor component is adjacent to the first semiconductor component. The packaging layer has a first side and surrounds the first semiconductor component and the second semiconductor component. The circuit layer is disposed on the first side of the packaging layer. The packaging layer has a first thickness, and the first semiconductor component has a second thickness. The first thickness is greater than the second thickness. The difference between the first thickness and the second thickness is greater than half of the first thickness and less than three times the second thickness. In top view, the packaging layer has a first area, the first semiconductor component has a second area, the second semiconductor component has a third area, and the sum of the second area and the third area is greater than half of the first area.

[0007] According to embodiments disclosed herein, a method for manufacturing an electronic device includes the following steps: Providing a first semiconductor component and a second semiconductor component. The first semiconductor component is adjacent to the second semiconductor component. Forming an encapsulation layer to surround the first semiconductor component and the second semiconductor component. The encapsulation layer has a first side. Forming a circuit layer on the first side of the encapsulation layer. The encapsulation layer has a first thickness, and the first semiconductor component has a second thickness, wherein the first thickness is greater than the second thickness, and the difference between the first thickness and the second thickness is greater than half of the first thickness and less than three times the second thickness. In top view, the encapsulation layer has a first area, the first semiconductor component has a second area, the second semiconductor component has a third area, and the sum of the second area and the third area is greater than half of the first area.

[0008] According to embodiments disclosed herein, a package structure includes a first semiconductor component, a second semiconductor component, and a package layer. The second semiconductor component is adjacent to the first semiconductor component. The package layer surrounds the first semiconductor component and the second semiconductor component. The package layer has a first thickness, and the first semiconductor component has a second thickness, the first thickness being greater than the second thickness. The difference between the first thickness and the second thickness is greater than half of the first thickness and less than three times the second thickness. Viewed from above, the package layer has a first area, the first semiconductor component has a second area, the second semiconductor component has a third area, and the sum of the second area and the third area is greater than half of the first area.

[0009] Based on the above, in the embodiments disclosed herein, the first thickness of the encapsulation layer is greater than the second thickness of the first semiconductor component, and the difference between the first thickness and the second thickness is greater than half of the first thickness and less than three times the second thickness. Viewed from above, the sum of the second area of ​​the first semiconductor component and the third area of ​​the second semiconductor component is greater than half of the first area of ​​the encapsulation layer. This design effectively reduces the risk of the encapsulation layer cracking due to warping of the encapsulation structure, enabling the electronic device disclosed herein to have better structural reliability.

[0010] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1A This is a top view schematic diagram of an embodiment of the packaging structure disclosed herein;

[0012] Figure 1B It is along Figure 1A A schematic cross-sectional view of line II;

[0013] Figure 2 This diagram illustrates the relationship between the thickness of the semiconductor component from the back side to the second side of the encapsulation layer and the warpage of the encapsulation structure.

[0014] Figure 3 This is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0015] Figures 4A to 4F This is a cross-sectional schematic diagram of partial steps in a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0016] Figures 5A to 5E This is a cross-sectional schematic diagram of partial steps in a method for manufacturing an electronic device according to another embodiment of the present disclosure;

[0017] Figure 6 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0018] Figures 7A to 7C This is a cross-sectional schematic diagram of partial steps in a method for manufacturing an electronic device according to another embodiment of the present disclosure;

[0019] Figures 8A to 8C This is a cross-sectional schematic diagram of partial steps in a method for manufacturing an electronic device according to another embodiment of the present disclosure.

[0020] Explanation of reference numerals in the attached figures

[0021] 10, 30, 50: Supporting substrate;

[0022] 20, 40, 60: Adhesive layer;

[0023] 100, 100', 100a, 100c: Package structure;

[0024] 110, 110', 110a: First semiconductor component;

[0025] 111, 111a: Back side;

[0026] 112, 122: Semiconductor units;

[0027] 113, 113a: Active side;

[0028] 114, 124: Conductive pads;

[0029] 116, 126: Insulation layer;

[0030] 120, 120a: Second semiconductor components;

[0031] 121, 121a: Reverse side;

[0032] 123, 123a: Active side;

[0033] 130, 130', 130a, 130c: Encapsulation layers;

[0034] 131, 131a, 131c: First side;

[0035] 132a, 132c: Packaging section;

[0036] 133, 133', 133a, 133c: Second side;

[0037] 134a, 134c: Support parts;

[0038] 136a, 136c: Adhesive parts;

[0039] 200a, 200b, 200c, 200d, 200e: Electronic devices;

[0040] 210: Circuit layer;

[0041] 212: Insulation layer;

[0042] 214: Conductive layer;

[0043] 214a: Connecting part;

[0044] 214b: Trace;

[0045] 220: Joining assembly;

[0046] 230: Insulation layer;

[0047] 240, 240c: Thermally conductive structure;

[0048] 241: Upper surface;

[0049] 242: Main body;

[0050] 244: Extension;

[0051] 246: Heat dissipation fin section;

[0052] A: The thickness of the semiconductor component;

[0053] A1: First area;

[0054] A2: Second area;

[0055] A3: Third area;

[0056] B: Vertical distance between the semiconductor component and the second side of the encapsulation layer;

[0057] C1, C2, C3, C4: Curves;

[0058] T1, T1', T11, T21: First thickness;

[0059] T2, T12, T22: Second thickness;

[0060] T3: Third thickness;

[0061] T4, T14, T24: Fourth thickness;

[0062] T5, T5': Fifth thickness;

[0063] S1: Side view;

[0064] S2: Side surface;

[0065] L: Length;

[0066] W: Width. Detailed Implementation

[0067] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0068] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that function identically but have different names.

[0069] In the following description and claims, the words “containing” and “including” are open-ended terms, and therefore should be interpreted as “containing but not limited to…”.

[0070] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element of the figures to another element. It is understood that if the apparatus in the figures is flipped so that it is upside down, the element described as being on the "below" side will become the element on the "above" side.

[0071] In some embodiments disclosed herein, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct (indirect) contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding engagement and connection may also include situations where both structures are movable or both structures are fixed. In addition, the term "coupling" includes the transfer of energy between two structures through direct or indirect electrical connection, or the transfer of energy between two separate structures through mutual induction.

[0072] It should be understood that when an element or membrane is referred to as being "on" or "connected" to another element or membrane, it can be directly on or directly connected to that other element or membrane, or there may be an inserted element or membrane between them (indirect cases). Conversely, when an element is referred to as being "directly" on or "directly connected" to another element or membrane, there may be no inserted element or membrane between them.

[0073] The terms “approximately,” “equal to,” “equivalent to,” “same,” “substantially,” or “roughly” are generally interpreted as being within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Furthermore, the phrases “range from the first value to the second value” or “range between the first value and the second value” indicate that the range includes the first value, the second value, and other values ​​in between.

[0074] In this disclosure, the area, width, thickness, or height of each component, or the distance or spacing between components, can be measured using an optical microscopy (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structural image including the component to be measured, and to measure the area, width, thickness, or height of each component, or the distance or spacing between components.

[0075] In this disclosure, roughness judgment is defined by SEM observation, where the peaks and valleys of surface undulations on an uneven surface have a distance difference of 0.15 micrometers (μm) to 1 μm. Roughness judgment measurement can involve using SEM, transmission electron microscope (TEM), etc., to observe the surface undulations at an appropriate magnification, and comparing the undulations by taking a sample of unit length (e.g., 10 μm) to determine its roughness range. Here, "appropriate magnification" means that at least one surface can show at least 10 undulating peaks in the field of view at this magnification, indicating a roughness (Rz) or average roughness (Ra).

[0076] As used herein, the terms “film” and / or “layer” can refer to any continuous or discontinuous structure and material (such as materials deposited by the methods disclosed herein). For example, films and / or layers can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers, or partial or complete atomic layers, or atomic and / or molecular clusters. Films or layers may contain materials or layers with pinholes and may be at least partially continuous.

[0077] Although the terms first, second, third… can be used to describe multiple components, the components are not limited to these terms. These terms are used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but rather replaced by first, second, third… in the order of the elements declared in the claims. Therefore, in the following description, a first component may be a second component in the claims.

[0078] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein.

[0079] It should be understood that the technical features of several different embodiments can be replaced, reorganized, or mixed to complete other embodiments without departing from the spirit of this disclosure.

[0080] The electronic devices disclosed herein may include, but are not limited to, power modules, semiconductor devices, semiconductor packaging devices, display devices, antenna devices, sensing devices, light-emitting devices, or splicing devices. Electronic devices may include bendable or flexible electronic devices. Electronic devices may include electronic components. Electronic components may include semiconductor components, passive components, active components, or combinations thereof, such as integrated circuit chips, high-bandwidth memory, capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS) components, liquid crystal chips, etc., but are not limited to these. Diodes may include light-emitting diodes or non-light-emitting diodes. Diodes include PN junction diodes, PIN diodes, or constant current diodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (mini LEDs), micro LEDs, quantum dot LEDs, fluorescent, phosphorescent, or other suitable materials, or combinations thereof, but are not limited to these. Sensors may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but are not limited thereto. The following description uses a display device as an example of an electronic device to illustrate the content of this disclosure, but this disclosure is not limited thereto. According to embodiments of this disclosure, the manufacturing method of the provided electronic device can be applied, for example, to wafer-level package (WLP) or panel-level package (PLP) processes, and can employ chip-first or chip-last / RDL-first processes, as will be further described below. The electronic device referred to in this disclosure may include a system-on-package (SoC), a system-in-package (SiP), an antenna-in-package (AiP), a co-packaged optical (CPO), or a combination thereof, but is not limited thereto.

[0081] Reference will now be made in detail to the exemplary embodiments disclosed herein, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0082] Figure 1A This is a top view schematic diagram of an embodiment of the packaging structure disclosed herein. Figure 1B It is along Figure 1A A schematic cross-sectional view of line II. Figure 2 This diagram illustrates the relationship between the thickness of the semiconductor component from the back side to the second side of the encapsulation layer and the warpage of the encapsulation structure.

[0083] Please refer to the following at the same time. Figure 1A as well as Figure 1B In this embodiment, the encapsulation structure 100 includes a first semiconductor component 110, a second semiconductor component 120, and an encapsulation layer 130. The second semiconductor component 120 is adjacent to the first semiconductor component 110. The encapsulation layer 130 surrounds the first semiconductor component 110 and the second semiconductor component 120. The encapsulation layer 130 has a first thickness T1, and the first semiconductor component 110 has a second thickness T2, wherein the first thickness T1 is greater than the second thickness T2. The difference between the first thickness T1 and the second thickness T2 is greater than half of the first thickness T1 and less than three times the second thickness T2. Viewed from above, the encapsulation layer 130 has a first area A1, the first semiconductor component 110 has a second area A2, and the second semiconductor component 120 has a third area A3, wherein the sum of the second area A2 and the third area A3 is greater than half of the first area A1.

[0084] In detail, the encapsulation structure 100 of this embodiment is disposed on the carrier substrate 10 via the adhesive layer 20, that is, the carrier substrate 10 serves as a support structure to support the encapsulation structure 100. In one embodiment, the carrier substrate 10 is, for example, quartz, glass, stainless steel, sapphire, other suitable materials, or combinations thereof, but is not limited thereto. In one embodiment, the adhesive layer 20 may be a temporary adhesive layer, which may include a thermally-type release material or an optically-type release material with adhesive properties, so that subsequently formed working units, components, or films can be temporarily attached to the adhesive layer 20. For example, the adhesive layer 20 may be a thermal release tape (HRT) or a light-to-heat-conversion (LTHC) release coating. When an optical release material is used to form adhesive layer 20, the optical release material loses its adhesiveness when exposed to radiation, such as ultraviolet light (UV light), allowing components or films formed on it to be peeled off from adhesive layer 20. For example, adhesive layer 20 may be a UV adhesive.

[0085] Furthermore, the second semiconductor component 120 is adjacent to the first semiconductor component 110. Here, "adjacent" means adjacent in the horizontal direction (e.g., the X direction). According to some embodiments, the distance between the first semiconductor component 110 and the second semiconductor component 120 may be greater than or equal to 0.2 * the first length L1 of the second semiconductor component 120 and less than or equal to 1.5 * the first length L1 of the second semiconductor component 120, thereby avoiding signal interference between semiconductor components, but is not limited thereto. The second semiconductor component 120 of this embodiment includes at least one semiconductor cell (schematically shown as a semiconductor cell 122). In one embodiment, a single semiconductor cell 122 may be, for example, a die, a component having a semiconductor structure, but is not limited thereto. In one embodiment, the second semiconductor component 120 may include a plurality of stacked semiconductor cells, and the stacked plurality of semiconductor cells may be, for example, memory (e.g., RAM), but is not limited thereto. In one embodiment, the second semiconductor component 120 may also include conductive pads 124 and an insulating layer 126 located between the conductive pads 124. The conductive pads 124 of the second semiconductor component 120 and the insulating layer 126 located between the conductive pads 124 are contactable with the adhesive layer 20. In one embodiment, the second semiconductor component 120 may include a plurality of stacked semiconductor cells 122, conductive pads 124, and an insulating layer 126 located between the conductive pads 124. The second thickness T2 of the first semiconductor component 110, in cross-sectional view, is the thickness of the first semiconductor component 110 surrounded by the encapsulation layer 130, and this thickness can be measured along the Z direction. The third thickness T3 of the second semiconductor component 120, in cross-sectional view, is the thickness of the second semiconductor component 120 surrounded by the encapsulation layer 130, and this thickness can be measured along the Z direction. In one embodiment, the second thickness T2 of the first semiconductor component 110 is greater than the third thickness T3 of the second semiconductor component 120. In one embodiment, the first semiconductor component 110 may be, for example, the thickest semiconductor component in the package structure 100.

[0086] The encapsulation layer 130 has a first side 131 and a second side 133 opposite to each other, wherein the first side 131 contacts the adhesive layer 20. The active surface 113 of the first semiconductor component 110 and the active surface 123 of the second semiconductor component 120 are substantially coplanar with the first side 131 of the encapsulation layer 130. In one embodiment, the back surface 111 of the first semiconductor component 110 and the back surface 121 of the second semiconductor component 120 are covered by the encapsulation layer 130. The encapsulation layer 130 surrounds the first semiconductor component 110 and the second semiconductor component 120. Here, the encapsulation layer 130 “surrounds” the semiconductor component (e.g., the first semiconductor component 110 or the second semiconductor component 120) can refer to a perspective view (i.e., orthographic projection) in the top view where the encapsulation layer 130 surrounds the semiconductor component, and in a cross-sectional view, “the side surface S1 of the encapsulation layer 130 is adjacent to the side surface S2 of the semiconductor component.” In other words, “the encapsulation layer 130 may include at least one accommodating space to accommodate the semiconductor component.” Figure 1B As shown, the encapsulation layer 130 can directly contact the side surfaces of the first semiconductor component 110 and the second semiconductor component 120. The encapsulation layer 130 provides waterproofing for the first semiconductor component 110 and the second semiconductor component 120, thereby improving the reliability of the encapsulation structure 100. In one embodiment, the ratio of the coefficient of thermal expansion of the encapsulation layer 130 to the coefficient of thermal expansion of a single semiconductor unit 122 is between 1.2 and 3. Through the above design, the risk of separation or breakage between the encapsulation layer 130 and the semiconductor component can be reduced. In one embodiment, the encapsulation layer 130 may include any suitable organic or inorganic material, such as epoxy molding compound (EMC), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), but is not limited thereto.

[0087] Please refer to this again. Figure 1BThe first thickness T1 of the encapsulation layer 130 is the vertical distance (e.g., along the Z direction) between the second side 133 and the first side 131 of the encapsulation layer 120. Since the first semiconductor component 110 and the second semiconductor component 120 can be directly attached to the adhesive layer 20 and approximately flush with the first side 131 of the encapsulation layer 130, the second thickness T2 of the first semiconductor component 110 can also be the vertical distance between the back surface 111 of the first semiconductor component 110 and the first side 131 of the encapsulation layer 130, and the third thickness T3 of the second semiconductor component 120 can also be the vertical distance between the back surface 121 of the second semiconductor component 120 and the first side 131 of the encapsulation layer 130. In one embodiment, the second thickness T2 of the first semiconductor component 110 is less than the first thickness T1 of the encapsulation layer 130, and the third thickness T3 of the second semiconductor component 120 is less than the second thickness T2 of the first semiconductor component 110. In one embodiment, the third thickness T3 of the second semiconductor component 120 can be less than or equal to the first thickness T1 of the encapsulation layer 130.

[0088] On the other hand, the vertical distance between the back surface 111 of the first semiconductor component 110 and the second side 133 of the encapsulation layer 130 is a fourth thickness T4, and the vertical distance between the back surface 121 of the second semiconductor component 120 and the second side 133 of the encapsulation layer 130 is a fifth thickness T5. Here, the fourth thickness T4 is equal to the difference between the first thickness T1 and the second thickness T2, and the fifth thickness T5 is equal to the difference between the first thickness T1 and the thickness T3. More specifically, the fourth thickness T4 is a local thickness of the encapsulation layer 130. Here, "local" refers to the portion of the encapsulation layer 130 whose orthographic projection falls on the first semiconductor component 110, and whose thickness can be measured from the back surface 111 of the first semiconductor component 110 along the normal direction to the second side 133 of the encapsulation layer 130. The fourth thickness T4 is greater than the second thickness T2 of the first semiconductor component 110 and less than three times the first thickness T2 of the first semiconductor component 110. The fifth thickness T5 is a local thickness of the encapsulation layer 130. Here, "partial" refers to the portion of the encapsulation layer 130 whose orthographic projection falls on the second semiconductor component 120, and whose thickness can be measured from the back surface 121 of the second semiconductor component 120 along the normal direction to the second side 133 of the encapsulation layer 130. In one embodiment, the fourth thickness T4 is less than the fifth thickness T5.

[0089] Please refer to this again. Figure 1AViewed from above, the first semiconductor component 110, the second semiconductor component 120, and the encapsulation layer 130 have rectangular shapes. The encapsulation layer 130 has a first top-view area A1, where the first area A1 is equal to the length L multiplied by the width W. Here, the sum of the second top-view area A2 of the first semiconductor component 110 and the third top-view area A3 of the second semiconductor component 120 is greater than half of the first area A1 of the encapsulation layer 130. The "second top-view area A2" and "third top-view area A3" refer to the maximum length of one of the semiconductor components along a direction (e.g., the X direction) multiplied by the maximum width W along a second direction (e.g., the Y direction), where the first direction is perpendicular to the second direction.

[0090] Please refer to Figure 2 In this diagram, B and A will exhibit different degrees of warpage in the encapsulation layer at different scales. B represents the vertical distance between the semiconductor component and the second side of the encapsulation layer (e.g., ...). Figure 1B The fourth thickness T4 in the figure), while A represents the thickness of the semiconductor component (e.g., the thickness of the fourth thickness T4). Figure 1B The second thickness T2 in the diagram. Curves C1, C2, C3, and C4 represent different proportions of semiconductor components per unit area. For example, the proportion of semiconductor components in the package structure of curve C1 is greater than that in the package structure of curve C4. This means the ratio of the projected area of ​​the semiconductor component on the package layer to the area of ​​the package layer. Therefore, it is necessary to select parameters based on the relationship between B and A, which should be close to or fall within the low-risk region, to improve the yield of the package structure 100. For example... Figure 2 As shown, when the semiconductor component is in the packaging layer 130 (see reference) Figure 1B The encapsulation layer 130, whose projected area on the surface is greater than or equal to 50%, is a portion of the total area of ​​the encapsulation layer. (Please refer to [reference]). Figure 1B When the area is 1.5A, the encapsulation layer size can be reduced by 130 (please refer to...). Figure 1B The problem of cracking due to warping of the packaging structure 100 can be addressed by making the packaging structure have better structural reliability.

[0091] In one embodiment, the coefficient of thermal expansion of the semiconductor component is less than that of the encapsulation layer. For example, the coefficient of thermal expansion of the semiconductor component is 5.43, while that of the encapsulation layer is, for example, 7. In this case, when the thickness of the semiconductor component is less than half the thickness of the encapsulation layer, better warpage resistance can be achieved. That is, half the height of the encapsulation structure (i.e., centerline C) should fall on the side of the encapsulation layer 130. Furthermore, in a cross-sectional view (see reference...), Figure 3The centerline C of the package structure is perpendicular to the Z direction, and the extension direction of the centerline C of the package structure passes through the package layer 130. This design allows the semiconductor component to have better warp resistance, but is not limited thereto. The centerline C referred to in this disclosure means that the distance from the second side 133' of the package layer 130 to the centerline C is equal to the distance from one side 210' of the circuit layer 210 to the centerline C, wherein one side 210' of the circuit layer 210 is a surface away from the second side 133' of the package layer 130.

[0092] It should be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals used to represent the same or similar components, and descriptions of the same technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0093] Figure 3 This is a cross-sectional schematic diagram of an electronic device according to an embodiment of this disclosure. Please also refer to... Figure 1B as well as Figure 3 In this embodiment, electronic device 200a includes a package structure 100' and a circuit layer 210. Specifically, electronic device 200a includes a first semiconductor component 110, a second semiconductor component 120, a package layer 130', and a circuit layer 210. The second semiconductor component 120 is adjacent to the first semiconductor component 110. The package layer 130' has a first side 131 and surrounds the first semiconductor component 110 and the second semiconductor component 120. The first semiconductor component 110, the second semiconductor component 120, and the package layer 130' define the package structure 100'. The circuit layer 210 is disposed on the first side 131 of the package layer 130'. The package layer 130' has a first thickness T1', and the first semiconductor component 110 has a second thickness T2. The first thickness T1' is equal to the second thickness T2. That is, the back surface 111 of the first semiconductor component 110 is exposed outside the package layer 130. Viewed from above, the second area of ​​the first semiconductor component 110 (e.g., ...) Figure 1A A2) and the third area of ​​the second semiconductor component 120 (e.g. Figure 1A The sum of A3) is greater than the first area of ​​the encapsulation layer 130' (e.g. Figure 1A Half of A1). In one embodiment, the fifth thickness T5' from the back surface 121 of the second semiconductor component 120 to the second side 133' of the encapsulation layer 130' can be greater than half of the third thickness T3 and less than three times the third thickness T3 to prevent warping. In one embodiment, the second thickness T2 can be selectively less than the first thickness T1'. That is, the back surface 111 of the first semiconductor component 110 can also be covered by the encapsulation layer 130, and the difference between the first thickness T1' and the second thickness T2 is greater than the second thickness T2.

[0094] In this embodiment, the circuit layer 210 is disposed on the first side 131 of the encapsulation layer 130', and the stacking direction of the insulating layer 212 and the conductive layer 214 of the circuit layer 210 can be along the Z direction and can be stacked into any suitable structure. That is, the first side 131 of the encapsulation layer 130' is the side on which the circuit layer 210 is disposed, and the second side 133' is the side facing the first side 131 and away from the circuit layer 210. In one embodiment, the circuit layer 210 can directly contact the first side 131 of the encapsulation layer 130', the active surface 113 of the first semiconductor component 110, and the active surface 123 of the second semiconductor component 120, and the first semiconductor component 110 and the second semiconductor component 120 are electrically connected to the circuit layer 210. In one embodiment, the conductive layer 214 is, for example, a line, a conductive via, a conductive blind via, a pad, or a combination thereof; as long as it has a conductive function, it belongs to the conductive part described in this disclosure. In one embodiment, the conductive layer 214 includes, for example, a connector and a trace. The connector refers to the portion located within an opening in the insulating layer or the encapsulation layer, used for signal transmission in the vertical direction (e.g., the Z direction), while the trace refers to the portion outside the connector, used for signal transmission in the horizontal direction (e.g., the X or Y direction). In one embodiment, the material of the conductive layer 214 may be, for example, an alloy or combination of copper (Cu), aluminum (Al), nickel (Ni), molybdenum (Mo), titanium (Ti), gold (Au), tin (Sn), gallium (Ga), ruthenium (Ru), tantalum (Ta), or other suitable materials, but is not limited thereto. In one embodiment, the insulating layer 212 may be, for example, a buildup film, polyimide, epoxy, silicon dioxide, silicon nitride, solder resist, or a combination thereof, but is not limited thereto.

[0095] In one embodiment, circuit layer 210 may also be referred to as a redistribution layer. The redistribution layer can be electrically connected to a chip, semiconductor component, or other electronic component via solder balls or other bonding components. The redistribution layer may include at least one dielectric layer (or insulating layer) and at least one conductive layer alternately stacked along the Z-direction. The at least one dielectric layer and at least one conductive layer allow for circuit redistribution and / or increase in line fan-out or fan-in area, or allow different electronic components to be electrically connected to each other via the redistribution layer. For example, the pitch of two adjacent contact pads at the end of the redistribution layer that contacts the semiconductor component or electronic component may be less than or equal to the pitch of two adjacent contact pads at the end of the redistribution layer that is away from the semiconductor component or electronic component. Therefore, the redistribution layer can adjust the line fan-out or electrically connect a circuit structure / electronic component with a first pitch to a circuit structure / electronic component with a second pitch, but is not limited thereto. Methods for forming redistribution structures may include using lithography, surface treatment, laser processing, electroplating, deposition, or other processes to form at least one dielectric layer and at least one conductive layer. Surface treatment processes include roughening or activating the surface of the dielectric layer or the conductive layer to improve its adhesion, for example, by increasing surface roughness to enhance the adhesion to subsequent film layers.

[0096] Furthermore, the electronic device 200a of this embodiment also includes a bonding component 220 disposed on the side of the circuit layer 210 away from the package layer 130, wherein the circuit layer 210 is located between the package layer 130 and the bonding component 220, and the bonding component 220 is electrically connected to the circuit layer 210. The electronic device 200a can be electrically connected to an external circuit through the bonding component 220. In one embodiment, the material of the bonding component 220 may be, for example, tin, nickel, gold, silver, palladium, copper, gallium, the above alloys, or combinations thereof, but is not limited thereto. In one embodiment, the bonding component 220 is, for example, a solder ball, but is not limited thereto.

[0097] In summary, in the embodiments disclosed herein, the first thickness T1' of the encapsulation layer 130' is greater than or equal to the second thickness T2 of the first semiconductor component 110. When the first thickness T1' is greater than the second thickness T2, the difference between the first thickness T1' and the second thickness T2 is greater than half of the first thickness T1' and less than three times the second thickness T2. Viewed from above, the sum of the second area of ​​the first semiconductor component 110 and the third area of ​​the second semiconductor component 120 is greater than half of the first area of ​​the encapsulation layer 130'. When the first thickness T1' is equal to the second thickness T2, the fifth thickness T5' of the encapsulation layer 130' can be greater than half of the third thickness T3 and less than three times the third thickness T3. Viewed from above, the sum of the second area A2 of the first semiconductor component 110 and the third area A3 of the second semiconductor component 120 is greater than half of the first area A1 of the encapsulation layer 130'. This design effectively reduces / mitigates the risk of cracking of the packaging layer 130' due to warping when the packaging structure 100' is flipped off the carrier substrate, thus enabling the electronic device 200a disclosed herein to have better structural reliability.

[0098] Figures 4A to 4F This is a cross-sectional schematic diagram showing partial steps of a method for manufacturing an electronic device according to an embodiment of this disclosure. Please refer to [the diagram first]. Figure 4A Regarding the method of manufacturing the electronic device in this embodiment, firstly, a first semiconductor component 110 and a second semiconductor component 120 are provided. The first semiconductor component 110 is adjacent to the second semiconductor component 120. Next, the first semiconductor component 110 and the second semiconductor component 120 are disposed on a carrier substrate 10 via an adhesive layer 20. Here, the carrier substrate 10 can serve as a support structure to support the first semiconductor component 110 and the second semiconductor component 120. In one embodiment, the carrier substrate 10 is, for example, quartz, glass, stainless steel, sapphire, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the dissociation method of the adhesive layer 20 may include photodissociation, thermal dissociation, other suitable methods, or any combination of two of the above. For example, depending on the dissociation method, the adhesive layer 20 can be used with different types of carrier plates; for example, a photodissociation type adhesive layer 20 can be used with a transparent glass substrate, while a thermal dissociation type adhesive layer 20 can be used with a steel plate. The adhesive layer 20 may include, for example, an ultraviolet (UV) descaling film, a heat release tape (HRT), other suitable materials, or a combination of any two of the above. By providing the adhesive layer 20 on the carrier substrate 10, the encapsulation structure can be effectively separated.

[0099] In one embodiment, a first semiconductor component 110 and a second semiconductor component 120 are disposed on a carrier substrate 10 with their active surfaces 113 and 123 facing the carrier substrate 10. Then, an encapsulation layer 130 is formed around the first semiconductor component 110 and the second semiconductor component 120. The encapsulation layer 130 selectively exposes the back surface 111 of the first semiconductor component 110 and the top surface 121 of the second semiconductor component 120, a process known as a face-down process. The encapsulation layer 130 is formed on the adhesive layer 20 and covers the first semiconductor component 110 and the second semiconductor component 120. Next, the encapsulation layer 130 is ground to give it a flat surface. At this point, the encapsulation layer 130 still covers the back surface 111 of the first semiconductor component 110 and the back surface 121 of the second semiconductor component 120. The encapsulation layer 130 has a first side 131 and a second side 133 opposite to each other, wherein the first side 131 contacts the adhesive layer 20. The encapsulation layer 130 has a first thickness T1, and the first semiconductor component 110 has a second thickness T2. The first thickness T1 is greater than the second thickness T2. The difference between the first thickness T1 and the second thickness T2 is greater than half of the first thickness T1 and less than three times the second thickness T2. This completes the process. Figure 1B The packaging structure is 100. For example... Figure 1A As shown, viewed from above, the encapsulation layer 130 has a first area A1, the first semiconductor component 110 has a second area A2, the second semiconductor component 120 has a third area A3, and the sum of the second area A2 and the third area A3 is greater than half of the first area A1.

[0100] Next, please refer to Figure 4B After the packaging structure 100 is formed by the molding process, the packaging structure 100 is flipped and disposed on the carrier substrate 30 by the adhesive layer 40. At this time, the carrier substrate 10 and the adhesive layer 20 thereon are removed to expose the first side 131 of the packaging layer 130, the active surface 113 of the first semiconductor component 110 and the active surface 123 of the second semiconductor component 120.

[0101] Next, please refer to Figure 4CA conductive layer 214 is formed on the first side 131 of the encapsulation layer 130 to electrically connect the first semiconductor component 110 and the active surface of the second semiconductor component 120. In one embodiment, the conductive layer 214 may be, for example, a circuit, a conductive via, a conductive blind via, a pad, or a combination thereof; as long as it has conductive function, it belongs to the conductive portion described in this disclosure. In one embodiment, the conductive layer 214 may include a connection portion and a trace, wherein the connection portion 214a refers to the portion located in the opening of the insulating layer or the opening of the encapsulation layer, and the trace 214b refers to the portion other than the connection portion. In one embodiment, the material of the conductive layer 214 may be, for example, an alloy or combination of copper (Cu), aluminum (Al), nickel (Ni), molybdenum (Mo), titanium (Ti), gold (Au), tin (Sn), gallium (Ga), ruthenium (Ru), tantalum (Ta), or other suitable materials, but is not limited thereto.

[0102] Next, please refer to Figure 4D An insulating layer 212 is formed on the first side 131 of the encapsulation layer 130 to cover the conductive layer 214 and the active surfaces of the first semiconductor component 110 and the second semiconductor component 120.

[0103] In one embodiment, the insulating layer 212 may be made of, for example, build-up film, polyimide, epoxy, silicon dioxide, silicon nitride, solder resist, or a combination thereof, but is not limited thereto.

[0104] Next, please refer to Figure 4E The insulating layer 212 is ground until the conductive layer 214 is exposed, wherein the insulating layer 212 and the conductive layer 214 define the circuit layer 210. At this point, the circuit layer 210 has been formed on the first side 131 of the package layer 130, wherein the circuit layer 210 is electrically connected to the first semiconductor component 110 and the second semiconductor component 120.

[0105] Next, please refer to Figure 4F The above Figure 4E The structure is flipped and disposed on the carrier substrate 50 through the adhesive layer 60.

[0106] Afterwards, please refer to the following: Figure 4F as well as Figure 3 The encapsulation layer 130 is polished to form the second side 133' of the encapsulation layer 130'. The polishing process may selectively expose the back side 111 of the first semiconductor component 110 and the back side 121 of the second semiconductor component 120, or selectively expose only the back side 111 of the first semiconductor component 110, or neither of the semiconductor components is exposed.

[0107] Finally, please refer to... Figure 3A bonding assembly 220 is formed on the circuit layer 210, wherein the circuit layer 210 is located between the encapsulation layer 130' and the bonding assembly 220, and the bonding assembly 220 is electrically connected to the circuit layer 210. The electronic device 200a can be electrically connected to an external circuit through the bonding assembly 220. At this point, the fabrication of the electronic device 200a is complete.

[0108] Figures 5A to 5E This is a cross-sectional schematic diagram showing partial steps of a method for manufacturing an electronic device according to another embodiment of this disclosure. Please refer to [the diagram first]. Figure 5A Regarding the method of manufacturing the electronic device in this embodiment, firstly, a first semiconductor component 110' and a second semiconductor component 120 are provided. The first semiconductor component 110' is adjacent to the second semiconductor component 120. In this embodiment, the first semiconductor component 110' includes a semiconductor cell 112, a conductive pad 114, and an insulating layer 116 located between the conductive pads 114. Next, the first semiconductor component 110' and the second semiconductor component 120 are disposed on a carrier substrate 10 via an adhesive layer 20. Next, an encapsulation layer 130 is formed to surround the first semiconductor component 110' and the second semiconductor component 120. The encapsulation layer 130 is formed on the adhesive layer 20 and covers the first semiconductor component 110' and the second semiconductor component 120.

[0109] Next, please refer to the following: Figure 5A as well as Figure 5BThe encapsulation layer 130 is ground until the back surface 111 of the first semiconductor component 110 is exposed. Next, the encapsulation layer 130' is patterned and a thermally conductive structure 240 is provided, wherein the thermally conductive structure 240 is disposed on a second side 133' of the encapsulation layer 130' and directly contacts the back surface 111 of the first semiconductor component 110. In one embodiment, the thermally conductive structure 240 includes a main body 242 and a plurality of extensions 244, wherein the extensions 244 connect to the main body 242 and pass through the encapsulation layer 130 to contact the back surface 121 of the second semiconductor layer 120. In one embodiment, the orthographic projection area of ​​the main body 242 on the encapsulation layer 130' is smaller than the area of ​​the encapsulation layer 130'. In one embodiment, the orthographic projection area of ​​the main body 242 on the encapsulation layer 130' completely covers the orthographic projections of the first semiconductor component 110 and the second semiconductor component 120 on the encapsulation layer 130'. In one embodiment, the material of the thermally conductive structure 240 may include epoxy resin, die attach film (DAF), thermal interface material (TIM), other suitable adhesive materials, or combinations thereof, but is not limited thereto. In one embodiment, the thermally conductive structure 240 may contact a surface of the semiconductor component. The thermally conductive structure 240 may include a material with heat dissipation function, such as silicone sheet, metal, graphene, silicon carbide, diamond, but is not limited thereto. The thermally conductive structure 240 may include an adhesive material with heat dissipation particles, such as epoxy resin containing graphite particles or epoxy resin containing ceramic heat dissipation particles, but is not limited thereto. In one embodiment, the material of the thermally conductive structure 240 is, for example, a conductive material, such as copper. In one embodiment, the material of the thermally conductive structure 240 includes a conductive material, i.e., conductive, so that both sides of the semiconductor component can have the function of receiving or transmitting signals. In other words, the first side 131 and the second side 133' of the encapsulation layer 130' are both adjacent to the circuit / conductive layer. The heat transfer coefficient of the thermally conductive structure 240 is greater than that of the encapsulation layer 130'. For example, the heat transfer coefficient of the thermally conductive structure 240 can be between 20 W / m·K and 500 W / m·K.

[0110] Next, please refer to Figure 5B An insulating layer 230 is provided to cover the thermally conductive structure 240. Next, the insulating layer 230 is ground until the upper surface 241 of the thermally conductive structure 240 is exposed. Here, the insulating layer 230 has a protective function, protecting the side surfaces of the thermally conductive structure 240.

[0111] Next, please refer to the following: Figure 5B as well as Figure 5C ,Will Figure 5BThe structure is flipped and disposed on the carrier substrate 30 via the adhesive layer 40. At this time, the carrier substrate 10 and the adhesive layer 20 thereon are removed to expose the active surface 113 of the first semiconductor component 110 and the active surface 123 of the second semiconductor component 120. Next, a conductive layer 214 is formed on the first side 131 of the encapsulation layer 130 to electrically connect the active surface 113 of the first semiconductor component 110 and the active surface 123 of the second semiconductor component 120. Please refer to... Figure 5C In this embodiment, a portion of the trace 214b of the conductive layer 214 may be electrically connected to the first semiconductor component 110 and the second semiconductor component 130 simultaneously as needed, but is not limited thereto.

[0112] Next, please refer to Figure 5D An insulating layer 212 is formed on the first side 131 of the encapsulation layer 130' to cover the conductive layer 214, the active surface 113 of the first semiconductor component 110, and the active surface 123 of the second semiconductor component 120.

[0113] Next, please refer to the following: Figure 5D as well as Figure 5E The insulating layer 212 is ground until at least a portion of the conductive layer 214 is exposed, wherein the insulating layer 212 and the conductive layer 214 define the circuit layer 210. Thus, the circuit layer 210 is formed on the first side 131 of the package layer 130', wherein the circuit layer 210 is electrically connected to the first semiconductor component 110 and the second semiconductor component 120.

[0114] Finally, please refer to Figure 5E A bonding assembly 220 is formed on the circuit layer 210, wherein the circuit layer 210 is located between the encapsulation layer 130' and the bonding assembly 220, and the bonding assembly 220 is in contact with the circuit layer 210 and electrically connected to the conductive layer 214. The electronic device 200b can be electrically connected to an external circuit through the bonding assembly 220. At this point, the fabrication of the electronic device 200b is complete.

[0115] Figure 6 This is a cross-sectional schematic diagram of an electronic device according to another embodiment of this disclosure. Please also refer to... Figure 5E and Figure 6 The electronic device 200c in this embodiment and Figure 5ESimilar to the electronic device 100b, the difference lies in that, in this embodiment, the heat-conducting structure 240c, in addition to the main body 242 and the extension 244, also includes a plurality of heat dissipation fins 246. In one embodiment, the main body 242 may contact the second side 133' of the encapsulation layer 130', or selectively cover the second side 133' of the encapsulation layer 130', while the heat dissipation fins 246 are distributed on the side of the main body 242 relatively away from the extension 244. In one embodiment, the cross-sectional shape of the heat dissipation fins 246 may be, for example, rectangular, square, rectangular, trapezoidal, triangular, semi-circular, elliptical, arc-shaped, or a combination of the above shapes, which can increase the heat dissipation surface area. In one embodiment, the main body 242, the extension 244, and the heat dissipation fins 246 may be an integrally formed structure, but this is not a limitation.

[0116] In terms of manufacturing process, the thermally conductive structure 240c can be... Figures 5B to 5C Between the steps, the main body 242 of the heat-conducting structure 240c is patterned to form a heat-conducting structure 240c with heat dissipation fins 246. Alternatively, it can be done in... Figures 5D to 5E Between the steps, first Figure 5D The structure is flipped onto another carrier substrate (not shown), and the carrier substrate 30 and its adhesive layer 40 are removed to expose the main body 242 of the thermally conductive structure 240. The main body 242 is then patterned to form a thermally conductive structure 240c with heat dissipation fins 246. Next, the structure is flipped onto yet another carrier substrate (not shown), and the insulating layer 212 is polished to expose the conductive layer 214. Alternatively, it can be... Figure 5E Following this step, the main body 242 of the heat-conducting structure 240c is patterned to form a heat-conducting structure 240c with heat dissipation fins 246. Finally, continuing... Figure 5E The steps are followed to complete the production of the electronic device 200c.

[0117] Figures 7A to 7C This is a cross-sectional schematic diagram showing partial steps of a method for manufacturing an electronic device according to another embodiment of this disclosure. Please refer to [the diagram first]. Figure 7ARegarding the method of manufacturing the electronic device in this embodiment, firstly, a support portion 134a and an adhesive portion 136a disposed on the support portion 134a are provided. Next, a first semiconductor component 110a and a second semiconductor component 120a are provided on the support portion 134a, wherein the first semiconductor component 110a and the second semiconductor component 120a are fixed to the support portion 134a by the adhesive portion 136a. The first semiconductor component 110a is adjacent to the second semiconductor component 120a. Next, the first semiconductor component 110a and the second semiconductor component 120a fixed to the support portion 134a are disposed on the carrier substrate 10 by an adhesive layer 20. The back surface 111a of the first semiconductor component 110a and the back surface 121a of the second semiconductor component 120a face the carrier substrate 10. Next, an encapsulation portion 132a is formed to surround the first semiconductor component 110a and the second semiconductor component 120a. The encapsulation portion 132a is located on the adhesive portion 136a and exposes the active surface 113a of the first semiconductor component 110a. Here, the encapsulation portion 132a, the support portion 134a, and the adhesive portion 136a define the encapsulation layer 130a. In this embodiment, the material of the encapsulation portion 132a may be the same as the material of the support portion 134a. In one embodiment, the material of the encapsulation portion 132a may be different from the material of the support portion 134a. Furthermore, the coefficient of thermal expansion of the support portion 134a may be less than the coefficient of thermal expansion of the encapsulation portion 132a. In this case, the first semiconductor component 110a, the second semiconductor component 120a, and the encapsulation layer 130a can be defined as the encapsulation structure 100a.

[0118] Next, please refer to Figure 7B A conductive layer 214 is formed on the first side 131a of the encapsulation layer 130a and electrically connects the first semiconductor component 110a and the second semiconductor component 120a. In one embodiment, a portion of the trace 214b of the conductive layer 214 may electrically connect the first semiconductor component 110a and the second semiconductor component 130a simultaneously as needed, but is not limited thereto. Here, the first thickness T11 of the encapsulation layer 130a is the vertical distance (e.g., along the Z direction) between the second side 133a and the first side 131a of the encapsulation layer 130a. The first thickness T11 of the encapsulation layer 130a is greater than the second thickness T12 of the first semiconductor component 110a, and the difference between the first thickness T11 and the second thickness T12 is greater than half of the first thickness T11 and less than three times the second thickness T12. In one embodiment, the vertical distance between the back surface 111a of the first semiconductor component 110a and the second side 133a of the encapsulation layer 130a is a fourth thickness T14. In one embodiment, if there is no adhesive layer 136a, the thickness of the support portion 134a is the fourth thickness T14.

[0119] The fourth thickness T14 is the difference between the first thickness T11 and the second thickness T12, and the fourth thickness T14 is greater than the second thickness T12.

[0120] Next, please refer to Figure 7C An insulating layer 212 is formed on the first side 131a of the encapsulation layer 130a to cover the conductive layer 214 and the active surface 113a of the first semiconductor component 110a and the active surface 123a of the second semiconductor component 120a. The insulating layer 212 is ground until the conductive layer 214 is exposed, wherein the insulating layer 212 and the conductive layer 214 define the circuit layer 210. At this time, the first semiconductor component 110a and the second semiconductor component 120a are disposed between the support portion 134a and the circuit layer 210.

[0121] Finally, please refer to Figure 7C A bonding assembly 220 is formed on the circuit layer 210, wherein the circuit layer 210 is located between the encapsulation layer 130a and the bonding assembly 220, and the bonding assembly 220 is electrically connected to the circuit layer 210. The electronic device 200d can be electrically connected to an external circuit through the bonding assembly 220. At this point, the fabrication of the electronic device 200d is complete.

[0122] Figures 8A to 8C This is a cross-sectional schematic diagram showing partial steps of a method for manufacturing an electronic device according to another embodiment of this disclosure. Please refer to [the diagram first]. Figure 8ARegarding the method of manufacturing the electronic device in this embodiment, firstly, a support portion 134c and an adhesive portion 136c disposed on the support portion 134c are provided, wherein the support portion 134c is a patterned structural layer, and the adhesive portion 136c is conformally disposed with the support portion 134c. Next, a first semiconductor component 110a and a second semiconductor component 120a are provided on the support portion 134c, wherein the first semiconductor component 110a and the second semiconductor component 120a are fixed to the support portion 134c by the adhesive portion 136c. The first semiconductor component 110a is adjacent to the second semiconductor component 120a. Next, the first semiconductor component 110a and the second semiconductor component 120a fixed to the support portion 134c are disposed on the carrier substrate 10 by the adhesive layer 20. The back surface 111a of the first semiconductor component 110a and the back surface 121a of the second semiconductor component 120a face the carrier substrate 10. Next, a package portion 132c is formed to surround the first semiconductor component 110a and the second semiconductor component 120a. The package portion 132a is located on the adhesive portion 136c and exposes the active surface 113a of the first semiconductor component 110a. Here, the package portion 132c, the support portion 134c, and the adhesive portion 136c define a package layer 130c. In one embodiment, the material of the package portion 132c may be the same as or different from the material of the support portion 134c. In one embodiment, the coefficient of thermal expansion of the support portion 134c may not be the same as the coefficient of thermal expansion of the package portion 132b. The coefficient of thermal expansion of the support portion 134c may be smaller than the coefficient of thermal expansion of the package portion 132c, but is not limited thereto. In one embodiment, in the normal direction (e.g., the Z direction), the expansion trend of the support portion 134c is different from that of the package portion 132c, for example, opposite. Furthermore, the coefficient of thermal expansion of the support portion 134c may be different from the coefficient of thermal expansion of the semiconductor component. At this time, the first semiconductor component 110a, the second semiconductor component 120a, and the packaging layer 130c can be defined as the packaging structure 100c.

[0123] Here, the first thickness T21 of the encapsulation layer 130c is the vertical distance (e.g., along the Z direction) between the second side 133c and the first side 131c of the encapsulation layer 130c. The first thickness T21 of the encapsulation layer 130c is greater than the second thickness T22 of the first semiconductor component 110a, and the difference between the first thickness T21 and the second thickness T22 is greater than half of the first thickness T21 and less than three times the second thickness T22. In one embodiment, the vertical distance between the back surface 111a of the first semiconductor component 110a and the second side 133c of the encapsulation layer 130c is a fourth thickness T24. In one embodiment, the thickness of the support portion 134b is the fourth thickness T24.

[0124] Next, please refer to Figure 8BA conductive layer 214 is formed on the first side 131c of the encapsulation layer 130c to electrically connect the active surface 113a of the first semiconductor component 110a and the active surface 123a of the second semiconductor component 120a. In one embodiment, the conductive layer 214 may electrically connect the first semiconductor component 110a and the second semiconductor component 120a simultaneously as needed, but is not limited thereto.

[0125] Please refer to the following: Figure 8B An insulating layer 212 is formed on the first side 131c of the encapsulation layer 130c to cover the conductive layer 214 and the active surface 113a of the first semiconductor component 110a and the active surface 123a of the second semiconductor component 120a. The insulating layer 212 is ground until the conductive layer 214 is exposed, wherein the insulating layer 212 and the conductive layer 214 define the circuit layer 210. At this time, the first semiconductor component 110a and the second semiconductor component 120a are disposed between the support portion 134c and the circuit layer 210.

[0126] Finally, please refer to Figure 8C A bonding assembly 220 is formed on the circuit layer 210, wherein the circuit layer 210 is located between the encapsulation layer 130c and the bonding assembly 220, and the bonding assembly 220 is electrically connected to the circuit layer 210. The electronic device 200e can be electrically connected to an external circuit through the bonding assembly 220. At this point, the fabrication of the electronic device 200e is complete.

[0127] In summary, in the embodiments disclosed herein, the first thickness of the encapsulation layer is greater than the second thickness of the first semiconductor component, and the difference between the first and second thicknesses is greater than half the first thickness and less than three times the second thickness. From a top view, the sum of the second area of ​​the first semiconductor component and the third area of ​​the second semiconductor component is greater than half the first area of ​​the encapsulation layer. This design effectively reduces the risk of encapsulation layer cracking due to warping of the encapsulation structure, enabling the electronic device disclosed herein to have better structural reliability.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device, characterized in that, include: First semiconductor component; A second semiconductor component is located adjacent to the first semiconductor component; An encapsulation layer having a first side, wherein the encapsulation layer surrounds the first semiconductor component and the second semiconductor component; as well as The circuit layer is disposed on the first side of the encapsulation layer. The encapsulation layer has a first thickness, the first semiconductor component has a second thickness, the first thickness is greater than the second thickness, and the difference between the first thickness and the second thickness is greater than half of the first thickness and less than three times the second thickness. From a top view, the encapsulation layer has a first area, the first semiconductor component has a second area, the second semiconductor component has a third area, and the sum of the second area and the third area is greater than half of the first area.

2. The electronic device according to claim 1, characterized in that, The second semiconductor component includes at least one semiconductor unit.

3. The electronic device according to claim 2, characterized in that, The ratio of the coefficient of thermal expansion of the encapsulation layer to the coefficient of thermal expansion of one of the at least one semiconductor unit is between 1.2 and 3.

4. The electronic device according to claim 1, characterized in that, Also includes: A thermally conductive structure is provided on the second side of the encapsulation layer, which is opposite to the first side.

5. The electronic device according to claim 4, characterized in that, The thermally conductive structure is made of conductive materials.

6. The electronic device according to claim 1, characterized in that, The encapsulation layer includes an encapsulation portion and a support portion. The encapsulation portion surrounds the first semiconductor component and the second semiconductor component, and the first semiconductor component and the second semiconductor component are disposed between the support portion and the circuit layer.

7. The electronic device according to claim 1, characterized in that, Also includes: A bonding assembly is disposed on the side of the circuit layer away from the package layer, wherein the circuit layer is located between the package layer and the bonding assembly.

8. A method for manufacturing an electronic device, characterized in that, include: A first semiconductor component and a second semiconductor component are provided, wherein the first semiconductor component is adjacent to the second semiconductor component; An encapsulation layer is formed to surround the first semiconductor component and the second semiconductor component, the encapsulation layer having a first side; as well as A circuit layer is formed on the first side of the encapsulation layer. The encapsulation layer has a first thickness, the first semiconductor component has a second thickness, the first thickness is greater than the second thickness, and the difference between the first thickness and the second thickness is greater than half of the first thickness and less than three times the second thickness. From a top view, the encapsulation layer has a first area, the first semiconductor component has a second area, the second semiconductor component has a third area, and the sum of the second area and the third area is greater than half of the first area.

9. The method for manufacturing an electronic device according to claim 8, characterized in that, Also includes: A bonding assembly is formed on the circuit layer, wherein the circuit layer is located between the encapsulation layer and the bonding assembly.

10. A packaging structure, characterized in that, include: First semiconductor component; A second semiconductor component is located adjacent to the first semiconductor component; as well as An encapsulation layer surrounds the first semiconductor component and the second semiconductor component; The encapsulation layer has a first thickness, the first semiconductor component has a second thickness, the first thickness is greater than the second thickness, and the difference between the first thickness and the second thickness is greater than half of the first thickness and less than three times the second thickness. From a top view, the encapsulation layer has a first area, the first semiconductor component has a second area, the second semiconductor component has a third area, and the sum of the second area and the third area is greater than half of the first area.

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