Broadcasting power limit management responses in processor-based systems in integrated circuit (IC) chips

Abstract

Broadcasting a power limit management response in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip includes a processor-based system that includes a power estimation and restriction (PEL) circuit, a restricted management throughput throttling (LMTT) source circuit, a plurality of activity management (AM) circuits, and an LMTT bus communicatively coupling the LMTT source circuit with each of the plurality of AM circuits. The LMTT source circuit receives a power limit management response from the PEL circuit via a communication network of the processor-based system and generates an LMTT command based on the power limit management response. The LMTT source circuit broadcasts the LMTT command to each of the plurality of AM circuits via the LMTT bus.

Description

Priority application

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 339,504, filed June 22, 2023, entitled “BROADCASTING POWER LIMITING MANAGEMENT RESPONSES IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to processor-based systems (e.g., central processing unit (CPU)-based systems, graphics processing unit (GPU)-based systems, or neural network processing unit (NPU)-based systems), and more specifically to power distribution management of circuits in processor-based systems. Background Technology

[0003] Microprocessors, also known as processing units (PUs), perform computational tasks in a wide variety of applications. One type of conventional microprocessor or PU is the Central Processing Unit (CPU). Another type of microprocessor or PU is a dedicated processing unit called a Graphics Processing Unit (GPU). GPUs are designed with dedicated hardware to accelerate the rendering of graphics and video data to be displayed. GPUs can be implemented as integrated components of a general-purpose CPU or as discrete hardware components separate from the CPU. Other examples of PUs may include neural network processing units or neural processing units (NPUs). In the case of a PU, the PU is configured to execute software instructions that instruct the processor to fetch data from locations in memory and use the fetched data to perform one or more processor operations.

[0004] A Processing Unit (PU) is included in a computer system that includes other supporting processing devices (circuitets) accessed in connection with performing computational operations within the computer system or as part of performing computational operations within the computer system. Examples of these other supporting processing devices include memory, input / output (I / O) devices, secondary storage devices, modems, video processors, and associated interface circuitry. The PU and supporting processing devices are collectively referred to as processing devices. Processing devices for processor-based systems can be provided in separate ICs within a single IC chip. Alternatively, processing devices for processor-based systems can also be aggregated in a larger IC (such as a System-on-Chip (SoC) IC), where some or all of these processing devices are integrated into the same IC chip. For example, an SoC IC chip may include a PU comprising multiple processor cores and supporting processing devices, such as a memory system including cache memory and a memory controller for controlling access to external memory, I / O interfaces, a power management system, etc. SoCs may be particularly advantageous for applications where a limited area is available for the computer system (e.g., mobile computing devices such as cellular devices). To manage the power distributed to the processing devices, the SoC may also include a power management system comprising one or more power rails within the SoC that supply power to its components. A separate power management integrated circuit (PMIC), which can be on-chip or off-chip with a SoC, can independently control the power supplied to the power rails. An SoC can be designed with multiple different power rails distributed throughout the SoC to provide power to various clusters of processing devices for their operation. For example, all processor cores in an SoC can be coupled to a common power rail for power supply, while supporting processing devices can be powered from individual power rails within the SoC, depending on the SoC design. Summary of the Invention

[0005] This document discloses aspects including hierarchical power estimation and control in processor-based systems within integrated circuit (IC) chips. Related power management and power control methods are also disclosed. The IC chip includes a processor and integrated supporting processing devices (e.g., network nodes, memory controllers, internal memory, input / output (I / O) interface circuitry, etc.) for the processor. For example, the processor may be a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU), wherein the processor includes multiple processing units (PUs) and / or processor cores. The processor-based system may be provided as a system-on-a-chip (SoC), which includes the processor and integrated supporting processing devices for the PUs. As an example, the SoC can be used in smaller mobile devices (e.g., cellular phones, laptops) and enterprise systems (such as server chips in computer servers). The IC chip also includes a hierarchical power management system configured to control the power consumption of the processor-based system at both a local level and a centralized level to achieve desired performance within the IC chip's total power budget. The hierarchical power management system may be configured to control power consumption by controlling the power levels (e.g., voltage levels) distributed at one or more power rails in the IC chip that supply power to the PUs and integrated supporting processing devices. For example, a tiered power management system can be configured to provide additional power to certain power rails supplying power to devices that require higher current for enhanced performance, while providing less power to other power rails to keep the total power within the IC chip's power and / or thermal limits. A tiered power management system can also be configured to control power consumption by moderating the performance (e.g., frequency) of processing devices in a processor-based system, which in turn moderates (i.e., reduces, maintains, or increases) their current demand and thus their power consumption. Note that, as used herein, moderating can mean taking action that reduces or increases parameters affecting power and thus results in a corresponding reduction or increase in power consumption.

[0006] A tiered power management system is configured to regulate the performance of processing devices in a processor-based system, as the level of processing activity in the processing devices within an SoC can vary based on workload conditions. Some power rails in an SoC may experience increased current demands. It is expected that these current demands will not exceed the maximum current limit of their respective power rails. Even if the higher current demand on a power rail is within its maximum current limit, the increased activity of the processing devices in the SoC can cause a sudden increase in the current demand from its power rail, known as a "di / dt" event. This di / dt event can cause a voltage drop in the power rail, negatively impacting the performance of the processing devices powered by such power rails. Moreover, even if the higher current demand on a power rail is within its maximum current limit, the higher current demand can still increase the total power consumption of the SoC. The processing device may have a maximum rated power that operates correctly and / or does not undesirably affect performance. Higher current demands from the processing device can also generate excessive heat. Therefore, the maximum rated power of the SoC may be based in part on the SoC's ability to dissipate the heat generated by the processing devices during their operation.

[0007] In an exemplary aspect, the hierarchical power management system includes local area management (LAM) circuitry distributed throughout an IC chip, each LAM circuitry associated with one or more processing devices within the IC chip. The LAM circuitry is configured to generate power events associated with the processing devices it monitors within the IC chip, representing power consumption associated with the monitored processing devices. Power events can be reported from the local area within the IC chip performing power estimation for a specific monitored processing device to centralized power estimation and limiting (PEL) circuitry in the hierarchical power management system. The PEL circuitry is configured to estimate and control (i.e., moderate) power in the processor-based system within the IC chip to achieve desired performance within the IC chip's total power budget. The PEL circuitry determines how to moderate power based on the received power events. For example, a power event may be associated with an estimate of power consumption, which, if the estimated power consumption exceeds the IC chip's power limits or negatively impacts performance, can be considered a power moderation recommendation for moderating power within the IC chip.

[0008] The activity of the processing devices in an IC chip affects its steady-state and transient current (i) demand (di / dt), and thus its power consumption. Because IC chips can be larger in die area due to the integration of the PU and the integrated support processing devices, there can be a significant delay between the PEL circuit receiving a power event regarding the power consumption of the monitored processing device and the PEL circuit regulating the power in the IC chip in response. For example, this delay may cause devices in the IC chip to temporarily continue consuming excessive power, potentially leading to thermal and / or power problems (e.g., di / dt issues, voltage drops, heat generation) before the power management circuitry has time to react.

[0009] Mechanisms designed to address these issues may face additional challenges because the power limiting management determinations and corresponding commands generated by the PEL circuitry must be communicated to various destination elements within the SoC responsible for actually implementing the power limiting operations. Such power limiting management responses must reach the destination elements quickly enough to effectively manage local hotspots and peak power consumption. In conventional SoCs, commands for power limiting management can be sent using packetized commands transmitted via an on-chip communication network (i.e., the architecture). However, congestion of data traffic on the architecture can lead to increased latency and additional overhead. Furthermore, conventional architecture-based communication may employ addressing mechanisms based on source and destination identifiers, which can further delay time-sensitive power limiting management responses.

[0010] To broadcast power limit management responses in a processor-based system within an IC chip, some aspects of the hierarchical power management system disclosed herein provide a dedicated Limit Management Throughput Throttle (LMTT) bus, separate from the communication network (e.g., architecture) provided by the processor-based system within the IC chip. This bus enables an LMTT source circuit to directly broadcast LMTT commands to multiple Activity Management (AM) circuits. In exemplary operation, the LMTT source circuit receives a power limit management response from a PEL circuit via the communication network of the processor-based system. The LMTT source circuit generates an LMTT command based on the power limit management response and then broadcasts the LMTT command via the LMTT bus to each of the multiple AM ​​circuits in the processor-based system. Each AM circuit receives the LMTT command from the LMTT source circuit via the LMTT bus and performs power control operations based on the LMTT command.

[0011] According to some aspects, the LMTT source circuit may include local AM (RAM) circuitry of the IC, and each of the plurality of AM circuits may include LAM circuitry of the IC. In some aspects, the LMTT source circuit includes temperature sensor hub (THUB) circuitry of the IC, and each of the plurality of AM circuits includes LAM circuitry of the IC. Some aspects may specify that the LMTT source circuit includes THUB circuitry of the IC, and each of the plurality of AM circuits includes RAM circuitry of the IC. In some aspects, the LMTT source circuit may include drop detection circuitry of the IC, and each of the plurality of AM circuits may include RAM circuitry of the IC.

[0012] In some respects, the LMTT bus includes a three (3) wire bus, and the LMTT command includes an enable indication transmitted via the first wire of the three (3) wire bus, a control value indication transmitted via the second wire of the three (3) wire bus, and a control target indication transmitted via the third wire of the three (3) wire bus. Some of these respects may specify that the control value indication includes a three (3) bit value transmitted serially via the second wire of the three (3) wire bus, and the control target indication includes a two (2) bit value transmitted serially via the third wire of the three (3) wire bus.

[0013] In another exemplary aspect, an IC chip is disclosed. The IC chip includes a processor-based system comprising a power limit management (PEL) circuit, an LMTT source circuit communicatively coupled to the PEL circuit via a communication network, and a plurality of AM circuits. The processor-based system also includes an LMTT bus communicatively coupling the LMTT source circuit to each of the plurality of AM circuits. The LMTT source circuit is configured to receive a power limit management response from the PEL circuit via the communication network. The LMTT source circuit is also configured to generate an LMTT command based on the power limit management response. The LMTT source circuit is further configured to broadcast the LMTT command to each of the plurality of AM circuits via the LMTT bus.

[0014] In another exemplary aspect, an IC chip is disclosed. The IC chip includes a processor-based system comprising components for receiving a power limit management response from a PEL circuit via a communication network of the processor-based system. The processor-based system also includes components for generating an LMTT command based on the power limit management response. The processor-based system further includes components for broadcasting the LMTT command to each of a plurality of AM circuits in the processor-based system via an LMTT bus.

[0015] In another exemplary aspect, a method is provided for broadcasting a power limit management response in a processor-based system within an IC chip. The method includes: receiving a power limit management response from a power limit management circuit (PEL) via a communication network of the processor-based system. The method further includes: generating an LMTT command based on the power limit management response. The method also includes: broadcasting the LMTT command via an LMTT bus to each of a plurality of AM circuits in the processor-based system.

[0016] In another exemplary aspect, a non-transitory computer-readable medium is disclosed. This non-transitory computer-readable medium stores computer-executable instructions thereon that, when executed, cause a processor of a processor-based device to receive a power limit management response from a PEL circuit via a communication network of a processor-based system. The computer-executable instructions also cause the processor to generate an LMTT command based on the power limit management response. Furthermore, the computer-executable instructions cause the processor to broadcast the LMTT command to each of a plurality of AM circuits in the processor-based system via an LMTT bus. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an exemplary processor-based system in the form of an exemplary system-on-a-chip (SoC) in an integrated circuit (IC) chip;

[0018] Figure 2 yes Figure 1 The example logic diagram of a processor-based system illustrates processing circuitry and other supporting devices communicatively coupled to an internal communication network, as well as a hierarchical power management system configured to perform power estimation and power consumption control.

[0019] Figure 3 This is a top view of an exemplary physical layout of a semiconductor die (“die”), which is Figure 1 The SoC in the processor-based system-on-a-chip illustrates the physical layout of different tile regions and the devices that are physically present in such different tile regions and are coded with markers that indicate which devices are powered from separate power rails supplied with power from a hierarchical power management system.

[0020] Figure 4 This is an example of... Figure 1 An exemplary allocation of power rails driven by a corresponding power management IC (PMIC) in a processor-based system to devices in the processor-based system for supplying power to such devices;

[0021] Figure 5 yes Figure 1Another top view of a processor-based system in an IC chip illustrates a regional area management (LAM) circuit, a local area management (RAM) circuit, and a power estimation and limiting (PEL) circuit as part of a hierarchical power management system. The hierarchical power management system is configured to locally monitor the activity of devices in the processor-based system to estimate and control their power consumption, and to report active power events regarding the estimated power consumption to the PEL circuit. The PEL circuit is configured to collect active power events regarding the power consumption of the monitored processing devices and, in response, control the power in the IC chip. The LAM and RAM circuits are configured to communicate via an on-chip communication network (i.e., architecture).

[0022] Figure 6 It is possible Figure 1 A schematic diagram of an exemplary three (3) level power management system provided in a processor-based system in an IC chip, wherein the three (3) level power management system includes: a first local level LAM circuit configured to perform local device monitoring and power consumption control, and report active power events regarding the power consumption of the monitored processing device; a second intermediate level RAM circuit configured to receive and aggregate local active power events; and a third centralized level PEL circuit configured to collect aggregated active power events regarding the power consumption of the monitored processing device, and control the power in the IC chip in response;

[0023] Figure 7 It is possible Figure 1 A schematic diagram of another exemplary two (2) level hierarchical power management system provided in a processor-based system in an IC chip, wherein the two (2) level hierarchical power management system includes: a first local level LAM circuit configured to perform local device monitoring and power consumption control; and a second centralized level PEL circuit configured to collect aggregated active power events about the power consumption of the monitored processing device and control the power in the IC chip in response;

[0024] Figure 8 It is a flowchart, which illustrates... Figure 6 An exemplary process of a processor-based system hierarchical power management system locally monitors and controls the power consumption of the monitored processing device and hierarchically reports active power events related to the monitored power consumption to a PEL circuit configured to control power consumption in the processor-based system in response to received power events.

[0025] Figure 9A This is an example that can be found in Figure 6A schematic diagram of an exemplary di / dt circuit provided in the LAM circuit of the hierarchical power management system, wherein the di / dt circuit is configured to collect activity samples of the device monitored by the LAM circuit and correlate the activity samples to estimate the current and generate estimated current samples within a specified time window. These estimated current samples can then be used to determine the slope of the rate of change of current / current flow rate (di / dt) consumed by the monitored processing device to determine whether the power consumption of the monitored processing device should be controlled by the LAM circuit.

[0026] Figure 9B This is an example of... Figure 9A A graph of an exemplary estimated current sample collected by the di / dt circuit in the diagram is plotted as it changes over time to determine the rate of change (di / dt) of the current flow rate consumed by the monitored processing device.

[0027] Figure 10 This is a logic diagram of an exemplary PEL circuit that may be provided in a hierarchical power management system of a processor-based system, and illustrates exemplary components for receiving power events, decoding the received power events in a tracking circuit, and merging the tracked power events to generate a power limit management response thereby controlling power consumption in the processor-based system in response to the received power events.

[0028] Figure 11 This is a block diagram illustrating an IC chip for a processor-based system configured to provide a dedicated Limit Management Throughput Control (LMTT) bus, through which an LMTT source circuit can broadcast LMTT commands to each of multiple Activity Management (AM) circuits.

[0029] Figure 12 This is an example based on some aspects. Figure 11 An exemplary diagram of the transmission of an LMTT command on the LMTT bus, the LMTT command including an enable indication, a control value indication, and a control target indication;

[0030] Figure 13 A flowchart illustrating exemplary operations for broadcasting power limit management responses in a processor-based system within an IC chip, based on several aspects, is provided.

[0031] Figure 14This is a block diagram of another exemplary processor-based system including a hierarchical power management system configured to locally monitor the activity of devices in the processor-based system to estimate and control their power consumption and report activity power events related to the estimated power consumption to a PEL circuit, wherein the PEL circuit is configured to collect activity power events related to the power consumption of the monitored processing devices and, in response, control the power in an IC chip, including but not limited to... Figures 1 to 3 , Figures 5 to 7 , Figure 9A , Figure 10 and Figure 11 The graded power management system and its exemplary components in the text; and

[0032] Figure 15 This is a block diagram of an exemplary wireless communication device including a hierarchical power management system configured to locally monitor the activity of devices in a processor-based system to estimate and control their power consumption and report activity power events related to the estimated power consumption to a PEL circuit. The PEL circuit is configured to collect activity power events related to the power consumption of the monitored processing devices and, in response, control the power in an IC chip, including but not limited to… Figures 1 to 3 , Figures 5 to 7 , Figure 9A , Figure 10 and Figure 11 The graded power management system and its exemplary components. Detailed Implementation

[0033] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0034] This document discloses aspects including hierarchical power estimation and control in processor-based systems within integrated circuit (IC) chips. Related power management and power control methods are also disclosed. The IC chip includes a processor and integrated supporting processing devices (e.g., network nodes, memory controllers, internal memory, input / output (I / O) interface circuitry, etc.) for the processor. For example, the processor may be a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU), wherein the processor includes multiple processing units (PUs) and / or processor cores. The processor-based system may be provided as a system-on-a-chip (SoC), which includes the processor and integrated supporting processing devices for the PUs. As an example, the SoC can be used in smaller mobile devices (e.g., cellular phones, laptops) and enterprise systems (such as server chips in computer servers). The IC chip also includes a hierarchical power management system configured to control the power consumption of the processor-based system at both a local level and a centralized level to achieve desired performance within the IC chip's total power budget. The hierarchical power management system may be configured to control power consumption by controlling the power levels (e.g., voltage levels) distributed at one or more power rails in the IC chip that supply power to the PUs and integrated supporting processing devices. For example, a tiered power management system can be configured to provide additional power to certain power rails supplying power to devices that require higher current for enhanced performance, while providing less power to other power rails to keep the total power within the IC chip's power and / or thermal limits. A tiered power management system can also be configured to control power consumption by moderating the performance (e.g., frequency) of processing devices in a processor-based system, which in turn moderates (i.e., reduces, maintains, or increases) their current demand and thus their power consumption. Note that, as used herein, moderating can mean taking action that reduces or increases parameters affecting power and thus results in a corresponding reduction or increase in power consumption.

[0035] A tiered power management system is configured to regulate the performance of processing devices in a processor-based system, as the level of processing activity in the processing devices within an SoC can vary based on workload conditions. Some power rails in an SoC may experience increased current demands. It is expected that these current demands will not exceed the maximum current limit of their respective power rails. Even if the higher current demand on a power rail is within its maximum current limit, the increased activity of the processing devices in the SoC can cause a sudden increase in the current demand from its power rail, known as a "di / dt" event. This di / dt event can cause a voltage drop in the power rail, negatively impacting the performance of the processing devices powered by such power rails. Moreover, even if the higher current demand on a power rail is within its maximum current limit, the higher current demand can still increase the total power consumption of the SoC. The processing device may have a maximum rated power that operates correctly and / or does not undesirably affect performance. Higher current demands from the processing device can also generate excessive heat. Therefore, the maximum rated power of the SoC may be based in part on the SoC's ability to dissipate the heat generated by the processing devices during their operation.

[0036] In an exemplary aspect, the hierarchical power management system includes Local Area Management (LAM) circuitry distributed throughout an IC chip, each LAM circuitry associated with one or more processing devices within the IC chip. The LAM circuitry is configured to generate power events associated with the processing devices it monitors within the IC chip, representing power consumption associated with the monitored processing devices. Power events can be reported from a local area within the IC chip performing a power estimate for the specific monitored processing device to centralized power estimation and limiting (PEL) circuitry in the hierarchical power management system. The PEL circuitry is configured to estimate and control (i.e., moderate) power in a processor-based system within the IC chip to achieve desired performance within the IC chip's total power budget. The PEL circuitry determines how to moderate power based on the received power events. For example, a power event may be associated with an estimate of power consumption, which, if the estimated power consumption exceeds the IC chip's power limits or negatively impacts performance, can be considered a power moderation recommendation for moderating power within the IC chip.

[0037] The activity of the processing devices in an IC chip affects its steady-state and transient current (i) demand (di / dt), and thus its power consumption. Because IC chips can be larger in die area due to the integration of the PU and the integrated support processing devices, there can be a significant delay between the PEL circuit receiving a power event regarding the power consumption of the monitored processing device and the PEL circuit regulating the power in the IC chip in response. For example, this delay may cause devices in the IC chip to temporarily continue consuming excessive power, potentially leading to performance problems (e.g., di / dt issues, voltage drops, heat generation) before the power management circuitry has time to react.

[0038] Mechanisms designed to address these issues may face additional challenges because the power limiting management determinations and corresponding commands generated by the PEL circuitry must be communicated to various destination elements within the SoC responsible for actually implementing the power limiting operations. Such power limiting management responses must reach the destination elements quickly enough to effectively manage local hotspots and peak power consumption. In conventional SoCs, commands for power limiting management can be sent using packetized commands transmitted via an on-chip communication network (i.e., the architecture). However, congestion of data traffic on the architecture can lead to increased latency and additional overhead. Furthermore, conventional architecture-based communication may employ addressing mechanisms based on source and destination identifiers, which can further delay time-sensitive power limiting management responses.

[0039] To broadcast power limiting management responses in a processor-based system within an IC chip, some aspects of the hierarchical power management system disclosed herein provide a dedicated Limiting Management Throughput Control (LMTT) bus, separate from the communication network (e.g., architecture) provided by the processor-based system of the IC chip. This bus enables an LMTT source circuit to broadcast LMTT commands directly to multiple Activity Management (AM) circuits. In exemplary operation, the LMTT source circuit receives a power limiting management response from a PEL circuit via the communication network of the processor-based system. The LMTT source circuit generates an LMTT command based on the power limiting management response and then broadcasts the LMTT command to each of the multiple AM ​​circuits in the processor-based system via the LMTT bus. Each of the multiple AM ​​circuits receives the LMTT command from the LMTT source circuit via the LMTT bus and performs power control operations based on the LMTT command.

[0040] According to some aspects, the LMTT source circuit may include local AM (RAM) circuitry of the IC, and each of the plurality of AM circuits may include LAM circuitry of the IC. In some aspects, the LMTT source circuit includes a temperature sensor hub (THUB) circuitry of the IC, while each of the plurality of AM circuits includes LAM circuitry of the IC. Some aspects may specify that the LMTT source circuit includes a THUB circuitry of the IC, and each of the plurality of AM circuits includes RAM circuitry of the IC. In some aspects, the LMTT source circuit may include a drop detection circuitry of the IC, while each of the plurality of AM circuits may include RAM circuitry of the IC.

[0041] In some respects, the LMTT bus includes a three (3) wire bus, and the LMTT command includes an enable indication transmitted via the first wire of the three (3) wire bus, a control value indication transmitted via the second wire of the three (3) wire bus, and a control target indication transmitted via the third wire of the three (3) wire bus. Some of these respects may specify that the control value indication includes a three (3) bit value transmitted serially via the second wire of the three (3) wire bus, and the control target indication includes a two (2) bit value transmitted serially via the third wire of the three (3) wire bus.

[0042] On this point, Figure 1 This is a schematic diagram of an exemplary processor-based system 100 in the form of an exemplary system-on-chip (SoC) 102 in which a graded power management system may be provided. The SoC 102 can be used in smaller mobile devices (e.g., cellular phones, laptops) as well as enterprise systems (such as server chips in computer servers). First, regarding... Figure 1 The processor-based system 100 is described below, and then... Figure 2 The description begins with an exemplary hierarchical power management system that can be provided in a processor-based system 100 to estimate and control power consumption in an IC chip 104.

[0043] refer to Figure 1The processor-based system 100 is provided in a single semiconductor die 106, enabling integration of the processor-based system 100 into a single IC chip 104. The processor-based system 100 includes multiple processing unit (PU) clusters 108(0)-108(N), which are examples of processing devices 110 within the processor-based system 100. Each PU cluster 108(0)-108(N) may include one or more processor cores 112(0)-112(N), each configured to execute instructions (e.g., software, firmware) to perform a task known to the processor. For example, the PU cluster 108(0)-108(N) may be a central processing unit (CPU) cluster, wherein one or more processor cores among the processor cores 112(0)-112(N) include a CPU and / or a graphics processing unit (GPU) cluster, wherein one or more processor cores among the processor cores 112(0)-112(N) include a GPU. The processor-based system 100 includes an internal communication network 114 that facilitates communication paths between PU clusters 108(0)-108(N) and other supporting processing devices (which are also considered processing devices) to execute desired processing requests and associated processing tasks. The PU clusters 108(0)-108(N) are communicatively coupled to the internal communication network 114. The internal communication network 114 may be a coherent communication bus provided within the processor-based system 100. The internal communication network 114 may be a network structure, typically consisting of network nodes and their communication lines, wire networks, and / or communication channels that provide reliable communication paths between the different PU clusters 108(0)-108(N) and the supporting processing devices 110. Network nodes are circuits (such as interconnected switches and routers) that provide and receive data on the communication paths between the different PU clusters 108(0)-108(N) and the supporting processing devices 110. The architecture provided by the internal communication network 114 also includes a wire network or communication channel that allows different processing devices in the processor-based system 100 to communicate with each other and exchange data at high speed.

[0044] For example, such as Figure 1 As shown, the processor-based system 100 also includes an internal cache memory 116 and memory controllers (MC) 118(0)-118(M) as other types of processing devices 110 that provide access to memory. Figure 1The cache memory 116 shown is a shared cache memory communicatively coupled to the internal communication network 114 and accessible by the PU clusters 108(0)-108(N) via the internal communication network 114. The processor-based system 100 may also include private cache memories and / or private shared cache memories integrated by one or more of the respective PU clusters 108(0)-108(N) or accessible privately by them without needing to be accessed through the internal communication network 114. Memory controllers 118(0)-118(M) are communicatively coupled to the internal communication network 114 within the IC chip 104. The memory controllers 118(0)-118(M) provide the PU clusters 108(0)-108(N) with access to the memory for storing and retrieving data, thereby performing processing tasks. For example, the memory controllers 118(0)-118(M) may be coupled to external memory from the IC chip 104 or internal memory integrated within the IC chip 104.

[0045] Similarly, Figure 1 As shown, the processor-based system 100 in this example also includes I / O interface circuitry 120(0)-120(X) as another example of a processing device 110 that is also communicatively coupled to an internal communication network 114. I / O interface circuitry 120(0)-120(X) provides access to I / O devices, which may be internal to and integrated within the IC chip 104, or external to the IC chip 104. For example, I / O interface circuitry 120(0)-120(X) may be a peripheral component interconnect (PCI) interface circuitry used to connect I / O hardware devices to a processor-based system (such as...). Figure 1 The processor-based system 100 allows high-speed data transfer between devices and PU clusters 108(0)-108(N) within the processor-based system 100.

[0046] Similarly, Figure 1 As shown, the processor-based system 100 in this example also includes, as another example, a socket-to-socket (S2S) interface circuit 122(0)-122(Y) that is also communicatively coupled to the processing device 110, which is also communicatively coupled to the internal communication network 114. The S2S interface circuit 122(0)-122(Y) allows the processor-based system 100 to be coupled to another separate processor-based system (which may be similar to...) via a socket-to-socket connection. Figure 1 (The processor-based system 100 in the example). Figure 1 The processor-based system 100 shown may be a first CPU motherboard system that can be communicatively coupled to another processor-based system via an internal communication network 114 and coupled S2S interface circuits 122(0)-122(Y).

[0047] Similarly, Figure 1 As shown, the processor-based system 100 in this example also includes other interface (I / F) circuits 127(0)-127(Z) as another example of a processing device 110 also communicatively coupled to an internal communication network 114. Interface circuits 127(0)-127(Z) can provide additional external communication interfaces to the SoC 102 and can be configured to provide communication interfaces according to desired standards or protocols. For example, interface circuits 127(0)-127(Z) can be PCIe interface circuits configured to support PCIe communication with the SoC 102.

[0048] Therefore, in Figure 1 In the processor-based system 100, an internal communication network 114 enables different processing devices (such as PU clusters 108(0)-108(N) and their processor cores 112(0)-112(N), caches, memory controllers 118(0)-118(M), I / O interface circuits 120(0)-120(X) and / or S2S interface circuits 122(0)-122(Y)) to work together efficiently. The architecture provided by the internal communication network 114 is designed to provide high bandwidth, low latency, and efficient data routing between the different processing devices of the processor-based system 100.

[0049] Moreover, such as Figure 1As shown and described in more detail below, the processor-based system 100 also includes a hierarchical power management system 124. In this example, the hierarchical power management system 124 is integrated into the same IC chip 104 and in the same die 106 including the PU clusters 108(0)-108(N) and the internal communication network 114. The hierarchical power management system 124 is configured to control the power consumption of the processor-based system 100 by controlling the power consumption of some or all of the processing devices 110 in the IC chip 104. The hierarchical power management system 124 is configured to control power consumption to achieve desired performance within the total power budget of the IC chip 104. For example, the processor-based system 100 may have a total power budget based on the ability of the IC chip 104 to dissipate heat generated by the operation of the processor-based system 100. The processor-based system 100 may also have a total power budget based on the current limits of the power rails in the IC chip 104. The power budget of the processor-based system 100 may also be based on the power supply limits of the power source powering the processor-based system 100. Therefore, the hierarchical power management system 124 can be configured to control power consumption by controlling the power levels (e.g., voltage levels, operating frequencies) distributed across one or more power rails in the IC chip 104 that supply power to the processing device 110. For example, the hierarchical power management system 124 can be configured to supply additional power to some power rails to supply power to devices with higher current demands for higher performance, while supplying less power to other power rails to keep the total power within the power and / or thermal limits of the IC chip 104. For example, the hierarchical power management system 124 can be configured to communicate with or include a power management integrated circuit (PMIC) chip 125 (which may be on-chip or off-chip with the SoC 102) to effectively adjust the power supplied to certain power rails.

[0050] Furthermore, as discussed in more detail below, the hierarchical power management system 124 can also be configured to control power consumption in the processor-based system 100 by modulating the performance (e.g., frequency and / or voltage) of the processing device 110 in the processor-based system 100. Modulation can refer to any measure that achieves (i.e., reduces, maintains, or increases) power consumption (e.g., modifies the clock frequency and / or supply voltage). This, in turn, modifies (i.e., reduces, maintains, or increases) the current demand of such processing device 110, and thus modifies (i.e., reduces, maintains, or increases) its power consumption in the IC chip 104. According to the power equation P = cf V 2The performance of the clock control circuitry in the processing device 110 of the processor-based system 100 in terms of frequency (f) is related to power (P), where "c" is the capacitor and "V" is the voltage. Therefore, reducing the frequency and / or voltage of the clock control circuitry in the processing device 110 of the processor-based system 100 will also reduce its power consumption.

[0051] Figure 2 yes Figure 1 The example logic diagram of a processor-based system 100 illustrates a processing device 110 communicatively coupled to an internal communication network 114, and a hierarchical power management system 124 for controlling power consumption in an IC chip 104. Figure 1 and Figure 2 Common components in the processor-based system 100 are shown by common component numbers and therefore will not be described further. The IC chip 104 may also include target devices 200 whose control affects power; these target devices may include the processing device 110 and other circuitry described below. As will be discussed in more detail below, the hierarchical power management system 124 is configured to control power to both the target devices 200 and the processing device 110 to regulate power consumption in the IC chip 104.

[0052] Similarly, Figure 2As shown, the hierarchical power management system 124 includes a centralized power estimation and limiting (PEL) circuitry 126 configured to estimate power consumption in IC chip 104 and take action to limit or control power consumption in IC chip 104. In this example, PEL circuitry 126 may be provided as part of a power management integrated circuit (PMIC) 125 integrated into IC chip 104. PEL circuitry 126 may communicate such power control requests to a power management controller (PMC) 128, for example, which is configured to control the power supplied by voltage rails in IC chip 104. Controlling power consumption may include increasing power (e.g., increasing the voltage to the power rail), thereby increasing power consumption to increase performance, and decreasing power (e.g., decreasing the voltage to the power rail) to reduce power consumption. The hierarchical power management system 124 is configured to estimate power consumption in IC chip 104 by receiving power events 130 reported to it from devices at lower hierarchical levels in IC chip 104, which provide information that provides an indirect indication of power consumption. For example, IC chip 104 may have one or more temperature sensors 132 configured to report thermal power events 130(1) to PEL circuitry 126 to provide an indication of temperature in IC chip 104, which can then be correlated with the power consumption of processor-based system 100 in IC chip 104. As another example, IC chip 104 may have one or more telemetry sensors 134 (e.g., current sensors) configured to detect telemetry power events 130(2) and report them to PEL circuitry 126 to provide an indication of telematics information in IC chip 104, which can then also be correlated with the power consumption of processor-based system 100 in IC chip 104.

[0053] The power consumption of the processing device 110 in the processor-based system 100 contributes to the power consumption of the IC chip 104. Therefore, it may be desirable to also have a way for the PEL circuit 126 in the graded power management system 124 to receive a direct indication of the power consumption of the processing device 110. The PEL circuit 126 can then also use this information to estimate the power consumption in the IC chip 104 and use such information to regulate the power consumption in the IC chip 104. At this point, as... Figure 2 As shown, the graded power management system 124 also includes Local Area Management (LAM) circuitry 136, each associated with one or more processing devices 110 in the IC chip 104. The LAM circuitry 136 can be placed in various locations within the IC chip 104, including corners of the IC chip 104 where power estimation and power limiting may be required. For example, LAM circuitry 136(1)(0)-136(1)(N) can be associated with... Figure 2One or more PU clusters in PU clusters 108(0)-108(N) shown are associated with each other. As another example, LAM circuits 136(2)-136(5), 136(6)(0)-136(6)(X) may also be associated with one or more memory controllers in memory controller 118, internal communication network 114 (e.g., structure), one or more I / O interface circuits in I / O interface circuit 120, one or more S2S circuits in S2S circuit 122 and / or one or more interface circuits 127(0)-127(Z). Each LAM circuit 136(2)-136(5), 136(6)(0)-136(6)(X) is configured to monitor activities associated with the processing device 110 being monitored, and then generate corresponding activity power events 138(1)(0)-138(1)(N), 138(2)-138(5), 138(6)(0)-138(6)(Z), which are directly or indirectly transmitted to the PEL circuit 126. The activity power events 138(1)(0)-138(1)(N), 138(2)-138(5), 138(6)(0)-138(6)(Z) contain information related to the power consumption of the corresponding monitored processing device 110. For example, active power events 138(1)(0)-138(1)(N), 138(2)-138(5), and 138(6)(0)-138(6)(Z) may contain processing activity information or power consumption information generated by the corresponding LAM circuits 136(1)(0)-136(1)(N), 136(2)-136(5), and 136(6)(0)-136(6)(X) based on the processing activity of the monitored processing device 110 to estimate the power consumption of the monitored processing device 110. In either case, in this way, active power events 138 can be reported from the local area in the IC chip 104 that performs power estimation for a specific monitored processing device 110 to the centralized PEL circuit 126. PEL circuit 126 can then be configured to use the received active power event 138 and / or other power events 130 to estimate and control (i.e., regulate) the power in the processor-based system 100 within IC chip 104 to achieve desired performance within the total power budget of IC chip 104. For example, active power event 138 is associated with an estimate of the power consumption of processing device 110, which can be essentially considered a power regulation recommendation for PEL circuit 126 to regulate the power in IC chip 104 if the estimated power consumption exceeds the power limit of IC chip 104 or negatively impacts performance in an undesirable manner.

[0054] The PEL circuit 126 is configured to receive active power events 138 relating to the activity of individual processing devices 110 in the processor-based system 100. This also allows the PEL circuit 126 to locally control power consumption at certain processing devices 110 responsible for increased power consumption. This allows the PEL circuit 126 to control power more selectively, rather than just controlling power at power rails or in other ways within the IC chip 104, affecting the overall power delivered to the larger set of processing devices 110. For example, as discussed in more detail below, the PEL circuit 126 can be configured to use the received active power events 138 to perform performance control of the processing devices 110 in the processor-based system 100 to control their power consumption. The PEL circuit 126 can be configured to generate power limit management responses 140 to be communicated to certain LAM circuits 136 in the processor-based system 100, so that such LAM circuits 136 limit the performance of the processing devices 110 they monitor.

[0055] Performance control of the processing device 110 in the processor-based system 100 can be implemented in various ways to control its power consumption. For example, as discussed in more detail below, performance control can be achieved by PEL circuitry 126 generating a throughput control power limit management response 140, which is directed to LAM circuitry 136(3) associated with the internal communication network 114. LAM circuitry 136(3) can be configured to control the throughput of communication traffic in the internal communication network 114 (such as at a specific network node in the internal communication network 114) to control the current demand in the internal communication network 114 and thus its power consumption. Throughput control can be limited to certain areas or network nodes in the internal communication network 114. In another example, as discussed in more detail below, performance control in processor-based system 100 can be achieved by PEL circuitry 126 generating a clock control power limit management response 140 to cause clock circuitry (which may be clocking one or more processing devices in processing device 110) to control the speed (i.e., clock frequency) of certain clock-controlled processing devices 110. Clock control of processing device 110 controls its current demand, which in turn controls its power consumption. In another example, as discussed in more detail below, performance control in processor-based system 100 can be achieved by controlling or altering the power state of monitored processing device 110 to control its performance and thus its power consumption.

[0056] Figure 3 yes Figure 1A top view of an exemplary physical layout of the semiconductor die (“die”) 102 of the IC chip 104, which includes a processor-based system 100, to illustrate further exemplary details of the physical layout of the hierarchical power management system 124 and exemplary organization of the power rails provided in the processor-based system 100.

[0057] like Figure 3As shown, IC chip 104 has a physical layout including a central block (CTILE), a western block (WTILE), an eastern block (ETILE), a southern block (STILE), a northern block (NTILE), and an A block (ATILE). A block is a smaller portion of a semiconductor die that has already been processed during the wafer fabrication process and contains an assembly of IC components. In this example, the central block (CTILE) includes PU clusters 108(0)-108(N), shown as NCC0-NCC19. Different numbers of processor cores can be provided in different PU clusters 108(0)-108(N) and NCC0-NCC19. In this example, PU clusters 108(0)-108(N) and NCC0-NCC19 are all powered by the same power rail 300(1). The central block (CTILE) in this example also includes an internal communication network 114, which is shown by multiple central network nodes FABC00-FABC65. Network nodes FABC00-FABC65 are circuits that create a network structure (“structure”) between different PU clusters 108(0)-108(N) and supporting processing device 110. In this example, network nodes FABC00-FABC65 are powered by a second power rail 300(2). Network nodes FABC00-FABC65 are circuits that may include interconnected switches and / or routers that provide a reliable network structure for providing and receiving data on an internal communication network 104 between different PU clusters 108(0)-108(N) and supporting processing device 110. The central block CTILE in this example also includes system-level cache memories 116(0)-116(7) powered by a third power rail 300(3) to provide shared cache memory 116 for PU clusters 108(0)-108(N), NCC0-NCC19. System-level cache memories 116(0)-116(7) are organized adjacent to and coupled to different quadrants of corresponding memory circuits DDR0-DDR7, including corresponding memory controllers 118(0)-118(7) in the Western Block WTILE and coupled memories 304(0)-304(7) (e.g., Dynamic Data Random Access Memory (DDR) circuitry), to provide, for example, a memory interleaving scheme. Memory circuits DDR0-DDR7 may be powered by another separate fourth power rail 300(4). Memory circuits DDR0-DDR7 are also communicatively coupled to internal communication network 114 via corresponding network nodes FABC00-FABC05.

[0058] Continue to refer to Figure 3The central block CTILE in this example also includes system-level cache memories 116(8)-116(15), which are also powered by a third power rail 300(3) to provide additional shared cache memories 116 for PU clusters 108(0)-108(N), NCC0-NCC19. The system-level cache memories 116(8)-116(15) may be organized into different quadrants adjacent to the corresponding memory circuits DDR8-DDR15, which include the corresponding memory controllers 118(8)-118(15) and coupled memories 304(8)-304(15) (e.g., DDR circuits) in the eastern block ETILE, to provide, for example, a memory interleaving scheme. The memory circuits DDR8-DDR15 are also shown as being powered by the same fourth power rail 300(4) that powers the memory circuits DDR0-DDR7 in the western block WTILE. The memory circuits DDR8-DDR15 are also communicatively coupled to the internal communication network 114 via corresponding network nodes FABC60-FABC65.

[0059] Continue to refer to Figure 3 In this example, the central block CTILE of IC chip 104 includes request node circuits FABS00, FABS40, FABN57, and FABN47, which are coupled to an internal communication network 114 to provide a network interface between the I / O interface circuits 120(0)-120(3), 120(4)-120(7) in the corresponding southern block STILE and northern block NTILE and the internal communication network 114. The request node circuits FABS00, FABS40, FABN57, and FABN47 manage service requests from the I / O interface circuits 120(0)-120(3), 120(4)-120(7) to the internal communication network 114 and vice versa. In this example, the request node circuits FABS00, FABS40, FABN57, FABN47 and the I / O interface circuits 120(0)-120(3), 120(4)-120(7) are powered by the fifth power rail 300(5).

[0060] Continue to refer to Figure 3 In this example, block ATILE in IC chip 104 includes PEL circuit 126 and PMC 128 of graded power management system 124.

[0061] Therefore, as Figure 3As shown, the processing device 110 in the processor-based system 100 of IC chip 104 is powered by a series of different power rails 300(1)-300(5). Therefore, the PEL circuit 126 in the hierarchical power management system 124 has a resolution for each of these different power rails 300(1)-300(5), wherein the voltage on such power rails 300(1)-300(5) is changed based on power events 130, 138 to regulate the power consumption in IC chip 104. Note that each power rail 300(1)-300(5) may actually be included as a single or multiple power rails.

[0062] Figure 4 Table 400 illustrates an exemplary allocation of power management circuits AK0-AK5 in the PMIC 125 of a processor-based system 100 to devices within the processor-based system 100 for supplying power to such devices. The power management circuits AK0-AK5 are responsible for controlling, for example... Figure 3 One or more different power rails 300(1)-300(5) are shown to supply power to various components. Multiple devices in the processor-based system 100 can be coupled to the same power rail 300(1)-300(5) to receive power. For example, as Figure 4 As shown, in this example, PU clusters NCC19, 18, 15, and 14 are powered from the power rail controlled by power management circuit AK0; PU clusters NCC11-10 are powered from the power rail controlled by power management circuit AK1; PU clusters NCC2, 3, 6, and 7 are powered from the power rail controlled by power management circuit AK2; PU clusters NCC0, 1, 4, and 5 are powered from the power rail controlled by power management circuit AK3; PU clusters NCC9-8 are powered from the power rail controlled by power management circuit AK4; and PU clusters NCC12, 13, 16, and 17 are powered from the power rail controlled by power management circuit AK5. Furthermore, as... Figure 4 As shown, a single device in the processor-based system 100 can be coupled to more than one power rail to receive power. For example, the power supplied to the logic circuit (SoC_Logic) can be controlled by multiple power management circuits AK1-AK4. The cache memory 116 can be supplied with power from the power rails controlled by the power management circuits AK0-AK5. Different memory controllers 118 are shown as being powered by power rails controlled by the power management circuits AK0-AK5. The I / O interface circuits 120(0)-120(3) are shown as being powered by power rails controlled by separate corresponding power management circuits AK3, AK2, AK5, and AK0.

[0063] Figure 5 yes Figure 1Another top view of the processor-based system 100 in IC chip 104 illustrates Local Area Management (LAM) circuitry 136 and PEL circuitry 126 as part of a graded power management system 124. (See above regarding...) Figure 2 As discussed, the LAM circuit 136 is configured to locally monitor the activity of processing devices 110 (such as PU clusters 108(0)-108(N)) in the processor-based system 100 to estimate and regulate their power consumption, and to report activity power events 138 regarding the estimated power consumption to the PEL circuit 126. The processor-based system 100 in this example includes a clock circuit 506 that generates a clock signal 508 to clock the PU clusters 108(0)-108(N), thereby controlling the speed of the PU clusters 108(0)-108(N). The PEL circuit 126 is configured to collect activity power events 138 regarding the monitored power consumption of the processing devices 110, and in response, issue a power limit management response 140 to regulate power consumption in the IC chip 104.

[0064] like Figure 5 As shown, multiple LAM circuits 136(3) are distributed in the central block CTILE and associated with corresponding network nodes 500 (as processing devices 110) of the internal communication network 114. For example, the internal communication network 114 may be as follows: Figure 5 The mesh network shown in the figure. The internal communication network 114 is able to route communication services from PU clusters 108(0)-108(N) through different network nodes 500 based on the performance and service characteristics of the internal communication network 114. In this way, the throughput of the internal communication network 114 is not limited by any single network node 500. The processor-based system 100 in this example includes a clock circuit 510 that generates a clock signal 512 to clock the network nodes 500, thereby controlling the speed of the internal communication network 114. The clock circuit 510 is another example of the target device 200 in the IC chip 104. As will be discussed in more detail below, the LAM circuit 136(3) associated with the network nodes 500 in the internal communication network 114 is configured to sample the processing activity of the correspondingly assigned network nodes 500 to generate multiple activity samples. The LAM circuit 136(3) is then configured to estimate the power consumption of the assigned network node 500 based on activity samples of the assigned network node 500, so as to generate an active power event 138 based on such estimated power consumption of the corresponding network node 500.

[0065] Moreover, such as Figure 5As shown, in this example, the hierarchical power management system 124 also includes local activity management (RAM) circuitry 502(3) configured to monitor the activity of an internal communication network 114. RAM circuitry 502(3) is located in specific areas of the internal communication network 114, with each RAM circuitry assigned and coupled to a subset of LAM circuitry 136(3). RAM circuitry 502(3) is an intermediate power management circuitry in the hierarchical power management system 124. RAM circuitry 502(3) is coupled to PEL circuitry 126 via a second communication network 504. RAM circuitry 502(3) is communicatively and hierarchically located between LAM circuitry 136(3) and centralized PEL circuitry 126. RAM circuitry 502(3) is configured to receive and aggregate activity power events 138 reported by the assigned LAM circuitry 136(3) regarding the activity of the network nodes 500 it monitors. RAM circuit 502(3) can then aggregate these active power events 138 and report the aggregated active power events to PEL circuit 126, so that PEL circuit 126 can determine how to control the power consumption of network node 500 to achieve the desired overall performance of internal communication network 114 while keeping power consumption within desired limits. PEL circuit 126 can communicate power limit management response 140 back to given RAM circuit 502(3) to perform throughput control of given network node 500 in response to determining that the power consumption of network node 500 exceeds the desired limit. For example, as discussed in more detail below, RAM circuit 502(3) can be configured to control the throughput of given network node 500 by selectively enabling and disabling communication services through network node 500.

[0066] Moreover, such as Figure 5 As shown, in this example, multiple LAM circuits 136(2) are distributed across the western tile WTILE and the eastern tile ETILE, and are associated with corresponding memory circuits DDR0-DDR7, DDR8-DDR15 (as processing device 110). As will be discussed in more detail below, the LAM circuits 136(2) associated with memory circuits DDR0-DDR7, DDR8-DDR15 are configured to sample the processing activity of the correspondingly assigned memory circuits DDR0-DDR7, DDR8-DDR15 to generate multiple activity samples. The LAM circuits 136(2) are then configured to estimate the power consumption of the assigned memory circuits DDR0-DDR7, DDR8-DDR15 based on the activity samples with respect to the network node 500 to generate an activity power event 138 based on such estimated power consumption of the corresponding memory circuits DDR0-DDR7, DDR8-DDR15.

[0067] Moreover, such as Figure 5As shown, in this example, the hierarchical power management system 124 also includes RAM circuits 502(2) configured to monitor the activity of memory circuits DDR0-DDR7, DDR8-DDR15. RAM circuits 502(2) are located in specific regions of memory circuits DDR0-DDR7, DDR8-DDR15, with each RAM circuit allocated and coupled to a subset of LAM circuits 136(2). RAM circuits 502(2) are communicatively and hierarchically located between LAM circuits 136(2) and centralized PEL circuits 126. RAM circuits 502(2) are coupled to PEL circuits 126 via a second communication network 504. RAM circuits 502(2) are configured to receive and aggregate active power events 138 reported by the allocated LAM circuits 136(2) regarding the activity of the monitored memory circuits DDR0-DDR7, DDR8-DDR15. RAM circuit 502(2) can then aggregate these active power events 138 and report the aggregated active power events to PEL circuit 126, so that PEL circuit 126 can determine how to control the power consumption of memory circuits DDR0-DDR7, DDR8-DDR15 to achieve the desired overall performance of memory circuits DDR0-DDR7, DDR8-DDR15, while keeping the power consumption within the desired limits. PEL circuit 126 can communicate a power limit management response 140 back to the given RAM circuit 502(2) to perform throughput and / or performance control of the given memory circuits DDR0-DDR7, DDR8-DDR15 in response to determining that the power consumption of memory circuits DDR0-DDR7, DDR8-DDR15 exceeds the desired limits. For example, as discussed in more detail below, RAM circuit 502(2) can be configured to control the throughput and / or performance of the given memory circuits DDR0-DDR7, DDR8-DDR15 by selectively enabling and disabling memory access requests / responses to memory circuits DDR0-DDR7, DDR8-DDR15.

[0068] Moreover, such as Figure 5As shown, in this example, the hierarchical power management system 124 also includes RAM circuits 502(4) configured to monitor the activity of I / O interface circuits 120(0)-120(7). RAM circuits 502(4) are located in specific areas of the I / O interface circuits 120(0)-120(7), with each RAM circuit assigned and coupled to a subset of LAM circuits 136(4), as shown. RAM circuits 502(4) are communicatively and hierarchically located between LAM circuits 136(4) and centralized PEL circuits 126. RAM circuits 502(4) are coupled to PEL circuits 126 via a second communication network 504. RAM circuits 502(4) are configured to receive and aggregate active power events 138 reported by the assigned LAM circuits 136(4) regarding the activity of the I / O interface circuits 120(0)-120(7) they monitor. RAM circuit 502(4) can then aggregate these active power events 138 and report the aggregated active power events to PEL circuit 126, so that PEL circuit 126 can determine how to control the power consumption of I / O interface circuits 120(0)-120(7) to achieve the desired overall performance of I / O interface circuits 120(0)-120(7) while keeping the power consumption within the desired limits. PEL circuit 126 can communicate power limit management response 140 back to given RAM circuit 502(4) to perform throughput and / or performance control of given I / O interface circuits 120(0)-120(7) in response to determining that the power consumption of I / O interface circuits 120(0)-120(7) exceeds the desired limits. For example, as discussed in more detail below, RAM circuit 502(4) can be configured to control the throughput and / or performance of a given I / O interface circuit 120(0)-120(7) by selectively enabling and disabling access requests / responses to I / O interface circuits 120(0)-120(7).

[0069] like Figure 2As shown, LAM circuits 136(1)(0)-136(1)(N) can also be associated with each PU cluster 108(0)-108(N) in the processor-based system 100 to sample the activity therein, thereby estimating the power consumption in the corresponding PU cluster 108(0)-108(N). LAM circuits 136(1)(0)-136(1)(N) can be configured to generate active power events 138 including the estimated power consumption in response to RAM circuit 502, which in turn aggregates such active power events 138 to PEL circuit 126. RAM circuit 502 assigned to subsets of LAM circuits 136(1)(0)-136(1)(N) is coupled to PEL circuit 126 via a second communication network 504. PEL circuit 126 can generate power limiting management responses 140 in response to regulate the performance of PU clusters 108(0)-108(N).

[0070] Similarly, Figure 2 As shown, the LAM circuit 136(5) can also be associated with each S2S interface circuit 122(0)-122(Y) in the processor-based system 100 to sample the activity therein, thereby estimating the power consumption in the corresponding S2S interface circuit 122(0)-122(Y). The LAM circuit 136(5) can be configured to generate an activity power event 138 including the estimated power consumption in response to RAM circuit 502, which in turn aggregates such activity power events 138 to PEL circuit 126. RAM circuit 502 allocated to a subset of LAM circuit 136(5) is coupled to PEL circuit 126 via a second communication network 504. PEL circuit 126 can generate a power limiting management response 140 in response to regulate the performance of S2S interface circuits 122(0)-122(Y).

[0071] Return as Figure 2 As shown, LAM circuits 136(6)(0)-136(6)(X) can also be associated with each interface circuit 127(0)-127(Z) in the processor-based system 100 to sample the activity therein, thereby estimating the power consumption in the respective interface circuits 127(0)-127(Z). LAM circuits 136(6)(0)-136(6)(X) can be configured to generate active power events 138 including estimated power consumption in response to RAM circuit 502, which in turn aggregates such active power events 138 to PEL circuit 126. RAM circuit 502 assigned to subsets of LAM circuits 136(6)(0)-136(6)(X) is coupled to PEL circuit 126 via a second communication network 504. PEL circuit 126 can generate power limiting management responses 140 in response to regulate the performance of interface circuits 127(0)-127(Z).

[0072] In this example, any of the RAM circuits 502, 502(2)-504(4) discussed above may also include circuitry functionally oriented as LAM circuitry for the assigned processing device 110. At this point, any of the RAM circuits 502, 502(2)-504(4) may also be configured to sample the processing activity of its correspondingly assigned processing device 110 to generate multiple activity samples for such processing device 110. Such RAM circuits 502, 502(2)-504(4) may be configured to estimate the power consumption of their assigned processing device 110 based on the activity samples with respect to it, to generate aggregated activity power events based on such estimated power consumption of the corresponding processing device 110 and other received activity power events 138 from its coupled LAM circuits 136(1)(0)-(1)(N), 136(2)-136(5), 136(6)(0)-136(6)(X).

[0073] Note that in any of the examples referenced above, RAM circuit 502 is optional for any of the processing devices in the monitored processing device 110, and its corresponding LAM circuits 136(1)-136(6) can be configured to directly transmit the active power event 138 to PEL circuit 126.

[0074] Figure 6 Examples can be provided as Figures 1 to 3 and Figure 5 A schematic diagram of additional exemplary details of the three (3) level hierarchical power management system 624 of the processor-based system 100 in the IC chip 104. Figure 6 The graded power management system 624 and Figures 1 to 3 and Figure 5 The common components among the hierarchical power management system 124 are shown by common component numbers. At this point, Figure 6 An example is shown of a single LAM circuit 136 communicatively coupled to a single RAM circuit 502, which in turn is coupled to a PEL circuit 126. However, note that this is for simplicity. Figure 6 Examples in . exist Figure 6In the hierarchical power management system 624, there may be multiple RAM circuits 502 communicatively coupled to PEL circuit 126. There may also be multiple LAM circuits 136 communicatively coupled to each of the multiple RAM circuits 502. The following discussion of exemplary operation of LAM circuits 136 and RAM circuits 502 is equally applicable to any number of LAM circuits and RAM circuits included in a processor-based system, including LAM circuits 136(1)(0)-(1)(N), 136(2)-136(5), 136(6)(1)-136(6)(X) and RAM circuits 502, 502(2)-502(4).

[0075] refer to Figure 6 In this example, the LAM circuit 136 is configured to sample processing activity in each period of a given local time window as received activity samples 600 of the assigned monitored processing device 110. The LAM circuit 136 periodically samples the activity of its monitored processing device 110 within the local time window, representing the activity of the assigned monitored processing device 110 within that local time window. In this example, the LAM circuit 136 is configured to correlate the received activity samples 600 with power consumption during the given local time window for the activity of the processing device 110 within that given local time window. The LAM circuit 136 includes an accumulation circuit 602 configured to accumulate estimated power consumption based on the received activity samples 600 sampled within the given local time window to generate an estimated current demand 604 for the monitored processing device 110 within the local time window. The estimated current demand 604 is an estimate of the accumulated current measurements (i.e., power consumption) reported by the assigned processing device 110 within the local time window. The accumulator circuit 602 then provides an estimated current demand 604 (current demand over time) for each local time window of the active power events 606 generated on the second communication network 504, representing the estimated power consumption of the monitored processing device 110 that is communicated to the RAM circuit 502 allocated to the LAM circuit 136. The accumulator circuit 602 repeats the same process in subsequent local time windows to accumulate the estimated power consumption of the active samples 600 received during the local time window, thereby generating the next estimated current demand 604 for the monitored processing device 110.

[0076] Continue to refer to Figure 6The RAM circuit 502 includes an aggregation circuit 608 configured to aggregate active power events 606 received from its coupled LAM circuit 136 into a generated aggregated active power event 138. The RAM circuit 502 is then configured to transmit the aggregated active power event 138 to the PEL circuit 126 over a second communication network 504. Note that in this example, the RAM circuit 502 also includes its own LAM circuit 136R, which can act as... Figure 6 The LAM circuit 136 is configured as described above. At this point, the LAM circuit 136R is configured to sample the processing activity 600R of the assigned processing device 110 into multiple activity samples 600R. The processing activity 600R of the assigned processing device 110 is periodically sampled by the LAM circuit 136R to generate multiple activity samples within a given local time window, representing the activity of the assigned monitored processing device 110. The LAM circuit 136R is configured to determine the current flow rate and / or current flow rate variation (i.e., di / dt) of the assigned processing device 110 as represented by the received multiple activity samples 600R. The LAM circuit 136R can be programmed to correlate processing activity with power consumption to estimate the power consumption of the monitored processing device 110 within a local time window. LAM circuit 136R can then be configured to generate an active power event 606R representing the estimated power consumption of the monitored processing device 110, which is transmitted to aggregation circuit 608 of RAM circuit 502 to be aggregated into aggregate active power event 138.

[0077] Continue to refer to Figure 6The PEL circuit 126 is configured to receive aggregated active power events 138 from one or more RAM circuits 502 included in the hierarchical power management system 624. In this example, the PEL circuit 126 includes a decoding circuit 610 configured to decode the received aggregated active power events 138 into decoded active power events 611 for routing to corresponding activity tracker circuits 612(1)-612(T), each of which is associated with a monitored processing device 110 in the processor-based system 100. The PEL circuit 126 may also include other energy tracker circuits (not shown) associated with other power events (e.g., temperature, drop detection) that may also affect how the PEL circuit 126 determines how to control power. The activity tracker circuits 612(1)-612(T) are configured to aggregate the associated active power events 138 of the monitored processing device 110 to determine whether the power consumption of the monitored processing device 110 exceeds a defined threshold current flow rate / current flow rate change. The activity tracker circuits 612(1)-612(T) may each include a power limiting management strategy configured to generate corresponding power control recommendations 614(1)-614(T) for the PEL circuit 126 to determine how to control the distributed power and / or performance of the monitored processing device 110, thereby controlling power consumption.

[0078] Continue to refer to Figure 6 The PEL circuit 126 also includes a merging circuit 616 that merges the power control recommendations 614(1)-614(T) of each monitored processing device 110 into a merged power control recommendation 618(1)-618(Q). The merged power control recommendations 618(1)-618(Q) are provided to the correspondingly assigned target circuits 620(1)-620(Q). Each target circuit 620(1)-620(Q) is associated with a different target device 200 in the processor-based system 100, wherein the PEL circuit 126 may issue power limiting management responses 140(1)-140(Q) to limit the power consumption of such target devices 200. Target devices 200 are devices in the IC chip 104 whose operational controls (e.g., operating voltage, frequency, workload) can affect the power consumption in the IC chip 104. Target devices in the IC chip 104 may include more than just the processing devices 110 in the processor-based system 100. For example, target devices 200 may include, for example, devices such as... Figure 3The power rails 300(1)-300(5) shown and / or any processing device in the processing device 110 of the processor-based system 100. The PEL circuit 126 can be programmed to map the combined power control proposals 618(1)-618(Q) (e.g., via firmware, electronic fuses, etc.) to a specific target device 200, and thus to target circuits 620(1)-620(Q), which may not be directly related to each other. For example, it may be expected that the PEL circuit 126 controls the power consumption of the I / O interface circuits 120(0)-120(X) not only by controlling the power consumption of the I / O interface circuits 120(0)-120(X), but also by controlling the power consumption of the PU clusters 108(0)-108(N) that may contribute to the power consumption of the I / O interface circuits 120(0)-120(X). In this way, the combined power control recommendations 618(1)-618(Q) and / or other power events related to power issues and power consumption in IC chip 104 can be mapped in PEL circuit 126 to be associated with different target devices 200 for power control. The combined circuit 616 can be programmed in a "many-to-many mapping" to be associated with different power limit management responses within IC chip 104 in a desired manner, providing greater flexibility in managing power consumption in IC chip 104 while still achieving the desired performance. In this way, the power control management behavior of PEL circuit 126 can be configured and changed even after IC chip 104 has been deployed in the application.

[0079] Continue to refer to Figure 6 Each of the target circuits 620(1)-620(Q) is configured to determine whether the power consumption of the associated target device 200 in the processor-based system 100 should be controlled based on the combined power control proposal 618(1)-618(Q) provided to the target circuits 620(1)-620(Q). Each of the target circuits 620(1)-620(Q) may include finite state machine (FSM) circuits 622(1)-622(Q) configured to analyze the corresponding received combined power control proposal 618(1)-618(Q) to determine whether the power consumption of the associated target device 200 should be controlled. If the FSM circuits 622(1)-622(Q) determine that the power consumption of the associated target device 200 in the processor-based system 100 should be controlled, the FSM circuits 622(1)-622(Q) cause the associated power limiting command generation circuits 625(1)-625(Q) to generate power limiting management responses 140(1)-140(Q) to associate the power consumption of the target device 200 with the power limiting management responses 140(1)-140(Q) for limiting power consumption.

[0080] For example, if target circuits 620(1)-620(Q) are assigned to target device 200 on power rails 300(1)-300(5), then target circuits 620(1)-620(Q) can be configured to determine how to throttle the voltage to the associated power rails 300(1)-300(5) to control the power consumption of processing device 110 powered by such power rails 300(1)-300(5). Corresponding power limit command generation circuits 625(1)-625(Q) can be configured to generate performance throttle power limit management responses 140(1)-140(Q) to throttle the voltage supplied to the associated power rails 300(1)-300(5), thereby controlling the power consumption of processing device 110 powered by such associated power rails 300(1)-300(5).

[0081] In another example, if target circuits 620(1)-620(Q) are assigned to target device 200 (such as internal communication network 114), then target circuits 620(1)-620(Q) can be configured to determine how to moderate the performance of internal communication network 114 to control the power consumption of internal communication network 114. For example, to moderate the throughput performance of internal communication network 114, target device 200 can be a clock circuit 506 configured to clock internal communication network 114. Figure 5 Clock circuit 506 is another example of target device 200 in IC chip 104. Target circuits 620(1)-620(Q) can be determined by clock circuit 506. Figure 5 The frequency of the generated clock signal 508 is controlled to generate clock control power limit management responses 140(1)-140(Q). The clock control power limit management responses 140(1)-140(Q) will control the clock signal 508, which in turn will control the speed and throughput performance of the internal communication network 114, and thus control its power consumption and / or other circuits clocked by the clock signal 508.

[0082] In another example, if target circuits 620(1)-620(Q) are assigned to target device 200 as PU clusters 108(0)-108(N) or any other processing device 110, then target circuits 620(1)-620(Q) may be configured to determine how to throttle the performance of internal communication network 114 to control the power consumption of internal communication network 114. For example, to throttle the performance of PU clusters 108(0)-108(N) or other processing devices 110, target device 200 may also be a clock circuit 506 configured to clock PU clusters 108(0)-108(N). Figure 5The target circuits 620(1)-620(Q) determine the control frequency of the clock signal 508 generated by the clock circuit 506 for use in generating performance power limit management responses 140(1)-140(Q). The clock control power limit management responses 140(1)-140(Q) will control the clock signal 508, which in turn will control the performance of the PU clusters 108(0)-108(N) or other processing devices 110.

[0083] like Figure 6 As shown, in this example, in order to convey the power limit management responses 140(1)-140(Q) generated by the PEL circuit 126 to achieve power control of the target device 200 in the processor-based system 100, the power limit management responses 140(1)-140(Q) are conveyed to the target device 200 in the processor-based system 100. For the target device 200, which is a monitored processing device 110 monitored by the LAM circuit 136 or the RAM circuit 502, the PEL circuit 126 can be configured to convey the associated power limit management responses 140(1)-140(Q) to the RAM circuit 502. In this example, RAM circuit 502 includes a command processor 626 configured to receive and process power limit management responses 140(1)-140(Q) to identify the LAM circuit 136 to communicate with in order to implement the power control requested in the received power limit management responses 140(1)-140(Q). In this example, RAM circuit 502 also includes a limit command engine circuit 628 configured to generate a local power limit management response 630 directed to LAM circuit 136, which can implement the power control requested in the received power limit management responses 140(1)-140(Q). Note that if the local power limit management response 630 is to control the power consumption of multiple processing devices 110 monitored by multiple LAM circuits 136 associated with RAM circuit 502, then the limit command engine circuit 628 can address the local power limit management response 630 to the multiple LAM circuits 136. Also note that in this example, if RAM circuit 502 includes LAM circuit 136R, and RAM circuit 502 is monitoring processing devices 110 as target devices 200 to be controlled, then the limit command engine circuit 628 generates a local power limit management response 630 pointing to LAM circuit 136R.

[0084] Continue to refer to Figure 6In response to the LAM circuit 136 receiving a local power limit management response 630, the power limit management decoder and sequencer circuit 632 is configured to process the received local power limit management response 630. The power limit management decoder and sequencer circuit 632 is configured to determine, based on the local power limit management response 630, a power control response to be implemented to the monitored processing device 110. At this point, the power limit management decoder and sequencer circuit 632 is configured to generate a local control signal 634 to control power consumption in the processing device 110. For example, the power limit management decoder and sequencer circuit 632 may be configured to generate a sequence of local control signals 634 to continuously control the power consumption of the monitored processing device 110 associated with its LAM circuit 136 upwards or downwards.

[0085] Note that the sequence of operations and communications described above regarding LAM circuit 136 communicating active power event 606 to RAM circuit 502 and RAM circuit 502 communicating aggregated active power event 138 to PEL circuit 126 introduces a communication delay. There is a delay between the generation of active sample 600 of power consumption sampling in processing device 110 within LAM circuit 136 and the reporting and receiving of the associated aggregated active power event 138 in PEL circuit 126. This delay can be particularly large for IC chips 104 with large areas (such as IC chips comprising multiple PU clusters 108(0)-108(N) and other processing devices 110 in processor-based systems 100). When PEL circuit 126 receives and processes the associated aggregated power event 138 to generate the associated power limit management response 140(1)-140(Q), the power consumed by the monitored processing device 110 may have exceeded the expected power limit in an undesirable manner and / or for an undesirable amount of time, potentially causing the power consumption in IC chip 104 to exceed the designed power limit. Furthermore, the instantaneous current demand of the monitored processing device 110 may cause di / dt events or voltage drop events, which could lead to performance problems and / or malfunctions that PEL circuit 126 may not be able to resolve in a timely manner.

[0086] To mitigate the delay in PEL circuit 126 receiving aggregate active power events 138 associated with monitored processing devices 110 in the processor-based system 100 (which may affect power consumption control within the processor-based system 100), LAM circuits 136, 136R can also be configured to directly control the performance of their monitored processing devices 110 to control their current demands and thus their power consumption. This gives PEL circuit 126 more reaction time to receive and process aggregate active power events 138 to determine how power consumption in the processor-based system 100 should be controlled to achieve desired overall performance while keeping power consumption within desired limits. In this way, LAM circuits 136, 136R can then be able to mitigate power issues more promptly by locally controlling the power consumption of their specific monitored processing devices 110 at the device granularity (without having to control the performance in other processing devices 110). LAM circuits 136, 136R can be configured to locally and continuously monitor and control power consumption in the processing device 110 they monitor, which coexists with PEL circuit 126, generating a power limiting management response 140 to limit the power consumption of the target device 200 in the processor-based system 100.

[0087] In this respect, such as Figure 6As shown, the LAM circuit 136 in this example includes a di / dt circuit 636 to track the rate of change of power consumption of the processing device 110 for local power consumption control of the processing device 110 it monitors. At this point, the di / dt circuit 636 is configured to receive, in each local time window, an estimated current demand 604 of the activity of the processing device 110 sampled by the LAM circuit 136 from the accumulator circuit 602. For each incoming estimated current demand 604 received (e.g., received within a given local time window), the di / dt circuit 636 is configured to generate a next summed current demand 638 of such incoming estimated current demand 604 from the accumulator circuit 602 in the next local time window, plus one or more previously received estimated current demands 604 received in a previous local time window for a previous estimated current demand 604. In this way, the next summed current demand 638 is the running summation of the estimated current demands 604 of the processing device 110 over consecutive local time windows. The di / dt circuit 636 provides the next summation current demand 638 to the application processor 640, which, based on the next summation current demand 638, provides a determined next current flow rate 642 to the control FSM circuit 644. The control FSM circuit 644 is configured to continuously determine whether the next current flow rate 642 of the allocated processing device 110 exceeds a threshold current flow rate or current flow rate change of the monitored processing device 110 configured for use in the LAM circuit 136. In response to determining that the next current flow rate 642 of the allocated processing device 110 exceeds the threshold current flow rate, the control FSM circuit 644 is configured to generate a local control signal 634 to control the power consumption of the monitored processing device 110.

[0088] In this way, the LAM circuit 136 is configured to continuously monitor the continuous current flow rate of the monitored processing device 110 in order to locally control the power consumption of the monitored processing device 110. In this way, the LAM circuit 136 is configured to respond to power consumption issues caused by the current demand of the monitored processing device 110, such as di / dt events and voltage drops, more quickly than the PEL circuit 126 can respond.

[0089] As an example, if the processing device 110 monitored by LAM circuit 136 is a network node 500 of an internal communication network 114, the local control signal 634 generated by LAM circuit 136 can be throughput control to selectively enable and disable communication flows in network node 500, thereby controlling its throughput and thus its power consumption. As another example, if the processing device 110 monitored by LAM circuit 136 is a PU cluster 108(0)-108(N) or other processing device 110, the local control signal 634 generated by LAM circuit 136 can be performance control to selectively control the performance or workload of the monitored PU cluster 108(0)-108(N) or other processing device 110, thereby controlling its performance and thus its power consumption.

[0090] Note that the sampling of processing activity discussed herein can be accomplished by determining or sampling quantities associated with the transient activity of the monitored processing device 110. For example, the workload performed by the monitored processing device 100 can be determined or discovered indirectly to identify transient activity that may be associated with estimated current or power consumption. As another example, the activity of the monitored processing device 110 can be determined by sensing the temperature at a temperature sensor associated with the processing device 110. As another example, a voltage drop at the processing device 110 can be sensed to determine a sample of activity. Moreover, other quantities can be used to sample activity. As examples, incoming interrupts at the processing device, status registers, the state of the interrupt queue, or signals indicating whether the processing device is busy or idle can be used to sample processing activity.

[0091] Note that the component for performing local control in LAM circuit 136 may also be provided in LAM circuit 136R in RAM circuit 502, so that LAM circuit 136R is also configured as a processing device 110 for local control monitoring.

[0092] Note that in Figure 1 The hierarchical power management system 124 provided in the IC chip 104 of the processor-based system 100 is not limited to... Figure 6 The three (3) level graded power management system 624. For example, Figure 7 It can be provided as Figures 1 to 3 and Figure 5 A schematic diagram of the alternative two (2) level hierarchical power management systems 724 in the processor-based system 100 of the IC chip 104. Figure 7 The graded power management system 724 is similar to Figure 6 The graded power management system 624 in the middle only excludes the intermediate RAM circuit 502. Figure 7In the graded power management system 724, the LAM circuit 136 is configured to directly provide the active power event 606 to the PEL circuit 126 for processing. Figure 7 The graded power management system 724 and Figures 1 to 3 and Figure 5 Common components among the hierarchical power management systems 124 are shown by common component numbers and are not described further.

[0093] Furthermore, as discussed herein or in the claims, it is stated that the PEL circuit 126 receives an active power event 606 from the LAM circuit 136. This reception of the active power event 606 may be a direct reception from the LAM circuit 136 to the PEL circuit 126, or an indirect reception from one or more intermediate circuits including the RAM circuit 502. For example, as discussed above, the active power event 606 generated by the LAM circuit 136 may be indirectly reported to the PEL circuit 126 as part of an aggregated active power event 138 included in the active power event 606 generated by the RAM circuit 502 and reported to the PEL circuit 126 as part of the received active power event 606.

[0094] Figure 8 This is an example Figures 1 to 3 and Figures 5 to 7 A flowchart of an exemplary process 800 in which the LAM circuit 136 and / or RAM circuit 502 in the hierarchical power management systems 124, 624, and 724 locally monitor and control the power consumption of the monitored processing device 110 is provided. Process 800 further includes: in response to received active power events 606 and 138, hierarchically reporting the active power events 606 and 138 related to the monitored power consumption of the LAM circuit 136 and / or RAM circuit 502 to control power consumption in the processor-based system 100. As an example, hierarchical power management systems 624 and 724 are discussed. Figure 8 The process is 800.

[0095] In this respect, such as Figure 8 As shown, the first step of process 800 may be to sample the processing activities of the processing devices 110 assigned to at least one of the power rails 300(1)-300(5) coupled to the power rails 300(1)-300(5) to generate a plurality of activity samples 600. Figure 8 (See box 802 in the original text). The next step in process 800 may be to determine the current flow rate 642 of the assigned processing device 110 based on multiple activity samples 600. Figure 8 (See box 804 in the original text). The next step in process 800 may be to determine whether the current flow rate 642 of the assigned processing device 110 exceeds a defined threshold current flow rate. Figure 8(See box 806 in the original text). The next step in process 800 may be to control the processing activity of the allocated processing device 110 in response to determining that the current flow rate 642 of the allocated processing device 110 exceeds a threshold current flow rate, thereby controlling its power consumption. Figure 8 (See box 808 in the text). Furthermore, in addition to and / or in parallel with steps 804-808, another step in process 800 may be to estimate the power consumption of the allocated processing device 110 based on multiple activity samples 600. Figure 8 (See box 810 in the original text). The next step in process 800 may be to generate active power events 606, 138 based on the estimated power consumption of the assigned processing device 110. Figure 8 (See box 812 in the text). The next step in process 800 can be to receive multiple power events based on active power events 606, 138. Figure 8 (See box 814 in the original text). The next step in process 800 may be to generate a power limit management response 140 based on the received multiple active power events 606, 138 to control power consumption in IC chip 104. Figure 8 (Box 816 in the middle).

[0096] Figure 9A This is an example Figure 6 The diagram illustrates exemplary details of the di / dt circuit 636 and the control FSM circuit 644 in the LAM circuit 136. The di / dt circuit and the control FSM circuit are used to collect estimated current demands 604 received from the monitored processing activity of the processing device 110 within a local time window, and to determine whether the current flow rate and / or current flow rate variation of the monitored processing device 110 exceeds a threshold current flow rate. This information is used by the LAM circuit 136 to determine whether the processing device 110 it monitors should be locally controlled by its assigned LAM circuit 136, as previously described in... Figure 6 The discussion is ongoing.

[0097] In this respect, such as Figure 9A As shown, the di / dt circuit 636 is configured to receive the next estimated current demand 604 generated within each local time window of the LAM circuit 136, as... Figure 6The di / dt circuit 636 discussed includes a plurality of latch circuits 900(1)-900(4), which are clock-controlled circuits (e.g., flip-flops) and are configured to store the incoming next estimated current demand 604 and the previously received estimated current demand 604P(1)-604P(3). The latch circuit 900(1) stores the next incoming estimated current demand 604. Then, for each newly received incoming estimated current demand 604 representing a local time window, the next incoming estimated current demand 604 stored in the latch circuit 900(1) and the previously received estimated current demand 604P(1)-604P(3) stored in the latch circuits 900(1)-900(3) are shifted to the next corresponding latch circuit 900(2)-900(4). For each incoming estimated current demand 604 received, representing a local time window, the incoming estimated current demand 604 and the previously estimated current demands 604P(1)-604P(3) are provided to the corresponding summing circuits 902(1)-902(4). The summing circuits 902(1)-902(3) subtract the incoming estimated current demand 604 from the corresponding previously estimated current demands 604P(1)-604P(3) to generate the corresponding current flow rates (i.e., current flow rate changes) di_dt_1, di_dt_2, di_dt_3 on the local time window of the incoming estimated current demand 604 and the corresponding estimated current demands 604P(1)-604P(3), as discussed below. Therefore, the determined current flow rate changes di_dt_1, di_dt_2, and di_dt_3 represent the rate of change of the current flow rate or current demand of the monitored processing device 110 between the local time window when receiving the incoming estimated current demand 604 and the previous local time window of the corresponding previous estimated current demand 604P(1)-604P(3), and thus represent the rate of change of the power consumption of the monitored processing device. di_dt_1 is the change of current or current flow rate between the corresponding estimated current demand 604 and 604P(1). di_dt_2 is the change of current or current flow rate between the corresponding estimated current demand 604 and 604P(2). di_dt_3 is the change of current or current flow rate between the corresponding estimated current demand 604 and 604P(3).

[0098] Continue to refer to Figure 9AThese current rate changes di_dt_1, di_dt_2, and di_dt_3 are then provided to a multiplexing circuit 904, which can selectively provide one of the current rate changes di_dt_1, di_dt_2, and di_dt_3 as the next current rate 642 to the comparator circuit 906 in the controlled FSM circuit 644 discussed below. The selected current rate changes di_dt_1, di_dt_2, and di_dt_3 provided as the next current rate 642 to the multiplexing circuit 904 are based on a local time window selection signal sel_di_dt_window to select the local time window to be compared with each current rate. This allows the di / dt circuit 636 to be flexible enough to be programmed to select the local time window of the estimated current demand 604P(1) and 604P(2) to be compared with the incoming estimated current demand 604. For example, Figure 9B This is an example of... Figure 9A The exemplary incoming and estimated current demands 604, 604P(1)-604P(3) collected by the di / dt circuit 636 in the diagram 920 are plotted as varying with a local time window to show how the incoming and estimated current demands 604, 604P(1)-604P(3) can be subtracted to generate the corresponding current flow rate changes di_dt_1, di_dt_2, di_dt_3 between the incoming estimated current demand 604 and the estimated current demand 604P(1)-604P(3) on their respective local time windows twN, twN-1, twN-2, twN-3. The duration of the local time window is known. Therefore, the current flow rate changes di_dt_1, di_dt_2, and di_dt_3 represent the changes in current demand over the local time window difference between the incoming estimated current demand 604 and the corresponding previously estimated current demand 604P(1)-604P(3) in the current local time window. Current flow rate curve 922 represents the current flow rate of the processing device 110 during the local time windows twN-3, twN-2, twN-1, and twN. Figure 9B As shown, the slope of the current flow rate curve 922 changes at each of the local time windows twN-3, twN-2, twN-1, and twN based on the changes in current demand or current flow rate demand of the processing device 110 between the local time windows twN-3, twN-2, twN-1, and twN. Figure 9B It shows Figure 9AThe di / dt circuit 636 in the process can generate the basis for current flow rate variations di_dt_1, di_dt_2, di_dt_3, which represent the current demand variation over the difference between the incoming estimated current demand 604 and the corresponding previously estimated current demand 604P(1)-604P(3) in the current local time window, within their local time windows twN-3, twN-2, twN-1, and twN. This can be used to provide the current flow rate 642 of the processing device 110 for determining local power consumption control.

[0099] The selected next current rate 642 is provided by the di / dt circuit 636 to the comparator circuit 906 in the control FSM circuit 644. The control FSM circuit 644 is configured to generate a local control signal 634 to control the power consumption of the monitored processing device 110 based on whether the selected next current rate 642 (from the selection of current rate changes di_dt_1, di_dt_2, di_dt_3) exceeds the threshold current rate (which may include threshold current rate changes) of the monitored processing device 110. The threshold current rate of the monitored processing device 110 can be obtained from the current rate register 908. The current rate register 908 can be programmed with the threshold current rate of the monitored processing device 110. For example, the current flow rate register 908 can be programmed with different threshold current flow rates (e.g., minimum, level 1, level 2, maximum), such that the comparator circuit 906 can generate local control signals 634 for different power consumption control levels based on a comparison between the selected next current flow rate 642 (from the selection of current flow rate changes di_dt_1, di_dt_2, di_dt_3) and the selected threshold current flow rate obtained from the current flow rate register 908.

[0100] Note that when this article discusses current velocity, it also means current flow, and represents the current (I) (I / t) or the change in current velocity (di / dt) over a time period (t). A given change in current velocity (di / dt) is determined based on a given current velocity (t / T).

[0101] The above description Figures 1 to 3 and Figures 5 to 7 The components of the graded power management systems 124, 624, and 724 can be provided in different specific implementations. For example, Figure 10 This is a logic diagram of another exemplary PEL circuit 1026, which can be in... Figures 1 to 3 and Figures 5 to 7 The PEL circuit 126 provided in the graded power management systems 124, 624, and 724. Figure 10 PEL circuit 1026 and Figures 1 to 3 and Figures 5 to 7The common components among the PEL circuits 126 in the graded power management systems 124, 624, and 724 are shown by common component numbers.

[0102] In this respect, such as Figure 10 As shown, PEL circuit 1026 is configured to receive aggregated active power events 138(1)-138(5) from one or more RAM circuits 502. In this example, PEL circuit 1026 includes decoding circuit 610 configured to decode the received aggregated active power events 138(1)-138(5) into corresponding activity tracker circuits 612(1)-612(T), as previously described. PEL circuit 1026 in this example also includes energy tracker circuits 1000(1)-1000(E) associated with energy power events 1002 (such as PMIC telemetry power event 1002(1), temperature event 1002(2), and voltage drop detection event 1002(3) (all of which are examples of inactive power events)), which can also affect how PEL circuit 1026 determines to control power. The PEL circuit 1026 in this example also includes maximum average power (MAP) tracker circuits 1004(1)-1004(B), which are circuit trackers that track the total power consumed in the SoC 102 according to a defined maximum power consumption limit. Similar to the activity tracker circuits 612(1)-612(T), the energy tracker circuits 1000(1)-1000(E) and the MAP tracker circuits 1004(1)-1004(B) are configured to respond to corresponding energy power events 1002(1)-1002(3) and / or aggregate activity power events 138(1)-138(5) to determine whether there is a factor that depends on power consumption exceeding a defined power (e.g., current) threshold / limit.

[0103] Each of the energy tracker circuits 1000(1)-1000(E) includes a corresponding data aggregator circuit 1016(1)-1016(E), which is configured to aggregate received energy power events 1002 into corresponding aggregated energy power events 1018(1)-1018(E). Each of the activity tracker circuits 1000(1)-1000(E) also includes a corresponding data aggregator circuit 1020(1)-1020(T), which is configured to aggregate received energy power events into corresponding aggregated energy power events 1022(1)-1022(T). Each of the MAP tracker circuits 1004(1)-1004(B) also includes a corresponding data aggregator circuit 1024(1)-1024(B), which is configured to aggregate received energy power events into corresponding aggregated MAP power events 1027(1)-1027(B). In this example, the energy tracker circuits 1000(1)-1000(E), the activity tracker circuits 612(1)-612(T), and the MAP tracker circuits 1004(1)-1004(B) each include a corresponding energy power limitation management strategy circuit 1006, an activity power limitation management strategy circuit 1008, and a MAP power limitation management strategy circuit 1010, which are configured to generate corresponding energy power control recommendations 1012, activity power control recommendations 614, and MAP power control recommendations 1014. These generated corresponding energy power control recommendations 1012, active power control recommendations 614 and MAP power control recommendations 1014 are based on the corresponding received aggregated energy power events 1018(1)-1018(E), aggregated active power events 1022(1)-1022(T) and aggregated MAP power events 1027(1)-1027(B) for processing by the PEL circuit 126 to determine how to control the power consumption in the IC chip 104.

[0104] Continue to refer to Figure 10The energy tracker circuits 1000(1)-1000(E), 612(1)-612(T), and MAP tracker circuits 1004(1)-1004(B) are configured to compare the power consumption indicated by the corresponding aggregated energy power event 1018(1)-1018(E), aggregated activity power event 1022(1)-1022(T), and aggregated MAP power event 1027(1)-1027(B) with the corresponding energy power limit management strategy circuits 1006, 1008, and 1010, and the energy tracker circuits 1000(1)-1000(E), 612(1)-612(T), and MAP tracker circuits 1004(1)-1004(B). The energy tracker circuits 1000(1)-1000(E), activity tracker circuits 612(1)-612(T) and MAP tracker circuits 1004(1)-1004(B) are then configured to generate corresponding energy power control recommendations 1012, activity power control recommendations 614 and MAP power control recommendations 1014 based on the power consumption indicated by the corresponding aggregated power events 1018(1)-1018(E), 1022(1)-1022(T), 1027(1)-1027(B) and the comparison with the corresponding power limit management strategy circuits 1006, 1008, 1010. For example, the energy power limiting management strategy circuit 1006, the activity power limiting management strategy circuit 1008, and the MAP limiting management strategy circuit 1010 may each have a corresponding threshold power consumption, which is compared with the corresponding aggregated power events 1018(1)-1018(E), 1022(1)-1022(T), and 1027(1)-1027(B) to determine the corresponding power control recommendations 1012, 614, and 1014.

[0105] Continue to refer to Figure 10The PEL circuit 1026 also includes a merging circuit 616 that merges the energy power control recommendation 1012, the corresponding active power control recommendation 614, and the MAP power control recommendation 1014 into merged power control recommendations 618(1)-618(6). The merged power control recommendations 618(1)-618(6) are provided to the correspondingly assigned target circuits 620(1)-620(6). Note that each merged power control recommendation 618(1)-618(6) may be affected by power control recommendations from each of the energy power control recommendation 1012, the corresponding active power control recommendation 614, and the MAP power control recommendation 1014. Each target circuit 620(1)-620(6) is associated with a different target device 200 in the processor-based system 100, wherein the PEL circuit 1026 may issue power limiting management responses 140(1)-140(6) to limit the power consumption of such target device 200.

[0106] The target device 200 may include interface circuits 127(1)-127(Z) which may be controlled by a power limiting management response 140(1) transmitted to a RAM circuit 502(6) and / or a LAM circuit 136(6), the RAM circuit and / or the LAM circuit being configured to control power consumption in such interface circuits 127(1)-127(Z). The target device 200 may include PU clusters 108(0)-108(N) which may be controlled by a power limiting management response 140(2) transmitted to a RAM circuit 502(1) and / or a LAM circuit 136(1), the RAM circuit and / or the LAM circuit being configured to control power consumption in such PU clusters 108(0)-108(N). The target device 200 may include an internal communication network 114, which may be controlled by a power limiting management response 140(3) transmitted to a RAM circuit 502(3) and / or a LAM circuit 136(3), the RAM circuit and / or the LAM circuit being configured to control power consumption in such an internal communication network 114. The target device 200 may include memory controllers 118(0)-118(M), which may be controlled by a power limiting management response 140(4) transmitted to a RAM circuit 502(2) and / or a LAM circuit 136(2), the RAM circuit and / or the LAM circuit being configured to control power consumption in such memory controllers 118(0)-118(M). The target device 200 may include I / O interface circuits 120(0)-120(X) which may be controlled by a power limiting management response 140(5) transmitted to a RAM circuit 502(4) and / or a LAM circuit 136(4), the RAM circuit and / or the LAM circuit being configured to control power consumption in such I / O interface circuits 120(0)-120(X). The target device 200 may include S2S interface circuits 122(0)-122(Y) which may be controlled by a power limiting management response 140(6) transmitted to a RAM circuit 502(5) and / or a LAM circuit 136(5), the RAM circuit and / or the LAM circuit being configured to control power consumption in such S2S interface circuits 122(0)-122(Y).

[0107] The merging circuit 616 in PEL circuit 1026 can be programmed to map (e.g., via firmware, electronic fuses, etc.) merged power control recommendations 618(1)-618(6) to a specific target device 200, and thus to target circuits 620(1)-620(6), which may not be directly related to each other. In this way, merged power control recommendations 618(1)-618(6) related to power issues and power consumption in IC chip 104 can be mapped in PEL circuit 1026 to be associated with different target devices 200 for power consumption control. The merging circuit 616 can be programmed in a "many-to-many mapping" manner to be associated with different power limit management responses within IC chip 104 in a desired manner, to provide greater flexibility in managing power consumption in IC chip 104 while still achieving the desired performance. In this way, the power control management behavior of PEL circuit 1026 can be configured and changed even after IC chip 104 has been deployed in the application.

[0108] Continue to refer to Figure 10 Each of the target circuits 620(1)-620(6) is configured to determine whether the power consumption of the associated target device 200 in the processor-based system 100 should be controlled based on the combined power control recommendations 618(1)-618(6) provided to the target circuits 620(1)-620(6). Each of the target circuits 620(1)-620(6) is configured to analyze the corresponding received combined power control recommendations 618(1)-618(6) to determine whether the power consumption of the associated target device 200 should be controlled. If the target circuits 620(1)-620(Q) determine that the power consumption of the associated target device 200 in the processor-based system 100 should be controlled, the target circuits 620(1)-620(Q) cause the associated power limiting management responses 140(1)-140(6) to be generated and communicated to the corresponding RAM circuits 502(1)-502(6) and / or LAM circuits 136(1)-136(6), so that the power consumption of the target device 200 is associated with the power limiting management responses 140(1)-140(Q) for limiting power consumption.

[0109] As mentioned above Figure 6As discussed, in order to achieve the control of a target device (such as target device 200), a PEL circuit (such as PEL circuit 126) transmits power limit management responses 140(1)-140(Q) to target device 200 by transmitting power limit management responses 140(1)-140(Q) to, for example, RAM circuit 502. RAM circuit 502 then processes power limit management responses 140(1)-140(Q) to identify LAM circuit 136 with which it wishes to communicate to implement the power control requested in the received power limit management responses 140(1)-140(Q). RAM circuit 502 then generates a local power limit management response 630 directed to LAM circuit 136. However, as mentioned above, the local power limit management response 630 must arrive at LAM circuit 136 quickly enough for PEL circuit 126 to effectively manage local hotspots and peak power consumption. In a conventional SoC, local power limit management responses 630 can be sent using packetized commands transmitted via an on-chip communication network (such as the architecture provided by internal communication network 114). However, data traffic congestion on the architecture can lead to increased latency and additional overhead. Furthermore, conventional architecture-based communication may employ addressing mechanisms based on source and destination identifiers, which can result in further latency for time-sensitive power limit management responses.

[0110] On this point, Figure 11 An exemplary aspect of an IC chip 1100 providing a processor-based system 1102 is illustrated. The processor-based system 1102 includes a PEL circuit 1104 communicatively coupled to a communication network 1106. Figure 11 The PEL circuit 1104 functionally corresponds to, for example, the PEL circuit 126 discussed in more detail above, while the communication network 1106 functionally corresponds to, for example, the internal communication network 114 discussed in more detail above. RAM circuit (in Figure 11 Each of the two circuits is labeled "RAMCIR" (1108 and 1110) and the LAM circuit (in... Figure 11 Each of them is labeled as “LAM CIR” 1112(0)-1112(1) and 1114(0)-1114(1), and is also communicatively coupled to the communication network 1106. Figure 11 The processor-based system 1102 in the example also includes a temperature sensor hub (THUB) circuit (in Figure 11 The circuits 1116 and 1118, each labeled "THUB circuit," are communicatively coupled to a temperature sensor (not shown), such as those used to monitor temperature within a processor-based system 1102. Figure 10 Temperature sensor 132 for temperature event 1002(2). Figure 11The processor-based system 1102 further includes a fall detection circuit 1120, which is configured to monitor the fall detection circuitry within the processor-based system 1102. Figure 10 Voltage drop detection event 1002(3). It will be understood that... Figure 11 The processor-based system 1102 may include, for clarity, those not listed here. Figure 11 The additional components shown in the figure.

[0111] exist Figure 11 In the example, PEL circuit 1104 is configured to receive input power telemetry values ​​(not shown) from, for example, LAM circuits 1112(0)-1112(1) and 1114(0)-1114(1), RAM circuits 1108 and 1110, THUB circuits 1116 and 1118, and drop detection circuit 1120. Based on the input power telemetry values, the PEL circuit generates a power limiting management response (in Figure 11 The power limit management response 1122 (hereinafter referred to as "PLM RSP") is used to control power consumption in IC chip 1100 based on input power telemetry values. The power limit management response 1122 is sent via communication network 1106 to an element within processor-based system 1102 responsible for implementing the power control requested in the power limit management response 1122 (i.e., by generating and issuing LMTT commands). Such elements are generally referred to herein as "LMTT source circuits" and may include, for example, one or more of RAM circuits 1108 and 1110, THUB circuits 1116 and 1118, and / or drop detection circuit 1120. The element to which the LMTT command is transmitted is generally referred to herein as "AM circuits" and may include, for example, one or more LAM circuits 1112(0)-1112(1) and 1114(0)-1114(1) and / or one or more RAM circuits 1108 and 1110.

[0112] To enable faster and more efficient transmission of LMTT commands from the LMTT source circuit to multiple AM ​​circuits, the processor-based system 1102 provides LMTT buses 1124, 1126, 1128, 1130, and 1132, which are denoted by [unclear text - likely a formatting error]. Figure 11 The dashed line represents the LMTT bus. Each LMTT bus in LMTT buses 1124, 1126, 1128, 1130, and 1132 is separate from the communication network 1106 and provides a mechanism for the corresponding LMTT source circuit to broadcast LMTT commands to multiple AM ​​circuits. Figure 11In the example, LMTT bus 1124 connects RAM circuit 1108 to LAM circuits 1112(0)-1112(1), while LMTT bus 1126 connects RAM circuit 1110 to LAM circuits 1114(0)-1114(1). Similarly, LMTT bus 1128 connects THUB circuit 1116 to LAM circuits 1114(0)-1114(1), LMTT bus 1130 connects THUB circuit 1118 to RAM circuits 1108 and 1110, and LMTT bus 1132 connects fall detection circuit 1120 to RAM circuits 1108 and 1110. In some respects, each of the LMTT buses 1124, 1126, 1128, 1130, and 1132 comprises a three (3) wire bus. In some respects, the following refers to... Figure 12 The transmissions on LMTT buses 1124, 1126, 1128, 1130 and 1132 are discussed in more detail.

[0113] In an exemplary operation, an LMTT source circuit, such as RAM circuit 1108 (also referred to herein as "LMTT source circuit 1108"), receives a power limit management response 1122 from PEL circuit 1104 via communication network 1106. RAM circuit 1108 generates an LMTT command based on the power limit management response 1122. Figure 11 The LMTT command 1134 (i.e., the local power limit management response) is labeled as “LMTT” in the RAM circuit 1108. The RAM circuit 1108 then broadcasts the LMTT command 1134 to the LAM circuits 1112(0)-1112(1) (also referred to herein as “multiple AM ​​circuits 1112(0)-1112(1)”) via the LMTT bus 1124. Upon receiving the LMTT command 1134 broadcast via the LMTT bus 1124, the appropriate LAM circuits 1112(0)-1112(1) perform a power control operation based on the LMTT command 1134 (i.e., by performing an operation to achieve the power control requested in the power limit management response 1122 received by the RAM circuit 1108).

[0114] Will understand, Figure 11The different components shown can be considered as “LMTT source circuits” and “multiple AM ​​circuits”, depending on which components receive the power limit management response 1122 and broadcast the corresponding LMTT command. For example, the LMTT source circuit may include RAM circuit 1108 or RAM circuit 1110, and the multiple AM ​​circuits may each include LAM circuits 1112(0)-1112(1) or LAM circuits 1114(0)-1114(1). In some aspects, the LMTT source circuit may include THUB circuit 1116, while the multiple AM ​​circuits include LAM circuits 1114(0)-1114(1). Some aspects may specify that the LMTT source circuit includes THUB circuit 1118, and the multiple AM ​​circuits include RAM circuits 1108 and 1110. According to some aspects, the LMTT source circuit may include fall detection circuit 1120, while the multiple AM ​​circuits may include RAM circuits 1108 and 1110.

[0115] As mentioned above, some aspects can be specified for LMTT: LMTT bus (such as...) Figure 11 The LMTT buses 1124, 1126, 1128, 1130, and 1132 may include a three (3) wire bus (not shown). In some such aspects, LMTT commands (such as LMTT command 1134) include an enable indication transmitted via a first wire of the three (3) wire bus, a control value indication transmitted via a second wire of the three (3) wire bus, and a control target indication transmitted via a third wire of the three (3) wire bus. In some aspects, the control value indication may include a serially transmitted three (3) bit value, wherein the transmitted value indicates the suggested control value shown in Table 1 below: Table 1

[0116] Similarly, control target indications may, depending on the aspect, include serially transmitted two (2) bit values, wherein the transmitted values ​​indicate the target device for the control proposal, as shown in Table 2 below: Table 2

[0117] When the AM circuit receives an LMTT command 1134, which includes a control target indication, from the LMTT source circuit, the AM circuit matches and verifies the value of the target control indication in the LMTT command 1134, and then applies the control value indicated by the control value indication in the LMTT command 1134 to the appropriate target device. For example, if the AM circuit is a RAM circuit, the target device will be a LAM circuit, and therefore the RAM circuit will broadcast the LMTT command to the LAM circuit to which it is connected. If the AM circuit is a LAM circuit, the target device will be a device of the processor-based system 1102 that can be controlled by the LAM circuit through power limiting management response 1122. Therefore, the LAM circuit will generate a control signal to the target device based on the control target indication in the LMTT command 1134.

[0118] To illustrate via the LMTT bus (such as...) Figure 11 The exemplary transmission of LMTT commands (including enable indication, control value indication, and control target indication) for LMTT buses 1124, 1126, 1128, 1130, and 1132 is provided. Figure 12 . Figure 12 A clock signal 1200 provided by the core clock signal of the LMTT source circuit is shown, along with an enable signal 1202, a control value signal 1204, and a control target signal 1206, which together are used to transmit LMTT commands 1208(0) and 1208(1) via a three (3)-wire LMTT bus (not shown). Figure 12 In the example, each LMTT command in LMTT commands 1208(0) and 1208(1) requires three (3) clock cycles to transmit. LMTT command 1208(0) includes enable indication 1210(0), control value indication 1212(0) and control target indication 1214(0), while LMTT command 1208(1) includes enable indication 1210(1), control value indication 1212(1) and control target indication 1214(1).

[0119] Figure 12 The enable signal 1202 shown is used to provide enable indications 1210(0) and 1210(1), which indicate the start of valid LMTT commands 1208(0) and 1208(1), respectively. For each enable indication in enable indications 1210(0) and 1210(1), enable signal 1202 is asserted for one (1) clock cycle, and is asserted only in the first of the three (3) clock cycles during which each LMTT command in LMTT commands 1208(0) and 1208(1) is sent.

[0120] Control value signal 1204 is used to send three (3) bits over three (3) clock cycles for each control value indication in control value indications 1212(0) and 1212(1). Figure 12 In the example, the least significant bit of each of the control values ​​indicated by 1212(0) and 1212(1) is sent in the first clock cycle, the middle bit is sent in the second clock cycle, and the most significant bit is sent in the third clock cycle. Therefore, in Figure 12 In the middle, the value sent for control value indication 1212(0) is 3'b001, while the value sent for control value indication 1212(1) is 3'b110.

[0121] The control target signal 1206 is used in a similar manner to provide two (2) bits for each of the control target indications 1214(0) and 1214(1) over two (2) clock cycles. The least significant bit of each of the control target indications 1214(0) and 1214(1) is transmitted in the first clock cycle, and the most significant bit is transmitted in the second clock cycle. Therefore, for each of the control target indications 1214(0) and 1214(1)... Figure 12 The value sent by the control target indication 1214(0) is 2'b10, and the value sent for the control target indication 1214(1) is 2'b01.

[0122] To illustrate exemplary operations for broadcast power limit management responses based on certain aspects, Figure 13 A flowchart illustrating exemplary operation 1300 is provided. For clarity, in the description... Figure 13 Referenced at the time Figure 11 and Figure 12 The components. It will be understood that, in some respects, Figure 13 The operations shown may be performed in a different order than those illustrated herein, and / or may be omitted.

[0123] Exemplary operation 1300 in Figure 13 Starting in the middle, where LMTT source circuits (such as Figure 11 RAM circuit 1108) via processor-based systems (such as Figure 11 The communication network of the processor-based system 1102 (e.g., Figure 11 The communication network 1106) from PEL circuits (such as Figure 11 The PEL circuit 1104 receives a power limiting management response (e.g., Figure 11 The power limit management response 1122 (box 1302). The LMTT source circuit 1108 generates an LMTT command based on the power limit management response 1122 (e.g., Figure 11The LMTT command 1134 (box 1304). The LMTT source circuit 1108 then transmits the command via the LMTT bus (such as...). Figure 11 The LMTT bus 1124 broadcasts the LMTT command 1134 to multiple AM ​​circuits of the processor-based system 1102 (e.g., Figure 11 Each AM circuit (box 1306) in the LAM circuits 1112(0)-1112(1)).

[0124] Some aspects may be specified: for one or more AM circuits among a plurality of AM circuits 1112(0)-1112(1) (e.g., Figure 11 The AM circuit 1112(0) performs another series of operations (box 1308). In this respect, the AM circuit 1112(0) receives LMTT command 1134 from the LMTT source circuit 1108 via the LMTT bus 1124 (box 1310). Because some AM circuits (such as AM circuit 1112(0)) can be configured to issue power control commands for more than one target type (e.g., architecture, DDR and / or I / O subsystem), in some respects, the AM circuit 1112(0) can be based on control target indications (such as... Figure 12 The control target indication 1214(0) determines whether the AM circuit 1112(0) is intended to achieve the LMTT command 1134 (box 1312). The AM circuit 1112(0) then performs power control operation based on the LMTT command 1134 (box 1314).

[0125] A hierarchical power management system, which can be provided in an IC chip for an integrated processor-based system, can be provided in or integrated into any processor-based device. This hierarchical power management system is configured to locally monitor the activity of devices in the processor-based system to locally estimate and control their power consumption, and report these activity power events, including but not limited to, those related to the estimated power consumption, to a centralized PEL circuit configured to collect activity power events related to the power consumption of the monitored processing devices and, in response, control the power in the IC chip. Figures 1 to 3 , Figures 5 to 7 and Figures 9A to 10 The graded power management system and its exemplary components; and according to Figure 8The exemplary process 800 and any aspects of operation disclosed herein are described. Examples, not limited to, include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0126] Figure 14 This is a block diagram of another exemplary processor-based system including a hierarchical power management system configured to locally monitor the activity of devices in the processor-based system to locally estimate and control their power consumption and report the activity power events related to the estimated power consumption to a centralized PEL circuit configured to collect activity power events related to the power consumption of the monitored processing devices and, in response, control the power in an IC chip. This includes, but is not limited to, activities related to, the hierarchical power management system. Figures 1 to 3 , Figures 5 to 7 and Figures 9A to 10 The graded power management systems 124, 624, 724 and their exemplary components are described in the text.

[0127] In this example, the processor-based system 1400 can be formed in IC 1402 and as a system-on-a-chip (SoC) 1404. The processor-based system 1400 includes a central processing unit (CPU) 1406, which includes one or more processors 1408, which may also be referred to as CPU cores or processor cores. CPU 1406 may have a cache memory 1410 coupled to CPU 1406 for fast access to data in temporary storage. CPU 1406 is coupled to a system bus 1412 and can couple master and slave devices included in the processor-based system 1400 to each other. As is well known, CPU 1406 communicates with these other devices by exchanging address, control, and data information via system bus 1412. For example, CPU 1406 may communicate a bus transaction request to a memory controller 1414, which is an example of a slave device. Figure 14 Not illustrated, but multiple system buses 1412 may be provided, each of which constitutes a different architecture.

[0128] Other master and slave devices can be connected to system bus 1412. For example... Figure 14 As illustrated, these devices may include a memory system 1416, one or more input devices 1420, one or more output devices 1422, one or more network interface devices 1424, and one or more display controllers 1426. The memory system includes a memory controller 1414 and a memory array 1418. Input devices 1420 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1422 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 1424 may be any device configured to allow data exchange to and from network 1428. Network 1428 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. ™ Networks and the Internet. The network interface device 1424 can be configured to support any type of desired communication protocol.

[0129] CPU 1406 can also be configured to access display controller 126 via system bus 1412 to control information transmitted to one or more displays 1430. Display controller 1426 transmits information to be displayed to the displays 1430 via one or more video processors 1432, which process the information to be displayed into a format suitable for use with the displays 1430. Displays 1430 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc. IC chip 1402 also includes PMIC 1434, which includes PEL circuitry 1436 as part of a graded power management system 1438. As an example, PEL circuitry 1436 may be... Figures 1 to 3 , Figures 5 to 7 And the PEL circuit 126 in the graded power management systems 124, 624, and 724 in Figure 9. The graded power management system 1438 may include one or more LAM circuits 1440(1)-1440(6) associated with one or more of the processor 1408, cache memory 1410, memory controller 1414, network interface device 1424, display controller 1426, and / or system bus 1412, which are configured to monitor the activity associated with these processing devices and report activity power events related to the activity of these devices within the graded power management system 1438. As an example, the LAM circuits 1440(1)-1440(6) may be Figures 1 to 3 , Figures 5 to 7 and Figure 10 LAM circuits 136 and 136R in the hierarchical power management systems 124, 624, and 724 of A. One or more RAM circuits 1442 may also be provided as part of the hierarchical power management system 1438 to receive active power events from packets of LAM circuits 1440(1)-1440(6), thereby aggregating such active power events into aggregated active power events to be communicated to PEL circuit 1436. As an example, RAM circuit 1442 may be Figures 1 to 3 and Figures 5 to 7 RAM circuit 502 in the graded power management system 124, 624, 724.

[0130] Figure 15 An exemplary wireless communication device 1500 is illustrated, which may include a hierarchical power management system 1502 configured to locally monitor the activity of devices in a processor-based system to locally estimate and control their power consumption and report the activity power events related to the estimated power consumption to a centralized PEL circuit configured to collect activity power events related to the power consumption of the monitored processing devices and, in response, control the power in an IC chip. This includes, but is not limited to, activities related to, the hierarchical power management system. Figures 1 to 3 , Figures 5 to 7 and Figures 9A to 10 The graded power management systems 124, 624, 724 and their exemplary components are described in the text.

[0131] like Figure 15 As shown, the wireless communication device 1500 includes an RF transceiver 1504 and a data processor 1506. The RF transceiver 1504 and / or the data processor 1506 may include corresponding hierarchical power management systems 1502(1), 1502(2), which are configured to locally monitor the activity of devices in a processor-based system to locally estimate and control their power consumption and report the estimated power consumption to a centralized PEL circuit configured to collect activity power events about the power consumption of the monitored processing devices and, in response, control the power in the IC chip. This includes, but is not limited to, activities related to, the estimated power consumption. Figures 1 to 3 , Figures 5 to 7 and Figures 9A to 10 The graded power management systems 124, 624, 724 and their exemplary components are described in the text.

[0132] The components of the RF transceiver 1504 and / or the data processor 1506 may be split among several different dies 1503(1), 1503(2). The data processor 1506 may include memory for storing data and program code. The RF transceiver 1504 includes a transmitter 1508 and a receiver 1510 supporting bidirectional communication. Generally, the wireless communication device 1500 may include any number of transmitters 1508 and / or receivers 1510 for any number of communication systems and frequency bands. All or part of the RF transceiver 1504 may be implemented on one or more analog ICs, RF ICs, mixed-signal ICs, etc.

[0133] The transmitter 1508 or receiver 1510 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband. For example, for receiver 1510, the signal is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 15 In the wireless communication device 1500, the transmitter 1508 and the receiver 1510 are implemented using a direct frequency conversion architecture.

[0134] In the transmission path, data processor 1506 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1508. In the exemplary wireless communication device 1500, data processor 1506 includes digital-to-analog converters (DACs) 1512(1) and 1512(2) to convert the digital signals generated by data processor 1506 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0135] Within transmitter 1508, low-pass filters 1514(1) and 1514(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1516(1) and 1516(2) amplify the signals from low-pass filters 1514(1) and 1514(2), respectively, and provide I and Q baseband signals. Upconverter 1518 upconverts the I and Q baseband signals using the I and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 1522 via mixers 1520(1) and 1520(2) to provide upconverted signal 1524. Filter 1526 filters upconverted signal 1524 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1528 amplifies the up-converted signal 1524 from filter 1526 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is routed through duplexer or switch 1530 and transmitted via antenna 1532.

[0136] In the receiving path, antenna 1532 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1530 and provided to low-noise amplifier (LNA) 1534. Duplexer or switch 1530 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1534 and filtered by filter 1536 to obtain the desired RF input signal. Downconversion mixers 1538(1) and 1538(2) mix the output of filter 1536 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1540 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1542(1) and 1542(2) and further filtered by low-pass filters 1544(1) and 1544(2) to obtain I and Q analog input signals, which are provided to data processor 1506. In this example, data processor 1506 includes analog-to-digital converters (ADCs) 1546(1) and 1546(2) to convert the analog input signals into digital signals to be further processed by data processor 1506.

[0137] exist Figure 15In the wireless communication device 1500, a TX LO signal generator 1522 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1540 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1548 receives timing information from a data processor 1506 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1522. Similarly, an RX PLL circuit 1550 receives timing information from a data processor 1506 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1540.

[0138] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0139] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0140] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory, flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0141] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0142] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0143] Specific implementation examples are described in the following numbered clauses: 1. An integrated circuit (IC) chip, the IC chip comprising a processor-based system, the processor-based system comprising: Power estimation and limiting (PEL) circuit; A Limit Management Throughput Control (LMTT) source circuit, which is communicatively coupled to the PEL circuit via a communication network; Multiple Activity Management (AM) circuits; and An LMTT bus, wherein the LMTT bus communicatively couples the LMTT source circuit to each of the plurality of AM circuits; The LMTT source circuit is configured as follows: Receive power limiting management response from the PEL circuit via the communication network; Generate an LMTT command based on the power limit management response; and The LMTT command is broadcast to each of the plurality of AM circuits via the LMTT bus. 2. The IC chip according to Clause 1, wherein one or more of the plurality of AM circuits are configured to: Receive the LMTT command from the LMTT source circuit via the LMTT bus; and Power control operations are performed based on the LMTT command. 3. The IC chip according to any one of clauses 1 to 2, wherein: The LMTT bus includes a three (3) wire bus; and The LMTT command includes: Enable indication sent via the first line of the three (3) line bus; The control value indication is sent via the second line of the three (3) wire bus; and Control target indication transmitted via the third line of the three (3) wire bus. 4. The IC chip according to Clause 3, wherein: The control value indication includes a three (3) bit value serially transmitted via the second line of the three (3)-wire bus; and The control target indication includes a two (2) bit value serially transmitted via the third line of the three (3)-wire bus. 5. The IC chip according to any one of clauses 1 to 4, wherein: The LMTT source circuit includes the local AM (RAM) circuit of the IC; and Each of the plurality of AM circuits includes the local AM (LAM) circuit of the IC. 6. The IC chip according to any one of clauses 1 to 4, wherein: The LMTT source circuit includes the temperature sensor hub (THUB) circuit of the IC; and Each of the plurality of AM circuits includes the local activity management (LAM) circuitry of the IC. 7. The IC chip according to any one of clauses 1 to 4, wherein: The LMTT source circuit includes the temperature sensor hub (THUB) circuit of the IC; and Each of the plurality of AM circuits includes a local AM (RAM) circuit of the IC. 8. The IC chip according to any one of clauses 1 to 4, wherein: The LMTT source circuit includes the descent detection circuit of the IC; and Each of the plurality of AM circuits includes a local AM (RAM) circuit of the IC. 9. An IC chip according to any one of Clauses 1 to 8, wherein the IC chip is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft. 10. An integrated circuit (IC) chip, the IC chip comprising a processor-based system, the processor-based system comprising: Components for receiving power limiting management responses from power estimation and limiting (PEL) circuitry via the communication network of the processor-based system; Components for generating Limit Management Throughput Control (LMTT) commands based on the power limit management response; and Components for broadcasting the LMTT command via the LMTT bus to each of the multiple Activity Management (AM) circuits in the processor-based system. 11. A method for broadcasting a power limit management response in a processor-based system within an integrated circuit (IC) chip, the method comprising: The power limiting management response is received from the power estimation and limiting (PEL) circuitry via the communication network of the processor-based system by the Limiting Management Throughput Control (LMTT) source circuitry. Generate an LMTT command based on the power limit management response; and The LMTT command is broadcast from the LMTT source circuit to each of the multiple Activity Management (AM) circuits in the processor-based system via the LMTT bus. 12. The method according to Clause 11, for each of one or more AM circuits in the plurality of AM circuits, the method further comprises: The AM circuit receives the LMTT command from the LMTT source circuit via the LMTT bus; and The AM circuit performs power control operations based on the LMTT command. 13. The method according to any one of clauses 11 to 12, wherein: The LMTT bus includes a three (3) wire bus; and The LMTT command includes: Enable indication sent via the first line of the three (3) line bus; The control value indication is sent via the second line of the three (3) wire bus; and Control target indication transmitted via the third line of the three (3) wire bus. 14. The method according to Clause 13, wherein: The control value indication includes a three (3) bit value serially transmitted via the second line of the three (3)-wire bus; and The control target indication includes a two (2) bit value serially transmitted via the third line of the three (3)-wire bus. 15. The method according to any one of clauses 11 to 14, wherein: The LMTT source circuit includes the local AM (RAM) circuit of the IC; and Each of the plurality of AM circuits includes the local AM (LAM) circuit of the IC. 16. The method according to any one of clauses 11 to 14, wherein: The LMTT source circuit includes the temperature sensor hub (THUB) circuit of the IC; and Each of the plurality of AM circuits includes the local activity management (LAM) circuitry of the IC. 17. The method according to any one of clauses 11 to 14, wherein: The LMTT source circuit includes the temperature sensor hub (THUB) circuit of the IC; and Each of the plurality of AM circuits includes a local AM (RAM) circuit of the IC. 18. The method according to any one of clauses 11 to 14, wherein: The LMTT source circuit includes the descent detection circuit of the IC; and Each of the plurality of AM circuits includes a local AM (RAM) circuit of the IC. 19. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed, cause a processor of a processor-based system to: The power limiting management response is received from the power estimation and limiting (PEL) circuitry via the communication network of the processor-based system. Generate a Limit Management Throughput Control (LMTT) command based on the power limiting management response; and The LMTT command is broadcast via the LMTT bus to each of the multiple Activity Management (AM) circuits in the processor-based system. 20. The non-transitory computer-readable medium according to Clause 19, wherein for one or more of the plurality of AM circuits, the computer-executable instructions further cause the processor to: Receive the LMTT command via the LMTT bus; and Power control operations are performed based on the LMTT command.

Claims

1. An integrated circuit (IC) chip, the IC chip comprising a processor-based system, the processor-based system comprising: Power estimation and limiting (PEL) circuit; A Limit Management Throughput Control (LMTT) source circuit, which is communicatively coupled to the PEL circuit via a communication network; Multiple Activity Management (AM) circuits; and An LMTT bus, wherein the LMTT bus communicatively couples the LMTT source circuit to each of the plurality of AM circuits; The LMTT source circuit is configured as follows: Receive power limiting management response from the PEL circuit via the communication network; Generate an LMTT command based on the power limit management response; and The LMTT command is broadcast to each of the plurality of AM circuits via the LMTT bus.

2. The IC chip according to claim 1, wherein one or more of the plurality of AM circuits are configured as follows: Receive the LMTT command from the LMTT source circuit via the LMTT bus; and Power control operations are performed based on the LMTT command.

3. The IC chip according to claim 1, wherein: The LMTT bus includes a three (3) wire bus; and The LMTT command includes: Enable indication sent via the first line of the three (3) line bus; The control value indication is sent via the second line of the three (3) wire bus; and Control target indication transmitted via the third line of the three (3)-wire bus.

4. The IC chip according to claim 3, wherein: The control value indication includes a three (3) bit value serially transmitted via the second line of the three (3)-wire bus; and The control target indication includes a two (2) bit value serially transmitted via the third line of the three (3)-wire bus.

5. The IC chip according to claim 1, wherein: The LMTT source circuit includes the local AM (RAM) circuit of the IC; and Each of the plurality of AM circuits includes the local AM (LAM) circuit of the IC.

6. The IC chip according to claim 1, wherein: The LMTT source circuit includes the temperature sensor hub (THUB) circuit of the IC; and Each of the plurality of AM circuits includes the local activity management (LAM) circuitry of the IC.

7. The IC chip according to claim 1, wherein: The LMTT source circuit includes the temperature sensor hub (THUB) circuit of the IC; and Each of the plurality of AM circuits includes a local AM (RAM) circuit of the IC.

8. The IC chip according to claim 1, wherein: The LMTT source circuit includes the descent detection circuit of the IC; and Each of the plurality of AM circuits includes a local AM (RAM) circuit of the IC.

9. The IC chip of claim 1, wherein the IC chip is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

10. An integrated circuit (IC) chip, the IC chip comprising a processor-based system, the processor-based system comprising: Components for receiving power limiting management responses from power estimation and limiting (PEL) circuitry via the communication network of the processor-based system; Components used to generate Limit Management Throughput Control (LMTT) commands based on the power limit management response; and Components for broadcasting the LMTT command via the LMTT bus to each of the multiple Activity Management (AM) circuits in the processor-based system.

11. A method for broadcasting a power limit management response in a processor-based system within an integrated circuit (IC) chip, the method comprising: The power limiting management response is received from the power estimation and limiting (PEL) circuitry via the communication network of the processor-based system by the Limiting Management Throughput Control (LMTT) source circuitry. Generate an LMTT command based on the power limit management response; as well as The LMTT command is broadcast from the LMTT source circuit to each of the multiple Activity Management (AM) circuits in the processor-based system via the LMTT bus.

12. The method of claim 11, wherein for each of one or more AM circuits in the plurality of AM circuits, the method further comprises: The AM circuit receives the LMTT command from the LMTT source circuit via the LMTT bus; as well as The AM circuit performs power control operations based on the LMTT command.

13. The method of claim 11, wherein: The LMTT bus includes a three (3) wire bus; and The LMTT command includes: Enable indication sent via the first line of the three (3) line bus; The control value indication is sent via the second line of the three (3) wire bus; and Control target indication transmitted via the third line of the three (3)-wire bus.

14. The method of claim 13, wherein: The control value indication includes a three (3) bit value serially transmitted via the second line of the three (3)-wire bus; and The control target indication includes a two (2) bit value serially transmitted via the third line of the three (3)-wire bus.

15. The method of claim 11, wherein: The LMTT source circuit includes the local AM (RAM) circuit of the IC; and Each of the plurality of AM circuits includes the local AM (LAM) circuit of the IC.

16. The method of claim 11, wherein: The LMTT source circuit includes the temperature sensor hub (THUB) circuit of the IC; and Each of the plurality of AM circuits includes the local activity management (LAM) circuitry of the IC.

17. The method of claim 11, wherein: The LMTT source circuit includes the temperature sensor hub (THUB) circuit of the IC; and Each of the plurality of AM circuits includes a local AM (RAM) circuit of the IC.

18. The method of claim 11, wherein: The LMTT source circuit includes the descent detection circuit of the IC; and Each of the plurality of AM circuits includes a local AM (RAM) circuit of the IC.

19. A non-transitory computer-readable medium having stored thereon computer-executable instructions, which, when executed, cause a processor of a processor-based system to: The power limiting management response is received from the power estimation and limiting (PEL) circuitry via the communication network of the processor-based system. Generate a Limit Management Throughput Control (LMTT) command based on the power limiting management response; and The LMTT command is broadcast via the LMTT bus to each of the multiple Activity Management (AM) circuits in the processor-based system.

20. The non-transitory computer-readable medium of claim 19, wherein for one or more of the plurality of AM circuits, the computer-executable instructions further cause the processor to: Receive the LMTT command via the LMTT bus; and Power control operations are performed based on the LMTT command.

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