Active quenching circuit and method for accelerating recovery of a negative feedback avalanche diode

Abstract

The application belongs to the technical field of single photon detection, and relates to an active quenching circuit and method for accelerating recovery of a negative feedback avalanche diode. The circuit comprises a high-speed comparator, a quenching transistor, a high-speed operational amplifier, a C-RC balanced noise elimination network and a T network. Avalanche pulses generated by an anode of the avalanche diode are sent to a non-inverting input end of the high-speed comparator through an alternating coupling capacitor, and at the same time, the avalanche pulses are connected to an inverting input end of the comparator through the C-RC balanced noise elimination network to inhibit noise. When the pulses exceed a set discrimination level, the comparator output flips, and a signal of the comparator is accelerated to drive the quenching transistor to be turned on through the T network, so that the voltage across the avalanche diode is rapidly reduced to achieve quenching. An FPGA controls a high-speed digital-to-analog converter to generate a signal, which is amplified by the high-speed operational amplifier and then sent to an output end of the quenching transistor to complete reset and prepare for next detection. The application accelerates recovery of the NFAD through active feedback and network optimization, and improves detection efficiency.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of single photon detection, and relates to an active quenching circuit and method for accelerating recovery of a negative feedback avalanche diode. BACKGROUND

[0002] As a mature semiconductor single photon detector, a single photon avalanche diode (SPAD) has low refrigeration requirements, fast response speed, small size, easy fiber and device coupling, and strong usability. A negative feedback avalanche diode (NFAD) is a special single photon avalanche diode, which introduces a negative feedback mechanism to realize self-quenching and self-recovery of the device without an external quenching circuit, has the advantages of simple driving circuit and application in a free running mode. The NFAD is in series with a large-value thin film resistor to realize passive quenching with good consistency. The large-value integrated thin film resistor not only accelerates quenching, but also greatly reduces the number of after-pulses of the single photon detector by limiting the number of avalanche carriers, so that the after-pulse has less impact on the maximum count rate of the single photon detector, which is a core indicator. However, the main disadvantage of the NFAD also comes from this built-in large-value quenching resistor. After quenching, the NFAD needs to charge the SPAD junction capacitor through the resistor. According to the RC constant, it usually takes tens to hundreds of nanoseconds, which is much longer than that of a conventional SPAD, that is, the recovery time of the NFAD is much longer than that of the conventional SPAD. The long recovery time leads to a longer time that the NFAD cannot be detected, which restricts the maximum count rate of the single photon detector.

[0003] File CN116380262A discloses an active quenching free running detector, which mainly solves the technical problem of realizing a large-amplitude and low-latency active quenching free running detector to improve the quenching signal amplitude, shorten the delay between the avalanche signal extraction and the bias control circuit, improve the performance of the active quenching circuit, solve the problem of high after-pulse rate of the existing free running single photon detector, and adjust the dead time length of the quenching circuit to improve the flexibility of the application of the free running detector. However, the patent mainly improves the NFAD quenching speed by improving the active quenching method, and does not optimize and improve the key problem of slow charging speed of the NFAD. File CN114061752A discloses a communication waveband miniaturized multi-channel free running mode single photon detector, which generates a quenching control signal by using an FPGA control module, and realizes active quenching control of the NFAD by using a low-power broadband operational amplifier circuit to reduce the after-pulse probability. The invention also optimizes the performance of the NFAD from the perspective of optimizing the performance of the active quenching and improving the quenching speed, and does not further reduce the dead time of the detector from the perspective of accelerating the recovery of the NFAD to improve the maximum count rate.

[0004] Therefore, the active quenching circuit with the accelerated negative feedback avalanche diode recovery capability has very important practical significance for further improving the performance of single photon detectors. SUMMARY

[0005] In view of the deficiencies of the prior art, the application provides an active quenching circuit and method for accelerating the recovery of a negative feedback avalanche diode.

[0006] The active quenching circuit for accelerating the recovery of a negative feedback avalanche diode provided by the application comprises a high-speed comparator, a quenching transistor, a high-speed operational amplifier, a high-speed digital-to-analog converter, a C-RC balanced noise elimination network and a T-type network, wherein the C-RC balanced noise elimination network comprises a first resistor, a first capacitor and a second capacitor, and the T-type network comprises a second resistor, a third resistor and a third capacitor.

[0007] The anode of the negative feedback avalanche diode is connected to an adjustable bias voltage source through a resistor; the anode of the negative feedback avalanche diode is connected to the non-inverting input terminal of the high-speed comparator through an alternating current coupling capacitor; the cathode of the negative feedback avalanche diode is connected to the inverting input terminal of the high-speed comparator through the C-RC balanced noise elimination network; the inverting input terminal of the high-speed comparator is connected to an adjustable discrimination level through a resistor R N ; the non-inverting input terminal of the high-speed comparator is connected to GND through a resistor R P ; the inverting output terminal of the high-speed comparator is connected to the latch enable inverting input terminal of the high-speed comparator; the inverting output terminal and the latch enable inverting input terminal of the high-speed comparator are connected to an FPGA.

[0008] The non-inverting output terminal of the high-speed comparator is connected to the input terminal of the quenching transistor through the T-type network; the output terminal of the quenching transistor is connected to the anode of the avalanche photodiode.

[0009] The FPGA controls the input of the high-speed digital-to-analog converter, and the differential signal output by the high-speed digital-to-analog converter is converted into a single-ended voltage signal after being amplified by the high-speed operational amplifier, and the voltage signal is connected to the output terminal of the quenching transistor.

[0010] The application further provides a method for accelerating the recovery of a negative feedback avalanche diode, which comprises the following steps:

[0011] When the negative feedback avalanche diode detects photons, the avalanche current generated has a direction from the cathode to the anode, and a resistor R PAs the current extraction resistance, when the avalanche voltage is higher than the discrimination level of the inverting input terminal of the high-speed comparator, the avalanche is discriminated, and the output level of the high-speed comparator is reversed; the non-inverting output terminal of the high-speed comparator drives the quenching transistor to output a reversal, and the third capacitor is used to accelerate the conduction of the quenching transistor, so that the cathode voltage of the avalanche photodiode is reduced, and the avalanche is quenched; at the same time, the inverting output terminal of the high-speed comparator latches the quenching state through the latch enable inverting input terminal; after the avalanche is quenched, the output of the high-speed digital-to-analog converter is pulled down, and the bias of the quenching transistor is cut off through the high-speed operational amplifier; at the same time, the reset lock signal is pulled down, so that the latch enable non-inverting input terminal of the high-speed comparator is locked at a low level, and the comparison function is restored; after the set dead time, the output of the high-speed digital-to-analog converter is controlled by the time-varying voltage of the FPGA, which is used to accelerate the recovery process of the negative feedback avalanche diode.

[0012] Preferably, the time-varying voltage output by the high-speed digital-to-analog converter is logically as follows: taking the clock of N high-speed digital-to-analog converters as a period, a dynamic voltage sequence is generated by the FPGA in one period; after the set dead time, the high-speed digital-to-analog converter outputs a voltage value higher than the working bias through the high-speed operational amplifier, so as to quickly charge the junction capacitor of the negative feedback avalanche diode, so that the node voltage of the negative feedback avalanche diode crosses the main voltage interval required by the passive RC recovery in a very short time; then the output of the high-speed digital-to-analog converter is lowered, so that the bias value required for the negative feedback avalanche diode to recover to normal working, at this time, the negative feedback avalanche diode recovers to work, and waits for the next detection.

[0013] The active quenching circuit and method for accelerating the recovery of the negative feedback avalanche diode provided by the application flexibly utilizes the FPGA to control the high-speed digital-to-analog converter to generate a dynamic voltage sequence, so as to accelerate the NFAD recovery (i.e. charging of the junction capacitor of the NFAD). BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The circuit structure block diagram of the active quenching circuit for accelerating the recovery of the negative feedback avalanche diode is described in the application;

[0015] Figure 2 The working timing diagram of the active quenching circuit for accelerating the recovery of the negative feedback avalanche diode is described in the application. DETAILED DESCRIPTION

[0016] To more clearly understand the technical content of this invention, its solution will now be described in detail with reference to the accompanying drawings and specific embodiments. The accompanying drawings show a preferred embodiment of this invention, but its scope of protection is not limited thereto, and can be flexibly adjusted according to specific usage requirements in practical applications. This embodiment aims to help those skilled in the art to fully and deeply understand the inventive concept of this solution.

[0017] like Figure 1 As shown, the active quenching circuit for accelerating the recovery of a negative feedback avalanche diode provided by the present invention includes a negative feedback avalanche diode (NFAD) D1 with integrated quenching resistor, a high-speed comparator U1, a quenching transistor Q1, a high-speed operational amplifier U2, a high-speed digital-to-analog converter (DAC) U3, a C-RC balanced noise reduction network and a T-type network. The C-RC balanced noise reduction network includes a first resistor R1, a first capacitor C1 and a second capacitor C2, and the T-type network includes a second resistor R2, a third resistor R3 and a third capacitor C3.

[0018] NFAD (Integrated High-Resistance Quenching Resistor) Anode through resistor R b Connected to an adjustable bias voltage source; the NFAD anode is connected to an AC coupling capacitor C. c The NFAD cathode is connected to the non-inverting input of the high-speed comparator U1 via a C-RC balanced noise reduction network; the inverting input of the high-speed comparator U1 is connected to the non-inverting input via a resistor R. N Connected to the adjustable discrimination level; the non-inverting input of the high-speed comparator U1 is connected to resistor R. P Connected to GND; the inverting output of high-speed comparator U1 is connected to the latch enable inverting input of high-speed comparator U1; the inverting output and latch enable inverting input of high-speed comparator U1 are connected to the FPGA.

[0019] The non-inverting output of the high-speed comparator U1 is connected to the input of the quench transistor Q1 via a T-network; the output of the quench transistor Q1 is connected to the anode of the APD.

[0020] The FPGA controls the input of the high-speed DAC U3. The differential signal output by the high-speed DAC U3 is amplified by the high-speed operational amplifier U2 and converted into a single-ended voltage signal. This voltage signal is connected to the output of the quench transistor Q1.

[0021] Based on the above-described active quenching circuit for accelerating the recovery of a negative feedback avalanche diode, this invention also provides a method for accelerating the recovery of a negative feedback avalanche diode, the steps of which are as follows:

[0022] In free-running mode, when there is no avalanche signal, the reset lock signal is in a high-impedance state, and the high-speed comparator U1 is in a normal comparison state. At this time, the quench transistor Q1 is in the off state.

[0023] When the NFAD detects a photon, the resulting avalanche current flows from the cathode to the anode, using a large-value resistor R. P As a current extraction resistor, when the avalanche voltage is higher than the discrimination level of the inverting input of the high-speed comparator U1, the avalanche is detected, and the output level of the high-speed comparator U1 is inverted. The non-inverting output of the high-speed comparator U1 drives the output of the quenching transistor Q1 to invert, and the third capacitor C3 is used to accelerate the conduction of the quenching transistor Q1. The cathode voltage of the APD decreases, and the avalanche is quenched. At the same time, the inverting output of the high-speed comparator U1 latches the quenching state through the latch enable inverting input. After the avalanche is quenched, the output of the high-speed DAC U3 is pulled low, and the bias of the quenching transistor Q1 is cut off through the high-speed operational amplifier U2 to achieve the lowest power consumption. At the same time, the reset lock signal is pulled low, locking the latch enable non-inverting input of the high-speed comparator U1 at a low level, restoring its comparison function. After the set dead time, the output of the high-speed DAC U3 is a time-varying voltage controlled by the FPGA to accelerate the recovery process of the NFAD. The voltage sequence logic of the output of the high-speed DAC U3 is as follows: Figure 2 As shown, with the clock of N DACs as one cycle, a dynamic voltage sequence is generated by the FPGA within the cycle: after the set dead time, the high-speed DAC U3 outputs a voltage value higher than the working bias voltage through the high-speed operational amplifier U2 to quickly charge the NFAD junction capacitance, so that the NFAD node voltage crosses the main voltage range required for passive RC recovery in a very short time; then the output of the high-speed DAC U3 is reduced so that the NFAD recovers the bias voltage value required for normal operation. At this time, the NFAD resumes operation and waits for the next probe.

Claims

1. An active quenching circuit for accelerating the recovery of a negative feedback avalanche diode, characterized in that: It includes a high-speed comparator, a quenching transistor, a high-speed operational amplifier, a high-speed digital-to-analog converter, a C-RC balanced noise reduction network, and a T-type network; the C-RC balanced noise reduction network includes a first resistor, a first capacitor, and a second capacitor, and the T-type network includes a second resistor, a third resistor, and a third capacitor; The anode of the negative feedback avalanche diode is connected to an adjustable bias voltage source via a resistor; the anode of the negative feedback avalanche diode is connected to the non-inverting input of a high-speed comparator via an AC coupling capacitor; the cathode of the negative feedback avalanche diode is connected to the inverting input of the first high-speed comparator via a C-RC balanced noise reduction network; the inverting input of the high-speed comparator is connected to the non-inverting input of the high-speed comparator via a resistor R. N Connected to the adjustable discrimination level; the non-inverting input of the high-speed comparator is connected to resistor R. P Connected to GND; the inverting output of the high-speed comparator is connected to the latch enable inverting input of the high-speed comparator; the inverting output and latch enable inverting input of the high-speed comparator are connected to the FPGA. The non-inverting output of the high-speed comparator is connected to the input of the quench transistor via a T-network; the output of the quench transistor is connected to the anode of the avalanche photodiode. The FPGA controls the input of the high-speed digital-to-analog converter. The differential signal output by the high-speed digital-to-analog converter is amplified by the high-speed operational amplifier and converted into a single-ended voltage signal, which is connected to the output of the quench transistor.

2. A method for accelerating the recovery of a negative feedback avalanche diode, characterized in that, This method uses the circuit described in claim 1 and includes the following steps: In free-running mode, when there is no avalanche signal, the reset lock signal is in a high-impedance state, the high-speed comparator is in a normal comparison state, and the quench transistor is in the off state. When a negative feedback avalanche diode detects a photon, the resulting avalanche current flows from the cathode to the anode. A large-value resistor R is then used. P As a current extraction resistor, when the avalanche voltage is higher than the discrimination level of the inverting input of the high-speed comparator, the avalanche is detected, and the output level of the high-speed comparator is inverted. The non-inverting output of the high-speed comparator drives the output of the quenching transistor to invert, and the third capacitor is used to accelerate the conduction of the quenching transistor. The cathode voltage of the avalanche photodiode decreases, and the avalanche quenching occurs. At the same time, the inverting output of the high-speed comparator latches the quenching state through the latch enable inverting input. After the avalanche quenching, the output of the high-speed digital-to-analog converter is pulled low, and the bias of the quenching transistor is cut off through the high-speed operational amplifier. At the same time, the reset lock signal is pulled low, locking the latch enable non-inverting input of the high-speed comparator at a low level, restoring its comparison function. After the set dead time, the output of the high-speed digital-to-analog converter is a time-varying voltage controlled by the FPGA to accelerate the recovery process of the negative feedback avalanche diode.

3. The method for accelerating the recovery of a negative feedback avalanche diode according to claim 2, characterized in that, The time-varying voltage logic of the high-speed digital-to-analog converter output is as follows: Using the clocks of N high-speed digital-to-analog converters as one cycle, a dynamic voltage sequence is generated by the FPGA within one cycle. After a set dead time, the high-speed digital-to-analog converter first outputs a voltage value higher than the operating bias voltage through a high-speed operational amplifier to quickly charge the junction capacitance of the negative feedback avalanche diode with integrated quenching resistor, so that the node voltage of the negative feedback avalanche diode crosses the main voltage range required for passive RC recovery in a very short time. Then, the output of the high-speed digital-to-analog converter is reduced so that the negative feedback avalanche diode returns to the bias voltage value required for normal operation. At this time, the negative feedback avalanche diode resumes operation and waits for the next detection.

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