Method and device for detecting connection relation of communication ports of multiple central processing units

Abstract

The embodiment of the invention provides a method and equipment for detecting the connection relation of communication ports of multiple central processing units. The method comprises the following steps: sending a preset signal to a communication port of a central processing unit to be processed, and detecting port states of communication ports of other central processing units; wherein the other central processing units are the at least two central processing units except the central processing unit to be processed; if it is determined that the port states of the communication ports of the other central processing units have the response of the preset signal, it is determined that the communication port of the to-be-processed central processing unit has a connection relation with the communication ports of the other central processing units; if it is determined that the connection relationship is consistent with a preset topological relationship, determining that the communication port connection relationship of the at least two central processing units is correct; wherein the topological relation is a correct communication port connection relation of the at least two central processing units. The method is used for detecting the correctness of the connection relationship among the communication ports of the plurality of CPUs at low cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a detection method and device for a connection relationship of communication ports of multiple central processing units (CPUs). BACKGROUND

[0002] In the field of servers, some business scenarios require the deployment of multiple CPUs. These CPUs are connected through an interconnection bus for communication, forming a unified computing resource pool. The correctness of the connection relationship between the CPUs directly affects the running performance of the server system.

[0003] In some technologies, a specific mechanical structure is designed on the communication ports of the CPUs to prevent bus connection errors between the communication ports of the CPUs from a hardware perspective. In the above technology, customized hardware modules need to be designed for the server, which is costly.

[0004] Therefore, there is an urgent need for a solution that can detect the correctness of the connection relationship between the communication ports of multiple CPUs from a software perspective at a low cost. SUMMARY

[0005] The detection method and device for a connection relationship of communication ports of multiple CPUs provided by the embodiments of the present application are used to achieve low-cost detection of the correctness of the connection relationship between the communication ports of multiple CPUs.

[0006] In a first aspect, the embodiments of the present application provide a detection method for a connection relationship of communication ports of multiple CPUs, which is applied to a baseboard management controller in a server. The baseboard management controller is connected with at least two CPUs in the server. The method comprises the following steps.

[0007] A preset signal is sent to a communication port of a to-be-processed CPU, and the port state of a communication port of another CPU is detected. The other CPU is a CPU other than the to-be-processed CPU among the at least two CPUs.

[0008] If it is determined that the port state of the communication port of the other CPU has a response to the preset signal, it is determined that the communication port of the to-be-processed CPU and the communication port of the other CPU have a connection relationship.

[0009] If it is determined that the connection relationship is consistent with a preset topological relationship, it is determined that the connection relationship of the communication ports of the at least two CPUs is correct. The topological relationship is a correct connection relationship of the communication ports of the at least two CPUs.

[0010] In a possible implementation, each central processor is provided with at least one communication port; a preset signal is sent to the communication port of the central processor to be processed; the port state of the communication port of the other central processor is detected, including:

[0011] The following steps are repeatedly executed until the preset signal is sent to each communication port of the central processor to be processed:

[0012] The preset signal is sent to the i-th communication port of the central processor to be processed; wherein i is an integer greater than or equal to 1, and the initial value of i is 1;

[0013] The port state of the communication port of the other central processor is detected;

[0014] The value of i is added by 1.

[0015] In a possible implementation, the port state of each communication port of the other central processor is detected, including:

[0016] The following steps are repeatedly executed until the port state of the communication port of each other central processor is detected:

[0017] The port state of each communication port of the j-th other central processor is detected in sequence; wherein j is an integer greater than or equal to 1, and the initial value of j is 1;

[0018] The value of j is added by 1.

[0019] In a possible implementation, after the port state of the communication port of the other central processor is detected, the method further includes:

[0020] A reset signal is sent to the i-th communication port of the central processor to be processed; wherein the reset signal is used to restore the port state of the i-th communication port, and / or the port state of the connection port, the connection port being the communication port of the other central processor connected with the i-th communication port.

[0021] In a possible implementation, the preset signal is a correctable error signal.

[0022] In a possible implementation, the method further includes:

[0023] If it is determined that the connection relationship is inconsistent with the preset topological relationship, at least one of the following is performed:

[0024] At least two central processors are prohibited from starting;

[0025] A system indicator light is turned on; wherein the system indicator light is used to indicate that the connection relationship of the communication port of at least two central processors in the server is wrong;

[0026] Generate alarm information; wherein, the alarm information is used to inform the user that the communication port connection relationship of at least two central processing units in the server is incorrect.

[0027] In one possible implementation, the method further includes:

[0028] Based on the connection relationships, draw a connection relationship diagram; wherein the connection relationship diagram includes multiple connection relationships, each connection relationship represents the connection between the communication port of the central processing unit to be processed and the communication port of other processors;

[0029] The connection diagram is displayed on the preset interface.

[0030] In one possible implementation, the method further includes:

[0031] On the preset interface, a preset topology diagram is displayed alongside the connection diagram; the topology diagram includes multiple topology relationships.

[0032] Secondly, embodiments of this application provide a device for detecting the communication port connection relationship of multiple central processing units, comprising:

[0033] The detection module is used to send a preset signal to the communication port of the CPU to be processed and detect the port status of the communication ports of other CPUs; wherein, other CPUs are at least two CPUs other than the CPU to be processed.

[0034] The processing module is used to determine that the communication port of the CPU to be processed has a connection relationship with the communication ports of other processors if it is determined that the port status of the communication port of another CPU responds to a preset signal.

[0035] The comparison module is used to determine that the communication port connection relationship of at least two central processing units is correct if the connection relationship is consistent with the preset topology relationship; wherein, the topology relationship is the correct communication port connection relationship of at least two central processing units.

[0036] In one possible implementation, each central processing unit (CPU) has at least one communication port; a preset signal is sent to the communication port of the CPU to be processed, and the port status of the communication ports of other CPUs is detected. The detection module is used for:

[0037] Repeat the following steps until the preset signals have been sent to each communication port of the central processing unit to be processed:

[0038] Send a preset signal to the i-th communication port of the central processing unit to be processed; where i is an integer greater than or equal to 1, and the initial value of i is 1;

[0039] Detect the port status of communication ports of other central processing units;

[0040] Increment the value of i by 1.

[0041] In one possible implementation, the port status of each communication port of other central processing units is detected, and the detection module is used for:

[0042] Repeat the following steps until the port status of the communication ports of each other central processing unit is detected:

[0043] The port status of each communication port in the j-th other central processing unit is checked sequentially; where j is an integer greater than or equal to 1, and the initial value of j is 1;

[0044] Increment the value of j by 1.

[0045] In one possible implementation, after detecting the port status of the communication ports of other central processing units, the detection module is further configured to:

[0046] Send a reset signal to the i-th communication port of the CPU to be processed; wherein the reset signal is used to restore the port state of the i-th communication port, and / or the port state of the connected port, wherein the connected port is the communication port of another CPU connected to the i-th communication port.

[0047] In one possible implementation, the preset signal is a correctable error signal.

[0048] In one possible implementation, the comparison module is further used for:

[0049] If the connection relationship is determined to be inconsistent with the preset topology relationship, then at least one of the following shall be executed:

[0050] Prevent at least two central processing units from starting;

[0051] The system control indicator lights are turned on; these indicator lights are used to indicate that the communication port connection relationship between at least two central processing units in the server is incorrect.

[0052] Generate alarm information; wherein, the alarm information is used to inform the user that the communication port connection relationship of at least two central processing units in the server is incorrect.

[0053] In one possible implementation, the processing module is further configured to:

[0054] Based on the connection relationships, draw a connection relationship diagram; wherein the connection relationship diagram includes multiple connection relationships, each connection relationship represents the connection between the communication port of the central processing unit to be processed and the communication port of other processors;

[0055] The connection diagram is displayed on the preset interface.

[0056] In one possible implementation, the processing module is further configured to:

[0057] On the preset interface, a preset topology diagram is displayed alongside the connection diagram; the topology diagram includes multiple topology relationships.

[0058] Thirdly, embodiments of this application provide a baseboard management controller, including: a memory and a processor;

[0059] The memory stores the instructions that the computer executes;

[0060] The processor executes computer execution instructions stored in memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0061] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0062] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0063] The method and apparatus for detecting the communication port connection relationship of multiple central processing units (CPUs) provided in this application embodiment send a preset signal to the communication port of the CPU to be processed through a baseboard management controller in a server, and detect the port status of the communication ports of other CPUs. If the port status responds to the preset signal, it is determined that the communication port of the CPU to be processed has a connection relationship with the communication ports of other CPUs. If the connection relationship obtained by comparison is consistent with the preset correct connection relationship, it is determined that the connection relationship of the communication ports of multiple CPUs in the server is correct. The correctness of the connection relationship of the interconnection bus between multiple CPUs in the server is detected by software, without the need for specific mechanical structures, thus reducing costs. Attached Figure Description

[0064] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0065] Figure 1 A schematic diagram of the structure of an exemplary server Figure 1 ;

[0066] Figure 2A schematic diagram of the structure of an exemplary server Figure 2 ;

[0067] Figure 3 A flowchart illustrating the method for detecting the communication port connection relationship of multiple central processing units provided in this application. Figure 1 ;

[0068] Figure 4 A flowchart illustrating the method for detecting the communication port connection relationship of multiple central processing units provided in this application. Figure 2 ;

[0069] Figure 5 A schematic diagram of the structure of an exemplary server Figure 3 ;

[0070] Figure 6 A schematic diagram of the structure of the detection device for the communication port connection relationship of multiple central processing units provided in this application;

[0071] Figure 7 A schematic diagram of the structure of the baseboard management controller provided in this application.

[0072] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0073] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0074] First, let me explain the terms used in this application:

[0075] Central Processing Unit (CPU): In a server, the CPU is responsible for executing instructions from the operating system and applications, performing data processing, logical judgments, and coordinating and controlling other hardware components within the server.

[0076] Baseboard Management Controller (BMC): A BMC is a dedicated, independent microcontroller embedded on the server motherboard. Operating independently of the operating system and CPU, the BMC performs monitoring and management functions. Within the server, the BMC connects to the CPU via a management bus to monitor and diagnose CPU status.

[0077] Correctable Error (CE) signal: This refers to a low-level, non-fatal hardware error detected by the hardware.

[0078] Figure 1 A schematic diagram of the structure of an exemplary server Figure 1 ,like Figure 1 As shown, the specific application scenario of this application is in the server field. Figure 1 As shown, in some specific business scenarios, servers need to be deployed with multiple CPUs, such as... Figure 1 The diagram shows CPU1 and CPU2. CPU1 and CPU2 are interconnected via their communication ports. (See diagram for example.) Figure 1 As shown in [a], CPU1's communication port 3 is connected to CPU2's communication port 2 via an interconnect bus; CPU1's communication port 4 is connected to CPU2's communication port 1 via an interconnect bus; CPU1's communication port 7 is connected to CPU2's communication port 6 via an interconnect bus; and CPU1's communication port 8 is connected to CPU2's communication port 5 via an interconnect bus.

[0079] like Figure 1 As shown in [b], communication port 2 of CPU1 is connected to communication port 2 of CPU2 via the interconnect bus; communication port 3 of CPU1 is connected to communication port 3 of CPU2 via the interconnect bus; communication port 6 of CPU1 is connected to communication port 6 of CPU2 via the interconnect bus; and communication port 7 of CPU1 is connected to communication port 7 of CPU2 via the interconnect bus.

[0080] It's understandable that when multiple CPUs are deployed in a server, an interconnect bus can connect these CPUs to form a unified pool of computing resources. Combined with... Figure 2 As can be seen, the connection relationships between multiple CPUs can exist in various ways. Therefore, the correctness of the connection relationships between CPUs directly affects the operating performance of the server system.

[0081] In some embodiments, by designing specific mechanical structures, such as slot limiters, on the CPU's communication port, physical prevention of interconnect bus misconnection can be achieved from a hardware perspective.

[0082] In the above embodiments, ensuring the correct connection of the interconnect bus for the CPU's communication interface through hardware requires customized hardware modules, which is costly.

[0083] In other embodiments, the server's Basic Input Output System (BIOS) detects the configuration information of the communication port during the CPU's communication port configuration process. If the configuration information is inconsistent with the correct configuration, it is considered that the communication port is misconnected.

[0084] In the above embodiments, detecting the correctness of the interconnect bus wiring of the CPU's communication port through BIOS cannot cover all incorrect wiring cases. Furthermore, detection through BIOS requires the server to be actually running before the wiring correctness can be checked, which is inefficient.

[0085] The method for detecting the connection relationship of communication ports of multiple central processing units (CPUs) provided in this application embodiment sends a preset signal to the communication port of the CPU to be processed through a baseboard management controller in a server, and detects the port status of the communication ports of other CPUs. If the port status responds to the preset signal, it is determined that the communication port of the CPU to be processed has a connection relationship with the communication ports of other CPUs. If the connection relationship obtained by comparison is consistent with the preset correct connection relationship, it is determined that the connection relationship of the communication ports of multiple CPUs in the server is correct. This method achieves the correctness of the connection relationship of the interconnection bus between multiple CPUs in the server through software, without the need for specific mechanical structures, thus reducing costs.

[0086] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0087] Figure 2 A schematic diagram of the structure of an exemplary server Figure 2 .like Figure 3 As shown in the embodiments of this application, the method provided is applied to a baseboard management controller (BMC) in a server, and the server is provided with at least two central processing units (CPUs). The BMC is connected to each CPU.

[0088] It should be noted that,Figure 1 The number of CPUs and their interconnections shown are for illustrative purposes only and do not represent a limitation on the number of CPUs and their interconnections in a server. In practical applications, the number of CPUs can be 2, 3, 4, or 8.

[0089] Specifically, when the BMC connects to each CPU, it can do so through a management bus. The management bus can take the form of, but is not limited to, the Improved Inter-Integrated Circuit (I3C bus) or the Joint Test Action Group (JTAG bus).

[0090] Specifically, CPUs can be connected via an interconnect bus. In one possible implementation, the type of interconnect bus is associated with the CPU model. For example, some CPU platforms may use Ultra Path Interconnect (UPI) for connection. Other platforms may use Cross-Generator Mesh Interface (xGMI). Still others may use Cache Coherent Interconnect for Accelerators (CCIX).

[0091] Figure 3 A flowchart illustrating the method for detecting the communication port connection relationship of multiple central processing units provided in this application. Figure 2 ,like Figure 4 As shown, this method can be applied to, for example Figure 2 The method includes: A baseboard management controller (BMC) in the server shown.

[0092] Step 301. Send a preset signal to the communication port of the CPU to be processed and detect the port status of the communication ports of other CPUs.

[0093] Among them, the other central processing units are at least two central processing units other than the central processing unit to be processed.

[0094] For example, in conjunction with the previous example, the server's BMC connects to each CPU via a management bus. A CPU is selected from all CPUs as the CPU to be processed. A preset signal is sent to the communication port of the CPU to be processed via the management bus. Specifically, the BMC writes to the internal management module or registers of the CPU to be processed via the I3C bus or JTAG bus. The preset signal is then sent to the communication port of the CPU to be processed.

[0095] It is understandable that if the communication port is connected to the communication port of another CPU, the communication port of the other CPU will respond to the preset signal.

[0096] The BMC monitors the port status of other CPUs' communication ports via the management bus. Specifically, the BMC reads the registers of other CPUs' communication ports through the I3C or JTAG bus. It then detects and records the port status of these communication ports.

[0097] Step 302. If it is determined that the port status of the communication port of another central processing unit has a preset signal response, then it is determined that the communication port of the central processing unit to be processed has a connection relationship with the communication ports of other processors.

[0098] For example, based on the port status of the communication ports of other CPUs obtained in the aforementioned steps, a detection and judgment are performed. If it is determined that the port status of the communication ports of other CPUs has a response to the preset signal, it indicates that the communication port of the CPU to be processed that sent the preset signal has a connection relationship with the communication port of the other CPU that has a response to the preset signal.

[0099] In practical applications, a server can have multiple CPUs. Each CPU can act as a processing CPU to execute the above process. Therefore, the connection relationships of the different communication ports of each CPU can be obtained.

[0100] Step 303. If the connection relationship is found to be consistent with the preset topology relationship, then the communication port connection relationship of at least two central processing units is determined to be correct.

[0101] The topology relationship refers to the correct communication port connection relationship between at least two central processing units.

[0102] For example, the above connection relationship is compared with the preset topology relationship. If the comparison results are consistent, it is determined that the communication port connection relationship of the CPU in the server is correct.

[0103] It is understandable that each CPU in the server can act as a CPU to perform the above process. Therefore, the connection relationships of each communication port of each CPU will be determined. These connection relationships can be in the form of data rows or in the form of a topology diagram.

[0104] For example, a connection might include two communication ports connected via an interconnect bus. Each data row represents a connection, and within each data row, the labels of the two communication ports connected and their respective CPUs are recorded.

[0105] Compare these connection relationships with the preset communication port connection relationships when the CPUs in the server are correctly connected. If the comparison results are consistent, it can be concluded that the communication port connection relationships between the CPUs in the current server are correct.

[0106] The method for detecting the communication port connection relationship of multiple CPUs provided in this application embodiment sends a preset signal to the communication port of the CPU to be processed through the Baseboard Management Controller (BMC) in the server, and detects the port status of the communication ports of other CPUs. If the port status responds to the preset signal, it is determined that the communication port of the CPU to be processed has a connection relationship with the communication ports of other CPUs. If the connection relationship obtained by comparison is consistent with the preset correct connection relationship, it is determined that the connection relationship of the communication ports of multiple CPUs in the server is correct. The correctness of the connection relationship of the interconnection bus between multiple CPUs in the server is realized by software, without the need for specific mechanical structures, thus reducing costs.

[0107] Furthermore, by communicating directly with the CPU through the BMC, the connection relationship of the CPU's interconnect bus can be detected directly, improving detection efficiency.

[0108] Figure 4 A flowchart illustrating the method for detecting the communication port connection relationship of multiple central processing units provided in this application. Figure 5 ,like Figure 3 As shown, in the process of detecting the port status of the communication ports of other central processing units, the method may specifically include repeatedly executing the following steps 401 to 403 until the preset signals are sent to each communication port of the central processing unit to be processed:

[0109] Step 401. Send a preset signal to the i-th communication port of the central processing unit to be processed.

[0110] Where i is an integer greater than or equal to 1, and the initial value of i is 1.

[0111] For example, in practical applications, each CPU can have multiple communication ports. Therefore, when sending a preset signal to the CPU to be processed, the preset signal is sent to one communication port at a time, and this process is repeated until the preset signal has been sent to every communication port of the CPU to be processed.

[0112] In one example, the CPUs of the server are connected via a UPI bus. Based on this, the preset signal is a correctable error signal (CE signal).

[0113] For example, a preset signal is sent to the CPU to be processed to write to the i-th communication port of the CPU to be processed, injecting a specific error (i.e., CE signal) into the UPI controller inside the CPU to be processed.

[0114] By injecting a CE signal into the CPU's communication port, the response of other CPUs' communication ports can be polled to determine whether there is an interconnect bus connection between the communication ports of that CPU and the communication ports of other CPUs. This can cover complex error scenarios that traditional basic input / output systems (BIOS) cannot detect, thus improving detection accuracy. Furthermore, without relying on BIOS preset logic, the BMC can independently complete the detection of connection relationships, enhancing system flexibility.

[0115] Step 402. Detect the port status of the communication ports of other central processing units.

[0116] For example, after injecting a CE signal into the i-th communication port of the CPU to be processed, the port status of the communication ports of other central processing units is detected.

[0117] Specifically, the BMC reads the registers of other CPUs' communication ports via the I3C bus or JTAG bus. The registers record the port status of that communication port.

[0118] If the port status of a communication port of another CPU responds to the CE signal, it indicates that the communication port is connected to the i-th communication port of the CPU to be processed.

[0119] The CE (Corrective Error) signal is a correctable error signal. When two CPUs' communication ports are connected, if a CE signal is injected into one communication port, the other connected communication port will respond accordingly. For example, the CPU's communication port register is the Machine Check Architecture (MCA) register. The MCA register may contain a correctable error flag. If this flag is set to 1, it indicates that a CE signal has been detected.

[0120] In practical applications, a server may have more than two CPUs. In this case, there will be multiple other CPUs, and each CPU will also have multiple communication ports.

[0121] Therefore, when checking the port status of other CPUs' communication ports, each CPU checks sequentially; when a single CPU checks, it checks the port status of each communication port of that CPU sequentially.

[0122] Specifically, steps 4021 to 4022 can be repeated until the port status of the communication ports of other CPUs is detected:

[0123] Step 4021. Sequentially check the port status of each communication port in the j-th other central processing unit.

[0124] Where j is an integer greater than or equal to 1, and the initial value of j is 1.

[0125] For example, when there are multiple other CPUs, the port status of the communication port of one other CPU is checked at a time.

[0126] Specifically, the BMC reads the registers of each communication port in the j-th other CPU, thereby obtaining the port status of each communication port in the j-th other CPU.

[0127] Optionally, during the process of reading the registers of each communication port in the j-th other CPU, the registers of different communication ports can be read sequentially, or the registers of each communication port can be read simultaneously.

[0128] Obtain the port status of each communication port of the j-th other CPU and perform detection; if the port status has the response of the CE signal, it indicates that the communication port of the j-th other CPU has a connection relationship with the i-th communication port of the CPU to be processed.

[0129] Step 4022. Increment the value of j by 1.

[0130] For example, the value of j is incremented by 1, and the port status of each communication port of the next CPU is read and detected.

[0131] It should be noted that the initial value of j is 1, and the final value of j is M-1; where M is the number of CPUs in the server.

[0132] By sequentially checking the port status of the communication ports of other CPUs, it is possible to traverse all other CPUs and detect whether there is a connection between the communication port of each other CPU and the communication port of the CPU currently injecting the CE signal. This achieves comprehensive detection of the connection relationships between CPUs.

[0133] Step 403. Increment the value of i by 1.

[0134] For example, after reading and detecting the port status of each communication port of other CPUs, it can be determined which communication ports of other CPUs the i-th communication port of the CPU to be processed has a connection relationship with.

[0135] To further test other communication ports of the CPU to be processed, the value of i needs to be incremented by 1, and the above steps need to be repeated.

[0136] It should be noted that the initial value of i is 1, and the final value of i is N; where N is the number of communication ports of the CPU to be processed.

[0137] It should also be noted that the server has at least two CPUs. Therefore, each CPU in the server can be used as a processing CPU to perform the above operations.

[0138] Through the above process, the polling mechanism can send CE signals to each communication interface of the CPU to be processed, and when CE signals are injected into each communication interface of the CPU to be processed, the port status of each communication interface of other CPUs can be detected, thereby realizing a comprehensive detection of the connection relationship between the communication ports of the CPUs in the server.

[0139] In one example, after detecting the port status of the communication ports of other CPUs in step 402, the method may further include:

[0140] Send a reset signal to the i-th communication port of the central processing unit to be processed.

[0141] The reset signal is used to restore the port state of the i-th communication port and / or the port state of the connection port, where the connection port is a communication port of another central processing unit connected to the i-th communication port.

[0142] For example, after detecting the port status of the communication ports of other CPUs, before accumulating the value of i, it is necessary to restore the CE signal injected into the i-th communication port of the CPU to be processed.

[0143] Specifically, a restoration signal is sent to the i-th communication port of the CPU to be processed, so as to restore the port state of the i-th communication port of the CPU to be processed; if the i-th communication port of the CPU to be processed has communication ports of other CPUs connected to it, the restoration signal can also restore the port state of the communication ports of the other CPUs connected to it.

[0144] Optionally, the BMC can also read the port status of other CPUs' communication ports via the I3C bus or JTAG bus to determine if the port status of these other CPUs' communication ports has been restored. This avoids situations where, when a CE signal is sent to the next communication port of the CPU being processed, other CPUs' communication ports that are not physically connected to the next communication port also exhibit corresponding CE signal responses.

[0145] In the example above, after injecting a CE signal into the communication port of the CPU to be processed, the port status of the communication ports of other CPUs is detected. After the detection is complete, a CE signal can be injected into the next communication port of the CPU to be processed. Before injecting a CE signal into the next communication port, the previous CE signal needs to be reset. This ensures that the connection relationship of one communication port of the CPU to be processed is detected each time, ensuring the accuracy of the connection relationship detection of multiple CPUs in the server.

[0146] Using the previous example, let's take a server with two CPUs as an example.

[0147] For example, Figure 5 A schematic diagram of the structure of an exemplary server Figure 5 .like Figure 5 As shown, the server's interior contains a Baseboard Management Controller (BMC) and two Central Processing Units (CPUs). Each CPU has at least one communication port, such as... Figure 5 As shown, CPU0 has two communication ports, labeled 1 and 2 respectively; CPU1 has two communication ports, labeled 3 and 4 respectively.

[0148] like Figure 5 As shown, the BMC is connected to the management ports of each CPU via the I3C bus or JTAG bus; the communication ports between the CPUs are connected via the UPI interconnect bus.

[0149] Combination Figure 5 The method provided in this application is explained below. The server is connected to alternating current (AC) power, enabling the BMC in the server to be powered on by AC and start up. The server system boots up, and the BIOS executes the power-on self-test (POST) process.

[0150] Combination Figure 5 To explain, CPU0 is designated as the central processing unit to be processed. The BMC communicates with the first communication port via the I3C bus or JTAG bus. Figure 5A preset signal is sent to port 1 of CPU0, i.e., a CE signal is injected. Specifically, the management module or registers inside CPU0 are written to achieve control over CPU0's UPI PORT1 ( Figure 5 Inject a CE signal into port 1 of CPU0.

[0151] The BMC polls the registers of CPU1 via the I3C bus or JTAG bus to check for a CE signal response and records the port status of each communication port of CPU1. It can be understood that CPU1 is the other CPUs mentioned in the previous example.

[0152] Specifically, the BMC reads the UPI management module or registers inside CPU1 to detect the port status of each communication port of CPU1 and whether there is a corresponding CE signal response.

[0153] Combination Figure 6 The connection relationship shown indicates that port 4 of CPU1 has a corresponding CE signal response, while port 3 of CPU1 does not. Therefore, it can be determined that port 1 of CPU0 and port 4 of CPU1 are connected.

[0154] Furthermore, the BMC sends a reset signal to port 1 of CPU0 via the I3C bus or JTAG bus to reset the port state of port 1 of CPU0, and the port state of port 4 of CPU1 will also be reset accordingly.

[0155] Next, the BMC sends a CE signal to port 2 of CPU0 via the I3C bus or JTAG bus. The BMC also polls the registers of CPU1 via the I3C bus or JTAG bus to check for a CE signal response and records the port status of each communication port of CPU1. Combined with... Figure 6 The connection relationship shown indicates that port 3 of CPU1 has a corresponding CE signal response, while port 4 of CPU1 does not. Therefore, it can be determined that port 2 of CPU0 and port 3 of CPU1 are connected.

[0156] Based on the two connection relationships mentioned above, compare them with the preset topology. If the correct communication port connection relationships in the preset topology are: CPU0's port 1 is connected to CPU1's port 4, and CPU0's port 2 is connected to CPU1's port 3, then the connection relationships are consistent with the preset topology, indicating that the communication port connection relationships of the CPUs in the current server are correct.

[0157] Building upon any of the aforementioned examples, corresponding prompts and warnings can also be triggered when an error is detected in the CPU connection relationship on the server.

[0158] Specifically, in one example, the method also includes:

[0159] If the connection relationship is determined to be inconsistent with the preset topology relationship, then at least one of the following shall be executed:

[0160] Prevent at least two central processing units from starting;

[0161] The system control indicator lights are turned on; these indicator lights are used to indicate that the communication port connection relationship between at least two central processing units in the server is incorrect.

[0162] Generate alarm information; wherein, the alarm information is used to inform the user that the communication port connection relationship of at least two central processing units in the server is incorrect.

[0163] For example, if a connection relationship is detected to be inconsistent with the preset topology, it indicates that there is a misconnection between the communication ports of the CPUs in the current server. The system can prompt the user to check and repair the connection; it can also control the CPU to prevent the server from malfunctioning due to incorrect interconnect bus connections.

[0164] In one example, the BMC controls to prevent at least two central processing units from starting.

[0165] Specifically, the BMC can control the CPU's power module and cut off the power supply to each CPU when the connection relationship is inconsistent with the preset topology relationship, thereby preventing the CPU from powering on and prohibiting the CPU from starting.

[0166] Optionally, after the user repairs the connection relationship of the CPU's communication port, the detection process of the method provided in this application is retried. If the detected connection relationship is consistent with the preset topology relationship, the CPU can be controlled to start.

[0167] In one example, the BMC control system indicator light is turned on.

[0168] Specifically, the BMC sends commands to the system indicator light controller via the server's internal standard hardware bus. The system indicator light controller responds by outputting a high-level signal, thus turning on the system indicator lights. These system indicator lights are used to show the user that the communication interfaces of the CPUs in the server are connected incorrectly, i.e., there is a misconnection.

[0169] In one example, the BMC generates an alarm message.

[0170] Specifically, the BMC generates an alarm message and displays a pop-up notification on a pre-defined web interface. This alarm message indicates to the user that the communication interfaces of the CPUs in the current server are incorrectly connected, i.e., there is a misconnection.

[0171] In the example above, when the BMC detects an error in the CPU connection of the server, it can trigger various forms of prompts and control actions. On the one hand, this ensures the normal operation of the server, and on the other hand, it prompts the user to check and repair, further ensuring the normal operation of the server.

[0172] Based on any of the aforementioned examples, and assuming the connection relationships between each CPU are determined, a connection relationship diagram can be drawn and visualized, allowing users to clearly understand the connection relationships between CPUs in the current server.

[0173] Specifically, in one example, the method also includes:

[0174] Draw a connection diagram based on the connections. Display the connection diagram on a preset interface.

[0175] The connection diagram includes multiple connections, each representing the connection between the communication port of the central processing unit to be processed and the communication ports of other processors.

[0176] For example, a connection relationship diagram is obtained by visually drawing a graph based on the detected connection relationships between the communication ports of each CPU.

[0177] The connectivity diagram includes the CPUs in the server and their communication ports. Furthermore, the diagram includes multiple connections. Each connection represents a link between the communication ports of the CPUs.

[0178] For example, combining Figure 7 The connection relationships shown are explained below. The connection diagram includes CPU0 and CPU1; ports 1 and 2 on CPU0; ports 3 and 4 on CPU1; the connection relationship between port 1 of CPU0 and port 4 of CPU1; and the connection relationship between port 2 of CPU0 and port 3 of CPU1.

[0179] Furthermore, this connection relationship is visualized on a preset interface. This preset interface can be a web interface.

[0180] Furthermore, a topology diagram can be pre-defined in BMC. Based on this example, the method can also include:

[0181] On the preset interface, a preset topology diagram is displayed alongside the connection diagram; the topology diagram includes multiple topology relationships.

[0182] For example, a topology diagram is pre-defined in BMC. This diagram includes multiple topological relationships. As illustrated in the previous example, the topology represents the correct communication port connections between the CPUs in the server. In essence, the topology diagram is a visual representation of the correct CPU communication port connections.

[0183] Based on this, the connection diagram and the topology diagram are displayed side by side on the preset interface, so as to visually compare the connection relationship of the communication ports of each CPU in the current server with the correct connection relationship.

[0184] Optionally, in the aforementioned example, the BMC has preset topology relationships. As can be seen from this example, the BMC can also have preset topology diagrams. These topology relationships and diagrams correspond to the server models. It can be understood that the BMC can have preset topology relationships and / or topology diagrams for CPU communication ports under various server models.

[0185] BMC can also identify the current server model based on hardware signals, selecting the topology and / or topology diagram corresponding to the current server model from the CPU communication port topology and / or topology diagrams of various server models, and comparing it with the detected connection relationships and / or connection diagrams.

[0186] In the example above, the graphical display of connection relationships helps users clearly and directly understand the connection relationships between multiple CPUs on the server. When connection errors occur, the communication ports of the incorrect connections can be quickly located. Furthermore, it can automatically compare the topology diagram with the correct connection relationships, reducing the time spent manually troubleshooting connection errors and improving system deployment efficiency.

[0187] The method for detecting the communication port connection relationship of multiple CPUs provided in this application injects a CE signal into the communication port of the CPU to be processed and detects the port status of the communication ports of other CPUs. If the port status responds to the CE signal, it is determined that there is a connection relationship between the two communication ports to be processed. If the connection relationship obtained is consistent with the preset correct connection relationship, it is determined that the connection relationship between the CPUs in the server is correct. This method achieves the detection of the correctness of the interconnection bus connection relationship between multiple CPUs in a server through software, without the need for specific mechanical structures, thus reducing costs.

[0188] Furthermore, the polling mechanism can comprehensively cover every communication port of every CPU in the server, ensuring the comprehensiveness and accuracy of connection relationship detection.

[0189] In addition, the BMC can operate independently of the BIOS, enabling flexible configuration without relying on the server's BIOS.

[0190] Furthermore, the connection diagram is displayed visually, allowing users to clearly and intuitively determine the connection relationships between the CPUs within the server. Moreover, when errors occur in the connection relationships, timely prompts and control actions are taken to ensure the normal operation of the server.

[0191] Figure 7 A schematic diagram of the structure of the detection device for the communication port connection relationship of multiple central processing units provided in this application is shown below. ​ As shown, the detection device 60 for the communication port connection relationship of multiple central processing units provided in this embodiment includes:

[0192] The detection module 601 is used to send a preset signal to the communication port of the CPU to be processed and detect the port status of the communication ports of other CPUs; wherein, the other CPUs are at least two CPUs other than the CPU to be processed.

[0193] The processing module 602 is used to determine that the communication port of the central processing unit to be processed has a connection relationship with the communication ports of other processors if it is determined that the port status of the communication port of another central processing unit has a response of a preset signal.

[0194] The comparison module 603 is used to determine that the communication port connection relationship of at least two central processing units is correct if the connection relationship is consistent with the preset topology relationship; wherein, the topology relationship is the correct communication port connection relationship of at least two central processing units.

[0195] In one possible implementation, each central processing unit (CPU) has at least one communication port; a preset signal is sent to the communication port of the CPU to be processed, and the port status of the communication ports of other CPUs is detected. The detection module 601 is used for:

[0196] Repeat the following steps until the preset signals have been sent to each communication port of the central processing unit to be processed:

[0197] Send a preset signal to the i-th communication port of the central processing unit to be processed; where i is an integer greater than or equal to 1, and the initial value of i is 1;

[0198] Detect the port status of communication ports of other central processing units;

[0199] Increment the value of i by 1.

[0200] In one possible implementation, the detection module 601 detects the port status of each communication port of other central processing units, and is used for:

[0201] Repeat the following steps until the port status of the communication ports of each other central processing unit is detected:

[0202] The port status of each communication port in the j-th other central processing unit is checked sequentially; where j is an integer greater than or equal to 1, and the initial value of j is 1;

[0203] Increment the value of j by 1.

[0204] In one possible implementation, after detecting the port status of the communication ports of other central processing units, the detection module 601 is further configured to:

[0205] Send a reset signal to the i-th communication port of the CPU to be processed; wherein the reset signal is used to restore the port state of the i-th communication port, and / or the port state of the connected port, wherein the connected port is the communication port of another CPU connected to the i-th communication port.

[0206] In one possible implementation, the preset signal is a correctable error signal.

[0207] In one possible implementation, the comparison module 603 is further configured to:

[0208] If the connection relationship is determined to be inconsistent with the preset topology relationship, then at least one of the following shall be executed:

[0209] Prevent at least two central processing units from starting;

[0210] The system control indicator lights are turned on; these indicator lights are used to indicate that the communication port connection relationship between at least two central processing units in the server is incorrect.

[0211] Generate alarm information; wherein, the alarm information is used to inform the user that the communication port connection relationship of at least two central processing units in the server is incorrect.

[0212] In one possible implementation, the processing module 602 is further configured to:

[0213] Based on the connection relationships, draw a connection relationship diagram; wherein the connection relationship diagram includes multiple connection relationships, each connection relationship represents the connection between the communication port of the central processing unit to be processed and the communication port of other processors;

[0214] The connection diagram is displayed on the preset interface.

[0215] In one possible implementation, the processing module 602 is further configured to:

[0216] On the preset interface, a preset topology diagram is displayed alongside the connection diagram; the topology diagram includes multiple topology relationships.

[0217] The detection device for the communication port connection relationship of multiple central processing units provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0218] ​ A schematic diagram of the structure of the baseboard management controller provided in this application. ​ As shown, the baseboard management controller 70 provided in this embodiment includes at least one processor 701 and a memory 702. Optionally, the baseboard management controller 70 further includes a communication component 703. The processor 701, memory 702, and communication component 703 are connected via a bus 704.

[0219] In a specific implementation, at least one processor 701 executes computer execution instructions stored in memory 702, causing at least one processor 701 to perform the above-described method.

[0220] The specific implementation process of processor 701 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0221] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0222] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0223] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0224] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0225] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0226] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0227] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0228] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0229] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0230] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0231] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0232] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0233] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for detecting a connection relationship of communication ports of a plurality of central processing units, characterized by, A baseboard management controller applied to a server, the baseboard management controller is connected with at least two central processing units in the server respectively; the method comprises: sending a preset signal to a communication port of a to-be-processed central processing unit, and detecting a port state of a communication port of another central processing unit; wherein the another central processing unit is a central processing unit other than the to-be-processed central processing unit among the at least two central processing units; if it is determined that the port state of the communication port of the another central processing unit has a response of the preset signal, it is determined that the communication port of the to-be-processed central processing unit and the communication port of the another central processing unit have a connection relationship; if it is determined that the connection relationship is consistent with a preset topological relationship, it is determined that the connection relationship of the communication ports of the at least two central processing units is correct; wherein the topological relationship is a correct connection relationship of the communication ports of the at least two central processing units.

2. The method of claim 1, wherein, Each of the central processing units has at least one communication port; sending a preset signal to a communication port of a to-be-processed central processing unit, and detecting a port state of a communication port of another central processing unit, comprises: repeating the following steps until the preset signal is sent to each communication port of the to-be-processed central processing unit: sending a preset signal to an i-th communication port of a to-be-processed central processing unit; wherein i is an integer greater than or equal to 1, and the initial value of i is 1; detecting the port state of the communication port of the another central processing unit; adding 1 to the value of i.

3. The method of claim 2, wherein, Detecting the port state of each communication port of the another central processing unit comprises: repeating the following steps until the port state of each communication port of the another central processing unit is detected: sequentially detecting the port state of each communication port in a j-th another central processing unit; wherein j is an integer greater than or equal to 1, and the initial value of j is 1; adding 1 to the value of j.

4. The method of claim 2, wherein, After detecting the port state of the communication port of the another central processing unit, the method further comprises: sending a reset signal to the i-th communication port of the to-be-processed central processing unit; wherein the reset signal is used to restore the port state of the i-th communication port, and / or the port state of a connection port, the connection port being a communication port of the another central processing unit connected with the i-th communication port.

5. The method of claim 1, wherein, The preset signal is a correctable error signal.

6. The method according to any one of claims 1-5, characterized in that, The method further comprises: if it is determined that the connection relationship is inconsistent with the preset topological relationship, at least one of the following is performed: inhibiting the at least two central processing units from starting; controlling a system indicator light to turn on; wherein the system indicator light is used to indicate that the connection relationship of the communication ports of the at least two central processing units in the server is incorrect; generating an alarm information; wherein the alarm information is used to prompt a user that the connection relationship of the communication ports of the at least two central processing units in the server is incorrect.

7. The method according to any one of claims 1-5, characterized in that, The method further comprises: drawing a connection relationship diagram according to the connection relationship; wherein the connection relationship diagram comprises a plurality of connection relationships, and each of the connection relationships represents a connection between the communication port of the to-be-processed central processing unit and the communication port of the another central processing unit; displaying the connection relationship diagram on a preset interface.

8. The method of claim 7, wherein, The method further comprises: On the preset interface, a preset topological relationship diagram is displayed in parallel with the connection relationship diagram; the topological relationship diagram comprises a plurality of topological relationships.

9. A device for detecting the communication port connection relationship of multiple central processing units, characterized in that, Comprise: A detection module configured to send a preset signal to a communication port of a to-be-processed central processing unit and detect port states of communication ports of other central processing units; the other central processing units are central processing units other than the to-be-processed central processing unit among at least two central processing units; A processing module configured to determine that the communication port of the to-be-processed central processing unit has a connection relationship with the communication ports of the other central processing units if it is determined that the port states of the communication ports of the other central processing units have responses to the preset signal; A comparison module configured to determine that the connection relationship between the communication ports of the at least two central processing units is correct if it is determined that the connection relationship is consistent with a preset topological relationship; the topological relationship is a correct communication port connection relationship of the at least two central processing units.

10. A baseboard management controller, comprising: Comprise: A memory, a processor; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory, so that the processor executes the method of any one of claims 1-8.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the method of any one of claims 1-8.

12. A computer program product, characterised in that, A computer program is included, and the computer program is executed by the processor to implement the method of any one of claims 1-8.

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