Memory self-checking method and device and electronic equipment

Abstract

The invention relates to a memory self-checking method and device and electronic equipment. The method comprises the steps of determining a target self-checking mode in response to a self-checking enabling instruction issued for a memory; if the target self-check mode comprises a pseudo-random self-check mode, performing multiple rounds of random self-check on a target address space of the memory; each round of random self-check comprises the steps of generating a random write address, a random write length and random write data, and writing the random write data into the memory based on the random write address and the random write length; generating a random read address and a random read length, and reading the first data from the memory based on the random read address and the random read length; the random read address and the random write address correspond to the same characteristic polynomial and seed, and the random read length and the random write length correspond to the same characteristic polynomial and seed; and performing data comparison on the random write data and the first data to obtain a random self-check result of the round. The method can improve the self-checking effect and reduce the error code problem.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, and in particular to a memory self-checking method and device and electronic equipment. BACKGROUND

[0002] In the field of semiconductor testing, especially in the field of high-speed analog testing, when a tester operates a memory (such as a DDR), an error code problem is likely to occur. The error code problem refers to the fact that the data read out for the same address is inconsistent with the data written. Therefore, the error code problem needs to be discovered in advance through memory self-checking.

[0003] Traditional memory self-checking methods mostly perform memory self-checking by writing self-incrementing and self-decrementing data into the memory and reading back and comparing. However, this method is insufficient in terms of the pressure on the address lines and data lines, and is likely to cause the error code problem of the memory in the self-checking process to be exposed, resulting in an unsatisfactory self-checking effect. SUMMARY

[0004] Therefore, it is necessary to provide a memory self-checking method, device, electronic equipment, computer readable storage medium and computer program product capable of reducing error code problems.

[0005] In a first aspect, the present application provides a memory self-checking method, which comprises:

[0006] In response to a self-checking enabling instruction issued for the memory, a target self-checking mode is determined.

[0007] If the target self-checking mode includes a pseudo-random self-checking mode, a plurality of rounds of random self-checking are performed on a target address space of the memory; wherein each round of random self-checking comprises:

[0008] A random write address, a random write length and random write data are generated, and the random write data is written into the memory based on the random write address and the random write length;

[0009] A random read address and a random read length are generated, and first data is read from the memory based on the random read address and the random read length; the random read address corresponds to the same characteristic polynomial and seed as the random write address, and the random read length corresponds to the same characteristic polynomial and seed as the random write length;

[0010] The random write data and the first data are compared to obtain a random self-checking result of the current round.

[0011] In a second aspect, the present application further provides a memory self-checking method, which comprises:

[0012] A current test scenario is determined.

[0013] Determine the target self-test mode that matches the current test scenario; the target self-test mode includes the pseudo-random algorithm self-test mode; the pseudo-random algorithm self-test mode is used to instruct the logic module to perform multiple rounds of random self-tests on the target address space of memory. In each round of random self-tests, random write addresses, random write lengths and random write data are generated for random read and write tests.

[0014] Generate a memory self-test enable instruction based on the target self-test mode;

[0015] Issue a self-test enable command.

[0016] Thirdly, this application also provides a memory self-test device, the device comprising:

[0017] The self-test mode determination module is used to respond to the self-test enable command issued to the memory and determine the target self-test mode.

[0018] The random self-test module is used to perform multiple rounds of random self-tests on the target address space of memory if the target self-test mode includes a pseudo-random self-test mode.

[0019] In each round of random self-testing, the random self-testing module is also used to generate random write addresses, random write lengths, and random write data, and write the random write data to memory based on the random write addresses and random write lengths; generate random read addresses and random read lengths, and read the first data from memory based on the random read addresses and random read lengths; the random read addresses and random write addresses correspond to the same characteristic polynomials and seeds, and the random read lengths and random write lengths correspond to the same characteristic polynomials and seeds; compare the random write data with the first data to obtain the random self-testing result for this round.

[0020] Fourthly, this application also provides a memory self-test device, comprising:

[0021] The self-test mode determination module is used to determine the current test scenario;

[0022] Determine the target self-test mode that matches the current test scenario; the target self-test mode includes the pseudo-random algorithm self-test mode; the pseudo-random algorithm self-test mode is used to instruct the logic module to perform multiple rounds of random self-tests on the target address space of memory. In each round of random self-tests, random write addresses, random write lengths and random write data are generated for random read and write tests.

[0023] The self-test enable module is used to generate a memory self-test enable instruction based on the target self-test mode and to issue the self-test enable instruction.

[0024] Fifthly, this application also provides an electronic device. The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method mentioned in the first aspect above.

[0025] Sixthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of the method mentioned in the first aspect above.

[0026] In a seventh aspect, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the method mentioned in the first aspect above.

[0027] The aforementioned memory self-testing method, apparatus, electronic device, computer-readable storage medium, and computer program product, in response to a self-testing enable instruction issued to the memory, determine the target self-testing mode that matches the current state, thereby improving the accuracy of the self-test. Furthermore, the target self-testing mode includes a pseudo-random self-testing mode, which performs multiple rounds of random self-testing on the target address space of the memory. Each round of random self-testing includes: generating a random write address, random write length, and random write data, and writing the random write data to memory based on the random write address and random write length; generating a random read address and random read length, and reading first data from memory based on the random read address and random read length; the random read address and random write address correspond to the same characteristic polynomial and seed, and the random read length and random write length correspond to the same characteristic polynomial and seed; comparing the random write data with the first data to obtain the random self-testing result for this round. In other words, under the pseudo-random algorithm self-testing mode, multi-dimensional random read and write tests can be performed on address, length, and data in each round of random self-testing, greatly improving the fault coverage during testing, thus reducing bit error rate problems to a certain extent and improving the memory self-testing effect. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of a logic module in one embodiment;

[0029] Figure 2 This is a flowchart illustrating a memory self-test method in one embodiment;

[0030] Figure 3 This is a simplified diagram illustrating the principle of a memory self-test method in one embodiment;

[0031] Figure 4 This is a schematic diagram illustrating the principle of a random generation algorithm in one embodiment;

[0032] Figure 5 This is a schematic diagram illustrating the principle of pseudo-random self-testing mode in one embodiment;

[0033] Figure 6 This is a schematic diagram of the memory self-test process in pseudo-random self-test mode in one embodiment;

[0034] Figure 7This is a schematic diagram illustrating the principle of the memory self-test process in address line self-test mode in one embodiment;

[0035] Figure 8 This is a schematic diagram illustrating the principle of the memory self-test process in the data line self-test mode of one embodiment;

[0036] Figure 9 This is a schematic diagram illustrating the principle of the memory self-test process in the self-test mode of the step optimization algorithm in one embodiment;

[0037] Figure 10 This is a schematic diagram illustrating the principle of data comparison in one embodiment;

[0038] Figure 11 This is a diagram of the internal structure of an electronic device in one embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] Some solutions use address incrementing or decrementing for memory self-testing. That is, starting from the beginning of the memory address, each address is sequentially read and written by incrementing or decrementing by 1. This method suffers from insufficient address line jumps. Problems caused by multiple address line jumps typically do not appear or rarely occur during self-testing. Therefore, even if the memory hardware has defects in multi-line jump scenarios, they are not easily detected. In practical applications, numerous address line jump scenarios often occur, causing undetected memory defects to be exposed, resulting in bit errors (i.e., read / write errors).

[0041] Other solutions employ memory self-testing using data increment or self-checking methods. That is, by continuously incrementing or decrementing the data to be written to memory by 1, read and write tests are performed on each address in memory. In this method, data jumps are very small, and interference caused by multiple data line jumps is minimal or nonexistent. Therefore, it cannot fully expose defects in the memory hardware caused by multiple data line jumps during the self-test phase. However, in real-world applications, during memory read and write operations, a large number of data lines typically jump simultaneously, exposing these undetected memory defects and easily leading to bit error rates.

[0042] To address the aforementioned issues, this application proposes a novel memory self-testing method. This method aims to perform a more thorough and effective self-test of the memory, thereby reducing bit error rates during subsequent memory use. The memory can be DDR (Double Data Rate) or other types of internal memory.

[0043] This memory self-test method is applied to a memory self-test system, which includes a host computer, logic modules (such as FPGAs), and memory chips. The method is implemented through the interaction between these devices or modules within the system. The overall process of this method includes:

[0044] (1) Power on the whole machine.

[0045] (2) The logic module performs initialization operations and waits for the self-test enable instruction for memory.

[0046] (3) The host computer sends a self-test enable instruction, which includes the target self-test mode, self-test address, and self-test length. The self-test address refers to the starting address of the memory self-test.

[0047] (4) After receiving the self-test enable instruction, the logic module performs a memory self-test operation according to the target self-test mode.

[0048] It should be understood that after enabling memory self-test, the self-test status can be set to "self-test in progress" before the self-test process is executed. For example, a self-test status of 000 indicates that no self-test has been performed, while setting it to 001 indicates that the self-test is in progress. The error message at this time does not represent the final error message.

[0049] (5) The host computer uses a blocking read operation to read the memory self-test result. Thus, after the logic module completes the memory self-test, it can directly return the memory self-test result. For example, after the self-test is completed, the self-test completion status is raised. The memory self-test result includes at least one of the following: the final self-test status, the target self-test mode, or exception information (i.e., error information). For instance, self-test status 010 indicates that the self-test is complete and successful, while self-test status 100 indicates that the self-test is complete but failed. In this case, exception information can be read for problem analysis and localization. Exception information includes at least one of the following: the number of errors, error addresses, or error data. Error addresses and data from the self-test can be cached, allowing the host computer to read and analyze error addresses and data, facilitating the localization of the cause of the exception.

[0050] It should be understood that when the host computer uses a blocking read operation, after the host computer initiates a request to read the memory self-test results, it will enter a waiting state until the logic module returns the memory self-test results. This reduces the interaction between the host computer and other instructions, while also supporting the operation of other instructions. This allows the host computer to perform diagnosis of other peripherals during the memory self-test process, which can greatly improve the efficiency of external device detection.

[0051] (6) If the host computer finds a self-test error based on the self-test status, it can use the read return instruction to read the error address and error data in order to analyze the cause of the error.

[0052] For example, the host computer can also perform targeted self-tests on the address space where the error occurred. For instance, the host computer can specify the address space where the error occurred in the self-test enable instruction, thereby enabling the logic module to perform self-tests on the specified address space.

[0053] As can be seen from the above, the memory self-test method in this application embodiment includes two parts. One part is the communication process with the host computer, which is responsible for the self-test enable sending and the reading back of the self-test status and abnormal information; the other part is the self-test function, which is responsible for the specific self-test process and the caching of the self-test status and abnormal information. The self-test function mainly corresponds to the above step (4).

[0054] Figure 1 This is used to illustrate structures related to memory self-testing in a logic module. For example... Figure 1 As shown, the logic module includes a communication module, a master control downlink module, a master control uplink module, a service downlink module, a service uplink module, a blocking uplink module, and a memory processing module. The memory processing module includes a memory self-test module and several read / write channels (e.g., write channel 0 to write channel n, read channel 0 to read channel n).

[0055] The communication module receives instructions from the host computer and sends them to the service downlink module via the main control downlink module. The service downlink module determines that the instruction is a memory self-test enable instruction, retrieves the self-test enable information, and sends it to the memory self-test module. Then, it executes the memory self-test method described in this embodiment to perform a memory self-test. After execution, the self-test status and abnormal information can be read back through the service uplink module, or the self-test status can be read back in a blocking manner by providing a return time through the blocking uplink module. Then, the self-test status and abnormal information are transmitted to the communication module via the main control uplink module, and subsequently to the host computer. The host computer can use this self-test status to determine the self-test time, success, or failure. Furthermore, the host computer can analyze the abnormal information to better identify problems with the link or component soldering.

[0056] like Figure 1 As shown, during the memory self-test process, the memory read / write interface can be called through the read / write channel to initiate read / write requests to the memory IP core, enabling the memory IP core to control the memory chips to perform data read / write processing. The memory self-test module can update the memory's self-test status and determine abnormal information based on the comparison results of read / write data. Memory chips are the storage units of memory.

[0057] For example, the memory self-test enable instruction can be issued in groups. That is, by issuing a single self-test enable instruction, multiple memory locations can be instructed to perform self-tests in parallel, reducing the time required for serial self-tests and the number of downlink instructions issued, thus improving efficiency. The memory self-test method will be described in more detail below.

[0058] like Figure 2 As shown, in some embodiments, a memory self-test method is provided. This method can be implemented by a logic module or through interaction between the logic module and a host computer, and specifically includes the following steps:

[0059] S21, responding to the self-test enable instruction issued for memory, determines the target self-test mode.

[0060] The self-test enable instruction is a command issued by the host computer to instruct the memory to perform a self-test. For example, the memory self-test system supports multiple self-test modes, offering greater flexibility in use and allowing different modes to be used for different scenarios. Specifically, the host computer can determine the target self-test mode matching the current test scenario, generate a memory self-test enable instruction based on the target self-test mode, and then send it to the logic module.

[0061] In some examples, the memory self-test system may support multiple self-test modes, including at least one of address line self-test mode, data line self-test mode, step-optimized algorithm self-test mode, pseudo-random self-test mode, or a combination of self-test modes. A combination of self-test modes is a combination of at least two of the individual self-test modes mentioned above. For example, suppose MODE0 represents address line shift self-test mode, MODE1 represents data line shift self-test mode, MODE2 represents step-optimized algorithm self-test mode, and MODE3 represents pseudo-random self-test mode. A combination of self-test modes could be MODE4 (fast self-test mode), including MODE0–MODE1, or it could be MODE5 (full self-test mode), including MODE0–MODE3.

[0062] Address line self-test mode is used to quickly test the address lines in memory. Unlike the traditional address increment or decrement method, each address line only needs to be read and written once, which can more quickly detect whether a single address line is normal.

[0063] The data cable self-test mode is used to quickly test the data cables in memory. Unlike the traditional data increment or decrement method, each data cable only needs to be read and written once, which can more quickly detect whether a single data cable is normal.

[0064] The address line self-test mode and data line self-test mode can quickly perform self-tests on the address lines and data lines, thus enabling faster and more effective identification of specific link and memory chip soldering problems.

[0065] The step-optimized algorithm self-test mode is a self-test method optimized from the traditional March algorithm. Compared with the traditional March algorithm, it adds test data with adjacent bits that have consecutive corresponding high levels and adjacent bits with high-low level transitions, such as 0xFFAA55FF and 0xCC3333CC. This can improve the scenario coverage of memory self-test and support the detection of faults such as fixed faults, coupling faults, address decoding faults, row / column interference (Row Hammer), data retention faults, and bridging faults, thereby improving the fault detection rate and reducing bit error rate.

[0066] The pseudo-random self-test mode instructs the logic module to perform multiple rounds of random self-tests on the target address space of memory. In each round of random self-tests, random write addresses, random write lengths, and random write data are generated for random read and write tests. In other words, the pseudo-random self-test mode can perform multi-dimensional random read and write self-test control from the perspectives of random addresses, random burst lengths, and random data. Compared to memory stress testing based solely on random data, it can control memory read and write operations under maximum pressure, supporting memory self-tests under greater pressure and in more application scenarios (especially scenarios with non-fixed addresses and non-fixed burst lengths). This improves the self-test rate and effectiveness, reduces or mitigates bit error issues, and thus ensures the stability of the program after self-testing.

[0067] The target self-test mode that matches the current test scenario can be a single self-test mode or a combination of multiple self-test modes (i.e., a combination of self-test modes).

[0068] Example 1: During the initial use phase of the board, the target self-test mode includes address line self-test mode (Mode0) and / or data line self-test mode (Mode1). During the initial use phase, Mode0 or Mode1 can be used to quickly and initially test the address lines or data lines to preliminarily assess whether the board is usable.

[0069] Example 2: During the initialization or power-on phase of the board, the target self-test mode is the step optimization algorithm self-test mode Mode2.

[0070] Example 3: During the memory stress test of the board, the target self-test mode is pseudo-random self-test mode Mode3.

[0071] Example 4: In the unit testing phase of the board, the target self-test mode is Mode4, which includes Modes 0 to 1. That is, under the target self-test mode, the address line self-test mode and the data line self-test mode are executed sequentially. Therefore, this allows for the rapid detection of data line and address line problems in the memory hardware link during the board unit testing phase, achieving maximum efficiency.

[0072] Example 5: In the full self-test scenario of the board, the target self-test mode is Mode5, which includes Mode0 to Mode3. The full self-test scenario is a scenario in which self-testing is performed throughout the entire usage phase of the board. In Mode5, the address line self-test mode, data line self-test mode, step-optimized algorithm self-test mode, and pseudo-random self-test mode are executed sequentially according to the order of the board's usage phases.

[0073] Specifically, the logic module receives and identifies self-test enable instructions; for example, the logic module can... Figure 1 The downstream service module identifies the self-test enable instruction and parses the memory-specific self-test enable information from it, which includes the target self-test mode. If the target self-test mode includes a pseudo-random self-test mode, then step S22 is executed.

[0074] like Figure 3 As shown, the memory self-test module includes a self-test enable control module and self-test modules corresponding to multiple self-test modes. For example, the pseudo-random self-test mode corresponds to a pseudo-random self-test module. After parsing the self-test enable information, the service downlink module can send it to the self-test enable control module. The self-test enable control module can determine the target self-test mode based on the self-test enable information and send an enable signal corresponding to the target self-test mode to trigger the self-test module corresponding to the target self-test mode. The self-test module corresponding to the target self-test mode can call the memory read / write interface to perform read / write tests on the memory chips based on the memory IP core.

[0075] S22, if the target self-test mode includes a pseudo-random self-test mode, then perform multiple rounds of random self-tests on the target address space of memory.

[0076] The target address space is the memory address space that needs to be tested. In this application embodiment, any self-test mode supports specifying a memory address space for targeted testing.

[0077] In some embodiments, the target address space can be specified using a self-test enable instruction. For example, the self-test enable information in the self-test enable instruction also includes a specified self-test start address and self-test length. Specifically, the host computer can respond to the self-test space specification operation, determine the specified self-test start address and self-test length, and generate a self-test enable instruction based on the target self-test mode, self-test start address, and self-test length. The logic module can extract the self-test start address and self-test length from the self-test enable information parsed from the self-test enable instruction, and then perform multiple rounds of random self-tests based on the target address space indicated by the self-test start address and self-test length. If no address space is specified, the target address space can be the entire address space of memory; that is, the default self-test start address is 0, and the self-test length is the maximum address space. It should be noted that the self-test length in this embodiment refers to the address space of the self-test, determining the entire space range of the read / write test. The read / write length is the burst length, which is the basic unit of each read / write operation in the self-test, determining the minimum step size of the read / write test.

[0078] Specifically, when the target self-test mode includes a pseudo-random self-test mode, the target self-test mode can be a single pseudo-random self-test mode or a combination of self-test modes including pseudo-random self-test modes (for example, the aforementioned full self-test mode MODE5). If the target self-test mode is a combination of self-test modes including pseudo-random self-test modes, then each self-test mode can be executed sequentially. For example, if MODE5 includes MODE0 to MODE3, then MODE0, MODE1, MODE2, and MODE3 can be executed sequentially. When executing MODE3 (pseudo-random self-test mode), multiple rounds of random self-tests of the memory can be performed according to step S22.

[0079] For example, each round of random self-testing includes the following steps S221 to S223, wherein:

[0080] S221 generates a random write address, a random write length, and random write data in each round of random self-test, and writes the random write data to memory based on the random write address and random write length.

[0081] Specifically, a pseudo-random data generation algorithm is used to generate the starting address (i.e., random write address), burst length (i.e., random write length), and data (i.e., random write data) for each memory write. The pseudo-random data generation algorithm can be based on LFSR (Linear Feedback Shift Register) to generate pseudo-random sequences. LFSR is a hardware-friendly pseudo-random number generator that generates periodic pseudo-random sequences from dimensions such as address, burst length, and data through shift registers and feedback logic (XOR operation), thus obtaining random write addresses, random write lengths, and random write data. The characteristics of LFSR are: given an initial seed, the generated sequence is predictable, exhibiting high randomness and low resource consumption, making it suitable for logic module implementation.

[0082] It should be understood that, in order to ensure that the read and write addresses, read and write lengths, and read and write data are consistent in each random read and write test, the modules that generate random write addresses and random read addresses, the modules that generate random write lengths and random read lengths, and the modules that generate random write data and random read data all need to be consistent.

[0083] Since the generation principle of the same type of information is the same in the reading and writing stages, for the sake of simplicity... Figure 4 In this document, the modules for generating random write addresses and random read addresses are uniformly referred to as the "Random Address Generation Module," the modules for generating random write lengths and random read lengths are uniformly referred to as the "Random Length Generation Module," and the modules for generating random write data and random read data are uniformly referred to as the "Random Data Generation Module." In practical use, the information for the random read and write stages can be generated using the same module, or it can be generated using different modules. For example, the random write address generation module generates random write addresses, and the random read address generation module generates random read addresses; the random write length generation module generates random write lengths, and the random read length generation module generates random read lengths; the random write data generation module generates random write data, and the random read data generation module generates random read data.

[0084] like Figure 4 As shown in (a), an address enable signal can be input, causing the random address generation module to output a random address (random write address or random read address) and a random address identifier in the next clock cycle. The address validity signal is confirmed by the random address identifier lasting for one clock cycle. For example, the size of the random address is a preset address size (e.g., 26 bits).

[0085] It should be understood that in each round of random self-testing, the random address generation module generates a random write address or a random read address based on the corresponding characteristic polynomial and the initial random number seed (also referred to as the seed) for this round. For example, the characteristic polynomial can be x^26+x^8+x^7+x^1+x^0, and the initial random number seed for this round can be 0X1b5c396.

[0086] like Figure 4 As shown in (b), a length enable signal can be input, causing the random length generation module to output a random length (random write length or random read length) and a random length identifier in the next clock cycle. The length validity signal is confirmed by the random length identifier lasting for one clock cycle. For example, the size of the random length is a preset length size (e.g., 6 bits).

[0087] In each round of random self-testing, the random length generation module generates a random write length or random read length based on the corresponding characteristic polynomial and the initial random number seed for this round. For example, the characteristic polynomial can be x^6 + x^5 + x^0, and the initial random number seed for this round can be 0x36. For instance, taking a preset length of 6 bits as an example, the random length generation module outputs randomly from 0 to 63 (where 63 is obtained by subtracting 1 from 2 to the power of 6). Therefore, its output result may be 0. To avoid a random write length of 0 (an abnormal situation), 1 can be added to the output result of the random length generation module to obtain the final random write length, ensuring that a situation of reading or writing 0 data points will not occur.

[0088] It should be understood that the maximum amount of data read and written to memory in a single operation may vary in different application scenarios. Therefore, the data bit width of random length (write length / read length) can be adaptively modified to adapt to self-testing in different environments.

[0089] like Figure 4 As shown in (c), a data enable signal can be input, causing the random data generation module to output random data (random write data or random read data) and a random data identifier in the next clock cycle. The data validity signal is confirmed by the random data identifier lasting for one clock cycle. For example, the size of the random write data is a first preset data (e.g., 32 bits).

[0090] In each round of random self-testing, the random data generation module generates random write data or random read data based on the corresponding characteristic polynomial and the initial random number seed for this round. For example, the characteristic polynomial can be x^32+x^22+x^2+x^1+x^0, and the initial random number seed for this round is 0x8E29Cb73.

[0091] In some examples, random write data can be one or more lines of randomly generated memory data. For instance, assuming a random write length Y0 = 1, the random write data could be one line of randomly generated memory data.

[0092] In other examples, due to the large data width of memory, generating one or more rows of memory data would result in an excessively large data volume. Therefore, smaller amounts of random write data can be generated as the data units to be written. Then, multiple random write data are concatenated to form a row of memory data and written into memory. This achieves the purpose of randomly generating data for testing while avoiding the problem of excessive layout and routing pressure on the logic modules due to the large volume of a single generated data.

[0093] Specifically, N identical random write data units can be generated as data units to be written. The size of each data unit is 1 / N of the memory data width, where N > 1 and is an integer. Then, the N data units are concatenated to generate a single row of memory data to be written. In random self-test mode, since a random write length is generated (i.e., the burst length of each read / write test is random), the random write data needs to be written to memory based on the random write length. Specifically, the N random write data units form a random data combination (i.e., a single row of memory data), and the random write length Y0 is greater than or equal to 1. When the random write length Y0 is greater than 1 (i.e., a single read / write test requires writing Y0 rows of data, not 1 row), Y0 random data combinations (i.e., Y0 rows of memory data) are generated. In this read / write test, the Y0 random data combinations are sequentially written to memory based on the random write address (i.e., the randomly generated starting address).

[0094] Taking a 512-bit memory data width as an example, directly generating a single 512-bit line of data would result in an excessively large data volume. Since memory data widths are typically multiples of 32 bits, 16 random data generation modules can be used to generate 16 32-bit data units. Each 32-bit data unit represents a data cell to be written. These 16 32-bit data units are then concatenated to form a single 512-bit line, which is then written to memory. This method of supplying data using combinations of 16 32-bit data units reduces the placement and routing resources required for generating the data, thus alleviating placement and routing pressure. It should be understood that, assuming a random write length Y0 = 2, starting from the random write address, the concatenated 512-bit data is written line by line into memory, for a total of two lines, equivalent to writing two concatenated 512-bit data units into memory.

[0095] S222, generate a random read address and a random read length, and read the first data from memory based on the random read address and random read length; the random read address and the random write address correspond to the same characteristic polynomial and seed, and the random read length and the random write length correspond to the same characteristic polynomial and seed.

[0096] Specifically, a pseudo-random data generation algorithm is used to generate the starting address (i.e., random read address) and burst length (i.e., random read length) for each memory read. Then, data is read from memory based on the random read address and random read length.

[0097] It should be understood that the generated random read address and the random write address in S221 need to be consistent, therefore the same characteristic polynomial and seed must be used. Similarly, the generated random read length and the random write length in S221 need to be consistent, therefore the same characteristic polynomial and seed must be used. The methods and principles for generating random read addresses and random read lengths can be found in [references to be inserted here]. Figure 4 The relevant descriptions of (a) and (b) will not be repeated here.

[0098] S223, compare the randomly written data with the first data to obtain the random self-test result of this round.

[0099] In some examples, after generating random write data, the random write data can be cached, and then retrieved from the cache. The random write data is then compared with the first data read from memory (i.e., the data read from memory based on the random read address and random read length) to obtain the random self-test result for this round.

[0100] In other examples, the random write data corresponds to the first characteristic polynomial and the first seed. In this embodiment, step S223 compares the random write data with the first data, including: generating random data based on the first characteristic polynomial and the first seed; the random data equals the random write data; and comparing the random data with the first data. It should be understood that the data processed by the logic module in each clock cycle is temporary. If random write data is to be cached, the logic module needs to be modified or optimized to cache the random write data. To reduce this processing, in the data comparison stage, the same first characteristic polynomial and the first seed can be used to regenerate random data, which is the same as the random write data. Therefore, the regenerated random data can be compared with the first data to obtain the random self-test result of this round. The generation principle of random read data can be referred to... Figure 4 The relevant description of the random data generation module shown in (c).

[0101] After each round of random self-test is completed (i.e., the result of the random self-test for this round is obtained), steps S221-S223 can be re-executed until the entire target address space has been tested. In this way, the self-test result of the entire target address space can be obtained.

[0102] For example, if the data comparison result shows that the data is consistent, it indicates that the random self-test is normal. If the data comparison result shows that the data is inconsistent, it indicates that the random self-test is abnormal. In the case of an abnormal random self-test result, the abnormal address and abnormal data can be cached as abnormal information. For example, if the comparison is incorrect (i.e., the data is inconsistent), the corresponding address and data are cached so that they can be transmitted to the host computer through the service uplink module for the host computer to make a judgment.

[0103] For ease of understanding, combined with Figure 5 The interaction relationships between modules in the pseudo-random self-test mode are illustrated. For example... Figure 5 As shown, the self-test enable control module sends an enable signal, and the write data control module enables the address and length respectively, so that the corresponding module generates a random write address and a random write length Y0. After obtaining the generated random write length Y0, data enable is performed, so that the random data generation module generates Y0 random write data * 16 and sends a write request. The memory read / write interface responds to the write request, receives the random write address, random write length Y0, and Y0 random write data * 16, and performs memory IP write control. Specifically, during the memory IP write control process, the memory read / write interface sends a write IP interface signal to the memory IP core, and caches the random write address and Y0 random write data * 16 into the first-in-first-out queue (FIFO) corresponding to the memory IP write control process based on the random write length Y0. After receiving the IP ready signal sent by the memory IP core, the memory IP core can write the cached random write address and Y0 random write data * 16 into memory.

[0104] During the data read phase, the data read control module enables the address and length, generates a random read address and random read length, and issues a read request. The memory read / write interface responds to the read request, receives the random read address and random read length, and performs memory IP read control. Specifically, in memory IP read control, the memory read / write interface sends a read IP interface signal to the memory IP core and caches the random read address and random read length in the FIFO queue corresponding to the memory IP read control process. After receiving the IP ready signal from the memory IP core, data can be read from memory through the memory IP core based on the cached random read address and random read length in the FIFO, and the read data is returned. The returned read data is valid as an enable to trigger the generation of random read data (the same as the generated random write data). Then, the generated random read data is compared with the read data obtained from memory. If the comparison fails (i.e., a read / write error), error address caching and error data caching are performed, and error counting control is implemented. Finally, the self-test status, error address, and error data are returned to the self-test enable control module. It can also be cached in the business upstream module for analysis by the host computer.

[0105] To facilitate a clearer understanding of the self-testing process in pseudo-random self-testing mode, the following is combined with... Figure 6 Provide a illustrative explanation. For example... Figure 6 As shown, after receiving the self-test enable command, the self-test process under the pseudo-random self-test model is as follows:

[0106] (1) Enable the random write address generation module and the random write length generation module to generate random write address X0 and random write length Y0.

[0107] (2) Enable the random write data generation module to generate random write data according to the random write length Y0, and generate Y0 random data combinations, each random data combination including N random write data.

[0108] It should be understood that the generated random write data is a data unit to be written. The size of the data unit to be written in each embodiment of this application is 1 / N of the data bit width of the memory, where N > 1 and is an integer. For example, N can be equal to 16.

[0109] (3) Initiate a write request to memory and send a random write address X0, a random write length Y0 and Y0 random data combinations to write Y0 random data combinations into memory according to the random write address X0 and the random write length Y0.

[0110] After the data writing phase is completed, (4) can be executed to trigger the data reading phase.

[0111] (4) Enable the random read address generation module and the random read length generation module to generate random read address X1 and random read length Y1, and start address counting in the data reading phase. It should be understood that X1 = X0, Y1 = Y0.

[0112] (5) Send a read request to memory and send a random read address and random read length to read the corresponding data from memory based on the random read address X1 and the random read length Y1.

[0113] That is, data is read from random read address X1 in memory until the length of the read data is Y1. Therefore, the length of the read data is also Y1, which includes Y1 sub-data, each of which is a row of data in memory.

[0114] (6) After the data read from memory is returned, enable the random read data generation module to generate random read data, and compare the random read data with each row of data in the Y1 row of data read from memory in turn.

[0115] For example, the generated random read data and the data read from memory can be input into the data comparison module for final comparison.

[0116] (7) Determine whether the comparison result of the current line indicates that the read and write are correct. If not, execute (8); if yes, execute (9).

[0117] The current row refers to the row in row Y1 where data comparison is currently being performed. The comparison result of the current row is obtained by comparing the data in the current row with the randomly read data. If the comparison result indicates that the read / write operation is correct, it means that the read / write operation of the current row is error-free and the self-check is normal. If the comparison result indicates that the read / write operation is incorrect, it means that the read / write operation of the current row is incorrect and a bit error has occurred.

[0118] (8) Increase the error count, cache the current address and error data, and continue to compare the next row of data.

[0119] (9) Continue to the next row of data comparison.

[0120] (10) Determine whether the comparison of data in row Y1 is complete.

[0121] If yes, it means that the random self-check of this round has ended, and then execute (11); if no, then take the next line as the new current line and return to execute (7).

[0122] (11) Determine whether the read / write test of the target address space is complete.

[0123] If not, return to execution (1) to enable the random write address generation module and the random write length generation module, regenerate the random write address X0 and the random write length Y0, and perform a new round of random self-checking. If yes, then end.

[0124] It should be understood that when the random read address generation module is enabled, address counting is already started, meaning the number of times an address is generated can be counted. Taking the target address space as the entire memory address space as an example, when the counter reaches 2... 26 When -1 (26 is the memory address width), it indicates that the read and write test of the entire memory address space is complete. At this time, the self-test is considered complete and a self-test completion signal can be output to the outside.

[0125] In some embodiments, if the target self-test mode includes an address line self-test mode, the least significant address line is determined as the current address line to be self-tested; the current address line is enabled to 1 and non-current address lines are set to 0 to determine the current address in memory; after writing the first preset data to the current address, the second data is read from the current address; the first preset data and the second data are compared to obtain the self-test result of the current address line; the next address line shifted to the left is determined as the new current address line; the process returns to enabling the current address line to 1 and setting non-current address lines to 0 to determine the current address in memory and subsequent steps, until all address lines are self-tested.

[0126] It should be understood that the idea behind the address line self-test mode is to enable only one address line as 1 at any given time, while setting the rest of the address lines to 0. This allows for better and faster judgment of address line anomalies.

[0127] like Figure 7 As shown, the address line self-test module receives the enable signal sent by the self-test enable control module for the address line self-test mode, enabling it to write data and generate addresses. Specifically, starting from the least significant address line, the current address line to be self-tested is determined sequentially. Each determined current address line is enabled to 1 (i.e., the bit corresponding to the current address line is set to 1), while non-current address lines (address lines other than the current address line) are set to 0 to determine the current address in memory. Then, a request is made to the memory read / write interface to call the write interface to write the first preset data to the current address. After writing the first preset data, a request is made to the memory read / write interface to call the read interface to read data from the current address (denoted as the second data). The first preset data and the second data are compared to obtain the self-test result of the current address line.

[0128] like Figure 7 As shown, during the data reading phase, the same first preset data can be regenerated using the same generation method as the first preset data written, through the comparison data generation module. The data comparison module then compares the regenerated first preset data with the second data being read. In other examples, referring to the data comparison processing for random data writing, the first preset data generated during the data writing phase can be cached. During the data reading phase, the cached first preset data is compared with the second data, without needing to regenerate the first preset data using the comparison data generation module.

[0129] It should be understood that if the data comparison is inconsistent, it indicates that the current address line self-test is abnormal, such as... Figure 7 As shown, the erroneous address line can be transmitted to the service uplink module, which then transmits it to the host computer. If the data matches, it indicates that the current address line self-test is normal. The address line can then be shifted left based on its address width, and the next address line to be shifted to is determined as the new current address line. The process repeats, enabling the current address line to 1 and setting non-current address lines to 0 to determine the current address in memory and subsequent steps. This process is repeated to perform a self-test on the new current address line until all address lines have completed their self-tests, thus detecting any problems with the corresponding address lines.

[0130] During each data write phase, the write length can be a fixed burst length. For example, a write length of 1 means writing one line of memory data at a time (i.e., the data written occupies one line of memory space). The write length can also be any other fixed length other than 1. Taking a write length of 1 as an example, the first preset data can be one line of memory data. Then, the second data read is also one line of memory data, so the first preset data and the second data can be directly compared. The first preset data can also be a small data unit (also called the data unit to be written), which is formed by concatenating multiple first preset data to form one line of memory data and writing it to the current address. For example, the size of the first preset data can also be 1 / N of the memory data width. Then, N first preset data are concatenated and written to the current address in memory.

[0131] Assuming the memory data width is 512 bits, and the first preset data can be a 32-bit data unit, such as A5A55A5A, then hA5A55A5A...A5A55A5A can be generated, where h represents hexadecimal. hA5A55A5A...A5A55A5A represents a 512-bit data line obtained by concatenating 16 A5A55A5A characters, which can then be written to the current address. During the data reading phase, the second data (i.e., a 512-bit data line) is read from the current address.

[0132] During the data comparison phase, if the first preset data is a data unit to be written (e.g., 32 bits), it can be retrieved from the cache or regenerated. Then, multiple rounds of self-comparison are performed on the second data (one line of memory data, i.e., the actual data read) read from memory. The final output data from these multiple rounds of self-comparison is the same size as the first preset data (also 32 bits). The final output data can then be compared with the first preset data. This method, compared to comparing the entire dataset, allows for more convenient and resource-efficient data comparison. Detailed processing of the multiple rounds of self-comparison is described below.

[0133] In some embodiments, if the target self-test mode includes a data line self-test mode, the least significant data line is determined as the current data line to be self-tested, the current data line is enabled to 1 and the non-current data lines are set to 0, so as to write test data to a specified address in memory; the third data is read from the specified address and compared with the test data to obtain the self-test result of the current data line; the next data line to which it is shifted left is determined as the new current data line, and the process of enabling the current data line to 1 and setting the non-current data lines to 0 to write test data to a specified address in memory and subsequent steps is repeated until all data lines are self-tested.

[0134] The idea behind data line shift self-test is to enable only one data line to 1 at any given time, while setting the rest of the data lines to 0. This allows for better and faster detection of data line anomalies.

[0135] like Figure 8 As shown, upon receiving the enable signal from the self-test enable control module, the data line self-test module can perform data writing and address generation. Specifically, starting from the least significant data line, the current data line to be self-tested is determined sequentially. Each determined current data line is enabled to 1 (i.e., the corresponding bit of the current data line is set to 1), and non-current data lines (other data lines besides the current data line) are set to 0 to generate test data. A request is made to the memory read / write interface to call the write interface to write the test data to the specified memory address. It should be understood that the specified address can be any specified memory address, such as address 0. After writing the test data, a request is made to the memory read / write interface to call the read interface to read data from the current address (denoted as the third data). The test data is compared with the third data to obtain the self-test result of the current data line.

[0136] like Figure 8 As shown, during the data reading phase, the same test data can be regenerated using the same method as the written test data through the comparison data generation module. The data comparison module then compares the regenerated test data with the read third-party data. In other examples, the test data generated during the data writing phase can be cached, and during the data reading phase, the cached test data can be compared with the third-party data.

[0137] It should be understood that if the data comparison is inconsistent, it indicates that the current data line self-test is abnormal, such as... Figure 8 As shown, the faulty data line can be transmitted to the business uplink module, which then transmits it to the host computer. If the data matches, it indicates that the current data line self-test is normal. The data line can then be shifted left based on its bit width, and the next bit shifted to is determined as the new current data line. The process repeats, enabling the current data line to 1 and setting non-current data lines to 0, to write test data and subsequent steps to a specified memory address. This process is repeated to perform a self-test on the new current data line until all data lines have completed their self-tests, thus detecting the problem with the corresponding data line.

[0138] During each data write phase, the write length can be a fixed burst length. For example, the write length can be 1, or it can be any other fixed length other than 1. Taking a write length of 1 as an example, the test data can be a single line of memory data. Then, the third line of memory data read can also be directly compared with the test data. The test data can also be a small data unit (also called a data unit to be written), which is formed by concatenating multiple test data to create a single line of memory data and writing it to the current address. For example, the size of the test data can also be 1 / N of the memory data width. Then, N test data are concatenated and written to the specified address in memory.

[0139] Assuming the memory data width is 512 bits, and the test data can be 32-bit data units, during the write phase, a 512-bit data line is obtained by concatenating 16 test data units, and then written to the current address. During the read phase, the third data (i.e., a 512-bit data line) is read from the current address.

[0140] During the data comparison phase, if the test data is a data unit to be written (e.g., 32 bits), the test data can be retrieved from the cache or regenerated. Then, multiple rounds of self-comparison are performed on the third data read from memory (one line of memory data, i.e., the actual read data). The final output data from these multiple rounds of self-comparison is the same size as the test data (also 32 bits). The final output data can then be compared with the test data. This method, compared to comparing the entire dataset, allows for a more convenient and resource-efficient data comparison. Detailed processing of the multi-round self-comparison is described below.

[0141] In some embodiments, if the target self-test mode includes a step-optimization algorithm self-test mode, then an ascending read-write test is performed on the addresses in the target address space; for each first current address in the ascending read-write test, a read-write test is performed on the first current address based on the address data of the first current address and at least one second preset data; a descending read-write test is performed on the addresses in the target address space, and for each second current address in the descending read-write test, a read-write test is performed on the second current address based on at least one second preset data and the address data of the second current address.

[0142] The second preset data includes consecutive adjacent bits corresponding to high levels and adjacent bits with high-low level transitions. The second preset data can be one or more types. For example, if there are multiple types of second preset data, they can be at least two types, such as 0xFFAA55FF, 0x0055AA00, and 0xCC3333CC. It should be understood that the traditional March algorithm uses address incrementing or decrementing for self-testing, resulting in low coverage. The step-optimized self-testing algorithm in this embodiment adds second preset data to the original March algorithm, improving the coverage of memory self-testing.

[0143] When there are multiple second preset data, one type of second preset data can be used sequentially to perform read / write tests on the first current address or the second current address. For details, please refer to the relevant descriptions in steps (3.1) to (3.4) or (4.1) to (4.4) below. Specifically, the memory self-test processing in the step-optimization algorithm self-test mode includes the following steps:

[0144] (1) The host computer sends the preset delay time (time) to the test. For example, the delay time unit can be us.

[0145] (2) Based on the starting address, traverse the target address space and write the address data of each address in the target address space into this address;

[0146] (3) Ascending order read / write test:

[0147] (3.1) Determine the current address based on the first starting address (i.e., the lowest address), denoted as the first current address. For the first current address, first read data from it, and determine whether the read data is the address data of the first current address to obtain the first self-test result; then write N 0xFFAA55FF (to facilitate differentiation from other second data, it is denoted as the second preset data 1) to the first current address, with a delay of time. The delay time refers to the preset delay duration (e.g., a few milliseconds) to simulate the data retention problem, which is closer to the actual scenario.

[0148] In this example, each type of second preset data is a data unit to be written, the size of which is 1 / N of the memory data width. N second preset data are concatenated to form a row of memory data. For example, if the memory data width is 512 bits and each type of second preset data is 32 bits, then each time a write operation is performed, 16 second preset data are concatenated and written to a row of memory address space. Similarly, the address data written in step (2) can also be a data unit to be written, and N address data are concatenated and written to a row of memory address space.

[0149] (3.2) Read data from the first current address and determine whether the read data is the N 0xFFAA55FF previously written, and obtain the second self-test result; then, write N 0X0055AA00 to the first current address (denoted as the second preset data 2), and delay for time as well;

[0150] (3.3) Read data from the first current address, determine whether the read data is the N 0x0055AA00 written earlier, and obtain the third self-test result; then, write N 0xCC3333CC (referred to as the second preset data 3) to the first current address and delay for time;

[0151] (3.4) Read data from the first current address, determine whether the read data is the N 0xCC3333CC that were written earlier, and obtain the fourth self-test result.

[0152] Thus, after completing the read / write test (i.e., self-test) of the first current address, step (3.5) can be executed. It should be understood that the self-test result of the first current address can be determined comprehensively based on the first to fourth self-test results. For example, if all four self-test results are normal, it indicates that the self-test of the first current address is normal; if any one of the four self-test results is abnormal, it indicates that the self-test of the first current address is abnormal.

[0153] (3.5) Increment the address by 1, increment the self-test length count by 1; execute (3.1) to (3.4); until the self-test length count matches the self-test length.

[0154] Increasing the address by 1 means setting the next address as the new first current address. By executing steps (3.1) to (3.4), read / write tests are performed on the new first current address. Thus, ascending-order read / write tests are performed on each address in the target address space. After performing ascending-order read / write tests on the target address space, step (4) can be executed to perform descending-order read / write tests.

[0155] (4) Descending order read / write test:

[0156] (4.1) Determine the current address based on the second starting address (i.e. the highest address), and denot it as the second current address. For the second current address, first read data from it and determine whether the read data is N second preset data 3: 0xCC3333CC, and obtain the fifth self-test result; then write N second preset data 2: 0X0055AA00 to the second current address, with a delay of time;

[0157] (4.2) Read data from the second current address, determine whether the read data is the N 0X0055AA00 written earlier, and obtain the sixth self-test result; then, write N second preset data 21: 0xFFAA55FF to the second current address, with a delay of time;

[0158] (4.3) Read data from the second current address, determine whether the read data is the N 0xFFAA55FF written earlier, and obtain the seventh self-test result; then write the address data of the second current address into the second current address (i.e., this address), and delay for time;

[0159] (4.4) Read data from the second current address, determine whether the read data is the address data of the second current address, and obtain the eighth self-test result;

[0160] Thus, after completing the read / write test (i.e., self-test) of the second current address, step (4.5) can be executed. It should be understood that the self-test result of the second current address can be determined comprehensively based on the results of the fifth to eighth self-tests mentioned above. For example, if all results of the fifth to eighth self-tests are normal, it indicates that the self-test of the second current address is normal; if any one of the results of the fifth to eighth self-tests is abnormal, it indicates that the self-test of the second current address is abnormal.

[0161] (4.5) Decrement the address by 1 and increment the self-test length count by 1; execute (4.1) to (4.4); until the self-test length count matches the self-test length;

[0162] It should be understood that decrementing the address by 1 means setting the next address as the new first current address. By executing steps (4.1) to (4.4), read and write tests are performed on the new first current address. In this way, descending read and write tests are performed on each address in the target address space. By executing the above steps, the read and write tests of the entire target address space can be completed.

[0163] like Figure 9 As shown, after the self-test enable control module determines that the target self-test mode is the step optimization algorithm self-test mode, it sends an enable signal to the step optimization algorithm self-test module, causing it to perform the relevant processing in the data writing stage. It should be understood that each time the first current address or the second current address is determined in steps (2) to (4) above, the following steps will be executed: Figure 9 In the write address generation process, each time data is written, write data generation processing is performed, and a request is made to the memory read / write interface to call the write interface in order to write the generated write data into memory.

[0164] In steps (2) to (4), each time the data read is compared with the previously written data (i.e., the data written), the comparison can be performed by... Figure 9The comparison data generation module regenerates the data, and the data comparison module compares the regenerated data with the data read from memory to see if they are consistent. In other examples, data written during the write phase can also be cached instead of being regenerated.

[0165] During the data comparison phase, if the cached or regenerated data (such as the second preset data or address data) is a small data unit to be written (e.g., 32 bits), multiple rounds of self-comparison can be performed on the data read from memory (referred to as the actual read data). The size of the data output from these multiple rounds of self-comparison is the same as the size of the data regenerated this time (e.g., both are 32 bits). Then, the final output data can be compared with the regenerated data. Detailed processing of the multiple rounds of self-comparison is described below. It should be understood that each time a data comparison is performed, if there is a discrepancy, the erroneous address and erroneous data are cached as exception information, waiting for the host computer to read them through the service uplink module.

[0166] In some embodiments, the random write length (random burst length for each write) corresponding to the pseudo-random self-test mode is Y0, and the corresponding random read length is Y1, where Y0 = Y1. The read and write lengths for each self-test mode other than the pseudo-random self-test mode are all 1. Each self-test mode other than the pseudo-random self-test mode generates N data units to be written, which are then concatenated to form a row of memory data and written to memory. See the previous text for a detailed description. The pseudo-random self-test mode generates Y0 random data combinations, each containing N data units to be written. The size of the data units to be written generated in each self-test mode is 1 / N of the memory's data bit width. In the pseudo-random self-test mode, the actual data read for random write data comparison is the first data, which includes Y1 sub-data, each of which is a row of data in memory.

[0167] As mentioned earlier, for each self-test mode, during the data comparison phase after reading data from memory, the data unit to be written can be compared with the corresponding data actually read from memory. During this comparison, the target data can be determined. Specifically, in the pseudo-random self-test mode, each sub-data unit is identified as the target data; in self-test modes other than pseudo-random self-test mode, the target data is the actually read data (i.e., a row of data in memory). Therefore, for any self-test mode, the target data is the row of data actually read from memory.

[0168] The data comparison module can divide the target data into N data blocks on average to obtain the dataset to be processed. It compares two adjacent data blocks in the dataset. If they are the same, one data block is retained. If they are different, a data block of the same size but different from the data unit to be written is generated, and the corresponding two adjacent data blocks are replaced with the newly generated data block to obtain the updated dataset. The same data block in the dataset is not compared repeatedly. For the updated dataset, the module returns to compare two adjacent data blocks in the dataset and the subsequent steps until only the last data block remains in the dataset. The last data block is compared with the data unit to be written.

[0169] like Figure 10 As shown, taking a memory data width of 512 bits as an example, during the data reading stage, a data unit identical to the data unit to be written can be regenerated, denoted as R0 (32 bits). After reading data from memory, the target data is determined based on the read data. The target data is a row of 512-bit data stored in memory. Therefore, the 512-bit target data can be split into 16 32-bit data blocks (denoted as d0~d15, each data block of d0~d15 is 32 bits), forming a dataset. Then, multiple rounds of self-comparison are performed based on the dataset, and the data in each round of self-comparison is denoted as D0. Specifically, in the first round of self-comparison, D′ is used. 16The identifier D0 indicates that there are 16 32-bit data blocks in this round of self-comparison. Adjacent data blocks can be compared, for example, d0 is compared with d1, d2 with d3, d4 with d5, and so on, up to d14 with d15. If the comparison is the same, one data block is retained. For example, if d0 and d1 are the same, only d0 is retained, thus turning two 32-bit data blocks into one 32-bit data block. If the comparison is different (for example, d2 and d3 are inconsistent), a new 32-bit data block that is inconsistent with data unit R0 is generated, and the two adjacent 32-bit data blocks that were inconsistent with the comparison are replaced with the newly generated 32-bit data block (i.e., d2 and d3 are replaced). In this way, after one round of self-comparison, the original 16 32-bit data blocks are reduced to 8 32-bit data blocks. Then, a second round of self-comparison is performed. D′8 is used to denote D0, indicating that there are a total of 8 32-bit data blocks in this round of self-comparison. Adjacent data blocks are compared among these 8 blocks. Similarly, if they match, one block is retained; if they differ, a new 32-bit data block, different from data unit R0, is generated to replace the two inconsistent 32-bit data blocks. After the second round of self-comparison, 4 32-bit data blocks will be output. This process is iterated until only one 32-bit data block is output, indicated by D′1, which is the final D0. Then, the remaining 32 bits of D0 are compared with data unit R0. If the comparison fails, an error flag is output; if the comparison succeeds, the self-check is normal.

[0170] For the pseudo-random self-test mode, in each round of random self-testing, during the data comparison phase after reading data from memory, one (i.e., one row) of sub-data from the actual read data (i.e., the first data) can be compared with the randomly written data using the aforementioned multi-round self-comparison method. Then, the next sub-data from the first data (i.e., the next row of data) can be compared with the randomly written data again using the aforementioned multi-round self-comparison method, until all Y1 sub-data have been compared, thus obtaining the result of this round of random self-testing. If the read / write test of the target address space is not completed, the next round of random self-testing begins.

[0171] The above scheme uses a serial pairwise self-comparison method, which can reduce the direct comparison of large-width data and reduce resource utilization.

[0172] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0173] Based on the same inventive concept, this application also provides a memory self-testing device for implementing the memory self-testing method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more memory self-testing device embodiments provided below can be found in the limitations of the memory self-testing method described above, and will not be repeated here.

[0174] In one embodiment, a memory self-test device (not shown in the figure) is provided, the device comprising:

[0175] The self-test mode determination module is used to respond to the self-test enable command issued to the memory and determine the target self-test mode.

[0176] The random self-test module is used to perform multiple rounds of random self-tests on the target address space of memory if the target self-test mode includes a pseudo-random self-test mode.

[0177] In each round of random self-testing, the random self-testing module is also used to generate random write addresses, random write lengths, and random write data, and write the random write data to memory based on the random write addresses and random write lengths; generate random read addresses and random read lengths, and read the first data from memory based on the random read addresses and random read lengths; the random read addresses and random write addresses correspond to the same characteristic polynomials and seeds, and the random read lengths and random write lengths correspond to the same characteristic polynomials and seeds; compare the random write data with the first data to obtain the random self-testing result for this round.

[0178] In one embodiment, a memory self-test device (not shown in the figure) is provided, the device comprising:

[0179] The self-test mode determination module is used to determine the current test scenario;

[0180] Determine the target self-test mode that matches the current test scenario; the target self-test mode includes the pseudo-random algorithm self-test mode; the pseudo-random algorithm self-test mode is used to instruct the logic module to perform multiple rounds of random self-tests on the target address space of memory. In each round of random self-tests, random write addresses, random write lengths and random write data are generated for random read and write tests.

[0181] The self-test enable module is used to generate and issue self-test enable instructions for memory based on the target self-test mode.

[0182] Each module in the aforementioned memory self-test device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the electronic device in hardware form or independent of it, or stored in the memory of the electronic device in software form, so that the processor can call and execute the operations corresponding to each module.

[0183] In one embodiment, an electronic device is provided, which may be a logic module or a host computer, and its internal structure diagram may be as follows: Figure 11 As shown, this electronic device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a memory self-test method.

[0184] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0185] In one embodiment, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the embodiments of the present application.

[0186] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the embodiments of this application.

[0187] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the embodiments of this application.

[0188] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited thereto.

[0189] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0190] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A memory self-test method, comprising: The method comprises: in response to a self-checking enabling instruction issued for the memory, determining a target self-checking mode; if the target self-checking mode comprises a pseudo-random self-checking mode, performing a plurality of rounds of random self-checking on a target address space of the memory; each round of the random self-checking comprises: generating a random write address, a random write length and random write data, and writing the random write data into the memory based on the random write address and the random write length; generating a random read address and a random read length, and reading first data from the memory based on the random read address and the random read length; the random read address corresponds to the same characteristic polynomial and seed as the random write address, and the random read length corresponds to the same characteristic polynomial and seed as the random write length; comparing the random write data with the first data to obtain a random self-checking result of the round.

2. The method of claim 1, wherein, The random write data corresponds to a first characteristic polynomial and a first seed; the comparison of the random write data with the first data comprises: generating random data based on the first characteristic polynomial and the first seed; the random data is equal to the random write data; comparing the random data with the first data.

3. The method of claim 1, wherein, The method further comprises: if the target self-checking mode comprises an address line self-checking mode, determining a lowest bit address line as a current address line to be self-checked; enabling the current address line as 1 and setting non-current address lines as 0 to determine a current address in the memory, writing first preset data into the current address, reading second data from the current address, comparing the first preset data with the second data to obtain a self-checking result of the current address line; determining a next bit address line shifted to the left as a new current address line, and returning to execute the enabling of the current address line as 1 and the setting of non-current address lines as 0 to determine a current address in the memory and subsequent steps until all address lines are self-checked.

4. The method of claim 1, wherein, The method further comprises: if the target self-checking mode comprises a data line self-checking mode, determining a lowest bit data line as a current data line to be self-checked, enabling the current data line as 1 and setting non-current data lines as 0 to write test data into a specified address of the memory; reading third data from the specified address, and comparing the third data with the test data to obtain a self-checking result of the current data line; determining a next bit data line shifted to the left as a new current data line, and returning to execute the enabling of the current data line as 1 and the setting of non-current data lines as 0 to write test data into a specified address of the memory and subsequent steps until all data lines are self-checked.

5. The method of claim 1, wherein, The method further comprises: if the target self-checking mode comprises a step optimization algorithm self-checking mode, The addresses in the target address space are tested in ascending order, and for each first current address in the ascending read-write test, the first current address is tested in turn based on the address data of the first current address and at least one second preset data, wherein the second preset data has adjacent bit positions with continuous corresponding high levels and adjacent bit positions with high-low level transitions; The addresses in the target address space are tested in descending order, and for each second current address in the descending read-write test, the second current address is tested in turn based on the at least one second preset data and the address data of the second current address.

6. The method of claim 1, wherein, The random write length is Y0, the random read length is Y1, the write length corresponding to each self-test mode except the pseudo-random self-test mode is 1, and the size of the data unit to be written generated under different self-test modes is 1 / N of the data bit width of the memory, N>1 and is an integer; In the pseudo-random self-test mode, the data unit to be written is the random write data, Y0 random data combinations are written in the memory, each random data combination includes N random write data, and the actual read data for data comparison with the random write data is the first data, including Y1 sub-data, each sub-data being a row of data in the memory; And / or, In the address line self-test mode, the data unit to be written is the first preset data, N first preset data are written in the memory, and the actual read data for data comparison with the first preset data is the second data; And / or, In the data line self-test mode, the data unit to be written is the test data, N test data are written in the memory, and the actual read data for data comparison with the test data is the third data.

7. The method of claim 6, wherein, The process of comparing the data unit to be written with the corresponding actual read data includes: Determining target data; wherein in the pseudo-random self-test mode, each sub-data is determined as target data; in self-test modes other than the pseudo-random self-test mode, the target data is the actual read data; The target data is evenly split into N data blocks to obtain a data set to be processed; If the adjacent two data blocks in the data set are the same, one data block is retained, if they are different, a data block of the same size and different from the data unit to be written is generated, the corresponding adjacent two data blocks are replaced with the newly generated data block, and an updated data set is obtained; wherein the same data block in the data set is not repeatedly compared; For the updated data set, the comparison of the adjacent two data blocks in the data set and the subsequent steps are returned to be executed until only the last data block exists in the data set; The last data block is compared with the data unit to be written.

8. The method according to any one of claims 1 to 7, characterized in that, The target self-check mode is parsed from the self-check enabling instruction, and a specified self-check start address and a self-check length are parsed from the self-check enabling instruction; and the target address space is an address space specified for detection based on the self-check start address and the self-check length.

9. A memory self-test method, comprising: The method comprises: determining a current test scenario; determining a target self-check mode matching the current test scenario; the target self-check mode comprises a pseudo-random algorithm self-check mode; the pseudo-random algorithm self-check mode is used to instruct a logic module to perform multiple rounds of random self-checks on a target address space of a memory, and in each round of random self-check, a random write address, a random write length and random write data are generated for random read-write testing; generating a self-check enabling instruction for the memory according to the target self-check mode; issuing the self-check enabling instruction.

10. The method of claim 9, wherein, The method further comprises: in response to a self-check space specifying operation, determining a specified self-check start address and a self-check length; the generating of the self-check enabling instruction for the memory according to the target self-check mode comprises: generating the self-check enabling instruction according to the target self-check mode, the self-check start address and the self-check length.

11. The method according to claim 9 or 10, characterized in that, The target self-check mode is a single self-check mode or a combination of multiple self-check modes; in initial use of a board card, the target self-check mode comprises an address line self-check mode and / or a data line self-check mode; and / or, in an initialization stage or a power-on stage of the board card, the target self-check mode comprises a step optimization algorithm self-check mode; and / or, in a memory stress testing stage of the board card, the target self-check mode comprises the pseudo-random self-check mode; and / or, in a unit test stage of the board card, the target self-check mode comprises the address line self-check mode and the data line self-check mode; and / or, in a full self-check stage of the board card, the target self-check mode comprises an address line self-check mode, a data line self-check mode, a step optimization algorithm self-check mode and a pseudo-random self-check mode.

12. A memory self-test device, comprising: The apparatus comprises: a self-check mode determination module configured to determine a target self-check mode in response to a self-check enabling instruction issued for a memory; a random self-check module configured to perform multiple rounds of random self-checks on a target address space of a memory if the target self-check mode comprises a pseudo-random self-check mode; wherein in each round of the random self-check, the random self-check module is further configured to generate a random write address, a random write length and random write data, and write the random write data into the memory based on the random write address and the random write length; generate a random read address and a random read length, and read first data from the memory based on the random read address and the random read length; the random read address corresponds to the same characteristic polynomial and seed as the random write address, and the random read length corresponds to the same characteristic polynomial and seed as the random write length; and perform data comparison between the random write data and the first data to obtain a random self-check result of the round.

13. A memory self-test device, comprising: The apparatus comprises: a self-check mode determination module configured to determine a current test scenario; determining a target self-check mode matching the current test scenario; the target self-check mode comprises a pseudo-random algorithm self-check mode; the pseudo-random algorithm self-check mode is used to instruct a logic module to perform multi-round random self-check on a target address space of the memory, in each round of random self-check, a random write address, a random write length and random write data are generated for random read-write test; a self-check enabling module configured to generate a self-check enabling instruction for the memory according to the target self-check mode; and issue the self-check enabling instruction.

14. An electronic device, comprising: A computer readable storage medium storing a computer program, comprising a memory and a processor, wherein the memory stores the computer program, and the processor executes the computer program to implement the steps of the method in any one of claims 1 to 8 or 9 to 11.

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