Cache control system and cache control method

Abstract

The application discloses a cache control system and a cache control method, and relates to the technical field of memories.The cache control system adopts the characteristics of low latency and low energy consumption of a volatile cache module to realize high-performance cache of read and write data.On the basis of the volatile cache module, a dirty queue module for recording the addresses of dirty cache lines in the volatile cache module is introduced, and a counter for recording the number of dirty cache lines of the dirty queue module and a waterline threshold is configured to dynamically monitor the cache state, and then the dynamic adjustment of the cache state of the passive computing device is carried out according to the number of dirty cache lines and the waterline threshold, so that the high-performance cache in the high-performance mode is met, the non-volatile memory does not need to be accessed, and the asynchronous write-back operation is concurrently executed after the number of dirty cache lines reaches the waterline threshold, so that the cache of read and write data can be continuously realized, and the cached read and write data can be written back to the non-volatile memory in a non-blocking manner.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a cache control system and cache control method. Background Technology

[0002] Passive computing devices harvest energy from environmental sources for power. Due to the instability of these sources, passive computing devices often experience intermittent power shortages, leading to computational interruptions. To ensure continuous computation, the processors and memory components used in passive computing devices typically retain data even when power is lost; these are known as non-volatile processors (NVPs) and non-volatile memory (NVMs). However, NVMs suffer from high access latency and high power consumption, limiting the overall performance of the device.

[0003] In related technologies, a caching component can be introduced between the processor and memory to allow some read and write operations to be performed in the cache, thereby reducing the number of accesses to the NVM. Caching components typically use traditional volatile or non-volatile cache devices. If a traditional volatile cache device is used, a write pass-through strategy is required, still necessitating access to the NVM. Non-volatile cache devices themselves present performance issues when used as caches. Therefore, reducing access latency and energy consumption, and improving the overall performance of the device, are urgent technical problems to be solved. Summary of the Invention

[0004] This application provides a cache control system and a cache control method to at least solve the problems in related technologies of how to reduce access latency and access energy consumption and improve the overall performance of the device.

[0005] This application provides a cache control system, including:

[0006] A volatile cache module is connected to both a non-volatile processor and non-volatile memory. The volatile cache module is used to cache read and write data in the non-volatile processor. The volatile cache module includes a dirty queue module and a counting module. The dirty queue module is used to record the address of dirty cache lines in the volatile cache module. The counting module is connected to the dirty queue module and is used to record the number of dirty cache lines and the waterline threshold of the dirty queue module.

[0007] The control module is connected to the volatile cache module;

[0008] The control module is configured as follows:

[0009] When the number of dirty cache lines is less than the waterline threshold, the volatile cache module is controlled to receive and cache read and write data from the non-volatile processor.

[0010] When the number of dirty cache lines reaches or exceeds the waterline threshold, the volatile cache module is controlled to perform concurrent operations; wherein, the concurrent operations include: receiving and caching read and write data from the non-volatile processor, and writing the read and write data corresponding to at least one dirty cache line recorded in the dirty queue module back to the non-volatile memory.

[0011] This application also provides a cache control method, including:

[0012] Obtain the number of dirty cache lines and the waterline threshold of the dirty queue module in the volatile cache module; wherein, the dirty queue module is used to record the address of the dirty cache line corresponding to the read and write data cached in the volatile cache module;

[0013] When the number of dirty cache lines is less than the waterline threshold, the volatile cache module is controlled to receive and cache read and write data from the non-volatile processor.

[0014] When the number of dirty cache lines reaches or exceeds the waterline threshold, the volatile cache module is controlled to perform concurrent operations; wherein, the concurrent operations include: receiving and caching read and write data from the non-volatile processor, and writing the read and write data corresponding to at least one dirty cache line recorded in the dirty queue module back to the non-volatile memory.

[0015] This application describes a cache control system that utilizes the low latency and low power consumption characteristics of volatile cache modules to achieve high-performance read / write data caching. Based on the volatile cache module, a dirty queue module is introduced to record the addresses of dirty cache lines in the volatile cache module. A counter is configured to record the number of dirty cache lines and the waterline threshold of the dirty queue module, dynamically monitoring the cache status. This allows for dynamic adjustment of the passive computing device's cache status based on the number of dirty cache lines and the waterline threshold, achieving high-performance caching in high-performance mode without accessing non-volatile memory. Furthermore, once the number of dirty cache lines reaches the waterline threshold, asynchronous write-back operations are performed concurrently. This not only continues to cache read / write data but also enables non-blocking write-back of cached read / write data to non-volatile memory, reducing access latency and power consumption, and effectively improving the overall performance of the passive computing device. Attached Figure Description

[0016] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1This is a schematic diagram of a caching architecture provided in an embodiment of this application;

[0018] Figure 2 Schematic diagram of the cache control system provided in the embodiments of this application Figure 1 ;

[0019] Figure 3 Schematic diagram of the cache control system provided in the embodiments of this application Figure 2 ;

[0020] Figure 4 A schematic diagram illustrating the stack space occupancy status at different stages of program execution, provided for embodiments of this application;

[0021] Figure 5 A flowchart illustrating the cache control method provided in an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of the structure of the cache control device provided in the embodiments of this application;

[0023] Figure 7 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0025] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0026] Passive computing devices are computing devices that do not have battery power, instead harvesting energy from environmental sources such as radio frequency, sunlight, or wireless LANs. However, due to the instability of these environmental sources, passive computing devices often experience intermittent power shortages, leading to computational interruptions. To ensure continuous computation, the processors and memory components used in passive computing devices typically retain data even when power is lost; these are known as NVP and NVM. However, NVM suffers from high access latency and high power consumption, limiting the overall performance of the device. To address this, a caching component is introduced between the processor and memory, leveraging the locality of access principle to allow some read and write operations to be performed in the cache, thereby reducing the number of accesses to the NVM.

[0027] In related technologies, caching components are mostly implemented based on traditional SRAM or non-volatile caching devices. In one related technology, the caching component uses SRAM, which loses data upon power failure. To avoid computational errors caused by data loss, the cache must employ a write-through strategy, meaning each data write operation must write to both the cache and memory to prevent data loss. This approach still requires accessing the NVM for each write operation, resulting in minimal performance improvement. In another related technology, the caching component uses non-volatile devices, ensuring data retention even after power failure. This cache can employ a write-back strategy, where write operations are first performed in the cache without immediate writing to memory. Data is only written back to memory when it is replaced from the cache, reducing memory write operations. However, this non-volatile cache has higher access latency and higher energy consumption compared to traditional caches, offering limited performance improvement. In another related technology, the cache component is constructed using a hybrid of SRAM and non-volatile devices. Read and write operations primarily access the SRAM. When power is low, an immediate checkpointing mechanism is employed, storing the modified content in the SRAM onto the non-volatile device; this modified content is referred to as dirty data. Using this hybrid approach, to ensure the feasibility of the immediate checkpointing mechanism, the hardware must reserve sufficient power to write all data in the SRAM to the non-volatile device. In extreme cases, all data in the SRAM could potentially be dirty data, which to some extent limits the system's energy efficiency and performance, reserving more energy for data transfer rather than computation. Therefore, reducing access latency and energy consumption, and improving the overall performance of the device, are urgent technical problems that need to be solved.

[0028] To address the aforementioned issues, the cache control system and method provided in this application employ a volatile cache module to achieve high-performance data caching for reading and writing, resulting in a simple hardware structure. A dirty queue module is introduced to record the addresses of dirty cache lines in the volatile cache module. A counter is configured to record the number of dirty cache lines and the waterline threshold of the dirty queue module, dynamically monitoring the cache status and dynamically adjusting the cache status of the passive computing device based on the number of dirty cache lines and the waterline threshold, thereby optimizing the performance of the passive computing device.

[0029] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] This section describes the specific application environment architecture or hardware architecture upon which the execution of the cache control system and cache control method depends. (References) Figure 1 , Figure 1 This is a schematic diagram of a caching architecture provided in an embodiment of this application. This caching architecture is part of the caching control system. The caching control system and caching control method in this embodiment of the application rely on... Figure 1 The caching architecture implementation in [the context of the application]. For example... Figure 1 As shown, the cache architecture provided in this application embodiment includes a non-volatile processor 11, a volatile cache module 12, and a non-volatile memory 13. Figure 1 The arrows in the diagram indicate the direction of signal and data transmission.

[0031] Optionally, the non-volatile processor 11 includes a conventional register 110 and a non-volatile flip-flop 112.

[0032] Optionally, the volatile cache module 12 is used to cache read and write data in the non-volatile processor 11. The volatile cache module 12 includes SRAM and caches the read and write data in the non-volatile processor 11 into the SRAM of the volatile cache module 12.

[0033] Optionally, the volatile cache module 12 also includes a dirty queue module 121 and a counting module 122.

[0034] Here, the dirty queue module 121 is used to manage the dirty queue DirtyQueue. Each item in the dirty queue records the address of the dirty cache line contained in the SRAM of the volatile cache module 12.

[0035] The counting module 122 here may include multiple counters, which enable dynamic monitoring and management of the cache status of passive computing devices.

[0036] Figure 2Schematic diagram of the cache control system provided in the embodiments of this application Figure 1 ,like Figure 2 As shown, the cache control system provided in this application embodiment includes:

[0037] The volatile cache module 12 is connected to the non-volatile processor 11 and the non-volatile memory 13 respectively. The volatile cache module 12 is used to cache read and write data in the non-volatile processor 11.

[0038] The volatile cache module 12 includes a dirty queue module 121 and a counting module 122. The dirty queue module 121 is used to record the address of the dirty cache line in the volatile cache module 12. The counting module 122 is connected to the dirty queue module 121 and is used to record the number of dirty cache lines and the waterline threshold of the dirty queue module 121.

[0039] The control module 21 is connected to the volatile cache module 12.

[0040] The control module 21 is configured to: when the number of dirty cache lines is less than the waterline threshold, control the volatile cache module 12 to receive and cache read and write data from the non-volatile processor 11; when the number of dirty cache lines reaches or exceeds the waterline threshold, control the volatile cache module 12 to perform concurrent operations; wherein the concurrent operations include: receiving and caching read and write data from the non-volatile processor 11, and writing the read and write data corresponding to at least one dirty cache line recorded in the dirty queue module 121 back to the non-volatile memory 13.

[0041] The read / write data refers to the read / write data in the non-volatile processor 11, which is stored in the cache device of the volatile cache module 12 during the caching process. This cache device can be SRAM.

[0042] Dirty data refers to data that has been modified in the cache device of volatile cache module 12, but the modified version has not yet been written back to non-volatile memory 13. This data needs to be written back to non-volatile memory 13 before volatile cache module 12 loses power.

[0043] A dirty data line refers to the smallest cache unit that stores dirty data. The cache is organized and managed by lines, and a line usually contains multiple bytes with consecutive addresses. When any byte of data in a cache line becomes "dirty", the entire cache line is marked as a "dirty cache line". When the control module 21 performs asynchronous write-back or checkpoint backup, it writes the data back to non-volatile memory 13 based on the addresses in the dirty queue, in units of the entire cache line.

[0044] The cache control system provided in this application adopts the low latency and low power consumption characteristics of volatile cache modules to achieve high-performance read and write data caching. Based on the volatile cache module, a dirty queue module is introduced to record the addresses of dirty cache lines in the volatile cache module, and a counter is configured to record the number of dirty cache lines and the waterline threshold of the dirty queue module. The cache status is dynamically monitored, and the cache status of the passive computing device is dynamically adjusted according to the number of dirty cache lines and the waterline threshold. This satisfies the high-performance caching in high-performance mode without accessing non-volatile memory. After the number of dirty cache lines reaches the waterline threshold, asynchronous write-back operations are performed concurrently. This not only enables continued read and write data caching, but also allows the cached read and write data to be written back to non-volatile memory in a non-blocking manner, reducing access latency and access power consumption, and effectively improving the overall performance of the passive computing device.

[0045] In one possible implementation, the cache control system further includes a priority configuration module; the priority configuration module is connected to the volatile cache module 12 and the control module 21 respectively; the priority configuration module is used to add priority to the read and write data corresponding to the dirty cache line according to the priority characteristics of the read and write data corresponding to the dirty cache line in the volatile cache module 12; accordingly, the control module 21 is configured to: when performing the operation of writing back the read and write data corresponding to at least one dirty cache line recorded in the dirty queue module 121 to non-volatile memory, determine the write-back order of the dirty cache lines according to the priority.

[0046] In this embodiment, the dirty data in the dirty queue module 121 is configured with priorities. The priority configuration module marks the priority of dirty data according to a certain strategy, and the control module 21 determines the write-back order accordingly. For example, priority is given to writing back dirty data that is least likely to be used recently, while hot dirty data is kept in the cache for as long as possible. The priority configuration reduces the situation where useful data is squeezed out due to unreasonable write-back order, increases the resident ratio of effective data in the cache, and thus improves the cache hit rate and overall access performance. In passive devices, power failure is a random event. If the dirty data write-back order is improper, critical data may not have been backed up before the power failure. The priority strategy can be designed to prioritize writing back data that is critical to system consistency or difficult to regenerate. When a checkpoint is triggered due to insufficient energy, or when a power failure occurs during asynchronous write-back, the system prioritizes the protection of the most important data, reduces the degree of data loss in the worst case, and enhances the reliability and data security of the system.

[0047] In one possible implementation, priority characteristics include the time it enters the dirty queue and / or the number of times data is written back to non-volatile memory.

[0048] Optionally, priority can be configured using a first-in-first-out (FIFO) or last-in-first-out (LIFO) strategy. Alternatively, priority can be configured based on the number of times data is written back to non-volatile memory, dynamically identifying the active datasets in the current stage to achieve more granular cache management based on flexible and ever-changing user needs.

[0049] In one possible implementation, the counting module 122 includes a first counter (dirtyline) and a second counter (waterline). The first counter is connected to the dirty queue module and is used to record the number of dirty cache lines in the dirty queue module. The second counter is connected to the control module and is used to configure and / or update the recorded waterline threshold according to the waterline threshold configuration instruction and / or waterline threshold update instruction issued by the control module.

[0050] The first counter, dirtyline, records the number of dirty cache lines contained in the cache at the current moment.

[0051] The second counter, waterline, records a waterline threshold used to control the behavior of the caching system.

[0052] It is understood that the waterline threshold here can be determined according to the actual situation, and this application embodiment does not impose specific restrictions on it.

[0053] Specifically, when the dirty line is less than the waterline, the cache control system adopts a write-back strategy, writing data to the cache first, rather than immediately writing it to memory, to reduce memory write operations. When the dirty line is greater than or equal to the waterline, the cache system still adopts the write-back strategy, but this time, the cache system initiates asynchronous write-back operations. Asynchronous write-back operations are based on information recorded in the dirty queue. When non-volatile memory is idle, the corresponding dirty cache lines are written back to non-volatile memory one by one to avoid data loss in case of power failure, until the dirty line equals the waterline. Note that the asynchronous write-back operation only writes back the dirty cache line data in SRAM; it does not invalidate the cache line state, but only changes the cache line state from dirty to clean, while simultaneously decrementing the dirty line by 1. It is called asynchronous because during the write-back operation, program instructions can continue to execute without blocking, effectively improving program execution performance.

[0054] Optionally, it also includes a checkpoint triggering module; the checkpoint triggering module is connected to the control module, and the checkpoint triggering module is used to detect the voltage of the passive computing device corresponding to the cache control system, and after the voltage is less than the backup voltage threshold, it sends a checkpoint triggering signal to the control module; accordingly, the control module is also configured to: in response to the checkpoint triggering signal, write back the read and write data corresponding to all dirty cache lines recorded in the dirty queue module to non-volatile memory.

[0055] It is understood that the backup voltage threshold here can be determined according to the actual situation, and this application embodiment does not impose specific restrictions on it.

[0056] The counting module is also used to record the maximum dirty cache line count threshold; the maximum dirty cache line count threshold is greater than the waterline threshold; correspondingly, the control module is also configured to block the volatile cache module from receiving and caching read and write data from the non-volatile processor when the number of dirty cache lines is greater than the maximum dirty cache line count threshold.

[0057] Optionally, the counting module 122 here includes a third counter, maxline, which records a maximum dirty cache line count threshold, representing the maximum number of dirty cache lines that the cache can contain, which is less than or equal to the capacity of the dirty queue. When dirtyline equals maxline, subsequent write operations will be blocked until dirtyline is less than maxline, at which point the blocked write operations can continue to execute.

[0058] It is understood that the maximum number of dirty cache lines threshold here can be determined according to the actual situation, and this application embodiment does not impose specific restrictions on it.

[0059] By configuring the maximum number of dirty cache lines, the number of dirty cache lines can be limited to a preset range. This setting limits the upper limit of backup energy required by the checkpointing mechanism. Specifically, when the device voltage drops to the backup voltage threshold, the checkpointing mechanism is triggered to perform data backup. Based on the information recorded in the dirty queue, all corresponding dirty cache lines are written back to non-volatile memory, and the maxline and waterline are backed up. Therefore, the upper limit of the number of dirty cache lines written back is determined by the maxline, thus clearly limiting the upper limit of backup energy required by the checkpointing mechanism. This is lower than the energy required to back up the entire cache in related technologies, reducing the upper limit of dirty data that the system may accumulate at any time, thereby limiting the peak energy required for checkpoint backup in the worst case. This ensures that even under energy constraints, the system still has enough reserved energy to complete critical data backups, avoiding computational interruptions and data loss due to insufficient energy, effectively improving energy efficiency, and enhancing data stability and security.

[0060] Optionally, the backup voltage threshold can be dynamically adjusted based on the maximum dirty cache line count threshold to adapt to and meet different cache requirements, thereby improving the energy efficiency and computing efficiency of passive computing devices.

[0061] In one possible implementation, the counting module 122 includes a first counter, a second counter, and a third counter; wherein, the first counter is connected to the dirty queue module and is used to record the number of dirty cache lines in the dirty queue module; the second counter is connected to the control module 21 and is used to configure and / or update the recorded waterline threshold according to the waterline threshold configuration instruction and / or waterline threshold update instruction issued by the control module 21; the third counter is connected to the control module 21 and is used to configure and / or update the recorded maximum number of dirty cache lines threshold according to the dirty queue number threshold configuration instruction and / or dirty queue number threshold update instruction issued by the control module 21.

[0062] In one possible implementation, the control module 21 is further configured to: monitor the runtime status parameters of the cache control system; and dynamically generate at least one of the following based on the runtime status parameters: waterline threshold configuration instruction, waterline threshold update instruction, dirty queue number threshold configuration instruction, and dirty queue number threshold update instruction; wherein the runtime status parameters include at least one of the following: the program memory access mode of the non-volatile processor, the energy harvesting status and remaining energy level of the passive computing device, and the access latency and historical energy consumption statistics of the non-volatile memory.

[0063] By using the above methods, the waterline threshold and the maximum dirty cache line count threshold can be flexibly adjusted based on the monitoring of non-volatile memory access latency and historical energy consumption statistics. This allows asynchronous write-backs to be performed earlier and more smoothly, avoiding the triggering of intensive, high-energy-consuming batch write-backs in the later stages. It also allows for flexible control of the energy peak required for checkpoint backups in the worst-case scenario, thereby improving energy efficiency.

[0064] Optionally, Figure 3 Schematic diagram of the cache control system provided in the embodiments of this application Figure 2 ,like Figure 3 As shown, in Figure 2 Based on this, the cache control system provided in this application embodiment also includes a non-volatile processor 11.

[0065] Specifically, the non-volatile processor 11 is connected to the volatile cache module 12 and the control module 21 respectively; the non-volatile processor 11 is used to record the stack pointer information of the read and write data corresponding to the dirty cache line.

[0066] Accordingly, the control module 21 is also configured to: determine invalid data in the read / write data corresponding to the dirty cache line based on the stack pointer information; and skip invalid data when performing the operation of writing the read / write data corresponding to at least one dirty cache line recorded in the dirty queue module back to non-volatile memory.

[0067] In one possible implementation, the non-volatile processor includes a stack base register, a stack pointer register, and a lowest stack pointer register. For example... Figure 3As shown, the conventional registers 110 in the non-volatile processor 11 include a stack base address register 1101 and a stack pointer register 1102. Optionally, the non-volatile processor 11 also includes a lowest stack pointer register 1103. Optionally, Figure 3 For illustrative purposes only, the lowest stack pointer register 1103 can be configured inside or outside the conventional register 110.

[0068] Stack base address register 1101 is the raw stack base address register (BP) in the non-volatile processor 11, used to point to the stack base address of the stack space corresponding to the read / write data of the dirty cache line. Stack pointer register 1102 is the raw stack pointer register (SP) in the non-volatile processor 11, used to point to the stack pointer of the stack space corresponding to the read / write data of the dirty cache line. Based on the above, a lowest stack pointer register 1103 is added. The lowest stack pointer register 1103 is also called... This is the lowest address value in the stack space that points to the read / write data corresponding to the dirty cache line.

[0069] Accordingly, the control module 21 is specifically configured to: determine the currently active stack space based on the stack base address and the stack pointer; determine the released stack space based on the lowest address value of the stack space and the stack pointer; determine the read / write data of the dirty cache line located in the currently active stack space as valid data; and determine the read / write data of the dirty cache line located in the released stack space as invalid data.

[0070] In one possible implementation, a register is added to the non-volatile processor 11. The stack pointer register is used to record the lowest address reached since the last checkpoint. During program execution, a stack space exists to store data temporarily used during function execution; this data is no longer used after the function execution ends. The processor includes two registers defining this stack space: the stack base address register 1101 points to the high address of the stack space, and the stack pointer register 1102 points to the low address of the stack space. The stack space grows from high address to low address, and the stack space is expanded by decreasing the value of the stack pointer register 1102 each time a function is called.

[0071] like Figure 4 As shown, Figure 4This illustration shows the stack space occupancy status at different stages of program execution, as provided in this application embodiment. After each function call, the stack space used by the function is released by increasing the value of the stack pointer register 1102, while the lowest stack pointer register 1103 records the lowest value reached by the stack pointer register 1102 during the function call. Therefore, the address range between the lowest stack pointer register 1103 and the stack pointer register 1102 represents the released stack space, and the data it points to will not be used again.

[0072] Optionally, when the cache control system performs a replacement operation, if the cache line to be replaced is dirty and its address falls within the specified range, the system may choose to replace it. Within a certain range, there is no need to write back to non-volatile memory; the data can be discarded directly, reducing the number of write operations to non-volatile memory and improving energy efficiency.

[0073] Optionally, when performing asynchronous write-back operations and checkpointing mechanisms, and when writing back dirty data in SRAM based on the dirty queue, if the address of the dirty queue entry falls within... Within the specified range, there is no need to write back to non-volatile memory, further reducing the number of write operations to non-volatile memory and improving energy efficiency.

[0074] In some possible implementations, to ensure that the lowest stack pointer register 1103 records the lowest address reached by the stack pointer register 1102 since the last checkpoint, the changed stack pointer register value is compared each time the stack pointer register 1102 changes. and ,like Less than Then update for .

[0075] In some possible implementations, in order to ensure that the lowest stack pointer register 1103 correctly tracks the stack pointer register 1102, each time the checkpoint mechanism is executed, after completing the write-back of dirty data to the volatile cache module 12, the value of the lowest stack pointer register 1103 is not backed up, only the value of the stack pointer register 1102 is backed up, and when resuming execution from the checkpoint, the value of the lowest stack pointer register 1103 is set to the backed-up value of the stack pointer register 1102.

[0076] Figure 5 This is a flowchart illustrating the cache control method provided in this application embodiment. The execution entity of the cache control method provided in this application embodiment can be the aforementioned control module 21, such as... Figure 5 As shown, embodiments of this application provide a cache control method, which is described in detail below:

[0077] 501. Obtain the number of dirty cache lines and waterline threshold of the dirty queue module in the volatile cache module.

[0078] The dirty queue module is used to record the addresses of dirty cache lines corresponding to read and write data cached in the volatile cache module.

[0079] Optionally, the waterline threshold can be determined according to the actual situation. It can be a waterline threshold that is received by the user through the input / output device, or a waterline threshold that is dynamically determined according to the cache state of the passive computing device.

[0080] 502. When the number of dirty cache lines is less than the waterline threshold, the volatile cache module is controlled to receive and cache read and write data from the non-volatile processor.

[0081] 503. When the number of dirty cache lines reaches or exceeds the waterline threshold, control the volatile cache module to perform concurrent operations.

[0082] The concurrent operations include: receiving and caching read and write data from the non-volatile processor, and writing the read and write data corresponding to at least one dirty cache line recorded in the dirty queue module back to the non-volatile memory.

[0083] The cache control method provided in this application realizes intelligent switching and asynchronous optimization of cache write strategy by dynamically comparing the number of dirty cache lines with the waterline threshold. Specifically, when the amount of dirty data is lower than the threshold, the system adopts a pure write-back strategy, so that all write operations are completed only in the high-speed volatile cache, thereby significantly reducing data access latency and improving the processor's computing efficiency. Once the amount of dirty data reaches the threshold, the system maintains the front-end write performance while intelligently starting the background asynchronous write-back process, writing the historical data in the dirty queue back to non-volatile memory in batches and non-blocking, thereby improving the device's computing performance.

[0084] Optionally, in step S501, the maximum dirty cache line count threshold is also obtained. Accordingly, step S503 is: when the number of dirty cache lines reaches or exceeds the waterline threshold but is less than the maximum dirty cache line count threshold, the volatile cache module is controlled to perform concurrent operations.

[0085] The maximum dirty cache line count threshold represents the maximum number of dirty cache lines that the cache can contain. It is less than or equal to the capacity of the dirty queue. When the number of dirty cache lines equals the maximum dirty cache line count threshold, subsequent write operations will be blocked until the number of dirty cache lines is less than the maximum dirty cache line count threshold, at which point the blocked write operations can continue to execute.

[0086] This mechanism not only effectively reduces the frequency and energy consumption of accessing slow non-volatile memory, but also sets a safety boundary for dirty data accumulation through threshold control, making the backup energy requirements of the system under worst-case conditions deterministic and controllable. This method achieves synergistic optimization of low latency, low energy consumption, and high reliability, significantly improving the overall performance and energy utilization efficiency of passive computing devices in intermittent power supply environments.

[0087] Optionally, after step S503, this embodiment of the application further configures checkpoint data backup. Specifically, when the device voltage drops to the backup voltage threshold, the checkpoint mechanism is triggered to perform data backup. Based on the information recorded in the dirty queue, all corresponding dirty cache lines are written back to non-volatile memory, and the maximum dirty cache line count threshold and the waterline threshold are backed up. Therefore, the upper limit of the number of dirty cache lines written back is determined by the maximum dirty cache line count threshold, clearly limiting the upper limit of the backup energy required by the checkpoint mechanism, which is far lower than the energy required to back up the entire cache in previous schemes, effectively improving energy efficiency. The checkpoint mechanism's data backup ensures data security and reliability.

[0088] Optionally, for non-volatile processors, an additional register is added to record the lowest address reached by the stack pointer register since the last checkpoint. During program execution, a stack space exists to store data temporarily used during function execution; this data is no longer used after the function execution ends. The processor includes two registers defining this stack space: a stack base register pointing to a high address within the stack space, and a stack pointer register pointing to a low address. The stack space grows from high to low addresses, and is expanded by decreasing the value of the stack pointer register each time a function is called.

[0089] It should be noted that the functions that the above-mentioned cache control system can achieve are all applicable to the cache control method in the embodiments of this application, and will not be elaborated here.

[0090] Referring to the above embodiment of the cache control system, optionally, when the cache control system performs a replacement operation, if the cache line to be replaced is dirty and its address falls within... Within a certain range, there is no need to write back to non-volatile memory; the data can be discarded directly, reducing the number of write operations to non-volatile memory and improving energy efficiency.

[0091] Optionally, when performing asynchronous write-back operations and checkpointing mechanisms, and when writing back dirty data in SRAM based on the dirty queue, if the address of the dirty queue entry falls within... Within the specified range, there is no need to write back to non-volatile memory, further reducing the number of write operations to non-volatile memory and improving energy efficiency.

[0092] To more clearly illustrate the technical solutions of the embodiments of this application, the technical details of the embodiments of this application are now described in conjunction with specific examples. Assume that the execution state of a passive computing device at a certain moment is as follows: The address is 0x3000, SP is 0x4000, the maximum dirty cache line count threshold is 5, the waterline threshold is 3, the dirty cache line count is 2, and the dirty queue contains 2 entries with addresses 0x3240 and 0x100 respectively. The status of the dirty queue address information display box is shown in Table 1.

[0093] Table 1. Status Indicator of the Dirty Queue Address Information Display Box

[0094]

[0095] The subsequent sequence of operations is to write data to address 0x200 and add two registers (the stack pointer register and the stack base register).

[0096] A write operation is performed on address 0x200. Because the current number of dirty cache lines is less than the waterline threshold, a write-back strategy is executed. The write operation occurs in the cache and does not need to be written to non-volatile memory. After the write operation is complete, address 0x200 is added to the dirty queue, and the number of dirty cache lines is updated to 3. The status of the address information display box in the dirty queue is shown in Table 2, which is:

[0097] Table 2. Status 2 Diagram of the Address Information Display Box for the Dirty Queue

[0098]

[0099] A write operation is performed on address 0x300. Since the current number of dirty cache lines equals the waterline threshold, the write-back strategy continues, adding address 0x300 to the dirty queue and updating the dirty cache line count to 4. Simultaneously, an asynchronous write-back operation is initiated. The status 3 of the address information display box for the dirty queue is shown in Table 3, as follows:

[0100] Table 3. Status Diagram of the Dirty Queue Address Information Display Box

[0101]

[0102] Perform an addition operation on the original register. Simultaneously, perform a write-back operation on the cache line corresponding to 0x3240, since 0x3240 is in... Since the cache line is within the specified range, there's no need to write back to non-volatile memory; simply change the cache line status corresponding to 0x3240 to a clean state. Simultaneously, update the dirty cache line count to 3. The addition and write-back operations can be performed in parallel, which improves program performance. The status of the dirty queue address information display box is shown in Table 4, as follows:

[0103] Table 4. Status Diagram of the Dirty Queue Address Information Display Box

[0104]

[0105] A write operation is performed on address 0x240. Since the current number of dirty cache lines equals the waterline threshold, the write-back strategy continues, adding address 0x240 to the dirty queue and updating the dirty cache line count to 4. Simultaneously, an asynchronous write-back operation is initiated. The status 5 of the dirty queue address information display box is shown in Table 5, which is:

[0106] Table 5. Status Diagram of the Dirty Queue Address Information Display Box

[0107]

[0108] A write operation is performed on address 0x340. Because the number of dirty cache lines is greater than the waterline threshold but less than the maximum dirty cache line count threshold, the write-back policy continues, adding address 0x340 to the dirty queue and updating the dirty cache line count to 5. Assume the non-volatile memory bus is busy, and the asynchronous write-back operation is not executed immediately. The status of the address information display box in the dirty queue is shown in Table 6, as follows:

[0109] Table 6. Status Diagram of the Dirty Queue Address Information Display Box

[0110]

[0111] A write operation was attempted at address 0x500, but was blocked and paused because the number of dirty cache lines equaled the maximum dirty cache line threshold. Simultaneously, an asynchronous write-back operation was performed on the cache line corresponding to 0x100, since 0x100 was not currently in a state of readiness. Since the data is within the specified range, it needs to be written back to non-volatile memory, and the status of the cache lines and the number of dirty cache lines should be updated to 4. The status of the dirty queue address information display box is shown in Table 7, which is:

[0112] Table 7. Status Diagram of the Dirty Queue Address Information Display Box

[0113]

[0114] The previously blocked write operation at 0x500 will continue.

[0115] Through the above scheme, the embodiments of this application can not only utilize the low latency and low power consumption characteristics of traditional cache devices, but also improve execution performance by using write-back strategies. Furthermore, by setting a maximum dirty cache line number threshold to limit the upper limit of backup energy required by the checkpoint mechanism, energy efficiency is effectively improved compared to related technologies that require backup of the entire cache. Finally, by combining the tracking of the program stack space, the number of write operations to non-volatile memory is further reduced, thereby further improving computing performance.

[0116] For a description of the features in the embodiment corresponding to the cache control method, please refer to the relevant description of the embodiment corresponding to the cache control device, which will not be repeated here.

[0117] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0118] Figure 6 This is a schematic diagram of the structure of the cache control device provided in an embodiment of this application. Figure 6 As shown, embodiments of this application also provide a cache control device 60, including:

[0119] The acquisition module 601 is used to acquire the number of dirty cache lines and the waterline threshold of the dirty queue module in the volatile cache module; wherein, the dirty queue module is used to record the address of the dirty cache line corresponding to the read and write data cached in the volatile cache module;

[0120] The first control module 602 is used to control the volatile cache module to receive and cache read and write data from the non-volatile processor when the number of dirty cache lines is less than the waterline threshold.

[0121] The second control module 603 is used to control the volatile cache module to perform concurrent operations when the number of dirty cache lines reaches or exceeds the waterline threshold; wherein the concurrent operations include: receiving and caching read and write data from the non-volatile processor, and writing the read and write data corresponding to at least one dirty cache line recorded in the dirty queue module back to the non-volatile memory.

[0122] For a description of the features in the embodiment corresponding to the cache control device, please refer to the relevant description of the embodiment corresponding to the cache control method, which will not be repeated here.

[0123] Figure 7 A schematic diagram of the structure of the electronic device provided in this application. Figure 7As shown, the electronic device 70 provided in this embodiment includes at least one processor 701 and a memory 702. Optionally, the electronic device 70 further includes a communication component 703. The processor 701, memory 702, and communication component 703 are connected via a bus.

[0124] In a specific implementation, at least one processor 701 executes computer execution instructions stored in memory 702, causing at least one processor 701 to execute the above-described cache control method embodiment.

[0125] The specific implementation process of processor 701 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0126] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0127] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0128] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0129] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described cache control method embodiments at runtime.

[0130] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0131] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described cache control method embodiments.

[0132] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described cache control method embodiments.

[0133] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0134] The cache control method provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A cache control system for passive computing devices, characterized in that, include: A volatile cache module is connected to both the non-volatile processor and non-volatile memory. The volatile cache module is used to cache read and write data in the non-volatile processor. The volatile cache module includes a dirty queue module and a counting module. The dirty queue module records the addresses of dirty cache lines in the volatile cache module. The counting module is connected to the dirty queue module and records the number of dirty cache lines and a waterline threshold. The counting module also records a maximum dirty cache line count threshold. The maximum dirty cache line count threshold is greater than the waterline threshold and less than or equal to the dirty queue capacity. The control module is connected to the volatile cache module; A checkpoint triggering module is connected to the control module. The checkpoint triggering module is used to detect the voltage of the passive computing device corresponding to the cache control system, and to send a checkpoint triggering signal to the control module after the voltage is less than the backup voltage threshold. The control module is configured as follows: When the number of dirty cache lines is less than the waterline threshold, the volatile cache module is controlled to receive and cache read and write data from the non-volatile processor. When the number of dirty cache lines reaches or exceeds the waterline threshold, but is less than the maximum number of dirty cache lines threshold, the volatile cache module is controlled to perform concurrent operations; wherein, the concurrent operations include: receiving and caching read and write data from the non-volatile processor, and writing the read and write data corresponding to at least one dirty cache line recorded in the dirty queue module back to the non-volatile memory; When the number of dirty cache lines exceeds the maximum dirty cache line number threshold, the volatile cache module is blocked from receiving and caching read and write data from the non-volatile processor. The control module is also configured to: In response to the checkpoint trigger signal, all read and write data corresponding to dirty cache lines recorded in the dirty queue module are written back to the non-volatile memory.

2. The cache control system for passive computing devices according to claim 1, characterized in that, The counting module includes a first counter, a second counter, and a third counter; wherein, The first counter is connected to the dirty queue module and is used to record the number of dirty cache lines in the dirty queue module; The second counter is connected to the control module and is used to configure and / or update the recorded waterline threshold according to the waterline threshold configuration instruction and / or waterline threshold update instruction issued by the control module. The third counter is connected to the control module and configures and / or updates the maximum number of dirty cache lines recorded according to the dirty queue number threshold configuration instruction and / or dirty queue number threshold update instruction issued by the control module.

3. The cache control system for passive computing devices according to claim 2, characterized in that, The control module is also configured to: Monitor the runtime status parameters of the cache control system; Based on the runtime state parameters, at least one of the following is dynamically generated: the waterline threshold configuration instruction, the waterline threshold update instruction, the dirty queue number threshold configuration instruction, and the dirty queue number threshold update instruction; The runtime state parameters include at least one of the following: the program memory access mode of the non-volatile processor, the energy harvesting status and remaining energy level of the passive computing device, and the access latency and historical energy consumption statistics of the non-volatile memory.

4. The cache control system for passive computing devices according to any one of claims 1 to 3, characterized in that, It also includes a non-volatile processor, which is connected to the volatile cache module and the control module respectively; The non-volatile processor is used to record the stack pointer information of the read and write data corresponding to the dirty cache line; Accordingly, the control module is also configured to: Based on the stack pointer information, determine the invalid data in the read / write data corresponding to the dirty cache line; When performing the operation of writing the read / write data corresponding to at least one dirty cache line recorded in the dirty queue module back to the non-volatile memory, the invalid data is skipped.

5. The cache control system for passive computing devices according to claim 4, characterized in that, The non-volatile processor includes a stack base address register, a stack pointer register, and a lowest stack pointer register; The stack base address register is used to point to the stack base address of the stack space corresponding to the read / write data of the dirty cache line; The stack pointer register is used to point to the stack pointer of the stack space corresponding to the read / write data of the dirty cache line; The lowest stack pointer register is used to point to the lowest address value of the stack space for the read / write data corresponding to the dirty cache line; Accordingly, the control module is specifically configured as follows: The currently active stack space is determined based on the stack base address and the stack pointer; Based on the lowest address value of the stack space and the stack pointer, determine that the stack space has been released; The read / write data whose address is located in the currently active stack space of the dirty cache line is determined as valid data; Read / write data whose addresses are located in the freed stack space are determined to be invalid data.

6. The cache control system for passive computing devices according to any one of claims 1 to 3, characterized in that, It also includes a priority configuration module; The priority configuration module is connected to both the volatile cache module and the control module. The priority configuration module is used to add priority to the read and write data corresponding to the dirty cache line according to the priority characteristics of the read and write data corresponding to the dirty cache line in the volatile cache module; Accordingly, the control module is configured as follows: When performing the operation of writing back the read / write data corresponding to at least one dirty cache line recorded in the dirty queue module to the non-volatile memory, the write-back order of the dirty cache lines is determined according to the priority.

7. The cache control system for passive computing devices according to claim 6, characterized in that, The priority characteristics include the time it enters the dirty queue and / or the number of times data is written back to the non-volatile memory.

8. A cache control method applied to a passive computing device, characterized in that, include: Obtain the number of dirty cache lines and the waterline threshold of the dirty queue module in the volatile cache module; wherein, the dirty queue module is used to record the address of the dirty cache line corresponding to the read and write data cached in the volatile cache module; Obtain the maximum dirty cache line count threshold; the maximum dirty cache line count threshold is greater than the waterline threshold and less than or equal to the dirty queue capacity. When the number of dirty cache lines is less than the waterline threshold, the volatile cache module is controlled to receive and cache read and write data from the non-volatile processor. When the number of dirty cache lines reaches or exceeds the waterline threshold, but is less than the maximum number of dirty cache lines threshold, the volatile cache module is controlled to perform concurrent operations; wherein, the concurrent operations include: receiving and caching read and write data from the non-volatile processor, and writing the read and write data corresponding to at least one dirty cache line recorded in the dirty queue module back to the non-volatile memory; When the number of dirty cache lines exceeds the maximum dirty cache line number threshold, the volatile cache module is blocked from receiving and caching read and write data from the non-volatile processor. The method further includes: detecting the voltage of the passive computing device corresponding to the cache control system, and writing the read and write data corresponding to all dirty cache lines recorded in the dirty queue module back to the non-volatile memory after the voltage is less than the backup voltage threshold.

Images