Data processing method and electronic equipment

Abstract

The invention discloses a data processing method and electronic equipment, relates to the technical field of computers, and aims to realize hot data preliminary screening through performance data, refine access features by compressing a heat map, dynamically update a heat score, and realize dynamic classification and hierarchical storage of data by comparing a target threshold with the heat score. According to the method and the device, the distribution of the data between the DRAM and the CXL memory is completed, and the technical effects of accurately identifying the hot data and optimizing the storage position are achieved on the premise of ensuring low overhead, so that the overall performance of the system is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to a data processing method and an electronic device. Background Technology

[0002] Driven by digital transformation, modern computer systems face the dual challenges of exponential data growth and continuously increasing computational workload complexity, placing higher performance and capacity demands on storage systems. CXL (Compute Express Link) technology, with its cache coherence, low-latency interconnect, and memory pooling capabilities, has become a key technology for building heterogeneous memory architectures, effectively expanding memory capacity and improving resource utilization. However, CXL memory access latency is significantly higher than native DRAM (Dynamic Random Access Memory). If frequently accessed hot data is not identified and migrated to the high-speed storage layer in a timely manner, it will severely impact system performance. Summary of the Invention

[0003] This application provides a data processing method and an electronic device to at least solve the problem in the related art that hot data is not identified and migrated to high-speed storage in a timely manner, affecting system performance.

[0004] This application provides a data processing method, including:

[0005] Receive access events for the target memory and obtain the corresponding performance data for the access events. The target memory supports interconnect protocols.

[0006] If the performance data meets the set filtering conditions, obtain the heatmap data of the target memory.

[0007] Calculate the heat score of the target data to be operated on based on the heat map metadata;

[0008] The target data type is determined by comparing the target threshold and the popularity score. The target threshold is determined based on the node identifier of the non-uniform memory access node.

[0009] When the data type is hot data, the target data is migrated from the target memory data area to the hot data area. The access latency of the hot data area is less than that of the target memory data area.

[0010] This application also provides a data processing apparatus, including:

[0011] The receiving unit is used to receive access events to the target memory and obtain the performance data corresponding to the access events, wherein the target memory supports interconnection protocols;

[0012] The receiving unit is used to acquire heatmap data of the target memory when the performance data meets the set filtering conditions.

[0013] The calculation receiving unit is used to calculate the heat score of the target data to be operated on in the access event based on the heat map metadata.

[0014] A determination unit is used to compare the target threshold and the heat score to determine the data type of the target data, wherein the target threshold is determined based on the node identifier of the non-uniform memory access node;

[0015] The migration unit is used to migrate target data from the target memory corresponding data area to the hot data area when the data type is hot data. The access latency of the hot data area is less than that of the target memory corresponding data area.

[0016] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above data processing methods.

[0017] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described data processing methods.

[0018] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described data processing methods.

[0019] This application provides a data processing method that performs initial screening of hot data using performance data, refines access features by compressing heatmaps, dynamically updates heat scores, and achieves dynamic classification and hierarchical storage of data by comparing target thresholds and heat scores. It also completes the allocation of data between DRAM and CXL memory, achieving the technical effect of accurately identifying hot data and optimizing storage location while ensuring low overhead, thereby improving the overall system performance. Attached Figure Description

[0020] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0022] Figure 2A flowchart illustrating an overall data processing method provided in this application embodiment;

[0023] Figure 3 A flowchart illustrating the implementation of a distributed heat meter according to an embodiment of this application;

[0024] Figure 4 A flowchart illustrating the implementation of a NUMA-aware hierarchical system as provided in this application embodiment;

[0025] Figure 5 This is a flowchart illustrating the implementation of a migration strategy provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0027] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] The specific application environment architecture or specific hardware architecture on which the execution of the data processing method depends is described here.

[0030] Before providing a detailed explanation of this application, the technical terms involved will be explained first.

[0031] CPU (Central Processing Unit): The "brain" of a computer, the core hardware unit responsible for executing program instructions, processing data, and controlling the coordinated operation of various computer components.

[0032] CXL (Compute Express Link): A high-speed, cache-consistent interconnect protocol used to connect CPUs with memory expansion devices, accelerators, etc., aiming to reduce latency, increase bandwidth, and achieve unified management of heterogeneous memory resources.

[0033] CHMU (CXL Hot-Page Monitoring Unit): A hardware or firmware module designed specifically for CXL memory to monitor and identify frequently accessed hot memory pages in real time, providing a basis for data migration and performance optimization.

[0034] PMU (Performance Monitoring Unit): A hardware module built into the CPU used to collect low-level performance events, such as cache misses, instruction execution counts, and memory access counts. It is commonly used for performance analysis and tuning.

[0035] NUMA (Non-Uniform Memory Access): In multiprocessor systems, different CPUs access different locations, resulting in inconsistent memory latency. Local memory access is fast, while remote memory access is slow, requiring software optimization of data distribution.

[0036] DRAM (Dynamic Random Access Memory): The main type of computer main memory. It is fast, volatile (data is lost when power is off), and needs to be refreshed periodically. It is widely used for running programs and temporary data storage.

[0037] With the widespread adoption of CXL technology, heterogeneous memory systems (e.g., DRAM + CXL memory) have become the mainstream architecture for improving system performance. However, CXL memory exhibits a significant difference in access latency compared to traditional DRAM (approximately 2-3 times), which means that if hot data is not migrated to the high-speed storage layer in a timely manner, it will severely impact system throughput. Based on this, related technologies employ the following methods:

[0038] (1) Memory controller integrated monitoring unit

[0039] Memory controllers typically integrate hardware counters to track access frequency at the granular level of cache lines or pages.

[0040] (2) Performance monitoring unit (PMU) sampling

[0041] By capturing last-level cache miss events using the CPU's PMU, memory access hotspots can be indirectly inferred.

[0042] (3) Device-side hardware awareness (CHMU)

[0043] As a core component of the CXL 3.2 standard, the CHMU implements page-level access tracking through a hardware counter and supports automatic migration to DRAM.

[0044] However, the shortcomings of the relevant technology are:

[0045] (1) The hardware cost of the integrated monitoring unit of the memory controller is high. Among them, the counter array occupies 12%-15% of the chip area, which increases the cost of the memory module by 20%. There is also an energy efficiency bottleneck. The power consumption of the continuously activated counter increases by 15%-20% in the idle state, which affects the battery life, especially in mobile scenarios.

[0046] (2) The sampling frequency of the performance monitoring unit is limited. To control overhead, the PMU usually samples at a low frequency (e.g., 100Hz), resulting in a hotspot identification delay of up to 10ms under dynamic load. There is also a problem of poor cross-platform compatibility. The PMU interfaces and event definitions of different CPU manufacturers are significantly different, requiring customized adaptation code.

[0047] (3) There are differences in the implementation of hardware awareness on the device side among vendors. Different vendors have different error handling (e.g., poison data marking) and data cleanup mechanisms for CHMU, resulting in incompatibility of cross-device migration strategies. It is also limited by coarse granularity, only supporting page-level monitoring and unable to identify cache row-level hotspots, which may lead to a 5%-10% performance loss in tree-structured data structures.

[0048] To address the aforementioned technical problems, embodiments of this application provide a data processing method. Taking advantage of the heterogeneous characteristics of CXL memory (higher latency but larger capacity compared to DRAM), a three-level processing flow is designed, from hardware filtering to software statistics, ultimately achieving dynamic data classification and hierarchical storage. While ensuring low overhead, it accurately identifies hot data and optimizes storage locations, thereby improving overall system performance. The following embodiments, combined with the execution flow of the data processing method, provide a detailed description of the method.

[0049] Figure 1 A flowchart illustrating a data processing method provided in this application embodiment specifically includes, as follows: Figure 1 The following steps are shown:

[0050] S101. Receive access events for the target memory and obtain the performance data corresponding to the access events.

[0051] The target memory supports high-speed interconnect protocols.

[0052] Understandably, target memory refers to CXL memory, specifically memory devices connected to the host system via the CXL protocol, such as CXL memory expansion cards and CXL memory pool devices. An access event refers to an event where the target device, target program, or target CPU accesses CXL memory, such as a read or write operation. Specifically, it refers to a specific read, write, or instruction fetch operation initiated by the CPU or device to a target memory address. The target memory address stores target data or is used to store target data. Instruction fetch is the first basic operation when the CPU executes a program; it refers to the process where the CPU reads the next machine instruction to be executed from memory (or cache) and sends it to the instruction pipeline for subsequent processing (such as decoding and execution). Simultaneously with detecting an access event, performance data related to that access event is collected. Performance data refers to performance metrics related to that access event, used to analyze efficiency, latency, and resource usage, such as latency, access type, address, and the CPU that initiated the access.

[0053] The performance data includes at least one of the following: cache read hit count, access latency period, and bandwidth utilization.

[0054] Understandably, the CXL3.0 Performance Monitoring Unit (PMU) captures three key events to obtain performance data. These three key events include: counting cache read hits on the CXL device (CXL memory) (e.g., via the `cxl.cache_read_hits` command line) to identify frequently accessed cache lines; measuring memory access latency cycles (e.g., via the `cxl.mem_latency_cycles` command line) to mark access events with latency below a threshold (e.g., 100 ns) as potential hotspots; and monitoring bandwidth utilization (e.g., via the `cxl.bandwidth_util` command line) to mark channels with utilization exceeding 70% as high-load areas. The performance data includes cache read hit counts, access latency cycles, and bandwidth utilization. Access events can be quickly filtered using the CXL device's built-in hardware monitoring unit (such as the CHMU or PMU).

[0055] Optionally, after obtaining the performance data corresponding to the access event, the method also includes:

[0056] Determine whether the number of cache read hits is greater than the first preset threshold, whether the access latency period is less than the second preset threshold, and whether the bandwidth utilization is greater than the third preset threshold; if the number of cache read hits is greater than the first preset threshold, the access latency period is less than the second preset threshold, or the bandwidth utilization is greater than the third preset threshold, then determine that the performance data meets the set filtering conditions.

[0057] Understandably, a hardware filtering mechanism, or first-layer processing, is set up to quickly filter access events using hardware counters, marking data that meets the set filtering criteria as potential hot data. These criteria include a cache read hit count greater than a first preset threshold, an access latency period less than a second preset threshold, and bandwidth utilization greater than a third preset threshold. For example, the first preset threshold might be 10 times / second, the second 100ns, and the third 70%. If the cache read hit count > 10 times / second, the memory access latency < 100ns, or the bandwidth utilization > 70%, then the performance data meets the set filtering criteria, and the target data for the access event is considered potential hot data or high-probability hot data. Subsequently, the high-probability hot data is processed in the second layer. Low-probability data is directly routed to the CXL cold data area, avoiding unnecessary software overhead. The first-layer hardware-level filtering can directly exclude invalid data (e.g., temporary data accessed only once), reducing the pressure on subsequent processing.

[0058] S102. If the performance data meets the set filtering conditions, obtain the heat map data of the target memory.

[0059] Understandably, based on the above S101, if the performance data meets the preset filtering conditions, the heatmap metadata is obtained. The heatmap is used to update the hot data statistics or trigger migration decisions. The heatmap metadata is a set of structured, computable, and memory-stored metadata, usually stored in the local DRAM of each NUMA node (low-latency access), and is updated and maintained by the local hot data monitoring unit (e.g., CHMU, kernel module, PMU driver).

[0060] The heatmap metadata is an N-byte metadata structure, and the heatmap is distributed according to non-uniform memory access nodes. The metadata structure includes an access timestamp in the first byte, a heat score in the second byte, and an access permission identifier in the third byte. The total number of bytes in the first, second, and third bytes is N. The access timestamp is used to record the last access time, and the access permission identifier includes a read permission identifier, a write permission identifier, and a read-write permission identifier.

[0061] Understandably, the heatmap metadata is a compressed heatmap maintained in local memory, aggregated in units of pages (e.g., 4KB). Each 4KB page corresponds to a 12-byte metadata structure, where N can be 12 or a multiple of 12. Each 12-byte metadata structure for a 4KB page includes an access timestamp, a heat score, and access permission flags. For example, `struct cxl_heatmap{uint64_t timestamp; uint24_t heat_score; uint8_t access_flags;}`, where `timestamp` is an 8-byte access timestamp (millisecond precision), recording the last access time and used to calculate the access interval; in this case, the first byte is 8. `heat_score` is the core heat index (i.e., a 3-byte heat score), stored using a 24-bit unsigned integer to balance precision and space, with a dynamic range of 0-16777215; in this case, the second byte is 3. The access_flags are used to record read and write permissions and support the differentiation of different types of access operations. For example, access permissions can be marked by R / W / X bits, where R represents the read permission flag, W represents the write permission flag, and X represents the read and write permission flag. In this case, the third byte is 1, and the total number of bytes of the first, second, and third bytes is 12.

[0062] Understandably, this compressed heatmap metadata structure achieves two advantages. First, it compresses storage, with metadata overhead of 12 bytes / page being only 1 / 5 of that of related solutions (e.g., 64 bytes / page). Second, it adopts a distributed layout, with the heatmap distributed across NUMA nodes, reducing cross-node access latency. For example, in a 4-socket system, each node only needs to maintain a local copy of the heatmap.

[0063] S103. Calculate the heat score of the target data to be operated on by the access event based on the heat map data.

[0064] Understandably, based on the above S102, the current heat score is updated using an exponential decay model with coefficient compensation according to the heat map data, obtaining the actual / dynamic heat score of the target data, thus realizing fine-grained heat calculation and tracking of the potential hot data selected in the first layer. Understandably, S102 and S103 constitute the second layer of calculation. This layer achieves efficient and low-overhead memory hotspot identification by maintaining a lightweight compressed heat map and an exponential decay algorithm, providing a decision-making basis for the third layer of data classification and hierarchical storage. The specific calculation method is described in detail in the following embodiments.

[0065] Optionally, calculate the popularity score of the target data to be operated on by the access event based on the heatmap metadata, including:

[0066] The heat map data is updated with a heat score based on a pre-set decay factor, access coefficient compensation, and access weight of the access event. This yields the heat score of the target data to be processed by the access event. The decay factor controls the rate at which access is forgotten, the access coefficient compensation amplifies the access weight, and the access weight is determined based on the access type of the access event.

[0067] Understandably, the heat score in the heat map data is updated according to the pre-set attenuation factor, access coefficient compensation, and access weight of the access event, as shown in formula (1). The attenuation factor controls the rate at which historical accesses are forgotten; a larger attenuation factor allows the system to adapt to load changes more quickly. Since the CXL memory access latency is 2-3 times that of DRAM, the weight of CXL accesses can be amplified by β to ensure fairness in cross-media heat assessment. The access weight can be dynamically adjusted according to the access type; for example, the access weight for a read operation is 1, for a write operation is 2, and for an instruction fetch operation is 3. After updating the heat score, a timestamp and access identifier can be recorded and output to the third layer for data classification and hierarchical storage.

[0068] new_score=old_score×(1-α)+access_weight×β Formula (1)

[0069] In the formula, new_score is the dynamic popularity score, old_score is the current popularity score, α is the decay factor, β is the CXL access coefficient compensation, and access_weight is the access weight. For example, α = 0.2, β = 10, read = 1, write = 2, instruction fetch = 3.

[0070] S104. Compare the target threshold and the popularity score to determine the data type of the target data.

[0071] The target threshold is determined based on the node identifier of the non-uniform memory access node.

[0072] Understandably, based on S103 above, according to the heat score calculated in the second layer, and combined with the characteristics of the system's NUMA (Non-Uniform Memory Access) architecture, the target data is dynamically divided into different levels (each data type corresponds to one data level) and allocated to the optimal storage location. This layer achieves performance optimization of the heterogeneous memory system through adaptive thresholds, NUMA node awareness, and intelligent migration strategies. See the following embodiment for details.

[0073] Optionally, compare the target threshold and the popularity score to determine the data type of the target data, including:

[0074] The heat threshold is determined based on the node identifier of the non-uniform memory access node; the product of the heat threshold and the preset threshold is calculated to obtain the target threshold; the target threshold and the heat score are compared to determine the data type of the target data.

[0075] Understandably, a data tiering algorithm is designed to achieve more accurate and efficient data migration and resource scheduling. Specifically, a heat threshold is determined based on the node identifier of the non-uniform memory access node (target NUMA node). Different NUMA nodes have different heat thresholds due to differences in their local memory bandwidth, latency, load, and CXL topology location. The target NUMA node refers to the node that initiates the access event, i.e., the node used to determine whether data should be migrated from CXL to the target NUMA node's local DRAM. For example, the heat threshold can be obtained using the statement `local_threshold = get_numa_threshold(node_id)`, where `local_threshold` is the heat threshold and `node_id` is the node identifier of the target NUMA node. Subsequently, the product of the heat threshold and a preset threshold is calculated to obtain the target threshold. The target threshold and the heat score output by the second layer are compared to determine the data type of the target data, which is explained in detail in the following examples. The data types include hot data, warm data, and cold data; other possible data types can be set according to user needs.

[0076] Optionally, compare the target threshold and the popularity score to determine the data type of the target data, including:

[0077] If the heat score is greater than the first product of the heat threshold and the fourth preset threshold, the target data is determined as hot data; if the heat score is less than the first product but greater than the second product of the heat threshold and the fifth preset threshold, the target data is determined as warm data; if the heat score is less than the second product, the target data is determined as cold data. The target threshold includes the first and second products, and the preset thresholds include the fourth and fifth preset thresholds.

[0078] Understandably, the product of the heat threshold and the fourth preset threshold is calculated to obtain the first product. The heat score is then checked against this first product. If the heat score is greater than the first product, the target data is classified as hot data (HOT). For example, if the fourth preset threshold is 1.5, the score is checked to ensure it is greater than 1.5 * local_threshold, where score is the heat score. If the heat score is less than or equal to the first product, the product of the heat threshold and the fifth preset threshold is calculated to obtain the second product. The heat score is then checked against this second product. If the heat score is greater than the first product, the target data is classified as warm data (WARM). For example, if the fifth preset threshold is 0.7, the score is checked to ensure it is greater than 0.7 * local_threshold. If the heat score is less than or equal to the second product, the target data is classified as cold data (COLD). A grading ratio is set, using 1.5 times and 0.7 times the threshold to divide the data into three levels to balance performance and resource utilization.

[0079] S105. When the data type is hot data, migrate the target data from the target memory corresponding data area to the hot data area.

[0080] The access latency of the hot data area is shorter than that of the corresponding data area in the target memory.

[0081] Understandably, based on S104, in scenarios involving data migration in heterogeneous memory systems (e.g., CXL+DRAM architecture), if the popularity score of the target data exceeds the target threshold, the target data is identified as hot data. The specific memory object of the hot data (e.g., a set of cache lines) is then migrated from CXL memory (high latency, slow, extended memory) to the hot data area (high-performance storage area, typically the DRAM of the local NUMA node (low latency, high bandwidth)). In other words, when the system determines that a piece of data is hot data, it migrates it from its current location in slow memory (e.g., CXL memory) and places it in the high-speed local memory (e.g., DRAM) of the local node to reduce the latency of accessing that data.

[0082] Optionally, after determining the data type of the target data, the method may also include:

[0083] Target data of hot data type is stored in a predetermined hot data area, wherein the hot data area is a local dynamic random access memory and the latency is less than a first preset nanosecond; target data of warm data type is stored in a predetermined warm data area, wherein the warm data area is a high-performance area that supports high-speed interconnection protocols and the latency is greater than a second preset nanosecond and less than a third preset nanosecond, wherein the first preset nanosecond is less than the second preset nanosecond, and the access frequency of the high-performance area is greater than a sixth preset threshold; target data of cold data type is stored in a predetermined cold data area, wherein the cold data area is a low-performance area that supports high-speed interconnection protocols and the latency is greater than a fourth preset nanosecond, wherein the third preset nanosecond is less than the fourth preset nanosecond, and the access frequency of the low-performance area is less than the sixth preset threshold.

[0084] Understandably, after determining the data type of the target data or completing the data classification of the target data, if the target data is hot data, it will be migrated from the corresponding data area of ​​the target CXL device to the hot data area (HOT_DATA). That is, frequently accessed data will be migrated to the hot data area, which is local dynamic random access memory (local DRAM). The local DRAM can be from the target NUMA node or it can be migrated to the high-performance area of ​​the CXL device closest to the target CXL device. Furthermore, the hot data area is characterized by a latency of less than a first preset nanosecond (e.g., 100ns) and supports the highest priority access. If the target data is warm data, it will be retained in the warm data area (WARM_DATA). That is, warm data, which is not frequently accessed, will be retained in the CXL high-performance area. The warm data area is stored in the medium-performance area of ​​the CXL device (e.g., a memory channel 1-2 hops away from the CPU). The warm data area is characterized by a latency greater than a second preset nanosecond and less than a third preset nanosecond (e.g., 150-200ns) to balance performance and capacity. If the target data is cold data, the target data will be stored in the cold data area (COLD_DATA). That is, data with a long access interval (e.g., 1 hour) will be migrated to the cold data area. The storage location of the cold data area is the cold data area of ​​the CXL device (e.g., remote memory node or persistent memory). The characteristics of the cold data area are that the latency is greater than the fourth preset nanosecond (e.g., 300ns), and it has a large capacity and low cost.

[0085] Optionally, after storing the target data, which is of hot data type, in a pre-determined hot data area, the method further includes:

[0086] When local dynamic random access memory (DRAM) storage space is insufficient, the target data is migrated to a non-uniform memory access node (NUMB), which is the node where the target processor accessing the target data resides; or, the target data is migrated to the nearest idle node via a switch that supports high-speed interconnect protocols.

[0087] Understandably, for hot data, NUMA nodes can be identified, and hot data can be preferentially migrated to the NUMA node where the CPU accessing it resides. When the local node's DRAM is insufficient, the hot data is migrated to the nearest idle node via the CXL switch. Here, the NUMA node is the local node. Alternatively, if the local node's DRAM storage space is insufficient, the hot data is migrated to the NUMA node. If the NUMA node's storage space is also insufficient, the hot data is then migrated to the nearest idle node via the CXL switch.

[0088] Each non-uniform memory access node maintains an independent hotness threshold.

[0089] Optionally, before determining the heat threshold based on the node identifier of the non-uniform memory access node, the method further includes:

[0090] A heat threshold is determined based on the memory usage and access patterns of non-uniform memory access nodes; and / or, a heat threshold is determined using a clustering algorithm based on the historical heat distribution data of non-uniform memory access nodes; and / or, the load status is determined based on the performance data of non-uniform memory access nodes. If the load status is high, the heat threshold is increased; if the load status is low, the heat threshold is decreased. A correspondence is established between the node identifier of non-uniform memory access nodes and the heat threshold so that the heat threshold can be determined based on the node identifier.

[0091] Understandably, the popularity threshold corresponding to a node identifier can be dynamically adjusted; it is a dynamic threshold. In one embodiment, each NUMA node maintains an independent popularity threshold, thus dynamically adjusting the threshold based on the NUMA node's memory usage and access patterns. In another embodiment, a threshold adaptive mechanism is set up, using statistical learning to dynamically adjust the popularity threshold. For example, based on the historical popularity distribution of NUMA nodes, the optimal threshold is automatically discovered using a K-means clustering algorithm. Alternatively, a load-aware approach can be used to dynamically adjust the popularity threshold; for example, increasing the threshold under high load to reduce migration frequency and decreasing it under low load to improve data locality. Another example is real-time tracking of access latency, bandwidth utilization, and hit rate at each storage tier; when the CXL memory hit rate falls below a certain threshold (e.g., 60%), the popularity threshold is lowered, automatically increasing the proportion of hot data. Finally, based on feedback control theory, the tier / popularity threshold can be dynamically adjusted.

[0092] Optionally, after determining the data type of the target data, the method may also include:

[0093] If the target data is hot data, and the heat level of the target data changes, the utilization rate of the local dynamic random access memory storing the target data exceeds the seventh preset threshold, or the target data is detected as data to be migrated, then the target data will be migrated to other data areas, where other data areas are used to store data types other than hot data.

[0094] Understandably, a data migration strategy is set. The following embodiment uses the migration of hot data as an example for illustration. The triggering conditions for the migration strategy are changes in popularity, resource pressure, and a time window. Changes in popularity refer to changes in the data's popularity level (e.g., from WARM to HOT). Resource pressure refers to the activation of the cold data eviction mechanism when the DRAM utilization exceeds a certain threshold (e.g., 80%). The time window refers to performing a global scan every 100ms to detect data that needs to be migrated. If the popularity level of the target data changes, the local DRAM utilization exceeds a seventh preset threshold, or the target data is detected as data to be migrated during the scan, then the target data is migrated from the hot data area to other data areas.

[0095] Optionally, the target data may be migrated to other data areas, including:

[0096] The target data is constructed into a multi-page data structure, and at least some pages are migrated in batches to other data areas; or, before the target data is migrated, the target data is prefetched to the target area and then migrated from the target area to other data areas.

[0097] Understandably, the migration engine responds to migration trigger operations by performing migration optimizations, including batch migration, prefetching mechanisms, and write-back strategies. Batch migration refers to migrating multiple consecutive pages (e.g., 16-32 consecutive pages) at a time to reduce TLB (Translation Back Buffer) refresh overhead. Prefetching mechanisms involve prefetching data to the target location / region before migration, and then migrating it from the target region to other data regions to reduce access latency.

[0098] Optionally, during the migration of target data to other data areas, it is supported that the portion of target data that has not yet been migrated can continue to serve read requests.

[0099] Understandably, a write-back strategy refers to using an asynchronous write-back method to allow the source data to continue serving read requests during data migration.

[0100] The data processing method provided in this application constructs a hot data detection and migration mechanism for the CXL heterogeneous memory architecture. Specifically, through a three-level collaborative detection architecture, high-speed initial screening of access events is achieved using CXL hardware monitoring units (e.g., PMU / CHMU). Fine-grained feature statistics are performed by combining locally maintained compressed heat map data. Finally, a dynamic hierarchical strategy drives the precise migration of data between DRAM and CXL memory, forming a closed loop of perception, analysis, decision-making, and execution. Secondly, a deep hardware-software collaborative mechanism is adopted. The hardware layer efficiently filters invalid data, significantly reducing the software processing load. The software layer compensates for the coarse granularity and weak flexibility of hardware monitoring through lightweight data structures and adaptive algorithms, achieving extremely low system overhead while ensuring high detection accuracy. Finally, a dynamic hierarchical storage mechanism is introduced, which intelligently divides data into three storage levels—hot (local DRAM), warm (near-end CXL), and cold (far-end CXL)—based on real-time access heat / frequency. The data distribution is automatically adjusted according to load fluctuations, maximizing the bandwidth and latency advantages of heterogeneous memory and significantly improving throughput and response efficiency for high-performance loads.

[0101] Based on the above embodiments, Figure 2 A flowchart illustrating an overall data processing method provided in this application embodiment specifically includes, as follows: Figure 2 The following steps are shown:

[0102] CXL memory access events; First layer: Hardware-assisted filtering layer, used to filter out high-probability hot data; Second layer: Distributed heat counter, used to update heat scores; Third layer: Dynamic hierarchical storage layer, used to dynamically divide data into different levels and allocate them to the optimal storage location; Hot data is migrated to the local DRAM cache, warm data is kept in the CXL high-performance area, and cold data is stored in the CXL cold data area; Low-probability data filtered by the first layer is stored in the CXL cold data area.

[0103] As is understood, the implementation details of the above steps can be found in the above embodiments and will not be repeated here.

[0104] Based on the above embodiments, Figure 3 A flowchart illustrating the implementation of a distributed heat meter in this application embodiment is provided, specifically including the following: Figure 3 The following steps are shown:

[0105] Receive access events corresponding to high-probability hot data selected from the first layer; locate the hot data image data; obtain the current hot score; calculate the access time interval; determine the access weight according to the access type; update the hot score by applying the exponential decay formula; record the timestamp and access flag; output the updated hot score to the third layer.

[0106] As is understood, the implementation details of the above steps can be found in the above embodiments and will not be repeated here.

[0107] Based on the above embodiments, Figure 4 A flowchart illustrating the implementation of a NUMA-aware hierarchical system provided in this application embodiment specifically includes, as follows: Figure 4 The following steps are shown:

[0108] Receive hot data and NUMA node ID; obtain a dynamic threshold based on the node ID; perform hierarchical decision-making: if the score > 1.5 * threshold, it is identified as hot data and migrated to local DRAM or the high-performance area of ​​the nearest CXL device; if the score > 0.7 * threshold, it is identified as warm data and retained in the medium-performance area of ​​CXL; if the score < 0.7 * threshold, it is identified as cold data and stored in the cold data area of ​​CXL; perform adaptive adjustment, which includes threshold adjustment and migration frequency adjustment. The threshold adjustment includes: dynamically adjusting the threshold based on performance data feedback from performance monitoring; automatically finding the optimal threshold using the K-means clustering algorithm; adjusting the threshold based on load awareness (increasing the threshold under high load and decreasing the threshold under low load); automatically increasing the proportion of hot data when the CXL memory hit rate is below 60%; and dynamically adjusting the threshold based on feedback control theory.

[0109] Based on the above embodiments, Figure 5 A flowchart illustrating the implementation of a migration strategy provided in this application embodiment specifically includes, as follows: Figure 5 The following steps are shown:

[0110] Data migration is triggered by conditions including: changes in heat level, DRAM utilization exceeding 80%, and a global scan performed every 100ms time window to detect data that needs to be migrated. Migration frequency adjustment includes: reducing migration frequency under high load, dynamically adjusting migration frequency based on feedback control theory, and adjusting migration frequency through a dual-window mechanism (short window (10ms) to capture sudden hot spots, and long window (1s) to smooth system fluctuations). Migration optimization includes: batch migration, prefetch mechanism, and write-back strategy.

[0111] As is understood, the implementation details of the above steps can be found in the above embodiments and will not be repeated here.

[0112] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0113] Embodiments of this application also provide a data processing apparatus, including:

[0114] The receiving unit is used to receive access events to the target memory and obtain the performance data corresponding to the access events, wherein the target memory supports interconnection protocols;

[0115] The receiving unit is used to acquire heatmap data of the target memory when the performance data meets the set filtering conditions.

[0116] The calculation receiving unit is used to calculate the heat score of the target data to be operated on in the access event based on the heat map metadata.

[0117] A determination unit is used to compare the target threshold and the heat score to determine the data type of the target data, wherein the target threshold is determined based on the node identifier of the non-uniform memory access node;

[0118] The migration unit is used to migrate target data from the target memory corresponding data area to the hot data area when the data type is hot data. The access latency of the hot data area is less than that of the target memory corresponding data area.

[0119] The performance data includes at least one of the following: cache read hit count, access latency period, and bandwidth utilization.

[0120] Optionally, the device is also used for:

[0121] Determine whether the number of cache read hits is greater than the first preset threshold, whether the access latency period is less than the second preset threshold, and whether the bandwidth utilization is greater than the third preset threshold;

[0122] If the number of cache read hits is greater than the first preset threshold, the access latency period is less than the second preset threshold, or the bandwidth utilization is greater than the third preset threshold, then the performance data is determined to meet the set filtering conditions.

[0123] The heatmap metadata is an N-byte metadata structure, and the heatmap is distributed according to non-uniform memory access nodes. The metadata structure includes an access timestamp in the first byte, a heat score in the second byte, and an access permission identifier in the third byte. The total number of bytes in the first, second, and third bytes is N. The access timestamp is used to record the last access time, and the access permission identifier includes a read permission identifier, a write permission identifier, and a read-write permission identifier.

[0124] Optionally, the calculation receiving unit is used for:

[0125] The heat map data is updated with a heat score based on a pre-set decay factor, access coefficient compensation, and access weight of the access event. This yields the heat score of the target data to be processed by the access event. The decay factor controls the rate at which access is forgotten, the access coefficient compensation amplifies the access weight, and the access weight is determined based on the access type of the access event.

[0126] Optionally, the determining unit is used for:

[0127] The heat threshold is determined based on the node identifier of the non-uniform memory access node;

[0128] The target threshold is obtained by multiplying the heat threshold and the preset threshold.

[0129] Compare the target threshold and the popularity score to determine the data type of the target data.

[0130] Optionally, the determining unit is used for:

[0131] If the heat score is greater than the first product of the heat threshold and the fourth preset threshold, then the target data is determined as hot data.

[0132] If the heat score is less than the first product and greater than the second product of the heat threshold and the fifth preset threshold, then the target data is determined to be warm data.

[0133] If the heat score is less than the second product, the target data is determined to be cold data. The target threshold includes the first product and the second product, and the preset threshold includes the fourth preset threshold and the fifth preset threshold.

[0134] The hot data area is a local dynamic random access memory with a latency of less than a first preset nanosecond.

[0135] Optionally, the migration unit is used for:

[0136] The target data of data type warm data is stored in a predetermined warm data area, wherein the warm data area is or supports a high-performance area of ​​interconnection protocol, and the latency is greater than the second preset nanosecond and less than the third preset nanosecond, the first preset nanosecond is less than the second preset nanosecond, and the access frequency of the high-performance area is greater than the sixth preset threshold.

[0137] The target data of type cold data is stored in a predetermined cold data area. The cold data area is a low-performance area that supports the interconnection protocol, and the latency is greater than the fourth preset nanosecond, the third preset nanosecond is less than the fourth preset nanosecond, and the access frequency of the low-performance area is less than the sixth preset threshold.

[0138] Optionally, the device is also used for:

[0139] When local dynamic random access memory (DRAM) storage space is insufficient, the target data is migrated to a non-uniform memory access node (NUMB), which is the node where the target processor accessing the target data resides; or, the target data is migrated to the nearest idle node via a switch that supports interconnect protocols.

[0140] Each non-uniform memory access node maintains an independent hotness threshold.

[0141] Optionally, the device is also used for:

[0142] The heat threshold is determined based on the memory usage and access patterns of non-uniform memory access nodes; and / or, the heat threshold is determined by clustering algorithms based on the historical heat distribution data of non-uniform memory access nodes; and / or, the load status is determined based on the performance data of non-uniform memory access nodes. If the load status is high, the heat threshold is increased; if the load status is low, the heat threshold is decreased.

[0143] Establish a correspondence between node identifiers of non-uniform memory access nodes and popularity thresholds, so as to determine the popularity thresholds based on node identifiers.

[0144] Optionally, the device is also used for:

[0145] If the target data is hot data, and the heat level of the target data changes, the utilization rate of the local dynamic random access memory storing the target data exceeds the seventh preset threshold, or the target data is detected as data to be migrated, then the target data will be migrated to other data areas, where other data areas are used to store data types other than hot data.

[0146] Optionally, the migration unit is used for:

[0147] Construct the target data into a multi-page data structure, and migrate at least some pages in batches to other data areas; or...

[0148] Before migrating the target data, the target data is prefetched to the target area and then migrated from the target area to other data areas.

[0149] In the process of migrating target data to other data areas, it is supported that the target data that has not yet been migrated can continue to serve read requests.

[0150] For a description of the features in the embodiment corresponding to the data processing device, please refer to the relevant description in the embodiment corresponding to the data processing method, which will not be repeated here.

[0151] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described data processing method embodiments.

[0152] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above data processing method embodiments when it is run.

[0153] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0154] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above data processing method embodiments.

[0155] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above data processing method embodiments.

[0156] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0157] The above provides a detailed description of a data processing method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data processing method, characterized by, The method comprises the following steps: receiving an access event of a target memory, and obtaining performance data corresponding to the access event, wherein the target memory supports a high-speed interconnection protocol; when the performance data meets a set screening condition, obtaining hot map metadata of the target memory; calculating a hot score of target data to be operated according to the hot map metadata; comparing a target threshold value and the hot score to determine a data type of the target data, wherein the target threshold value is determined according to a node identifier of a non-uniform memory access node; when the data type is hot data, migrating the target data from a data area corresponding to the target memory to a hot data area, wherein an access delay time of the hot data area is smaller than that of the data area corresponding to the target memory.

2. The method of claim 1, wherein, The performance data comprises at least one of a cache read hit number, an access delay period and a bandwidth utilization rate, and after the performance data corresponding to the access event is obtained, the method further comprises: determining whether the cache read hit number is greater than a first preset threshold value, whether the access delay period is less than a second preset threshold value, and whether the bandwidth utilization rate is greater than a third preset threshold value; if the cache read hit number is greater than the first preset threshold value, the access delay period is less than the second preset threshold value, or the bandwidth utilization rate is greater than the third preset threshold value, it is determined that the performance data meets the set screening condition.

3. The method of claim 1, wherein, The hot map metadata is an N-byte metadata structure, and the hot map is distributed according to non-uniform memory access nodes, wherein the metadata structure comprises a first byte of an access timestamp, a second byte of a hot score and a third byte of an access permission identifier, the total byte number of the first byte, the second byte and the third byte is N, the access timestamp is used to record the last access time, and the access permission identifier comprises a read permission identifier, a write permission identifier and a read-write permission identifier.

4. The method of claim 1, wherein, The hot score of the target data to be operated is calculated according to the hot map metadata, which comprises: updating the hot score in the hot map metadata according to a pre-set decay factor, an access coefficient compensation and an access weight of the access event to obtain the hot score of the target data to be operated, wherein the decay factor is used to control the forgetting speed of access, the access coefficient compensation is used to amplify the access weight, and the access weight is determined according to the access type of the access event.

5. The method of claim 1, wherein, The hot score of the target data to be operated is calculated according to the hot map metadata, which comprises: determining a hot threshold value according to a node identifier of a non-uniform memory access node; calculating the product of the hot threshold value and a preset threshold value to obtain a target threshold value; comparing the target threshold value and the hot score to determine the data type of the target data.

6. The method of claim 5, wherein, The hot score of the target data to be operated is calculated according to the hot map metadata, which comprises: if the hot score is greater than the first product of the hot threshold value and a fourth preset threshold value, the target data is determined as hot data. if the hotness score is less than the first product and greater than a second product of the hotness threshold value and a fifth preset threshold value, the target data is determined as warm data; if the hotness score is less than the second product, the target data is determined as cold data, wherein the target threshold value includes the first product and the second product, and the preset threshold value includes the fourth preset threshold value and the fifth preset threshold value.

7. The method of claim 6, wherein, The hot data area is a local dynamic random access memory, and the delay time is less than a first preset nanosecond. After determining the data type of the target data, the method further comprises: storing the target data of the warm data type in a predetermined warm data area, wherein the warm data area is a high-performance area supporting an interconnection protocol, and the delay time is greater than a second preset nanosecond and less than a third preset nanosecond, the first preset nanosecond is less than the second preset nanosecond, and the access frequency of the high-performance area is greater than a sixth preset threshold value; storing the target data of the cold data type in a predetermined cold data area, wherein the cold data area is a low-performance area supporting an interconnection protocol, and the delay time is greater than a fourth preset nanosecond, the third preset nanosecond is less than the fourth preset nanosecond, and the access frequency of the low-performance area is less than the sixth preset threshold value.

8. The method of claim 7, wherein, After storing the target data of the hot data type in the predetermined hot data area, the method further comprises: in the case that the storage space of the local dynamic random access memory is insufficient, migrating the target data to the non-uniform memory access node, wherein the non-uniform memory access node is a node where a target processor accessing the target data is located; or migrating the target data to the nearest idle node through a switch supporting an interconnection protocol.

9. The method of claim 5, wherein, Each non-uniform memory access node maintains an independent hotness threshold value. Before determining the hotness threshold value according to the node identifier of the non-uniform memory access node, the method further comprises: determining the hotness threshold value according to the memory usage of the non-uniform memory access node and the access mode of the access event; and / or, determining the hotness threshold value through a clustering algorithm according to historical hotness distribution data of the non-uniform memory access node; and / or, determining a load state according to performance data of the non-uniform memory access node, if the load state is high load, increasing the hotness threshold value, and if the load state is low load, decreasing the hotness threshold value; establishing a correspondence between the node identifier of the non-uniform memory access node and the hotness threshold value, so as to determine the hotness threshold value according to the node identifier.

10. The method of claim 1, wherein, After determining the data type of the target data, the method further comprises: in the case that the target data is hot data, if the hotness level of the target data changes, the utilization rate of the local dynamic random access memory storing the target data exceeds a seventh preset threshold value, or it is detected that the target data is to be migrated data, migrating the target data to other data areas, wherein the other data areas are used to store other data types except the hot data.

11. The method of claim 10, wherein, The migrating the target data to other data area comprises: constructing the target data into a plurality of page data structures, and migrating at least part of the pages to other data area in batches; or prefetching the target data to a target area before migrating the target data, and migrating the target data from the target area to other data area.

12. An electronic device, comprising: comprise: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the data processing method according to any one of claims 1 to 11.

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