Interface parameter adjusting method and device and electronic equipment

Abstract

The invention discloses an interface parameter adjusting method and device and electronic equipment, relates to the technical field of interface control, and is applied to an interface controller which is in communication connection with main equipment and external storage equipment. The current access mode is determined based on the actual address difference value and the expected address difference value of the two adjacent accesses, the loopback boundary of the interface controller is adjusted based on the determined current access mode, dynamic adjustment of the loopback boundary is achieved, the loopback range can be matched with the actual access range of the main device, and the user experience is improved. The optimization of data reading efficiency is realized, and the data transmission efficiency in the direct reading mode is further improved.

Description

Technical Field

[0001] This application relates to the field of interface control technology, and in particular to an interface parameter adjustment method, device and electronic device. Background Technology

[0002] QSPI (Quad Serial Peripheral Interface) is a high-speed serial communication interface widely used in embedded systems for external memory access and real-time data stream transmission. With the rapid development of technologies such as the Internet of Things (IoT) and edge computing, systems are placing higher demands on the data transmission efficiency and real-time performance of QSPI controllers. Loopback mode can automatically generate a circular address sequence through hardware, eliminating the command overhead of repeatedly transmitting addresses and significantly improving effective data throughput.

[0003] However, in related technologies, the QSPI controller's support for loopback mode suffers from limitations such as the inability to adjust the loopback boundary and restrictions on the amount of loopback data imposed by the interface bus protocol between the QSPI controller and the master device, making it difficult to meet the requirements for efficient access. Therefore, there is an urgent need to propose a method for adjusting interface parameters to meet data transmission requirements. Summary of the Invention

[0004] This application provides an interface parameter adjustment method, apparatus, and electronic device to meet data transmission requirements.

[0005] This application provides an interface parameter adjustment method applied to an interface controller, which is communicatively connected to a host device and an external storage device. The method includes: if a loopback access request is received from the host device and the current mode of the interface controller is direct read mode, determining the actual address difference between two adjacent accesses based on the access address on the communication bus and determining the expected address difference based on a burst access signal on the communication bus; determining the current access mode based on the actual address difference and the expected address difference; and adjusting the loopback boundary based on the current access mode.

[0006] This application also provides an interface parameter adjustment device applied to an interface controller, which is communicatively connected to a host device and an external storage device. The device includes: a first determining module, configured to determine the actual address difference between two adjacent accesses based on the access address on the communication bus and the expected address difference based on a burst access signal on the communication bus if a loopback access request is received from the host device and the current mode of the interface controller is direct read mode; a second determining module, configured to determine the current access mode based on the actual address difference and the expected address difference; and a first adjusting module, configured to adjust the loopback boundary according to the current access mode.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described interface parameter adjustment methods when executing the computer program.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described interface parameter adjustment methods.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described interface parameter adjustment methods.

[0010] The interface parameter adjustment method provided in this application is applied to an interface controller that is communicatively connected to both the host device and an external storage device. If the interface controller receives a loopback access request sent by the host device and the current mode is direct read mode, the current access mode is determined based on the actual address difference and the expected address difference between two adjacent accesses. Based on the determined current access mode, the loopback boundary of the interface controller is adjusted to achieve dynamic adjustment of the loopback boundary. This allows the loopback range to be adapted to the actual access range of the host device, thereby optimizing data reading efficiency and further improving data transmission efficiency in direct read mode. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating an interface parameter adjustment method provided in an embodiment of this application;

[0013] Figure 2 A schematic diagram illustrating an interface parameter adjustment method provided in an embodiment of this application;

[0014] Figure 3 A schematic diagram illustrating an interface parameter adjustment method provided in an embodiment of this application;

[0015] Figure 4 A schematic diagram illustrating an interface parameter adjustment method provided in an embodiment of this application;

[0016] Figure 5 A schematic diagram illustrating an interface parameter adjustment method provided in an embodiment of this application;

[0017] Figure 6A schematic diagram illustrating an interface parameter adjustment method provided in an embodiment of this application;

[0018] Figure 7A This is a schematic diagram illustrating the effect of an interface parameter adjustment method provided in an embodiment of this application.

[0019] Figure 7B This is a schematic diagram illustrating the effect of an interface parameter adjustment method provided in an embodiment of this application.

[0020] Figure 8 A structural block diagram of an interface parameter adjustment device provided in an embodiment of this application;

[0021] Figure 9 A structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0023] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0024] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] QSPI (Quad Serial Peripheral Interface) is a high-speed serial communication interface widely used in embedded systems for external memory access and real-time data stream transmission. With the rapid development of technologies such as the Internet of Things (IoT) and edge computing, systems are placing higher demands on the data transmission efficiency and real-time performance of QSPI controllers. Loopback mode can automatically generate a circular address sequence through hardware, eliminating the command overhead of repeatedly transmitting addresses and significantly improving effective data throughput. However, in related technologies, QSPI IP cores typically only support fixed loopback boundaries (e.g., 8 bytes / 16 bytes / 32 bytes) and cannot be dynamically adjusted. For example, in ARM's Cortex-M series processors, the integrated QSPI IP loopback mode is used for cacheable operations, but the loopback boundary is fixed at 32 bytes, and the data volume is the size of one cache line in a STASP processor, which cannot meet the needs of processors with larger cache lines. A single QSPI IP can only support cacheable operations for a specific processor model, and cannot support cacheable operations for other processor models, which is a significant limitation. Furthermore, the AHB bus commonly used by QSPI controllers typically defines a maximum burst length of 16 transmissions, severely restricting the data volume limit for a single loopback operation. For example, with a 4-byte data unit, the AHB protocol's WRAP16 mode only supports a 64-byte loopback data block, which is insufficient for efficient access to large circular buffers (such as 1KB). Therefore, there is an urgent need to expand the loopback mode functionality to meet data transmission requirements.

[0026] This application provides an interface parameter adjustment method applied to an interface controller. The interface controller is communicatively connected to a master device and an external storage device. The master device can obtain data at a corresponding address from the external storage device through the interface by sending an access request. In this application embodiment, the interface controller is an example of a QSPI controller. Figure 1 As shown, it includes the following steps:

[0027] Step S101: If a loopback access request is received from the master device and the current mode of the interface controller is direct read mode, determine the actual address difference between two adjacent accesses based on the access address on the communication bus and determine the expected address difference based on the burst access signal on the communication bus.

[0028] For example, the interface controller's modes can include direct read mode, indirect read mode, and direct / indirect write mode, etc. The current mode can be determined by reading the mode configuration information. The interface controller can monitor the Master bus access address in real time and calculate the actual address difference (Δ) between two adjacent accesses. Each time QSPI access occurs, the difference between the current access address (Addr{n}) issued by the Master (such as CPU / DMA) and the previous access address (Addr{n-1}) can be recorded to obtain the actual access step size of the master device, which can be determined by the following formula (1):

[0029] Δ=Addr{n}-Addr{n-1}(1)

[0030] Analyzing the Master's bus behavior, assuming the burst access signal extracts a wrap value of m and a size (bytes per data unit) value of n, the expected address difference (Δ1) is:

[0031] Δ1=m×2 n (2)

[0032] Step S102: Determine the current access mode based on the actual address difference and the expected address difference. For example, if the actual address difference and the expected address difference are equal, it indicates that the current master device is following the loopback protocol standard, and the current access mode is determined to be continuous loopback access mode; if the actual address difference and the expected address difference are not equal, it indicates that the current access is fluctuating, and the current access mode is determined to be discontinuous loopback access mode.

[0033] Step S103: Adjust the loopback boundary according to the current access mode. For example, if the current access mode is continuous loopback, the loopback boundary can be appropriately expanded to improve the efficiency of subsequent data prefetching; if the current access mode is non-continuous loopback, the loopback boundary can be reduced or maintained to avoid invalid caching.

[0034] The interface parameter adjustment method provided in this application is applied to an interface controller that is communicatively connected to both a master device and an external storage device. If the interface controller receives a loopback access request sent by the master device and the current mode is direct read mode, the current access mode is determined based on the actual address difference and the expected address difference between two adjacent accesses. Based on the determined current access mode, the loopback boundary of the interface controller is adjusted to achieve dynamic adjustment of the loopback boundary. This allows the loopback range to be adapted to the actual access range of the master device, thereby optimizing data reading efficiency and further improving data transmission efficiency in direct read mode.

[0035] As an optional implementation of this application, step 102 includes: determining the trend of address change between two adjacent accesses based on the positive or negative result of the actual address difference; comparing the actual address difference with the expected address difference to obtain a size comparison result; determining a mode flag bit based on the trend of change, the size comparison result, and preset mode flag data; and determining the current access mode based on the mode flag bit.

[0036] For example, the sign of the actual address difference (e.g., Δ>0 or Δ<0) can be used to determine whether the trend of address change between two adjacent accesses is increasing or decreasing, thus distinguishing between "forward" and "reverse" modes. The actual address difference (Δ) is compared with the expected address difference (Δ1), and the comparison result is "Δ=Δ1" or "Δ≠Δ1". Based on the comparison result, it can be used to determine whether the address change conforms to the standard step size agreed upon in the protocol, and can be used to distinguish between "continuous mode" and "random mode". For example, "Δ=Δ1" indicates a "continuous mode"; "Δ≠Δ1" indicates a "random mode". The interface controller can pre-configure preset mode flag data, which can pre-integrate the mode flag bits corresponding to the mode under different conditions. Based on the determined trend and the magnitude comparison result, the current access mode can be determined by comparing the preset mode flag data. The data types included in the preset mode flag data can be shown in Table 1 below:

[0037] Table 1

[0038]

[0039] Referring to Table 1, when Δ > 0 and Δ = Δ1, meaning the address difference is positive (the later address is larger than the previous one), and the actual address difference equals the expected address difference Δ1, the value of Δ1 can be: 16Byte, 32Byte, or 64Byte (corresponding to different Burst and Size configurations). "Positive continuous" indicates that the master device is incrementing the address, and each step size is equal to "the amount of data transmitted in a single transaction (Δ1)", which conforms to the pattern of continuous read. The mode flag bits are: "Δ1 = 16Byte" corresponding to "0001", "Δ1 = 32Byte" corresponding to "0010", and "Δ1 = 64Byte" corresponding to "0011". When Δ < 0 and Δ = Δ1, meaning the address difference is negative (the later address is smaller than the previous one), and the actual address difference... The absolute value is equal to the expected address difference Δ1, which can be 16 bytes, 32 bytes, or 64 bytes. "Reverse continuous" indicates that the master device is decrementing the address, but the "step size of backtracking" is still equal to the "single data transmission amount (Δ1)", which belongs to "reverse continuous access". Mode flags: "Δ1 = 16 bytes" corresponds to "1001", "Δ1 = 32 bytes" corresponds to "1010", and "Δ1 = 64 bytes" corresponds to "1011". When Δ ≠ Δ1, that is, the actual address difference Δ is not equal to the expected address difference Δ1, it is "random" mode, which indicates that the address access of the master device has no fixed step size. It is neither forward continuous nor reverse continuous. The mode flag of random mode is "0000". The QSPI controller monitors the address access of the master device in real time. By calculating and comparing Δ and Δ1, and combining with Table 1, it can quickly determine whether the current access mode is continuous (forward / reverse) or random access. Furthermore, it can automatically adjust internal parameters (such as adjusting loopback boundaries and transmission efficiency optimization strategies) according to the mode corresponding to the "mode flag" so that the QSPI controller parameters can better adapt to the access patterns of the master device.

[0040] As an optional implementation of this application, determining the current access mode based on the mode flag includes: determining the current instant access mode based on the mode flag; using a sliding window statistics method to respond to the percentage statistics of access modes according to a preset window length, obtaining the percentage of consecutive accesses corresponding to the same access mode within the preset window length; and determining the current access mode based on the current instant access mode and the percentage of consecutive accesses corresponding to the same access mode within the preset window length.

[0041] For example, by combining the data in Table 1, the current instantaneous mode of a single access can be obtained. For example, if the current "Δ = Δ1" and is positive, then the current instantaneous mode is "positive continuous". In order to avoid misjudgment of the mode due to the single instantaneous mode, this application embodiment further performs mode determination within a certain time window. Specifically, the mode determination method based on the time window adopts the sliding window statistics method. Within a fixed window length (in this application embodiment, the window length can be configured according to actual needs, such as 32 accesses or 64 accesses. This application embodiment does not limit the size of the window length, and those skilled in the art can determine it according to actual needs), the proportion of continuous accesses of the same access mode is counted. The specific calculation method is as follows:

[0042] Percentage of consecutive visits = Number of consecutive visits / Window length (3)

[0043] In this embodiment of the application, the number of consecutive accesses in formula (3) can be the number of times the current instant access mode appears consecutively within the window length. For example, if the current instant mode is "positive continuous" and the proportion of "positive continuous" in the window is >80%, it is determined to be "stable positive continuous mode", and the current access mode can be determined to be positive continuous. If the instant mode is "random", but the proportion of random in the window is <50%, it may be determined to be "transitional random mode". Specifically, for different real-time modes, the mode determination based on the percentage of consecutive accesses can be as follows: if the percentage of 16 consecutive forward bytes is greater than 80%, then "current access mode = forward mode 16 bytes" is determined; if the percentage of 32 consecutive forward bytes is greater than 80%, then "current access mode = forward mode 32 bytes" is determined; if the percentage of 64 consecutive forward bytes is greater than 80%, then "current access mode = forward mode 64 bytes" is determined; if the percentage of 16 consecutive reverse bytes is greater than 80%, then "current access mode = reverse mode 16 bytes" is determined; if the percentage of 32 consecutive reverse bytes is greater than 80%, then "current access mode = reverse mode 32 bytes" is determined; if the percentage of 64 consecutive reverse bytes is greater than 80%, then "current access mode = reverse mode 64 bytes" is determined; otherwise, the current mode can be determined as a random mode. The specific comparison threshold can be configured according to actual needs, and this application embodiment does not limit it.

[0044] By classifying access modes, various granularities of forward or reverse continuous access on the Master bus are statistically analyzed. This granularity analysis is based on the characteristics of the bus protocol itself. For example, the AHB bus's burst transmission (HBURST) supports three loopback modes (wrap4, wrap8, wrap16). When the data width (HRDATA) is 4 bytes, the data volume of a single loopback is 16 bytes, 32 bytes, and 64 bytes, respectively. This application embodiment allows configuration based on the loopback data volume transmitted by different bus protocols before access mode statistics are performed. It sets the criteria for determining forward or reverse continuous data volume and customizes mode flags for various states, achieving flexible configuration and efficient statistics. For example, if the total data volume of continuous Master access is 16 bytes (corresponding to wrap4) and the address difference meets expectations (4 bytes), it can be determined as "forward mode 16 bytes". After configuration, when statistically analyzing Master bus access modes, the preset mode flag data can be directly compared. Assuming the access address sequence corresponding to the Master initiating access on the AHB bus is: 0x00→0x04→0x08→0x0C (i.e., a total of 4 accesses, each with a difference of 4 bytes, and a total data volume of 16 bytes, increasing in a positive direction), by referring to the preset mode flag data, it can be determined that the total data volume is 16 bytes and the mode flag corresponding to the positive difference is "0001", which can be directly counted as "positive mode 16 bytes". In this way, the percentage of continuous access within the window length can be realized.

[0045] Furthermore, in this embodiment, the calculation of the continuous access ratio of the "same access mode" can be performed by calculating the continuous access ratio of the "real-time access mode" within the window length after determining the current real-time access mode. That is, the "same access mode" is the determined "current real-time access mode," which is used to determine the stability of the determined current real-time access mode within the window length. When the continuous access ratio of this mode is greater than a preset threshold, it can be determined that the loop boundary can be adjusted according to the determined current real-time access mode. If the continuous access ratio of this mode is less than the preset threshold, the result of this real-time mode determination can be ignored, and the original mode can still be used, with the loop boundary remaining unchanged. Furthermore, if the continuous access ratio of the current real-time access mode does not meet the requirements, the ratio of the longest continuous access mode within the window length can be determined. When this ratio is greater than a preset threshold, it can be determined based on the configuration whether it is necessary to adjust according to the mode determined by the continuous access mode, so as to determine the current loop mode in a timely manner and adjust the corresponding loop boundary to improve data reading efficiency.

[0046] As an optional implementation of this application, step 103 includes: obtaining the loopback boundary adjustment strategy corresponding to the current access mode; and adjusting the loopback boundary corresponding to the current access mode according to the loopback boundary adjustment strategy.

[0047] For example, the loopback boundary is configured to dynamically adjust the loopback boundary value and generate configuration parameters based on the mode classification results to adapt to the data transmission requirements in different scenarios, maximizing bus utilization and cache efficiency. In this embodiment, loopback boundary adjustment strategy data corresponding to different access modes can be pre-configured. The determined current access mode can be compared with the loopback boundary adjustment strategy data, and the loopback boundary adjustment strategy corresponding to the corresponding access mode can be determined based on the comparison result and the configuration result, as shown in Table 2 below:

[0048] Table 2

[0049]

[0050]

[0051] The data granularity of access pattern statistics is based on the Master bus protocol. Simultaneously, the bus protocol limits the data volume of a single loopback operation. From multiple consecutive loopback operations, the expected data volume of the Master can be estimated. Adjusting the loopback boundary within QSPI can guide the amount of data prefetched from flash. The loopback boundary adjustment strategy is configurable, using 2x, 4x, or larger multiples of the data volume, or the entire flash page data volume (e.g., 256B), etc., which can be configured according to actual needs. For example, when the loopback boundary adjustment strategy is configured to 2x the data volume, if a positive 16-byte access is detected on the Master bus, the loopback boundary can be dynamically adjusted to 32 bytes, saving Master waiting time, releasing Master resources, and allowing the Master to read the data after the prefetch cache is complete. When a random access is detected on the Master bus, the loopback boundary remains unchanged, consistent with the bus protocol, reducing cache pollution and disabling invalid prefetches.

[0052] As an optional implementation of this application, after step 103, the method further includes: adjusting the prefetch length according to the adjusted loopback boundary and the data unit size corresponding to the communication bus.

[0053] For example, the loopback boundary configuration result can guide the QSPI controller to perform data fetching operations on Flash in advance, thereby improving bus utilization. In this embodiment, the prefetch length is adjusted according to the loopback boundary, as shown in the following equation (4):

[0054] Prefetch Depth = Loop Boundary / Data Unit Size (4)

[0055] For example, if the QSPI controller is operating in direct read mode and the connected Flash data unit size (i.e., the Size value in the bus protocol) is 4 bytes, and the current master device initiates an AHB bus wrap8 loopback access request, then according to the characteristics of the AHB bus protocol, the loopback boundary of wrap8 mode is wrap value × data unit size = 8 × 4 bytes = 32 bytes. According to formula (4), we get Prefetch Depth = 32 bytes / 4 bytes = 8, that is, the QSPI controller will read 8 data units (32 bytes in total) from the Flash in advance according to the calculated prefetch length. The prefetch length changes according to the loopback boundary parameter, realizing adaptive data prefetching, which provides a basis for the dynamic caching of subsequent data.

[0056] As an optional implementation of this application, the interface controller is communicatively connected to the cache space, and the cache space is communicatively connected to the master device; the method further includes: reading data of the prefetch length from the external storage device according to the prefetch length; and storing the read data in the cache space. For example, a dynamic caching method based on address increment analysis can adjust the size of the cache space for direct QSPI data reading according to the prefetch length. The data prefetch length is calculated based on the parameters configured at the loopback boundary, and a direct read operation is initiated to the Flash. Simultaneously, the prefetch length can also serve as the termination address of the cache space for the current operation, dynamically adjusting the cache granularity. If prefetching fails, the data in the cache is discarded, and address increment analysis is performed again; see [link to relevant documentation] for details. Figure 2 As shown.

[0057] As an optional implementation of this application, the interface controller is communicatively connected to the cache space, and the cache space is communicatively connected to the master device; the method further includes: configuring the cache capacity of the cache space based on the burst access signal read on the communication bus; reading data of a prefetch length from the external storage device according to the cache capacity; and storing the read data in the cache space.

[0058] For example, since the QSPI Master is a CPU or DMA (Direct Memory Access), they can be interconnected via the AHB bus. The QSPI controller dynamic caching method based on the bus protocol can parse the bus protocol to obtain the transmission size (e.g., 2 bytes or 4 bytes) to determine the data width of the loopback data buffer; and obtain the Burst value (wrap4, wrap8, or wrap16, etc.) to determine the depth of the loopback data buffer. The loopback operation is parsed internally by the QSPI controller to determine the data volume of this loopback operation. Based on this, the data read from Flash is cached, and the cache granularity is dynamically adjusted to complete a loopback operation issued by the Master. By dynamically adjusting the loopback boundary, no software parameter configuration is required. The QSPI controller can dynamically parse based on the bus protocol to implement loopback operations with different data volumes. This method is applicable to cacheable operations issued by the processor when performing direct read operations using QSPI. For details, please refer to [link to relevant documentation]. Figure 3 As shown.

[0059] As one specific implementation of this application, such as Figure 4 and Figure 5 The following steps can be followed:

[0060] (1) Determine whether the QSPI controller is configured for direct read mode: if it is in direct read mode, perform address increment analysis; if not, perform traditional QSPI operation.

[0061] (2) Perform address increment analysis, including:

[0062] (2-1) Address Calculation: The real-time address on the Master bus is parsed, the real-time address difference is calculated, and the real-time address difference is compared with...

[0063] (2-2) Compare the calculated expected address differences to obtain the flag bit; (2-2) Parse the bus protocol: obtain the values ​​of Size and Burst, and calculate the expected address. When selecting a bus protocol-based address cache, Size and Burst can be used to determine the cache data unit size and cache depth in loopback mode, respectively;

[0064] (3) Access pattern classification: The pattern flags are statistically analyzed under a fixed-granularity sliding window to complete the pattern determination;

[0065] (4) Loop boundary configuration: Based on the mode determination result, the loop boundary value is dynamically adjusted. If it is positive continuous, the loop boundary can be adjusted to twice or more of the original loop data volume. If it is negative continuous, the loop boundary can be adjusted to twice or more of the original loop data volume. If it is random, the loop boundary is not adjusted.

[0066] (5) Prefetch length calculation: The prefetch length for direct data reading can be calculated based on the loopback boundary and the data unit size;

[0067] (6) Cache granularity selection: Depending on the configuration, you can choose a dynamic cache based on the bus protocol or a dynamic cache strategy based on address increment;

[0068] (7) Cache granularity management: If it is a dynamic cache based on the bus protocol, the amount of data and the required cache space for this loop operation can be obtained based on the parsed Size and Burst values; if it is a dynamic cache based on address increment, the cache depth and bit width are calculated based on the prefetch length and data unit size in (5), and the cache granularity of the current loop operation is determined. When the current access mode change is determined, the cache granularity changes accordingly, realizing dynamic management of cache granularity.

[0069] (8) Initiate a direct read operation to the flash;

[0070] (9) Loopback data caching;

[0071] (10) Determine whether the loopback data volume of the next operation matches the expectation;

[0072] (11) If they match, read the cached data.

[0073] (12) If they do not match, discard the data in the cache and re-perform address increment analysis.

[0074] Specifically, assuming the Master continuously sends wrap8 operations with a size of 4 bytes, the specific processing flow is as follows:

[0075] (1) Determine if it is a direct read mode. If yes, proceed to (2) address increment analysis.

[0076] (2) Address increment analysis: The actual address difference Δ is calculated to be 32, and the expected address is 8*4Byte=32, so the mode flag is “0010”;

[0077] (3) Access mode classification: According to the configuration, count whether the consecutive number of "0010" exceeds 80% in a fixed window of 32 accesses. If it does, proceed to (4) Loop boundary configuration.

[0078] (4) Loop boundary configuration: Based on the configuration, select a boundary adjustment strategy with twice the data volume, and determine the loop boundary as 32 bytes * 2 = 64 bytes.

[0079] (5) Adaptive prefetching: Based on the loop boundary calculated in (4), the prefetch length is determined to be 64Byte / 4Byte = 16;

[0080] (6) Cache granularity selection: Select dynamic cache based on address increment analysis according to the configuration;

[0081] (7) Cache granularity management: Based on (6), the cache depth is determined to be 16 and the width is 4 bytes;

[0082] (8) Direct read operation: Initiate a direct read operation to the flash;

[0083] (9) Loopback data buffer: The data read back directly is buffered and sent out when the master bus initiates a direct read operation.

[0084] by Figure 6 For example, in the corresponding application scenarios, such as Figure 7A and Figure 7B As shown, Figure 7A The bus time required for traditional direct read loopback operation to read two wrap8 entries; Figure 7B The bus occupancy time for the loopback operation mode described in the embodiments of this application is as follows:

[0085] in, Figure 7A middle:

[0086] The total usage time of the AHB bus (400MHz) is:

[0087] (Address (1 cycle) + Data (QSPI bus time)) * 2

[0088] The QSPI bus (100MHz, 4-wire) requires the following data to be transmitted per transfer:

[0089] Command (1 Byte) + Address (3 Bytes) + Data Cycle (32 Bytes)

[0090] QSPI bus usage time:

[0091] 1Byte*8 / 4+3Byte*8 / 4+32Byte*8 / 4=72cycle=72*10ns=720ns

[0092] The Master interface bus occupancy time is:

[0093] (2.5 + 720) * 2 = 1445 ns

[0094] Figure 7B middle:

[0095] The AHB bus (400MHz) usage time includes:

[0096] First wrap operation:

[0097] Address (1 cycle) + Data (QSPI bus usage time)

[0098] The second wrap operation (prefetched by the QSPI controller):

[0099] Address (1 cycle) + Data (8 cycles)

[0100] QSPI bus usage time:

[0101] 1Byte*8 / 4+3Byte*8 / 4+32Byte*8 / 4=72cycle=72*10ns=720ns

[0102] The Master interface bus occupancy time is:

[0103] (2.5 + 720) + 2.5 + 2.5 * 4 = 735 ns

[0104] The bus occupancy time reduction percentage is:

[0105] (1445-735) / 1445 = 49.1%

[0106] The interface parameter adjustment method provided in this application embodiment realizes dynamic management of data prefetching and caching in direct read mode. When the loopback data volume is increased to twice its original size, the bus occupancy time is reduced by 49.1%. If the loopback data volume is increased to the page boundary of Flash, the bus efficiency will be even higher. Therefore, this application embodiment, through address prediction, access mode determination, loopback boundary adjustment, adaptive prefetching, and dynamic cache adjustment methods, can deeply integrate dynamic strategies with hardware logic, significantly reducing the waiting time of the Master device and improving data transmission efficiency. It breaks through the static limitations of the traditional QSPI controller loopback mode, realizing loopback operations with different data volumes, possessing flexibility and versatility, and significantly improving data transmission efficiency and system adaptability. It is applicable to scenarios such as direct read operations of cacheables initiated by processors with different cacheline sizes, and circular data access. The dynamic caching method based on address increment analysis can be applied to wrap and increase transmissions initiated by the Master; the access mode classification method based on address prediction can be applied to wrap and increase transmissions initiated by the Master; and the prediction of loopback boundaries within the controller can also be used for increase transmissions.

[0107] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0108] Embodiments of this application also provide an interface parameter adjustment device, applied to an interface controller, the interface controller being communicatively connected to both a host device and an external storage device; such as Figure 8 As shown, the device includes:

[0109] The first determining module 201 is used to determine the actual address difference between two adjacent accesses based on the access address on the communication bus and the expected address difference based on the burst access signal on the communication bus if a loopback access request is received from the master device and the current mode of the interface controller is direct read mode.

[0110] The second determining module 202 is used to determine the current access mode based on the actual address difference and the expected address difference;

[0111] The first adjustment module 203 is used to adjust the loop boundary according to the current access mode.

[0112] The interface parameter adjustment device provided in this application embodiment is applied to an interface controller that is communicatively connected to a master device and an external storage device. If the interface controller receives a loopback access request sent by the master device and the current mode is direct read mode, the current access mode is determined based on the actual address difference and the expected address difference between two adjacent accesses. Based on the determined current access mode, the loopback boundary of the interface controller is adjusted to achieve dynamic adjustment of the loopback boundary. This allows the loopback range to be adapted to the actual access range of the master device, thereby optimizing the data reading efficiency and further improving the data transmission efficiency in direct read mode.

[0113] As an optional implementation of this application, the second determining module 202 includes: a first determining submodule, used to determine the changing trend of two adjacent access addresses based on the positive or negative result of the actual address difference; a comparison submodule, used to compare the actual address difference with the expected address difference to obtain a size comparison result; a second determining submodule, used to determine a mode flag bit based on the changing trend, the size comparison result, and preset mode flag data; and a third determining submodule, used to determine the current access mode based on the mode flag bit.

[0114] As an optional implementation of this application, the third determining submodule includes: a first determining unit, configured to determine the current instant access mode based on the mode flag; a second determining unit, configured to respond to the percentage statistics of access modes using a sliding window statistical method according to a preset window length, to obtain the continuous access percentage corresponding to the same access mode within the preset window length; and a third determining unit, configured to determine the current access mode based on the current instant access mode and the continuous access percentage corresponding to the same access mode within the preset window length.

[0115] As an optional implementation of this application, the first adjustment module 203 includes: an acquisition submodule, used to acquire the loopback boundary adjustment strategy corresponding to the current access mode; and an adjustment submodule, used to adjust the loopback boundary corresponding to the current access mode according to the loopback boundary adjustment strategy.

[0116] As an optional implementation of this application, the device further includes: a second adjustment module, used to adjust the prefetch length according to the adjusted loopback boundary and the data unit size corresponding to the communication bus.

[0117] As an optional implementation of this application, the interface controller is communicatively connected to the cache space, and the cache space is communicatively connected to the main device; the device further includes: a first reading module, used to read data of a prefetch length from the external storage device according to the prefetch length; and a first storage module, used to store the read data in the cache space.

[0118] As an optional implementation of this application, the interface controller is communicatively connected to the cache space, and the cache space is communicatively connected to the master device; the device further includes: a configuration module, used to configure the cache capacity of the cache space based on the burst access signal read on the communication bus; a second reading module, used to read data of a prefetch length from the external storage device according to the cache capacity; and a second storage module, used to store the read data in the cache space.

[0119] For a description of the features in the embodiment corresponding to the interface parameter adjustment device, please refer to the relevant description in the embodiment corresponding to the interface parameter adjustment method, which will not be repeated here.

[0120] Embodiments of this application also provide an electronic device, such as... Figure 9 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the interface parameter adjustment method embodiments described above.

[0121] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described interface parameter adjustment method embodiments at runtime.

[0122] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0123] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described interface parameter adjustment method embodiments.

[0124] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described interface parameter adjustment method embodiments.

[0125] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0126] The foregoing has provided a detailed description of an interface parameter adjustment method, apparatus, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An interface parameter adjustment method, characterized by, The method is applied to an interface controller, which is connected with a host device and an external storage device respectively; the method comprises: If a loop access request sent by the host device is received and a current mode of the interface controller is a direct read mode, an actual address difference of adjacent two accesses is determined based on access addresses on a communication bus, and an expected address difference is determined based on a burst access signal on the communication bus; A current access mode is determined according to the actual address difference and the expected address difference; A loop boundary is adjusted according to the current access mode.

2. The interface parameter adjustment method of claim 1, wherein, The current access mode is determined according to the actual address difference and the expected address difference, which comprises: A change trend of adjacent two access addresses is determined according to a positive or negative result of the actual address difference; A size comparison result is obtained by comparing the actual address difference with the expected address difference; A mode flag bit is determined according to the change trend, the size comparison result and preset mode flag data; The current access mode is determined according to the mode flag bit.

3. The interface parameter adjustment method of claim 2, wherein, The current access mode is determined according to the mode flag bit, which comprises: A current immediate access mode is determined according to the mode flag bit; A continuous access proportion corresponding to a same access mode in a preset window length is obtained by using a sliding window statistical method to statistically respond to a proportion of the access mode according to the preset window length; The current access mode is determined according to the current immediate access mode and the continuous access proportion corresponding to the same access mode in the preset window length.

4. The interface parameter adjustment method of claim 1, wherein, The loop boundary is adjusted according to the current access mode, which comprises: A loop boundary adjustment strategy corresponding to the current access mode is obtained; The loop boundary corresponding to the current access mode is adjusted according to the loop boundary adjustment strategy.

5. The interface parameter adjustment method of claim 1, wherein, After the loop boundary is adjusted according to the current access mode, the method further comprises: A prefetch length is adjusted according to the adjusted loop boundary and a data unit size corresponding to the communication bus.

6. The interface parameter adjustment method of claim 5, wherein, The interface controller is connected with a cache space, and the cache space is connected with the host device; the method further comprises: Data of the prefetch length is read from the external storage device according to the prefetch length; The read data is stored in the cache space.

7. The interface parameter adjustment method of claim 1, wherein, The interface controller is connected with a cache space, and the cache space is connected with the host device; the method further comprises: A cache capacity of the cache space is configured based on the read burst access signal on the communication bus; Data of the prefetch length is read from the external storage device according to the cache capacity; The read data is stored in the cache space.

8. An interface parameter adjustment device, characterized in that, The method is applied to an interface controller, which is connected with a host device and an external storage device respectively; the device comprises: A first determination module, configured to, if a loop access request sent by the host device is received and a current mode of the interface controller is a direct read mode, determine an actual address difference of adjacent two accesses based on access addresses on a communication bus and determine an expected address difference based on a burst access signal on the communication bus; A second determining module, configured to determine a current access mode according to the actual address difference and the expected address difference; A first adjusting module, configured to adjust a loop boundary according to the current access mode.

9. An electronic device, comprising: The method comprises the following steps: A memory, configured to store a computer program; A processor, configured to execute the computer program to implement the steps of the interface parameter adjusting method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the interface parameter adjusting method according to any one of claims 1 to 7.

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